DATA SHEET MOS INTEGRATED CIRCUIT µPD431632L 1M-BIT CMOS SYNCHRONOUS FAST SRAM 32K-WORD BY 32-BIT PIPELINED OPERATION Description The µPD431632L is a 32,768-word by 32-bit synchronous static RAM fabricated with advanced CMOS technology using N-channel four-transistor memory cell. The µPD431632L integrates unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input (CLK). The µPD431632L is suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory. ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation. The µPD431632LGF is packaged in 100-pin plastic LQFP with a 1.4 mm package thickness high density and low capacitive loading. Features • 3.3 V (Chip) / 3.3 V or 2.5 V (I/O) Supply • Synchronous Operation • Internally self-timed Write control • Burst Read / Write: Interleaved Burst and Linear Burst Sequence • Fully Registered Inputs and Outputs for Pipelined operation • All Registers triggered off Positive Clock Edge • • Single-Cycle deselect timing • 3.3 V or 2.5 V LVTTL Compatible : All Inputs and Outputs • Fast Clock Access Time: 4.6 ns (150 MHz), 5 ns (133 MHz) • Asynchronous Output Enable: /G • Burst Sequence Selectable: MODE • Sleep Mode: ZZ (ZZ = Open or Low : Normal Operation ) • Separate Byte Write Enable: /BW1 - /BW4, /BWE Global Write Enable: /GW • Three Chip Enables for Easy Depth Expansion • Common I/O Using Three State Outputs Ordering Information Part number Access Time Clock frequency Package µPD431632LGF-A6 4.6 ns 150 MHz 100-PIN PLASTIC LQFP (14 x 20) µPD431632LGF-A7 5.0 ns 133 MHz 100-PIN PLASTIC LQFP (14 x 20) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M11347EJ6V0DS00 (6th edition) Date Published December 1999 NS CP(K) Printed in Japan The mark • shows major revised points. © 1996 µPD431632L Pin Configuration(Marking Side) /xxx indicates active low signal. 100-PIN PLASTIC LQFP (14 x 20) A9 A8 /ADV /AP /AC /G /BWE /GW CLK VSS VDD /CE2 /BW1 /BW2 /BW3 /BW4 CE2 /CE A7 A6 [ µPD431632LGF ] 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC 1 80 NC I/O17 2 79 I/O16 I/O18 3 78 I/O15 VDDQ 4 77 VDDQ VSSQ 5 76 VSSQ I/O19 6 75 I/O14 I/O20 7 74 I/O13 I/O21 8 73 I/O12 I/O22 9 72 I/O11 VSSQ 10 71 VSSQ VDDQ 11 70 VDDQ I/O23 12 69 I/O10 I/O24 13 68 I/O9 NC 14 67 VSS VDD 15 66 NC NC 16 65 VDD VSS 17 64 ZZ I/O25 18 63 I/O8 I/O26 19 62 I/O7 VDDQ 20 61 VDDQ VSSQ 21 60 VSSQ I/O27 22 59 I/O6 I/O28 23 58 I/O5 I/O29 24 57 I/O4 I/O30 25 56 I/O3 VSSQ 26 55 VSSQ VDDQ 27 54 VDDQ I/O31 28 53 I/O2 I/O32 29 52 I/O1 NC 30 51 NC Remark Refer to Package Drawing for the 1-pin index mark. 2 Data Sheet M11347EJ6V0DS00 NC NC A14 A13 A12 A11 A10 NC NC VSS VDD NC NC A0 A1 A2 A3 A4 A5 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE • µPD431632L Pin Identification Symbol Pin No. Description A0 - A14 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, Synchronous Address Input 47, 48 I/O1 - I/O32 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, 24, 25, 28, 29 Synchronous Data In, /ADV 83 Synchronous Burst Address Advance Input /AP 84 Synchronous Address Status Processor Input /AC 85 Synchronous Address Status Controller Input /CE,CE2, /CE2 98, 97, 92 Synchronous Chip Enable Input Synchronous / Asynchronous Data Out /BW1 - /BW4, /BWE 93, 94, 95, 96, 87 Synchronous Byte Write Enable Input /GW 88 Synchronous Global Write Input /G 86 Asynchronous Output Enable Input CLK 89 Clock Input MODE 31 Asynchronous Burst Sequence Select Input • Do not change state during normal operation ZZ 64 Asynchronous Power Down State Input VDD 15, 41, 65, 91 Power Supply VSS 17, 40, 67, 90 Ground VDDQ 4, 11, 20, 27, 54, 61, 70, 77 Output Buffer Power Supply VSSQ 5, 10, 21, 26, 55, 60, 71, 76 Output Buffer Ground NC 1, 14, 16, 30, 38, 39, 42, 43, 49, 50, 51, 66, 80 No Connection Data Sheet M11347EJ6V0DS00 3 µPD431632L Block Diagram A0 - A14 15 Address register MODE /ADV CLK 15 13 15 A0, A1 Binary Q1 A1’ counter and logic CLR Q0 A0’ /AC /AP Row & column decoder 8 Byte 1 Write register /BW1 /BW2 Byte 2 Write register /BW3 Byte 3 Write register /BW4 /BWE Byte 4 Write register 8 8 8 Byte 1 Write driver Memory matrix Byte 2 Write driver 512 rows Byte 3 Write driver 64 × 32 columns (1,048,576 bits) Byte 4 Write driver 32 /GW 32 Output register Enable register /CE CE2 /CE2 Enable delay register Input register /G 4 32 I/O1 - I/O32 Power down control ZZ Burst Sequence Interleaved Burst Sequence Table (MODE = Open or VDD) External Address A14 - A2, A1, A0 1st Burst Address A14 - A2, A1, /A0 2nd Burst Address A14 - A2, /A1, A0 3rd Burst Address A14 - A2, /A1, /A0 Linear Burst Sequence Table (MODE = VSS) External Address A14 - A2, 0, 0 A14 - A2, 0, 1 A14 - A2, 1, 0 A14 - A2, 1, 1 1st Burst Address A14 - A2, 0, 1 A14 - A2, 1, 0 A14 - A2, 1, 1 A14 - A2, 0, 0 2nd Burst Address A14 - A2, 1, 0 A14 - A2, 1, 1 A14 - A2, 0, 0 A14 - A2, 0, 1 3rd Burst Address A14 - A2, 1, 1 A14 - A2, 0, 0 A14 - A2, 0, 1 A14 - A2, 1, 0 4 Data Sheet M11347EJ6V0DS00 Output buffer µPD431632L Asynchronous Truth Table Operation /G I/O Read Cycle L Dout Read Cycle H Hi-Z Write Cycle X Hi-Z, Din Deselected X Hi-Z Remark X means “don’t care.” Synchronous Truth Table Operation /CE CE2 /CE2 /AP /AC /ADV /WRITE CLK Address H X X X L X X L→H N/A L L X L X X X L→H N/A L X H L X X X L→H N/A L L X H L X X L→H N/A L X H H L X X L→H N/A Read Cycle / Begin Burst L H L L X X X L→H External Read Cycle / Begin Burst L H L H L X H L→H External Read Cycle / Continue Burst X X X H H L H L→H Next Read Cycle / Continue Burst H X X X H L H L→H Next Read Cycle / Suspend Burst X X X H H H H L→H Current Read Cycle / Suspend Burst H X X X H H H L→H Current Write Cycle / Begin Burst L H L H L X L L→H External Write Cycle / Continue Burst X X X H H L L L→H Next Write Cycle / Continue Burst H X X X H L L L→H Next Write Cycle / Suspend Burst X X X H H H L L→H Current Write Cycle / Suspend Burst H X X X H H L L→H Current Deselected Deselected Deselected Deselected Deselected Note Note Note Note Note Note Deselect status is held until new “Begin Burst” entry. Remarks 1. X means “don’t care.” 2. /WRITE=L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) and /BWE are LOW or /GW is LOW. /WRITE=H means the following two cases. (1) /BWE and /GW are HIGH. (2) /BW1, /BW2, /BW3, /BW4 and /GW are HIGH, and /BWE is LOW. Data Sheet M11347EJ6V0DS00 5 µPD431632L Partial Truth Table for Write Enables Operation /GW /BWE /BW1 /BW2 /BW3 /BW4 Read Cycle H H X X X X Read Cycle H L H H H H Write Cycle / Byte 1 Only H L L H H H Write Cycle / All Bytes H L L L L L Write Cycle / All Bytes L X X X X X Remark X means “don’t care.” Pass-Through Truth Table Previous Cycle Present Cycle Operation Add /WRITE I/O Write Ak L Dn(Ak) Cycle Next Cycle Operation Add /CEs /WRITE /G I/O Operation Read Cycle Am L H L Q1(Ak) Read Q1(Am) - H X X Hi-Z No Carry Over from (Begin Burst) Deselected Previous Cycle Remarks 1. X means “don’t care.” 2. /WRITE=L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) and /BWE are LOW or /GW is LOW. /WRITE=H means the following two cases. (1) /BWE and /GW are HIGH. (2) /BW1, /BW2, /BW3, /BW4 and /GW are HIGH, and /BWE is LOW. /CEs=L means /CE is LOW, /CE2 is LOW and CE2 is HIGH. /CEs=H means /CE is HIGH or /CE2 is HIGH or CE2 is LOW. ZZ (Sleep) Truth Table 6 ZZ Chip Status ≤ 0.2 V Active Open Active ≥ VDD − 0.2 V Sleep Data Sheet M11347EJ6V0DS00 µPD431632L Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Symbol Conditions MIN. TYP. MAX. Unit Note VDD –0.5 +4.6 V VDDQ –0.5 VDD V Input voltage VIN –0.5 VDD + 0.5 V 1, 2 Input / Output voltage VI/O –0.5 VDDQ + 0.5 V 1, 2 Operating ambient temperature TA 0 70 °C Storage temperature Tstg –55 +125 °C Output supply voltage Notes 1. –2.0 V (MIN.)(Pulse width : 2 ns) 2. VDDQ + 2.3 V (MAX.)(Pulse width : 2 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (TA = 0 to 70 °C) for 2.5 V LVTTL interface Parameter Supply voltage Output supply voltage High level input voltage Symbol MIN. TYP. MAX. Unit VDD 3.135 3.3 3.465 V VDDQ 2.375 2.5 2.9 V VIH 1.7 VDDQ + 0.3 V +0.7 V Low level input voltage Conditions VIL –0.3 Note Note –0.8 V (MIN.) (Pulse width : 2 ns) for 3.3 V LVTTL interface Parameter Supply voltage Output supply voltage High level input voltage Symbol MIN. TYP. MAX. Unit VDD 3.135 3.3 3.465 V VDDQ 3.135 3.3 3.465 V VIH 2.0 VDDQ + 0.3 V +0.8 V MAX. Unit Low level input voltage Conditions VIL –0.3 Note Note –0.8 V (MIN.) (Pulse width : 2 ns) Capacitance (TA = 25 °C, f = 1 MHz) Parameter Symbol Test condition MIN. TYP. Input capacitance CIN VIN = 0 V 4 pF Input / Output capacitance CI/O VI/O = 0 V 7 pF Clock input capacitance Cclk Vclk = 0 V 4 pF Remark These parameters are periodically sampled and not 100% tested. Data Sheet M11347EJ6V0DS00 7 µPD431632L DC Characteristics (TA = 0 to 70 °C, VDD = 3.3 V ± 0.165 V) Parameter Input leakage current Symbol ILI Test condition MIN. TYP. MAX. Unit µA VIN (except ZZ, MODE) = 0 V to VDD –2 +2 ZZ, MODE = 0 V or VDD –5 +5 –2 +2 µA mA I/O leakage current ILO VI/O = 0 V to VDDQ, Outputs are disabled. Operating supply current IDD Device selected, Cycle = MAX. -A6 220 VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA -A7 200 Suspend cycle, Cycle = MAX. -A6 60 -A7 50 IDD1 /AC, /AP, /ADV, /GW, /BWEs ≥ VIH VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA Standby supply current ISB Device deselected, Cycle = 0 MHz 35 mA VIN ≤ VIL or VIN ≥ VIH, All inputs are static. ISB1 Device deselected, Cycle = 0 MHz 0.5 20 50 140 0.5 20 VIN ≤ 0.2 V or VIN ≥ VDD − 0.2V VI/O ≤ 0.2 V, All inputs are static. ISB2 Device deselected, Cycle = MAX. VIN ≤ VIL or VIN ≥ VIH ISBZZ ZZ ≥ VDD – 0.2 V, VI/O ≤ VDDQ + 0.2 V High level output voltage VOH IOH = –2.0 mA Low level output voltage VOL IOL = +2.0 mA High level output voltage VOH IOH = –4.0 mA Low level output voltage VOL IOL = +8.0 mA Power down supply current mA 2.5 V LVTTL interface 2.1 V 0.3 V 3.3 V LVTTL interface 8 Data Sheet M11347EJ6V0DS00 2.4 V 0.4 V Note µPD431632L AC Characteristics (TA = 0 to 70 °C, VDD = 3.3 V ± 0.165 V) AC Test Conditions 2.5 V LVTTL Interface Input waveform (Rise / Fall time ≤ 2.4 ns) 2.4 V 1.2 V Test points 1.2 V VSS Output waveform 1.2 V Test points 1.2 V 3.3 V LVTTL Interface Input waveform (Rise / Fall time ≤ 3.0 ns) 3.0 V 1.5 V Test points 1.5 V 1.5 V Test points 1.5 V VSS Output waveform Output load condition CL : 30 pF 5 pF (TKHQX1, TKHQX2, TGLQX, TGHQZ, TKHQZ) External load at test VT = +1.2 V/+1.5 V 50 Ω ZO = 50 Ω I/O (Output) CL Remark CL includes capacitances of the probe and jig, and stray capacitances. Data Sheet M11347EJ6V0DS00 9 µPD431632L Read and Write Cycle (2.5 V LVTTL Interface) Parameter Symbol -A6 -A7 (150 MHz) Unit Note (133 MHz) Standard Alias MIN. MAX. MIN. MAX. Cycle time TKHKH TCYC 6.6 – 7.5 – ns Clock access time TKHQV TCD – 4.6 – 5 ns Output enable access time TGLQV TOE – 4.8 – 4.8 ns Clock high to output active TKHQX1 TDC1 0 – 0 – ns Clock high to output change TKHQX2 TDC2 1.5 – 1.5 – ns Output enable to output active TGLQX TOLZ 0 – 0 – ns Output disable to output high-Z TGHQZ TOHZ 0 4.8 0 4.8 ns Clock high to output high-Z TKHQZ TCZ 1.5 5 1.5 5 ns Clock high pulse width TKHKL TCH 1.8 – 1.9 – ns Clock low pulse width TKLKH TCL 1.8 – 1.9 – ns Setup times Address TAVKH TAS 2 – 2 – ns TADSVKH TSS Data in TDVKH TDS Write enable TWVKH TWS TADVVKH – Chip enable TEVKH – Address TKHAX TAH 0.5 – 0.5 – ns TKHADSX TSH Data in TKHDX TDH Write enable TKHWX TWH TKHADVX – TKHEX – Power down entry setup TZZES TZZES 5 – 5 – ns 1 Power down entry hold TZZEH TZZEH 1 – 1 – ns 1 Power down recovery setup TZZRS TZZRS 6 – 6 – ns 1 Power down recovery hold TZZRH TZZRH 0 – 0 – ns 1 Address status Address advance Hold times Address status Address advance Chip enable Note 1. Although ZZ signal input is asynchronous, the signal must meet specified setup and hold times in order to be recognized. 10 Data Sheet M11347EJ6V0DS00 µPD431632L Read and Write Cycle (3.3 V LVTTL Interface) Parameter Symbol -A6 (150 MHz) -A7 (133 MHz) Unit Note Standard Alias MIN. MAX. MIN. MAX. Cycle time TKHKH TCYC 6.6 – 7.5 – ns Clock access time TKHQV TCD – 4.6 – 5 ns Output enable access time TGLQV TOE – 4.8 – 4.8 ns Clock high to output active TKHQX1 TDC1 0 – 0 – ns Clock high to output change TKHQX2 TDC2 1.5 – 1.5 – ns Output enable to output active TGLQX TOLZ 0 – 0 – ns Output disable to output high-Z TGHQZ TOHZ 0 4.8 0 4.8 ns Clock high to output high-Z TKHQZ TCZ 1.5 5 1.5 5 ns Clock high pulse width TKHKL TCH 2.5 – 2.5 – ns Clock low pulse width TKLKH TCL 3 – 3 – ns Setup times Address TAVKH TAS 2.5 – 2.5 – ns TADSVKH TSS Data in TDVKH TDS Write enable TWVKH TWS TADVVKH – Chip enable TEVKH – Address TKHAX TAH 1 – 1 – ns TKHADSX TSH Data in TKHDX TDH Write enable TKHWX TWH TKHADVX – TKHEX – Power down entry setup TZZES TZZES 5 – 5 – ns 1 Power down entry hold TZZEH TZZEH 1 – 1 – ns 1 Power down recovery setup TZZRS TZZRS 6 – 6 – ns 1 Power down recovery hold TZZRH TZZRH 0 – 0 – ns 1 Address status Address advance Hold times Address status Address advance Chip enable Note 1. Although ZZ signal input is asynchronous, the signal must meet specified setup and hold times in order to be recognized. Data Sheet M11347EJ6V0DS00 11 12 READ CYCLE TKHKH CLK TADSVKH TKHKL TKHADSX TKLKH /AP TADSVKH TKHADSX /AC TAVKH TKHAX A1 Address A2 A3 TADVVKH TKHADVX /ADV Data Sheet M11347EJ6V0DS00 TWVKH TKHWX TWVKH TKHWX /BWE /BWs /GW Note 1 TEVKH TKHEX /CEs /G TGLQV Data In TGHQZ TKHQX2 TGLQX Data Out Hi-Z Q1(A1) Q1(A2) TKHQV Q2(A2) TKHQZ Q3(A2) Q4(A2) Q1(A2) (Note 2) Notes 1. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. 2. Outputs are disabled within one clock cycle after deselect. Remark Qn(A2) refers to output from address A2. Q1-Q4 refer to outputs according to burst sequence. µPD431632L When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. WRITE CYCLE TKHKH CLK TADSVKH TKHADSX TKHKL TKLKH /AP TADSVKH TKHADSX /AC TAVKH Address TKHAX A1 A2 A3 TADVVKH TKHADVX /ADV Data Sheet M11347EJ6V0DS00 TWVKH /BWE Note1 /BWs TWVKH /GW Note1 /CEs Note2 TEVKH TKHWX TKHWX TKHEX /G TDVKH Data In D1(A1) TGHQZ Data Out D1(A2) TKHDX D2(A2) D2(A2) D3(A2) D4(A2) D1(A3) D2(A3) D3(A3) Hi-Z 2. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. 13 µPD431632L Notes 1. All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1-/BW4 LOW. 14 READ / WRITE CYCLE TKHKH CLK TKLKH TKHKL TADSVKH TKHADSX /AP TADSVKH TKHADSX /AC TKHAX TAVKH A1 Address A2 A3 TADVVKH TKHADVX Data Sheet M11347EJ6V0DS00 /ADV TWVKH TKHWX TWVKH TKHWX /BWE Note1 /BWs /GW Note1 TEVKH TKHEX /CEs Note2 /G TDVKH Data In TGHQZ Hi-Z Data Out TKHQV TKHQX1 TKHDX D1(A2) TGLQX Q1(A1) Q1(A2) Q1(A3) Q2(A3) Q3(A3) Q4(A3) 2. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. µPD431632L Notes 1. All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1-/BW4 LOW. SINGLE READ / WRITE CYCLE TKHKH CLK TKLKH TKHKL TADSVKH TKHADSX /AC TAVKH TKHAX Address A2 A1 A3 A5 A4 TWVKH TKHWX TWVKH TKHWX A7 A6 A8 A9 /BWE Note1 /BWs Data Sheet M11347EJ6V0DS00 /GW Note1 TEVKH TKHEX /CEs Note2 /G TDVKH TKHDX Data In D1(A5) Hi-Z Data Out TGLQV TGLQX Q1(A1) TGHQZ Q1(A2) Q1(A3) D1(A6) D1(A7) TKHQZ TKHQV Q1(A4) Q1(A7) Q1(A8) Q1(A9) (Note 3) Notes 1. All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1-/BW4 LOW. 2. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. Remark /AP is HIGH and /ADV is don't care. 15 µPD431632L 3. Outputs are disabled within one clock cycle after deselect. 16 POWER DOWN (ZZ) CYCLE TKHKH CLK TKHKL TKLKH /AP /AC Address A2 A1 Data Sheet M11347EJ6V0DS00 /ADV /BWE /BWs /GW /CEs /G Hi-Z Data Out Q1(A1) TZZEH Q1(A2) TZZES TZZRH Power Down (ISBZZ) State µPD431632L ZZ TZZRS STOP CLOCK CYCLE TKHKH CLK TKHKL TKLKH /AP /AC Address A2 A1 Data Sheet M11347EJ6V0DS00 /ADV /BWE /BWs /GW /CEs /G Data In Data Out Hi-Z Q1(A1) Q1(A2) Note VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V, VI/O ≤ 0.2 V 17 µPD431632L Power Down State (ISB1) Note µPD431632L • Package Drawing 100-PIN PLASTIC LQFP (14x20) A B 80 81 51 50 detail of lead end S C D R Q 31 30 100 1 F G H I J M K P S N S L M NOTE ITEM Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 22.0±0.2 B 20.0±0.2 C 14.0±0.2 D 16.0±0.2 F 0.825 G 0.575 H 0.32 +0.08 −0.07 I J 0.13 0.65 (T.P.) K 1.0±0.2 L 0.5±0.2 M 0.17 +0.06 −0.05 N 0.10 P 1.4 Q 0.125±0.075 R 3° +7° −3° S 1.7 MAX. S100GF-65-8ET-1 18 Data Sheet M11347EJ6V0DS00 µPD431632L Recommended Soldering Condition Please consult with our sales offices for soldering conditions of the µPD431632L. Type of Surface Mount Devices µPD431632LGF : 100-PIN PLASTIC LQFP (14 x 20) Data Sheet M11347EJ6V0DS00 19 µPD431632L [MEMO] 20 Data Sheet M11347EJ6V0DS00 µPD431632L [MEMO] Data Sheet M11347EJ6V0DS00 21 µPD431632L [MEMO] 22 Data Sheet M11347EJ6V0DS00 µPD431632L NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M11347EJ6V0DS00 23 µPD431632L • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8