DATA SHEET MOS INTEGRATED CIRCUIT µPD432232L 2M-BIT CMOS SYNCHRONOUS FAST SRAM 64K-WORD BY 32-BIT PIPELINED OPERATION Description The µPD432232L is a 65,536-word by 32-bit synchronous static RAM fabricated with advanced CMOS technology using N-channel four-transistor memory cell. The µPD432232L integrates unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input (CLK). The µPD432232L is suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory. ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation. The µPD432232LGF is packaged in 100-pin plastic LQFP with a 1.4 mm package thickness for high density and low capacitive loading. Features • 3.3 V (Chip) / 3.3V or 2.5V (I/O) Supply • Fast Clock Access Time: 5 ns / 100 MHz, 7 ns / 83 • Synchronous Operation MHz, 8 ns / 66 MHz • Internally self-timed Write control • Asynchronous Output Enable: /G • Burst Read / Write: Interleaved Burst and Linear Burst • Burst Sequence Selectable: MODE • Sleep Mode: ZZ (ZZ =Open or Low: Normal Operation) Sequence • Fully Registered Inputs and Outputs for Pipelined • Separate Byte Write Enable: /BW1 - /BW4, /BWE operation • Global Write Enable: /GW • All Registers triggered off Positive Clock Edge • Three Chip Enables for Easy Depth Expansion • Single-Cycle deselect timing • Common I/O Using Three State Outputs • 3.3 V or 2.5 V LVTTL Compatible: All Inputs and Outputs Ordering Information Part number Access Time Clock frequency Package µPD432232LGF-A5 5 ns 100 MHz 100-PIN PLASTIC LQFP (14 x 20) µPD432232LGF-A7 7 ns 83 MHz 100-PIN PLASTIC LQFP (14 x 20) µPD432232LGF-A8 8 ns 66 MHz 100-PIN PLASTIC LQFP (14 x 20) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M12180EJ6V0DSJ1 (6th edition) Date Published November 2000 NS CP(K) Printed in Japan The mark • shows major revised points. © 1996 µPD432232L Pin Configuration (Marking Side) /xxx indicates active low signal. 100-PIN PLASTIC LQFP (14 x 20) A9 A8 /ADV /AP /AC /G /BWE /GW CLK VSS VDD /CE2 /BW1 /BW2 /BW3 /BW4 CE2 /CE A7 A6 [ µPD432232LGF ] 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC 1 80 NC I/O17 2 79 I/O16 I/O18 3 78 I/O15 VDDQ 4 77 VDDQ VSSQ 5 76 VSSQ I/O19 6 75 I/O14 I/O20 7 74 I/O13 I/O21 8 73 I/O12 I/O22 9 72 I/O11 VSSQ 10 71 VSSQ VDDQ 11 70 VDDQ I/O23 12 69 I/O10 I/O24 13 68 I/O9 NC 14 67 VSS VDD 15 66 NC NC 16 65 VDD VSS 17 64 ZZ I/O25 18 63 I/O8 I/O26 19 62 I/O7 VDDQ 20 61 VDDQ VSSQ 21 60 VSSQ I/O27 22 59 I/O6 I/O28 23 58 I/O5 I/O29 24 57 I/O4 I/O30 25 56 I/O3 VSSQ 26 55 VSSQ VDDQ 27 54 VDDQ I/O31 28 53 I/O2 I/O32 29 52 I/O1 NC 30 51 NC Remark Refer to Package Drawing for the 1-pin index mark. 2 Data Sheet M12180EJ6V0DS NC A15 A14 A13 A12 A11 A10 NC NC VSS VDD NC A0 NC A1 A2 A3 A4 A5 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE • µPD432232L Pin Identification Symbol Pin No. Description A0 - A15 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49 Synchronous Address Input I/O1 - I/O32 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, Synchronous Data In, Synchronous / Asynchronous Data Out 22, 23, 24, 25, 28, 29 /ADV 83 Synchronous Burst Address Advance Input /AP 84 Synchronous Address Status Processor Input AC 85 Synchronous Address Status Controller Input /CE, CE2, /CE2 98, 97, 92 Synchronous Chip Enable Input /BW1 - /BW4, /BWE 93, 94, 95, 96, 87 Synchronous Byte Write Enable Input /GW 88 Synchronous Global Write Input /G 86 Asynchronous Output Enable Input CLK 89 Clock Input MODE 31 Asynchronous Burst Sequence Select Input • Do not change state during normal operation ZZ 64 Asynchronous Power Down State Input VDD 15, 41, 65, 91 Power Supply VSS 17, 40, 67, 90 Ground VDDQ 4, 11, 20, 27, 54, 61, 70, 77 Output Buffer Power Supply VSSQ 5, 10, 21, 26, 55, 60, 71, 76 Output Buffer Ground NC 1, 14, 16, 30, 38, 39, 42, 43, 50, 51, 66, 80 No Connection Data Sheet M12180EJ6V0DS 3 µPD432232L Block Diagram 16 Address register A0 - A15 MODE /ADV CLK 16 14 16 A0, A1 A1’ Binary Q1 counter and logic A0’ CLR Q0 /AC /AP Row & column decoder 8 Byte 1 Write register /BW1 /BW2 Byte 2 Write register /BW3 Byte 3 Write register /BW4 /BWE Byte 4 Write register 8 8 8 Byte 1 Write driver Memory matrix Byte 2 Write driver 1,024 rows Byte 3 Write driver Byte 4 Write driver 32 /GW 64 × 32 columns (2,097,152 bits) 32 Output register Enable register /CE CE2 /CE2 Enable delay register /G 4 Input register 32 I/O1 - I/O32 Power down control ZZ Burst Sequence Interleaved Burst Sequence Table (MODE = Open or VDD) External Address A15 - A2, A1, A0 1st Burst Address A15 - A2, A1, /A0 2nd Burst Address A15 - A2, /A1, A0 3rd Burst Address A15 - A2, /A1, /A0 Linear Burst Sequence Table (MODE = VSS) External Address A15 - A2, 0, 0 A15 - A2, 0, 1 A15 - A2, 1, 0 A15 - A2, 1, 1 1st Burst Address A15 - A2, 0, 1 A15 - A2, 1, 0 A15 - A2, 1, 1 A15 - A2, 0, 0 2nd Burst Address A15 - A2, 1, 0 A15 - A2, 1, 1 A15 - A2, 0, 0 A15 - A2, 0, 1 3rd Burst Address A15 - A2, 1, 1 A15 - A2, 0, 0 A15 - A2, 0, 1 A15 - A2, 1, 0 4 Data Sheet M12180EJ6V0DS Output buffer µPD432232L Asynchronous Truth Table Operation /G I/O Read Cycle L Dout Read Cycle H Hi-Z Write Cycle X Hi-Z, Din Deselected X Hi-Z Remark X means “don’t care.” Synchronous Truth Table Operation /CE CE2 /CE2 /AP /AC /ADV /WRITE CLK Address H X X X L X X L→H N/A L L X L X X X L→H N/A L X H L X X X L→H N/A L L X H L X X L→H N/A L X H H L X X L→H N/A Read Cycle / Begin Burst L H L L X X X L→H External Read Cycle / Begin Burst L H L H L X H L→H External Read Cycle / Continue Burst X X X H H L H L→H Next Read Cycle / Continue Burst H X X X H L H L→H Next Read Cycle / Suspend Burst X X X H H H H L→H Current Read Cycle / Suspend Burst H X X X H H H L→H Current Write Cycle / Begin Burst L H L H L X L L→H External Write Cycle / Continue Burst X X X H H L L L→H Next Write Cycle / Continue Burst H X X X H L L L→H Next Write Cycle / Suspend Burst X X X H H H L L→H Current Write Cycle / Suspend Burst H X X X H H L L→H Current Deselected Deselected Deselected Deselected Deselected Note Note Note Note Note Note Deselect status is held until new “Begin Burst” entry. Remarks 1. X means “don’t care.” 2. /WRITE = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) and /BWE are LOW or /GW is LOW. /WRITE = H means the following two cases. (1) /BWE and /GW are HIGH. (2) /BW1, /BW2, /BW3, /BW4 and /GW are HIGH, and /BWE is LOW. Data Sheet M12180EJ6V0DS 5 µPD432232L Partial Truth Table for Write Enables Operation /GW /BWE /BW1 /BW2 /BW3 /BW4 Read Cycle H H X X X X Read Cycle H L H H H H Write Cycle / Byte 1 Only H L L H H H Write Cycle / All Bytes H L L L L L Write Cycle / All Bytes L X X X X X Remark X means “don’t care.” Pass-Through Truth Table Previous Cycle Present Cycle Operation Add /WRITE I/O Write Ak L Dn(Ak) Cycle Next Cycle Operation Add /CEs /WRITE /G I/O Operation Read Cycle Am L H L Q1(Ak) Read Q1(Am) - H X X Hi-Z No Carry Over from (Begin Burst) Deselected Previous Cycle Remarks 1. X means “don’t care.” 2. /WRITE = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) and /BWE are LOW or /GW is LOW. /WRITE = H means the following two cases. (1) /BWE and /GW are HIGH. (2) /BW1, /BW2, /BW3, /BW4 and /GW are HIGH, and /BWE is LOW. /CEs = L means /CE is LOW, /CE2 is LOW and CE2 is HIGH. /CEs = H means /CE is HIGH or /CE2 is HIGH or CE2 is LOW. ZZ (Sleep) Truth Table 6 ZZ Chip Status ≤ 0.2V Active Open Active ≥ VDD − 0.2V Sleep Data Sheet M12180EJ6V0DS µPD432232L Electrical Specifications Absolute Maximum Ratings Parameter Symbol Supply voltage Conditions MIN. TYP. MAX. Unit Note VDD –0.5 +4.6 V VDDQ –0.5 VDD V Input voltage VIN –0.5 VDD + 0.5 V 1, 2 Input / Output voltage VI/O –0.5 VDDQ + 0.5 V 1, 2 Operating ambient temperature TA 0 70 °C Storage temperature Tstg –55 +125 °C Output supply voltage Notes 1. –2.0 V (MIN.)(Pulse width : 2 ns) 2. VDDQ + 2.3 V (MAX.)(Pulse width : 2 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (TA = 0 to 70 °C) for 2.5 V LVTTL interface Parameter Symbol MIN. TYP. MAX. Unit VDD 3.1 3.3 3.6 V VDDQ 2.375 2.5 2.9 V VIH 1.7 VDDQ + 0.3 V +0.7 V Supply voltage Output supply voltage High level input voltage Low level input voltage Conditions VIL –0.5 Note Note –0.8 V MIN. (Pulse Width : 2 ns) for 3.3 V LVTTL interface Parameter Symbol MIN. TYP. MAX. Unit VDD 3.1 3.3 3.6 V VDDQ 3.1 3.3 3.6 V VIH 2.0 VDDQ + 0.3 V +0.8 V MAX. Unit Supply voltage Output supply voltage High level input voltage Low level input voltage Conditions –0.5 VIL Note Note –0.8 V MIN. (Pulse Width : 2 ns) Capacitance (TA = 25 °C, f = 1MHz) Parameter Symbol Test conditions Input Capacitance CIN VIN = 0 V 4 pF Input / Output Capacitance CI/O VI/O = 0 V 7 pF Clock Input Capacitance Cclk Vclk = 0 V 4 pF Remark These parameters are sampled and not 100% tested. Data Sheet M12180EJ6V0DS 7 µPD432232L DC Characteristics (TA = 0 to 70°C, VDD = 3.1 to 3.6 V) Parameter Input leakage current Symbol ILI Test condition MIN. TYP. MAX. Unit µA VIN(except ZZ, MODE) = 0 V to VDD –2 +2 ZZ, MODE = 0 V or VDD –5 +5 –2 +2 µA 180 mA I/O leakage current ILO VI/O = 0 V to VDDQ, Output disabled Operating supply current IDD Device selected, Cycle = MAX. VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA IDD1 60 Suspend cycle, Cycle = MAX. /AC, /AP, /ADV, /GW, /BWEs ≥ VIH VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA Standby supply current ISB Device deselected, Cycle = 0 MHz 20 mA VIN ≤ VIL or VIN ≥ VIH, All inputs static ISB1 0.2 Device deselected, Cycle = 0 MHz 2.0 VIN ≤ 0.2V or VIN ≥ VDD – 0.2V, VI/O ≤ 0.2 V, All inputs static ISB2 Device deselected, Cycle = MAX. 60 VIN ≤ VIL or VIN ≥ VIH ISBZZ ZZ ≥ VDD – 0.2V, VI/O ≤ VDDQ + 0.2V High level output voltage VOH IOH = –2.0 mA Low level output voltage VOL IOL = +2.0 mA High level output voltage VOH IOH = –4.0 mA Low level output voltage VOL IOL = +8.0 mA Power down supply current 0.2 2.0 mA 2.5 V LVTTL interface 2.1 V 0.3 V 3.3 V LVTTL interface 8 Data Sheet M12180EJ6V0DS 2.4 V 0.4 V Note µPD432232L AC Characteristics (TA = 0 to 70 °C, VDD = 3.1 to 3.6 V) AC Test Conditions 2.5 V LVTTL interface Input waveform (Rise / Fall time ≤ 2.4 ns) 2.4 V 1.2 V Test points 1.2 V 1.2 V Test points 1.2 V 1.5 V Test points 1.5 V 1.5 V Test points 1.5 V VSS Output waveform 3.3 V LVTTL interface Input waveform (Rise / Fall time ≤ 3.0 ns) 3.0 V VSS Output waveform Output load condition CL : 30 pF 5 pF (TKHQX1, TKHQX2, TGLQX, TGHQZ, TKHQZ) External load at test VT = +1.2 V / +1.5 V 50 Ω ZO = 50 Ω I/O (Output) CL Remark CL includes capacitances of the probe and jig, and stray capacitances. Data Sheet M12180EJ6V0DS 9 µPD432232L Read and Write Cycle (2.5 V LVTTL interface) Parameter -A5 -A7 -A8 (100 MHz) (83 MHz) (66 MHz) Symbol Unit Standard Alias MIN. MAX. MIN. MAX. MIN. MAX. Cycle time TKHKH TCYC 10 – 12 – 15 – ns Clock access time TKHQV TCD – 5 – 7 – 8 ns Output enable access time TGLQV TOE – 4.5 – 5 – 5 ns Clock high to output active TKHQX1 TDC1 2 – 2 – 2 – ns Clock high to output change TKHQX2 TDC2 2.5 – 3 – 3 – ns Output enable to output active TGLQX TOLZ 2 – 2 – 2 – ns Output disable to output high-Z TGHQZ TOHZ 2 5 2 5 2 5 ns Clock high to output high-Z TKHQZ TCZ 2 5 2 5 2 5 ns Clock high pulse width TKHKL TCH 4 – 4.5 – 5 – ns Clock low pulse width TKLKH TCL 4 – 4.5 – 5 – ns Setup times TAVKH TAS 2.5 – 2.5 – 2.5 – ns TADSVKH TSS Data in TDVKH TDS 2.2 – Write enable TWVKH TWS 2.5 – 0.5 – 0.5 – 0.5 – ns Address Address status Hold times Address advance TADVVKH – Chip enable TEVKH – Address TKHAX TAH TKHADSX TSH Data in TKHDX TDH Write enable TKHWX TWH Address status Note Address advance TKHADVX – Chip enable TKHEX – Power down entry setup TZZES TZZES 8 – 8 – 8 – ns 1 Power down entry hold TZZEH TZZEH 0 – 0 – 0 – ns 1 Power down recovery setup TZZRS TZZRS 8 – 8 – 8 – ns 1 Power down recovery hold TZZRH TZZRH 0 – 0 – 0 – ns 1 Note 1. Although ZZ signal input is asynchronous, the signal must meet specified setup and hold times in order to be recognized. 10 Data Sheet M12180EJ6V0DS µPD432232L Read and Write Cycle (3.3 V LVTTL interface) Parameter Symbol -A5 -A7 -A8 Unit (100 MHz) (83 MHz) (66 MHz) Standard Alias MIN. MAX. MIN. MAX. MIN. MAX. Cycle time TKHKH TCYC 10 – 12 – 15 – ns Clock access time TKHQV TCD – 5 – 7 – 8 ns Output enable access time TGLQV TOE – 4.5 – 5 – 5 ns Clock high to output active TKHQX1 TDC1 2 – 2 – 2 – ns Clock high to output change TKHQX2 TDC2 2.5 – 3 – 3 – ns Output enable to output active TGLQX TOLZ 2 – 2 – 2 – ns Output disable to output high-Z TGHQZ TOHZ 2 5 2 5 2 5 ns Clock high to output high-Z TKHQZ TCZ 2 5 2 5 2 5 ns Clock high pulse width TKHKL TCH 4 – 4.5 – 5 – ns Clock low pulse width TKLKH TCL 4 – 4.5 – 5 – ns Setup times TAVKH TAS 2.5 – 2.5 – 2.5 – ns TADSVKH TSS Data in TDVKH TDS 2.2 – Write enable TWVKH TWS 2.5 – 0.5 – 0.5 – 0.5 – ns Address Address status Hold times Address advance TADVVKH – Chip enable TEVKH – Address TKHAX TAH TKHADSX TSH Data in TKHDX TDH Write enable TKHWX TWH Address status Note Address advance TKHADVX – Chip enable TKHEX – Power down entry setup TZZES TZZES 8 – 8 – 8 – ns 1 Power down entry hold TZZEH TZZEH 0 – 0 – 0 – ns 1 Power down recovery setup TZZRS TZZRS 8 – 8 – 8 – ns 1 Power down recovery hold TZZRH TZZRH 0 – 0 – 0 – ns 1 Note 1. Although ZZ signal input is asynchronous, the signal must meet specified setup and hold times in order to be recognized. Data Sheet M12180EJ6V0DS 11 12 READ CYCLE TKHKH CLK TADSVKH TKHKL TKHADSX TKLKH /AP TADSVKH TKHADSX /AC TAVKH TKHAX A1 Address A2 A3 TADVVKH TKHADVX /ADV Data Sheet M12180EJ6V0DS TWVKH TKHWX TWVKH TKHWX /BWE /BWs /GW Note 1 TEVKH TKHEX /CEs /G TGLQV Data In TGHQZ TKHQX2 TGLQX Data Out Hi-Z Q1(A1) Q1(A2) TKHQV Q2(A2) TKHQZ Q3(A2) Q4(A2) Q1(A2) (Note 2) Notes 1. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. 2. Outputs are disabled within one clock cycle after deselect. Remark Qn(A2) refers to output from address A2. Q1-Q4 refer to outputs according to burst sequence. µPD432232L When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. WRITE CYCLE TKHKH CLK TADSVKH TKHADSX TKHKL TKLKH /AP TADSVKH TKHADSX /AC TAVKH Address TKHAX A1 A2 A3 TADVVKH TKHADVX /ADV Data Sheet M12180EJ6V0DS TWVKH /BWE Note1 /BWs TWVKH /GW Note1 /CEs Note2 TEVKH TKHWX TKHWX TKHEX /G TDVKH Data In D1(A1) TGHQZ Data Out D1(A2) TKHDX D2(A2) D2(A2) D3(A2) D4(A2) D1(A3) D2(A3) D3(A3) Hi-Z 2. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. 13 µPD432232L Notes 1. All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1-/BW4 LOW. 14 READ / WRITE CYCLE TKHKH CLK TKLKH TKHKL TADSVKH TKHADSX /AP TADSVKH TKHADSX /AC TKHAX TAVKH A1 Address A2 A3 TADVVKH TKHADVX /ADV Data Sheet M12180EJ6V0DS TWVKH TKHWX TWVKH TKHWX /BWE Note1 /BWs /GW Note1 TEVKH TKHEX /CEs Note2 /G TDVKH Data In TGHQZ Hi-Z Data Out TKHQV TKHQX1 TKHDX D1(A2) TGLQX Q1(A1) Q1(A2) Q1(A3) Q2(A3) Q3(A3) Q4(A3) 2. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. µPD432232L Notes 1. All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1-/BW4 LOW. SINGLE READ / WRITE CYCLE TKHKH CLK TKLKH TKHKL TADSVKH TKHADSX /AC TAVKH TKHAX Address A2 A1 A3 A5 A4 TWVKH TKHWX TWVKH TKHWX A7 A6 A8 A9 /BWE Note1 /BWs Data Sheet M12180EJ6V0DS /GW Note1 TEVKH TKHEX /CEs Note2 /G TDVKH TKHDX Data In D1(A5) Hi-Z Data Out TGLQV TGLQX Q1(A1) TGHQZ Q1(A2) Q1(A3) D1(A6) D1(A7) TKHQZ TKHQV Q1(A4) Q1(A7) Q1(A8) Q1(A9) (Note 3) Notes 1. All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1-/BW4 LOW. 2. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. Remark /AP is HIGH and /ADV is don't care. 15 µPD432232L 3. Outputs are disabled within one clock cycle after deselect. 16 POWER DOWN (ZZ) CYCLE TKHKH CLK TKHKL TKLKH /AP /AC Address A2 A1 Data Sheet M12180EJ6V0DS /ADV /BWE /BWs /GW /CEs /G Hi-Z Data Out Q1(A1) TZZEH Q1(A2) TZZES TZZRH Power Down (ISBZZ) State µPD432232L ZZ TZZRS STOP CLOCK CYCLE TKHKH CLK TKHKL TKLKH /AP /AC Address A2 A1 Data Sheet M12180EJ6V0DS /ADV /BWE /BWs /GW /CEs /G Data In Data Out Hi-Z Q1(A1) Q1(A2) Note VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V, VI/O ≤ 0.2 V 17 µPD432232L Power Down State (ISB1) Note µPD432232L • Package Drawing 100-PIN PLASTIC LQFP (14x20) A B 80 81 51 50 detail of lead end S C D R Q 31 30 100 1 F G H I J M K P S N S L M NOTE ITEM Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 22.0±0.2 B 20.0±0.2 C 14.0±0.2 D 16.0±0.2 F 0.825 G 0.575 H 0.32 +0.08 −0.07 I J 0.13 0.65 (T.P.) K 1.0±0.2 L 0.5±0.2 M 0.17 +0.06 −0.05 N 0.10 P 1.4 Q 0.125±0.075 R 3° +7° −3° S 1.7 MAX. S100GF-65-8ET-1 18 Data Sheet M12180EJ6V0DS µPD432232L Recommended Soldering Condition Please consult with our sales offices for soldering conditions of the µPD432232L. Type of Surface Mount Devices µPD432232LGF : 100-PIN PLASTIC LQFP (14 x 20) Data Sheet M12180EJ6V0DS 19 µPD432232L [MEMO] 20 Data Sheet M12180EJ6V0DS µPD432232L [MEMO] Data Sheet M12180EJ6V0DS 21 µPD432232L [MEMO] 22 Data Sheet M12180EJ6V0DS µPD432232L NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M12180EJ6V0DS 23 µPD432232L • The information in this document is current as of November, 2000. The information is subject to change without notice. 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