DATA SHEET MOS INTEGRATED CIRCUIT µPD444012A-X 4M-BIT CMOS STATIC RAM 256K-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION Description The µPD444012A-X is a high speed, low power, 4,194,304 bits (262,144 words by 16 bits) CMOS static RAM. The µPD444012A-X has two chip enable pins (/CE1, CE2) to extend the capacity. The µPD444012A-X is packed in 48-pin PLASTIC TSOP (I) (Normal bent). Features • 262,144 words by 16 bits organization ★ • Fast access time: 50, 55, 70, 85, 100, 120 ns (MAX.) • Byte data control: /LB (I/O1 - I/O8), /UB (I/O9 - I/O16) ★ • Low voltage operation (B version: VCC = 2.7 to 3.6 V, C version: VCC = 2.2 to 3.6 V) • Low VCC data retention: 1.0 V (MIN.) • Operating ambient temperature: TA = –25 to +85°C • Output Enable input for easy application • Two Chip Enable inputs: /CE1, CE2 Part number ★ µPD444012A-BxxX µPD444012A-CxxX ★ 50 Access time Operating supply Operating ambient ns (MAX.) Voltage temperature At operating At standby At data retention V °C mA (MAX.) µA (MAX.) µA (MAX.) 2.7 to 3.6 −25 to +85 7 3 Note 1 , 55, 70, 85, 100 70, 85, 100, 120 2.2 to 3.6 Supply current 40 Note 2 45 Note 3 50 Note 4 40 Notes 1. VCC ≥ 3.0 V ★ 2. Cycle time ≥ 70 ns ★ 3. Cycle time = 55 ns ★ 4. Cycle time = 50 ns The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M14464EJ5V0DS00 (5th edition) Date Published July 2001 NS CP (K) Printed in Japan The mark ★ shows major revised points. © 1999 µPD444012A-X ★ Ordering Information Part number Package µPD444012AGY-B55X-MJH 48-pin PLASTIC TSOP (I) µPD444012AGY-B70X-MJH (12×18) (Normal bent) Access time Operating Operating ns (MAX.) supply voltage temperature V °C 2.7 to 3.6 −25 to +85 55, 50 Note B version 70 µPD444012AGY-B85X-MJH 85 µPD444012AGY-B10X-MJH 100 µPD444012AGY-C70X-MJH 70 µPD444012AGY-C85X-MJH 85 µPD444012AGY-C10X-MJH 100 µPD444012AGY-C12X-MJH 120 Note VCC ≥ 3.0 V 2 Remark Data Sheet M14464EJ5V0DS 2.2 to 3.6 C version µPD444012A-X ★ Pin Configuration (Marking Side) /xxx indicates active low signal. ×18) (Normal bent) 48-pin PLASTIC TSOP (I) (12× [ µPD444012AGY-BxxX-MJH ] [ µPD444012AGY-CxxX-MJH ] A15 A14 A13 A12 A11 A10 A9 A8 NC NC /WE CE2 NC /UB /LB NC A17 A7 A6 A5 A4 A3 A2 A1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A0 - A17 A16 NC GND I/O16 I/O8 I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 VCC I/O12 I/O4 I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 /OE GND /CE1 A0 : Address inputs I/O1 - I/O16 : Data inputs / outputs /CE1, CE2 : Chip Enable 1, 2 /WE : Write Enable /OE : Output Enable /LB, /UB : Byte data select VCC : Power supply GND : Ground NC : No Connection Remark Refer to Package Drawing for the 1-pin index mark. Data Sheet M14464EJ5V0DS 3 µPD444012A-X Block Diagram VCC GND A0 Address buffer A17 Row decoder Memory cell array 4,194,304 bits Sense amplifier / Switching circuit I/O1 - I/O8 Input data controller I/O9 - I/O16 Output data controller Column decoder Address buffer /CE1 CE2 /LB /UB /WE /OE Truth Table /CE1 CE2 /OE /WE /LB /UB Mode I/O I/O1 - I/O8 I/O9 - I/O16 Not selected High impedance High impedance ISB ICCA H × × × × × × L × × × × L H H H × × Output disable High impedance High impedance L H L L Word read DOUT DOUT L H Lower byte read DOUT High impedance H L Upper byte read High impedance DOUT L L Word write DIN DIN L H Lower byte write DIN High impedance H L Upper byte write High impedance DIN H H Not selected High impedance High impedance × × × × L × Remark × : VIH or VIL 4 Supply current Data Sheet M14464EJ5V0DS ISB µPD444012A-X Electrical Specifications Absolute Maximum Ratings Parameter Symbol Condition Rating –0.5 Note Unit Supply voltage VCC Input / Output voltage VT Operating ambient temperature TA –25 to +85 °C Storage temperature Tstg –55 to +125 °C –0.5 Note to +4.0 V to VCC + 0.4 (4.0 V MAX.) V Note –3.0 V (MIN.) (Pulse width : 30 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. ★ Recommended Operating Conditions Parameter Symbol Supply voltage VCC High level input voltage VIH Low level input voltage VIL Operating ambient temperature TA Condition µPD444012A-BxxX µPD444012A-CxxX Unit MIN. MAX. MIN. MAX. 2.7 3.6 2.2 3.6 V 2.7 V ≤ VCC ≤ 3.6 V 2.4 VCC+0.4 2.4 VCC+0.4 V 2.2 V ≤ VCC < 2.7 V – – 2.0 VCC+0.3 –0.3 Note –25 +0.5 –0.3 Note +0.3 V +85 –25 +85 °C MIN. TYP. MAX. Unit Note –1.5 V (MIN.) (Pulse width: 30 ns) Capacitance (TA = 25°°C, f = 1 MHz) Parameter Symbol Test condition Input capacitance CIN VIN = 0 V 8 pF Input / Output capacitance CI/O VI/O = 0 V 10 pF Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are not 100% tested. Data Sheet M14464EJ5V0DS 5 µPD444012A-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)(1/2) Parameter Symbol VCC ≥ 2.7 V Test condition Unit µPD444012A-BxxX MIN. TYP. MAX. Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0 µA I/O leakage current ILO VI/O = 0 V to VCC, /CE1 = VIH or –1.0 +1.0 µA mA CE2 = VIL or /WE = VIL or /OE = VIH ★ Operating supply current ICCA1 ★ ★ ICCA2 /CE1 = VIL, CE2 = VIH, Cycle time = 50 ns – 50 Minimum cycle time, Cycle time = 55 ns – 45 II/O = 0 mA Cycle time ≥ 70 ns – 40 – 4 – 6 – 0.6 mA µA /CE1 = VIL, CE2 = VIH, II/O = 0 mA, Cycle time = ∞ ★ ICCA3 /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, Cycle time = 1 µs, II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V Standby supply current ISB /CE1 = VIH or CE2 = VIL or /LB = /UB = VIH ISB1 /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V 0.5 7 ISB2 CE2 ≤ 0.2 V 0.5 7 ISB3 /LB = /UB ≥ VCC − 0.2 V, /CE1 ≤ 0.2 V, 0.5 7 CE2 ≥ VCC − 0.2 V High level output voltage VOH IOH = –0.5 mA Low level output voltage VOL IOL = 1.0 mA 2.4 0.4 Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of product specification. 6 V Data Sheet M14464EJ5V0DS V µPD444012A-X ★ DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)(2/2) Parameter Symbol VCC ≥ 2.2 V Test condition Unit µPD444012A-CxxX MIN. TYP. MAX. Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0 µA I/O leakage current ILO VI/O = 0 V to VCC, /CE1 = VIH or –1.0 +1.0 µA – 40 mA – 25 – 4 – 2 – 6 – 5 – 0.6 – 0.6 0.5 7 0.4 6 0.5 7 0.4 6 /LB = /UB ≥ VCC − 0.2 V, /CE1 ≤ 0.2 V, 0.5 7 CE2 ≥ VCC − 0.2 V 0.4 6 CE2 = VIL or /WE = VIL or /OE = VIH Operating supply current ICCA1 /CE1 = VIL, CE2 = VIH, Minimum cycle time, VCC ≤ 2.7 V II/O = 0 mA ICCA2 /CE1 = VIL, CE2 = VIH, II/O = 0 mA, Cycle time = ∞ ICCA3 VCC ≤ 2.7 V /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, Cycle time = 1 µs, II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V Standby supply current ISB /CE1 = VIH or CE2 = VIL or /LB = /UB = VIH ISB1 VCC ≤ 2.7 V /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V ISB2 VCC ≤ 2.7 V VCC ≤ 2.7 V CE2 ≤ 0.2 V VCC ≤ 2.7 V ISB3 High level output voltage VOH VCC ≤ 2.7 V IOH = –0.5 mA 2.4 VCC ≤ 2.7 V Low level output voltage VOL mA µA V 1.8 IOL = 1.0 mA 0.4 V Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of product classification. Data Sheet M14464EJ5V0DS 7 µPD444012A-X AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) ★ AC Test Conditions [ µPD444012A-B55X, µPD444012A-B70X, µPD444012A-B85X, µPD444012A-B10X ] Input Waveform (Rise and Fall Time ≤ 5 ns) 0.9 VCC VCC/2 Test points VCC/2 VCC/2 Test points VCC/2 0.1 VCC Output Waveform Output Load 1TTL + 50 pF [ µPD444012A-C70X, µPD444012A-C85X, µPD444012A-C10X, µPD444012A-C12X ] Input Waveform (Rise and Fall Time ≤ 5 ns) 0.9 VCC VCC/2 Test points VCC/2 VCC/2 Test points VCC/2 0.1 VCC Output Waveform Output Load 1TTL + 30 pF 8 Data Sheet M14464EJ5V0DS µPD444012A-X ★ Read Cycle (1/2) (B version) Parameter Symbol VCC ≥ 3.0 V VCC ≥ 2.7 V Unit Condition µPD444012A µPD444012A µPD444012A µPD444012A µPD444012A -B55X -B55X -B70X -B85X -B10X MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Read cycle time tRC Address access time tAA 50 50 55 55 70 70 85 85 100 100 ns ns /CE1 access time tCO1 50 55 70 85 100 ns CE2 access time tCO2 50 55 70 85 100 ns /OE to output valid tOE 30 30 35 40 50 ns /LB, /UB to output valid tBA 50 55 70 85 100 ns Output hold from address change tOH 10 10 10 10 10 ns /CE1 to output in low impedance tLZ1 10 10 10 10 10 ns CE2 to output in low impedance tLZ2 10 10 10 10 10 ns /OE to output in low impedance tOLZ 0 0 0 0 0 ns /LB, /UB to output in low impedance tBLZ 10 /CE1 to output in high impedance tHZ1 20 20 25 30 35 ns CE2 to output in high impedance tHZ2 20 20 25 30 35 ns /OE to output in high impedance tOHZ 20 20 25 30 35 ns /LB, /UB to output in high impedance tBHZ 20 20 25 30 35 ns 10 10 10 10 Note 1 Note 2 ns Notes 1. The output load is 1TTL + 50 pF. 2. The output load is 1TTL + 5 pF. Read Cycle (2/2) (C version) Parameter VCC ≥ 2.2 V Symbol Unit Condition µPD444012A µPD444012A µPD444012A µPD444012A -C70X -C85X -C10X -C12X MIN. MAX. 70 MIN. MAX. 85 MIN. MAX. 100 MIN. MAX. Read cycle time tRC Address access time tAA 70 85 100 120 120 ns ns /CE1 access time tCO1 70 85 100 120 ns CE2 access time tCO2 70 85 100 120 ns /OE to output valid tOE 35 40 50 60 ns /LB, /UB to output valid tBA 70 85 100 120 ns Output hold from address change tOH 10 10 10 10 ns /CE1 to output in low impedance tLZ1 10 10 10 10 ns CE2 to output in low impedance tLZ2 10 10 10 10 ns /OE to output in low impedance tOLZ 0 0 0 0 ns /LB, /UB to output in low impedance tBLZ 10 10 10 10 ns /CE1 to output in high impedance tHZ1 25 30 35 40 ns CE2 to output in high impedance tHZ2 25 30 35 40 ns /OE to output in high impedance tOHZ 25 30 35 40 ns /LB, /UB to output in high impedance tBHZ 25 30 35 40 ns Note 1 Note 2 Notes 1. The output load is 1TTL + 30 pF. 2. The output load is 1TTL + 5 pF. Data Sheet M14464EJ5V0DS 9 µPD444012A-X Read Cycle Timing Chart tRC Address (Input) tAA tOH /CE1 (Input) tHZ1 tCO1 tLZ1 CE2 (Input) tCO2 tHZ2 tLZ2 /OE (Input) tOE tOHZ tOLZ /LB, /UB (Input) tBA tBHZ tBLZ I/O (Output) Remark 10 High impedance In read cycle, /WE should be fixed to high level. Data Sheet M14464EJ5V0DS Data out µPD444012A-X ★ Write Cycle (1/2) (B version) Parameter Symbol VCC ≥ 3.0 V VCC ≥ 2.7 V Unit Condition µPD444012A µPD444012A µPD444012A µPD444012A µPD444012A -B55X MIN. -B55X MAX. MIN. -B70X MAX. MIN. -B85X MAX. MIN. -B10X MAX. MIN. MAX. Write cycle time tWC 50 55 70 85 100 ns /CE1 to end of write tCW1 45 50 55 70 80 ns CE2 to end of write tCW2 45 50 55 70 80 ns /LB, /UB to end of write tBW 45 50 55 70 80 ns Address valid to end of write tAW 45 50 55 70 80 ns Address setup time tAS 0 0 0 0 0 ns Write pulse width tWP 40 45 50 55 60 ns Write recovery time tWR 0 0 0 0 0 ns Data valid to end of write tDW 25 25 30 35 40 ns Data hold time tDH 0 0 0 0 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW 20 20 5 25 5 30 5 35 5 5 ns Note ns Note The output load is 1TTL + 5 pF. Write Cycle (2/2) (C version) Parameter VCC ≥ 2.2 V Symbol Unit Condition µPD444012A µPD444012A µPD444012A µPD444012A -C70X -C85X -C10X -C12X MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Write cycle time tWC 70 85 100 120 ns /CE1 to end of write tCW1 55 70 80 100 ns CE2 to end of write tCW2 55 70 80 100 ns /LB, /UB to end of write tBW 55 70 80 100 ns Address valid to end of write tAW 55 70 80 100 ns Address setup time tAS 0 0 0 0 ns Write pulse width tWP 50 55 60 85 ns Write recovery time tWR 0 0 0 0 ns Data valid to end of write tDW 30 35 40 60 ns Data hold time tDH 0 0 0 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW 25 5 30 5 35 5 40 5 ns Note ns Note The output load is 1TTL + 5 pF. Data Sheet M14464EJ5V0DS 11 µPD444012A-X Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tAS tWP tWR /WE (Input) tBW /LB, /UB (Input) tOW tWHZ I/O (Input / Output) Indefinite data out tDW High impedance tDH Data in High impedance Indefinite data out Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a high level CE2. 2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2 changes to high level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state. 3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. 12 Data Sheet M14464EJ5V0DS µPD444012A-X Write Cycle Timing Chart 2 (/CE1 Controlled) tWC Address (Input) tAS tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tWP tWR /WE (Input) tBW /LB, /UB (Input) tDW High impedance Data in I/O (Input) tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a high level CE2. Data Sheet M14464EJ5V0DS 13 µPD444012A-X Write Cycle Timing Chart 3 (CE2 Controlled) tWC Address (Input) tCW1 /CE1 (Input) tAS tCW2 CE2 (Input) tAW tWP tWR /WE (Input) tBW /LB, /UB (Input) tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a high level CE2. 14 Data Sheet M14464EJ5V0DS µPD444012A-X Write Cycle Timing Chart 4 (/LB, /UB Controlled) tWC Address (Input) tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tWP tWR /WE (Input) tAS tBW /LB, /UB (Input) tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a high level CE2. Data Sheet M14464EJ5V0DS 15 µPD444012A-X ★ Low VCC Data Retention Characteristics (TA = –25 to +85°°C) Parameter Symbol VCC ≥ 2.7 V VCC ≥ 2.2 V µPD444012A µPD444012A -B××X -C××X Test Condition MIN. TYP. MAX. MIN. TYP. Unit MAX. Data retention VCCDR1 /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V 1.0 3.6 1.0 3.6 supply voltage VCCDR2 CE2 ≤ 0.2 V 1.0 3.6 1.0 3.6 VCCDR3 /LB = /UB ≥ VCC − 0.2 V, 1.0 3.6 1.0 3.6 V /CE1 ≤ 0.2 V, CE2 ≥ VCC − 0.2 V Data retention ICCDR1 VCC = 1.5 V, /CE1 ≥ VCC − 0.2 V, 0.3 3.0 0.3 3.0 µA CE2 ≥ VCC − 0.2 V supply current ICCDR2 VCC = 1.5 V, CE2 ≤ 0.2 V 0.3 3.0 0.3 3.0 ICCDR3 VCC = 1.5 V, /LB = /UB ≥ VCC − 0.2 V, 0.3 3.0 0.3 3.0 /CE1 ≤ 0.2 V, CE2 ≥ VCC − 0.2 V Chip deselection tCDR 0 0 ns Note ns to data retention mode Operation tR tRC Note recovery time Note tRC : Read cycle time 16 Data Sheet M14464EJ5V0DS tRC µPD444012A-X Data Retention Timing Chart (1) /CE1 Controlled tCDR Data retention mode tR VCC VCC (MIN.) Note /CE1 VIH (MIN.) VCCDR (MIN.) /CE1 ≥ VCC – 0.2 V VIL (MAX.) GND ★ Note B version : 2.7 V, C version : 2.2 V Remark On the data retention mode by controlling /CE1, the input level of CE2 must be ≥ VCC − 0.2 V or ≤ 0.2 V. The other pins (Address, I/O, /WE, /OE, /LB, /UB) can be in high impedance state. (2) CE2 Controlled tCDR Data retention mode tR VCC VCC (MIN.) Note VIH (MIN.) VCCDR (MIN.) CE2 VIL (MAX.) CE2 ≤ 0.2 V GND ★ Note B version : 2.7 V, C version : 2.2 V Remark On the data retention mode by controlling CE2, The other pins (/CE1, Address, I/O, /WE, /OE, /LB, /UB) can be in high impedance state. Data Sheet M14464EJ5V0DS 17 µPD444012A-X (3) /LB, /UB Controlled tCDR Data retention mode tR VCC VCC (MIN.) Note /LB, /UB VIH (MIN.) VCCDR (MIN.) /LB, /UB ≥ VCC – 0.2 V VIL (MAX.) GND ★ Note B version : 2.7 V, C version : 2.2 V Remark On the data retention mode by controlling /LB and /UB, the input level of /CE1 and CE2 must be ≥ VCC − 0.2 V or ≤ 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state. 18 Data Sheet M14464EJ5V0DS µPD444012A-X Package Drawing 48-PIN PLASTIC TSOP(I) (12x18) 1 detail of lead end 48 F G R Q 24 L 25 S E P I A J C S D K N B M M S NOTES ITEM MILLIMETERS 1. Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. A 12.0±0.1 B 0.45 MAX. 2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.) C 0.5 (T.P.) D 0.22±0.05 E 0.1±0.05 F 1.2 MAX. G 1.0±0.05 I 16.4±0.1 J 0.8±0.2 K 0.145±0.05 L 0.5 M 0.10 N 0.10 P 18.0±0.2 Q 3° +5° −3° R S 0.25 0.60±0.15 S48GY-50-MJH1-1 Data Sheet M14464EJ5V0DS 19 µPD444012A-X Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD444012A-X. ★ Types of Surface Mount Device µPD444012AGY-BxxX-MJH: 48-pin PLASTIC TSOP (I) (12×18) (Normal bent) µPD444012AGY-CxxX-MJH: 48-pin PLASTIC TSOP (I) (12×18) (Normal bent) 20 Data Sheet M14464EJ5V0DS µPD444012A-X [ MEMO ] Data Sheet M14464EJ5V0DS 21 µPD444012A-X [ MEMO ] 22 Data Sheet M14464EJ5V0DS µPD444012A-X NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M14464EJ5V0DS 23 µPD444012A-X • The information in this document is current as of July, 2001. The information is subject to change without notice. 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