DATA SHEET MOS INTEGRATED CIRCUIT µPD4616112-X 16M-BIT CMOS MOBILE SPECIFIED RAM 1M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION Description The µPD4616112-X is a high speed, low power, 16,777,216 bits (1,048,576 words by 16 bits) CMOS mobile specified RAM featuring low power static RAM compatible function and pin configuration. The µPD4616112-X is fabricated with advanced CMOS technology using one-transistor memory cell. The µPD4616112-X is packed in 48-pin TAPE FBGA. Features • 1,048,576 words by 16 bits organization • Fast access time: 85, 95 ns (MAX.) • Byte data control: /LB (I/O0 - I/O7), /UB (I/O8 - I/O15) • Low voltage operation: VCC = 2.6 to 3.1 V • Operating ambient temperature: TA = –25 to +85 °C • Output Enable input for easy application • Chip Enable input: /CS pin • Standby Mode input: MODE pin • Standby Mode1: Normal standby (Memory cell data hold valid) • Standby Mode2: Memory cell data hold invalid Product name µPD4616112-BxxLX Access time Operating supply Operating ambient ns (MAX.) Voltage temperature At operating At standby °C mA (MAX.) µA (MAX.) –25 to +85 35 70 / 10 85, 95 2.6 to 3.1 Supply current The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M15794EJ2V0DS00 (2nd edition) Date Published January 2002 NS CP (K) Printed in Japan The mark ★ shows major revised points. © 2001 µPD4616112-X Ordering Information Part number µPD4616112F9-B85LX-BC2 Package 48-pin TAPE FBGA (8 x 6) µPD4616112F9-B95LX-BC2 Access time Operating Operating ns (MAX.) supply voltage temperature V °C 2.6 to 3.1 –25 to +85 85 95 Marking Image Part number Marking (XX) µPD4616112F9-B85LX-BC2 L1 µPD4616112F9-B95LX-BC2 L2 J MS16M0-XX Index mark 2 Lot number Data Sheet M15794EJ2V0DS Remark B version µPD4616112-X Pin Configuration /xxx indicates active low signal. 48-pin TAPE FBGA (8 x 6) Top View Bottom View A B C D E F G H 1 1 2 A /LB B I/O8 2 3 4 3 4 /OE A0 /UB A3 5 6 6 5 6 4 5 5 6 A1 A2 MODE A MODE A2 A4 /CS I/O0 B I/O0 /CS 3 2 4 1 3 2 1 A1 A0 /OE /LB A4 A3 /UB I/O8 C I/O9 I/O10 A5 A6 I/O1 I/O2 C I/O2 I/O1 A6 A5 I/O10 I/O9 D GND I/O11 A17 A7 I/O3 VCC D VCC I/O3 A7 A17 I/O11 GND E VCC I/O12 GND A16 I/O4 GND E GND I/O4 A16 GND I/O12 VCC F I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O6 I/O5 A15 A14 I/O13 I/O14 G I/O15 A19 A12 A13 /WE I/O7 G I/O7 /WE A13 A12 A19 I/O15 H A18 A8 A9 A10 A11 GND H GND A11 A10 A9 A8 A18 A0 - A19 : Address inputs /OE : Output enable I/O0 - I/O15 : Data inputs / outputs /LB, /UB : Byte data select /CS : Chip Select VCC : Power supply MODE : Standby mode GND : Ground /WE : Write enable Remark Refer to Package Drawing for the index mark. Data Sheet M15794EJ2V0DS 3 µPD4616112-X Block Diagram Standby mode control VCC Refresh control GND Memory cell array 16,777,216 bits Refresh counter A0 A19 Row decoder Address buffer I/O0 - I/O7 I/O8 - I/O15 Input data controller Sense amplifier / Switching circuit Column decoder Address buffer /CS MODE /LB /UB /WE /OE 4 Data Sheet M15794EJ2V0DS Output data controller µPD4616112-X Truth Table /CS MODE /OE /WE /LB /UB Mode H H × × × × Not selected (Standby Mode 1) I/O Supply current I/O0 - I/O7 I/O8 - I/O15 High impedance High impedance ISB1 H L × × × × Not selected (Standby Mode 2) High impedance High impedance ISB2 L H H H × × Output disable High impedance High impedance ICCA L H L L Word read DOUT DOUT L H Lower byte read DOUT High impedance H L Upper byte read High impedance DOUT H H Output disable High impedance High impedance × L L L Word write DIN DIN L H Lower byte write DIN High impedance H L Upper byte write High impedance DIN H H Write abort High impedance High impedance Caution MODE pin must be fixed to High except Standby Mode 2. Remark ×: VIH or VIL Initialization The µPD4616112-X is initialized in the power-on sequence according to the following. (1) To stabilize internal circuits, before turning on the power, a 200 µs or longer wait time must precede any signal toggling. (2) After the wait time, read operation must be performed at least 3 times. After that, it can be normal operation. Initialization Timing Chart VCC (MIN.) VCC Address (Input) MODE (Input) VIH (MIN.) tRC /CS (Input) tCP VIH (MIN.) Power On Wait Time Read Operation 3 times 200 µs Normal Operation Cautions 1. Following power application, make MODE and /CS high level during the wait time interval. 2. Following power application, make MODE high level during the wait time and three read operations. 3. The read operation must satisfy the specs described on page 10 (Read Cycle (B Version)). 4. The address is don’t care (VIH or VIL) during read operation. 5. Read operation must be executed with toggled the /CS pin. 6. To prevent bus contention, it is recommended to set /OE to high level. 7. Do not input data to the I/O pins if /OE is low level during a read operation. Data Sheet M15794EJ2V0DS 5 µPD4616112-X Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Symbol Condition Rating VCC –0.5 –0.5 Note Note Unit to +3.3 V to VCC + 0.4 (3.3 V MAX). V Input / Output voltage VT Operating ambient temperature TA –25 to +85 °C Storage temperature Tstg –55 to +125 °C Note –1.0 V (MIN.) (Pulse width: 30 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol µPD4616112-BxxLX Condition Unit MIN. MAX. Supply voltage VCC 2.6 3.1 V High level input voltage VIH 0.8 VCC VCC+0.3 V 0.2 VCC V +85 °C Low level input voltage VIL Operating ambient temperature TA –0.3 Note –25 Note –0.5 V (MIN.) (Pulse width: 30 ns) Capacitance (TA = 25°°C, f = 1 MHz) Parameter Symbol Test condition MIN. TYP. MAX. Unit Input capacitance CIN VIN = 0 V 8 pF Input / Output capacitance CI/O VI/O = 0 V 10 pF Remarks 1. VIN: Input voltage VI/O: Input / Output voltage 2. These parameters are not 100% tested. 6 Data Sheet M15794EJ2V0DS µPD4616112-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter Symbol µPD4616112-BxxLX Test condition MIN. TYP. Unit MAX. Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0 µA I/O leakage current ILO VI/O = 0 V to VCC, /CS = VIH or –1.0 +1.0 µA /WE = VIL or /OE = VIH Operating supply current ICCA /CS = VIL, Minimum cycle time, II/O = 0 mA 35 mA Standby supply current ISB1 /CS ≥ VCC − 0.2 V, MODE ≥ VCC − 0.2 V 70 µA ISB2 /CS ≥ VCC − 0.2 V, MODE ≤ 0.2 V 10 High level output voltage VOH IOH = –0.5 mA Low level output voltage VOL IOL = 1 mA 0.8 VCC V 0.2 VCC V Remarks 1. VIN: Input voltage VI/O: Input / Output voltage 2. These DC characteristics are in common regardless of product classifications. Data Sheet M15794EJ2V0DS 7 µPD4616112-X Standby Mode State Machine Power on /CS = VIH, MODE = VIH Wait 200 µ s Dummy read operation (3 times) Initial State /CS = VIL /CS = VIH, MODE = VIH MODE = VIH Active /CS = VIH, MODE = VIH /CS = VIH, MODE = VIL /CS = VIL, MODE = VIH Standby Mode1 /CS = VIH, MODE = VIL Standby Mode Characteristics 8 Standby Mode Memory Cell Data Hold Standby Supply Current (µA) Mode 1 Valid 70 (ISB1) Mode 2 Invalid 10 (ISB2) Data Sheet M15794EJ2V0DS Standby Mode2 µPD4616112-X AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions [ µPD4616112-B85LX, µPD4616112-B95LX ] Input Waveform (Rise and Fall Time ≤ 5 ns) Vcc 0.8 Vcc Vcc/2 Test points Vcc/2 0.2 Vcc GND 5ns Output Waveform Vcc/2 Test points Vcc/2 Output Load AC characteristics directed with the note should be measured with the output load shown in Figure 1. Figure 1 CL: 50 pF 5 pF (tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, tOW ) ZO = 50 Ω I/O (Output) 50 Ω CL VCC/2 Data Sheet M15794EJ2V0DS 9 µPD4616112-X Read Cycle (B version) Parameter Symbol µPD4616112-B85LX µPD4616112-B95LX MIN. MAX. MIN. MAX. Unit Note Read cycle time tRC 85 10,000 95 10,000 ns 1 Identical address read cycle time tRC1 85 10,000 95 10,000 ns 2 20 ns 3 Address skew time tSKEW 10 /CS pulse width tCP 10 10 ns Address access time tAA 85 95 ns /CS access time tACS 85 95 ns /OE to output valid tOE 35 40 ns /LB, /UB to output valid tBA 35 40 ns Output hold from address change tOH 10 10 ns /CS to output in low impedance tCLZ 10 10 ns /OE to output in low impedance tOLZ 5 5 ns /LB, /UB to output in low impedance tBLZ 5 5 ns /CS to output in high impedance tCHZ 25 25 ns /OE to output in high impedance tOHZ 25 25 ns /LB, /UB to output in high impedance tBHZ 25 25 ns 4 5 Notes 1. One read cycle (tRC) must satisfy the minimum value (tRC(MIN.)) and maximum value (tRC(MAX.) = 10 µs). tRC indicates the time from the /CS low level input point or address change start point, whichever is later, to the /CS high level input point or the next address change start point, whichever is earlier. As a result, there are the following four conditions for tRC. 1) Time from address change start point to /CS high level input point (address access) 2) Time from address change start point to next address change start point (address access) 3) Time from /CS low level input point to next address change start point (/CS access) 4) Time from /CS low level input point to /CS high level input point (/CS access) 2. The identical address read cycle time (tRC1) is the cycle time of one read operation when performing continuous read operations toggling /OE , /LB, and /UB with the address fixed and /CS low level. Perform settings so that the sum (tRC) of the identical address read cycle times (tRC1) is 10 µs or less. 3. tSKEW indicates the following three types of time depending on the condition. 1) When switching /CS from high level to low level, tSKEW is the time from the /CS low level input point until the next address is determined. 2) When switching /CS from low level to high level, tSKEW is the time from the address change start point to the /CS high level input point. 3) When /CS is fixed to low level, tSKEW is the time from the address change start point until the next address is determined. Since specs are defined for tSKEW only when /CS is active, tSKEW is not subject to limitations when /CS is switched from high level to low level following address determination, or when the address is changed after /CS is switched from low level to high level. 4. Regarding tAA and tACS, only tAA is satisfied during address access (refer to 1) and 2) of Note 1), and only tACS is satisfied during /CS access (refer to 3) of Note 1). 5. Regarding tBA and tOE, only tBA is satisfied if /OE becomes active later than /UB and /LB, and only tOE is satisfied if /UB and /LB become active before /OE. 10 Data Sheet M15794EJ2V0DS µPD4616112-X Read Cycle Timing Chart 1 tSKEW tSKEW Address (Input) tCP tRC tCP /CS (Input) tACS tCHZ tCLZ /OE (Input) tOE tOHZ tOLZ /LB, /UB (Input) tBA tBHZ tBLZ High impedance tOH Data out I/O (Output) tRC tSKEW tSKEW Address (Input) tCP tCP tACS /CS (Input) tCHZ tCLZ /OE (Input) tOE tOHZ tOLZ /LB, /UB (Input) tBA tBHZ tBLZ High impedance Data out I/O (Output) Caution If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle time (tRC), none of the data can be guaranteed. Remark In read cycle, /WE should be fixed to High. Data Sheet M15794EJ2V0DS 11 12 Read Cycle Timing Chart 2 tRC tRC tSKEW tSKEW tSKEW tSKEW Address (Input) tCP tACS tRC tRC tCP tRC tAA Data Sheet M15794EJ2V0DS tAA /CS (Input) tCLZ tCHZ tACS tCHZ tCLZ /OE (Input) tACS tCHZ tCLZ tOE tOLZ tOHZ /LB, /UB (Input) tBA tBHZ tOH tBLZ tBA tBHZ tBLZ High impedance I/O (Output) Data out Data out tBA tBHZ tOH tOH tBLZ Data out Data out Data out time (tRC), none of the data can be guaranteed. Remark In read cycle, /WE should be fixed to High. µPD4616112-X Caution If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle Read Cycle Timing Chart 3 tRC tRC tSKEW tRC tSKEW tRC tSKEW tSKEW tRC tSKEW Address (Input) tACS tAA tAA /CS (Input) tCLZ Data Sheet M15794EJ2V0DS tOHZ tOH tBLZ Hi-Z Data out /UB (Input) tBA High impedance tBHZ tBLZ tOH Data out tBA tBHZ tOH tBLZ Data out tBHZ tBLZ tOH Data out Caution If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle time (tRC), none of the data can be guaranteed. 13 Remark In read cycle, /WE should be fixed to High. µPD4616112-X I/O8~15 (Output) tOLZ tBA tBA tBHZ I/O0~7 (Output) tOHZ tOHZ tOLZ tOLZ /LB (Input) tOE tOE tOE /OE (Input) µPD4616112-X Read Cycle Timing Chart 4 tRC tSKEW tSKEW Address (Input) tRC1 Note tRC1 Note tACS /CS (Input) tOE tOE tOLZ /OE (Input) tOLZ tOHZ tBA tBLZ tBA tBLZ tOHZ /LB, /UB (Input) tBHZ I/O (Output) Data out High impedance tBHZ Data out High impedance Caution If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle time (tRC), none of the data can be guaranteed. Note To perform a continuous read toggling /OE, /UB, and /LB with /CS low level at an identical address, make settings so that the sum (tRC) of the identical address read cycle times (tRC1) is 10 µs or less. Remark In read cycle, /WE should be fixed to High. 14 Data Sheet M15794EJ2V0DS µPD4616112-X Write Cycle (B version) Parameter Symbol µPD4616112-B85LX µPD4616112-B95LX MIN. MAX. MIN. MAX. Unit Note Write cycle time tWC 85 10,000 95 10,000 ns 1 Identical address write cycle time tWC1 85 10,000 95 10,000 ns 2 Address skew time tSKEW 20 ns 3 /CS to end of write tCW 40 50 ns 4 /LB, /UB to end of write tBW 30 35 ns Address valid to end of write tAW 35 45 ns Write pulse width tWP 30 35 ns Write recovery time tWR 20 20 ns /CS pulse width tCP 10 10 ns Address setup time tAS 0 0 ns Byte write hold time tBWH 20 20 ns Data valid to end of write tDW 20 25 ns Data hold time tDH 0 0 ns /OE to output in low impedance tOLZ 5 5 ns /WE to output in high impedance tWHZ 25 25 ns /OE to output in high impedance tOHZ 25 25 ns Output active from end of write tOW 10 5 5 5 ns Notes 1. One write cycle (tWC) must satisfy the minimum value (tWC(MIN.)) and the maximum value (tWC(MAX.) = 10 µs). tWC indicates the time from the /CS low level input point or address change start point, whichever is after, to the /CS high level input point or the next address change start point, whichever is earlier. As a result, there are the following four conditions for tWC. 1) Time from address change start point to /CS high level input point 2) Time from address change start point to next address change start point 3) Time from /CS low level input point to next address change start point 4) Time from /CS low level input point to /CS high level input point 2. The identical address read cycle time (tWC1) is the cycle time of one write cycle when performing continuous write operations with the address fixed and /CS low level, changing /LB and /UB at the same time, and toggling /WE, as well as when performing a continuous write toggling /LB and /UB. Make settings so that the sum (tWC) of the identical address write cycle times (tWC1) is 10 µs or less. 3. tSKEW indicates the following three types of time depending on the condition. 1) When switching /CS from high level to low level, tSKEW is the time from the /CS low level input point until the next address is determined. 2) When switching /CS from low level to high level, tSKEW is the time from the address change start point to the /CS high level input point. 3) When /CS is fixed to low level, tSKEW is the time from the address change start point until the next address is determined. Since specs are defined for tSKEW only when /CS is active, tSKEW is not subject to limitations when /CS is switched from high level to low level following address determination, or when the address is changed after /CS is switched from low level to high level. Data Sheet M15794EJ2V0DS 15 µPD4616112-X 4. Definition of write start and write end /CS /WE /LB, /UB Status Write start pattern 1 H to L L L If /WE, /LB, /UB are low level, time when /CS changes from high level to low level Write start pattern 2 L H to L L If /CS, /LB, /UB are low level, time when /WE changes from high level to low level Write start pattern 3 L L H to L Write end pattern 1 L L to H L If /CS, /WE, /LB, /UB are low level, time when /WE changes from low level to high level Write end pattern 2 L L L to H When /CS, /WE, /LB, /UB are low level, time when /LB or /UB changes from low level to high level If /CS, /WE are low level, time when /LB or /UB changes from high level to low level 5. Definition of write end recovery time (tWR) 1) Time from write end to address change start point, or from write end to /CS high level input point 2) When /CS, /LB, /UB are low level and continuously written to the identical address, time from /WE high level input point to /WE low level input point 3) When /CS, /WE are low level and continuously written to the identical address, time from /LB or /UB high level input point, whichever is later, to /LB or /UB low level input point, whichever is earlier. 4) When /CS is low level and continuously written to the identical address, time from write end to point at which /WE , /LB, or /UB starts to change from high level to low level, whichever is earliest. 16 Data Sheet M15794EJ2V0DS µPD4616112-X Write Cycle Timing Chart 1 tWC tWC tSKEW tSKEW Address (Input) tCW tCW tCP /CS (Input) tWP tAS tWR tWP tWR /WE (Input) tAS tBW tBW /LB, /UB (Input) tDW I/O (Input) tDW tDH High impedance tDH High impedance Data in tSKEW Data in tSKEW tWC tSKEW tWC Address (Input) tCW tCP tCW /CS (Input) tWP tWP tWR tWR /WE (Input) tBW tBW /LB, /UB (Input) tDW I/O (Input) High impedance tDW tDH Data in High impedance tDH Data in Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (tWC), none of the data can be guaranteed. Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB. Data Sheet M15794EJ2V0DS 17 µPD4616112-X Write Cycle Timing Chart 2 (/WE Controlled) tWC tWC tSKEW tWC tSKEW tSKEW tSKEW tSKEW Address (Input) tCP tAW tAW tCW /CS (Input) tAS tAS /WE (Input) tWR tWP tAS tAW tWR tWP tOW tWP tWR tWHZ /OE (Input) tDW I/O (Input / Output) High impedance tDH tOLZ tOHZ tDW Indefinite data out Data in High impedance tDH tDW Data in Data in High impedance High impedance tDH High impedance tWC tSKEW tSKEW Address (Input) Note Note tWC1 tWC1 /CS (Input) tAS tWP tWR tWP tWR /WE (Input) tBW /LB, /UB (Input) tDW I/O (Input) tDH tDW Data in High impedance tDH Data in High impedance High impedance Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (tWC), none of the data can be guaranteed. Note If /LB and /UB are changed at the same time with /CS low level and a continuous write operation toggling /WE is performed, make settings so that the sum (tWC) of the identical address write cycle time (tWC1) is 10 µs or less. Remarks 1. Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB. 2. When /WE is at Low, the I/O pins are always high impedance. When /WE is at High, read operation is executed. Therefore /OE should be at High to make the I/O pins high impedance. 18 Data Sheet M15794EJ2V0DS µPD4616112-X Write Cycle Timing Chart 3 (/CS Controlled) Address (Input) tWC tWC /CS (Input) tAS tWR tCW tAS tWR tCW /WE (Input) /LB, /UB (Input) tDW I/O (Input) tDH Data in High impedance tDW tDH Data in High impedance High impedance Address (Input) tWC tWC /CS (Input) tAS tWR tCW tAS tWR tCW /WE (Input) /LB, /UB (Input) tDW I/O (Input) tDH tDW Data in High impedance tDH Data in High impedance High impedance Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (tWC), none of the data can be guaranteed. Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB. Data Sheet M15794EJ2V0DS 19 µPD4616112-X Write Cycle Timing Chart 4 (/LB, /UB Controlled 1) tWC tWC tSKEW tSKEW Address (Input) tCW tAW /CS (Input) tWP /WE (Input) tAS tBW tWR tAS tBW tWR /LB, /UB (Input) tDW I/O (Input) tDW tDH High impedance tDH High impedance Data in Data in tWC tSKEW tWC tSKEW Address (Input) tAW tCW /CS (Input) tWP /WE (Input) tAS tBW tWR tAS tBW tWR /LB, /UB (Input) tDW I/O (Input) tDW tDH High impedance tDH High impedance Data in Data in Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (tWC), none of the data can be guaranteed. Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB. 20 Data Sheet M15794EJ2V0DS µPD4616112-X Write Cycle Timing Chart 5 (/LB, /UB Controlled 2) tWC tSKEW tSKEW Address (Input) tWC1 Note tWC1 Note /CS (Input) tWP /WE (Input) tAS tBW tWR tWR tBW /LB, /UB (Input) tDW I/O (Input) High impedance tDH Data in tDW High impedance tDH Data in High impedance Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (tWC), none of the data can be guaranteed. Note If /LB and /UB are changed at the same time with /CS low level and a continuous write operation toggling /WE is performed, make settings so that the sum (tWC) of the identical address write cycle time (tWC1) is 10 µs or less. Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB. Data Sheet M15794EJ2V0DS 21 µPD4616112-X Write Cycle Timing Chart 6 (/LB, /UB Independent Controlled 1) tWC Address (Input) tWC1 Note tWC1 Note /CS (Input) tCW tWP /WE (Input) /LB (Input) tAS tBW tWR tWR tBW /UB (Input) tDW I/O0 - 7 (Input) tDH Data in High impedance High impedance tDW I/O8 - 15 (Input) tDH Data in High impedance High impedance Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (tWC), none of the data can be guaranteed. Note If /LB and /UB are changed at the same time with /CS low level and a continuous write operation toggling /WE is performed, make settings so that the sum (tWC) of the identical address write cycle time (tWC1) is 10 µs or less. Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB. 22 Data Sheet M15794EJ2V0DS µPD4616112-X Write Cycle Timing Chart 7 (/LB, /UB Independent Controlled 2) Address (Input) tWC /CS (Input) tCW tCW tWP tWP /WE (Input) tBW tWR /LB (Input) tAS tBWH tWR tBW /UB (Input) tAS tDW tDH Data in I/O0 - 7 (Input) High impedance High impedance tDW I/O8 - 15 (Input) tDH Data in High impedance High impedance Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (tWC), none of the data can be guaranteed. Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB. Data Sheet M15794EJ2V0DS 23 µPD4616112-X Read Write Cycle (B version) Parameter Symbol MIN. MAX. Unit Note 10,000 ns 1, 2 Read write cycle time tRWC Byte write setup time tBWS 20 ns Byte read setup time tBRS 20 ns Notes 1. Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical address write cycle time (tWC1) is 10 µs or less when a write is performed at the identical address using /UB following a read using /LB with /CS low level, or when a write is performed using /LB following a read using /UB. 2. Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical address write cycle time (tWC1) is 10 µs or less when a read is performed at the identical address using /UB following a write using /LB with /CS low level, or when a read is performed using /LB following a write using /UB. 24 Data Sheet M15794EJ2V0DS µPD4616112-X Read Write Cycle Timing Chart 1 (/LB, /UB Independent Controlled 1) tRWC Address (Input) tRC1 Note tWC1 Note tAA /CS (Input) tACS tWP /WE (Input) tBWS /LB (Input) tWR tBW /UB (Input) tCLZ tBLZ I/O0 - 7 (Output) tBHZ Data out High impedance High impedance tDW I/O8 - 15 (Input) tDH Data in High impedance High impedance Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the identical address read cycle time (tRC1) and the identical address write cycle time (tWC1), none of the data can be guaranteed. Note Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical address write cycle time (tWC1) is 10 µs or less when a write is performed at the identical address using /UB following a read using /LB with /CS low level, or when a write is performed using /LB following a read using /UB. Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB. Data Sheet M15794EJ2V0DS 25 µPD4616112-X Read Write Cycle Timing Chart 2 (/LB, /UB Independent Controlled 2) tRWC Address (Input) tWC1 Note tRC1 Note tCW /CS (Input) tWR tWP /WE (Input) tBW /LB (Input) tAS tBRS /UB (Input) tDW I/O0 - 7 (Input) tDH Data in High impedance High impedance tBHZ tBA tBLZ I/O8 - 15 (Output) Data out High impedance High impedance Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the identical address read cycle time (tRC1) and the identical address write cycle time (tWC1), none of the data can be guaranteed. Note Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical address write cycle time (tWC1) is 10 µs or less when a write is performed at the identical address using /UB following a read using /LB with /CS low level, or when a write is performed using /LB following a read using /UB. Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB. 26 Data Sheet M15794EJ2V0DS µPD4616112-X Read Write Cycle Timing Chart 3 (/LB, /UB Independent Controlled 3) tRWC Address (Input) tWC1Note Note tRC1 tCW /CS (Input) tWR tWP /WE (Input) tAS tBW /LB (Input) /UB (Input) tDW I/O0 - 7 (Input) tDH Data in High impedance High impedance tBHZ tBA tBLZ I/O8 - 15 (Output) Data out High impedance High impedance Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the identical address read cycle time (tRC1) and the identical address write cycle time (tWC1), none of the data can be guaranteed. Note Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical address write cycle time (tWC1) is 10 µs or less when a write is performed at the identical address using /UB following a read using /LB with /CS low level, or when a write is performed using /LB following a read using /UB. Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB. Data Sheet M15794EJ2V0DS 27 µPD4616112-X Standby Mode 2 entry and recovery Timing Chart Address (Input) MODE (Input) tRC /CS (Input) tCP tCM Standby Wait Time 200 µs Read Operation 3 times Mode 2 (Data invalid) Parameter /CS High to MODE Low Symbol MIN. tCM 0 MAX. Normal Operation Unit Note ns Cautions 1. Make MODE and /CS high level during the wait time. 2. Make MODE high level during the wait time and three read operations. 3. The read operation must satisfy the specs described on page 10 (Read Cycle (B Version)). 4. The read operation address can be either VIH or VIL. 5. Perform reading by toggling /CS. 6. To prevent bus contention, it is recommended to set /OE to high level. 7. Do not input data to the I/O pins if /OE is low level during a read operation. 28 Data Sheet M15794EJ2V0DS µPD4616112-X Package Drawing 48-PIN TAPE FBGA (8x6) ZE E w ZD S B B 6 5 4 3 2 1 A D H G F E D C B A INDEX MARK w S A INDEX MARK A A2 y1 S S y e S φb φx A1 M S AB ITEM D MILLIMETERS 6.0±0.1 E 8.0±0.1 w e 0.2 0.75 A A1 A2 0.94±0.10 0.24±0.05 0.70 b x 0.40±0.05 0.08 y y1 0.1 0.2 ZD 1.125 ZE 1.375 P48F9-75-BC2 Data Sheet M15794EJ2V0DS 29 µPD4616112-X Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD4616112-X. Type of Surface Mount Device µPD4616112F9-BxxLX-BC2: 48-pin TAPE FBGA (8 x 6) 30 Data Sheet M15794EJ2V0DS µPD4616112-X NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M15794EJ2V0DS 31 µPD4616112-X • The information in this document is current as of January, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4