ETC UPD98412N7-H6

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD98412
1.5G ATM SWITCH LSI
DESCRIPTION
The µPD98412 (NEASCOT-X15) is an LSI integrating ATM switch functions on a single chip. It has UTOPIA
Level2 interfaces and can switch 30 × 30 circuits by connecting multiple PHY devices. This LSI employs a shared
buffer non-blocking type switch and realizes a switch capacity of 1.5G bps by using an externally connected SRAM
for buffering cells.
For a detailed description of the functions of the controller, refer to the following User’s Manual:
µPD98412 User’s Manual: S14169E
FEATURES
• Conforms to ATM FORUM UNI Version 3.1 & Traffic Management 4.0
• Realizes all switch functions with a single chip
• Non-blocking type with switch capacity of 1.5G bps
• UTOPIA Level2 interface allowing you to select bit widths
(4 ports × 8 bits, 2 ports × 8 bits + 1 port × 16 bits, 2 ports × 16 bits)
• Various polling modes for UTOPIA Level2 interface
• Can switch 30 logical ports
• Multi-speed (622M bps, 155M bps, 52M bps, 25M bps, etc.)
• Microprocessor connecting port can be set for signaling processing and OAM cell processing
• Supports 16K/32K/64K uni-cast VP/VC and 1K/2K/4K multi-cast VP/VC
• Shared buffer architecture using standard SRAM
• Cell buffer capacity: 12.8K/25.6K/51.2K cells
• Supports four QOS classes (CBR, VBR, ABR, UBR)
• ABR traffic control (binary mode)
• Supports EPD (Early Packet Discard) and PPD (Partial Packet Discard)
• +3.3-V single power source (directly connectable with +5-V TTL level signals)
• Test function: Supports JTAG (IEEE 1149.1)
Remark Active low pins are indicated as ×××_B (symbol_B after pin names) in this document.
ORDERING INFORMATION
Part Number
Package
µPD98412N7-H6
576-pin tape BGA (40 × 40)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14237EJ2V0DS00 (2nd edition)
Date Published April 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1999
µPD98412
EXAMPLE OF SYSTEM CONFIGURATION (APPLICATION)
The µPD98412 can be used to realize an ATM layer cell switching function by connecting it to a microprocessor,
SRAM for use as a cell buffer, and a header translation table (HTT)/SRAM for storing control information as shown
below.
Microprocesser
PHY #0
#1
8-bit
33 MHz
PHY #29
µ PD98412
NEASCOT/X15
#3
2
#0 PHY
#1
8-bit
33 MHz
#3
32-bit
+parity
HTT &
control
memory
Logical outport
#2
#2
UTOPIA level 2
PHY #28
Physical
outport
#0
UTOPIA level 2
Logical inport
Physical
inport
#0
16-bit
50 MHz
UTOPIA level 2
UTOPIA level 2
16-bit
50 MHz
#28 PHY
#29 PHY
92-bit
Cell buffer (Memory )
Data Sheet S14237EJ2V0DS00
HTT: Header Translation Table
µPD98412
BLOCK DIAGRAM
UTOPIA
receive
port 2
UTOPIA
receive
port 3
Input
header
selector
Output payload
selector
Cell buffer interface
Output
header
selector
Queue
controller
Microprocessor
interface
HTT &
Control memory
interface
Microprocessor
HTT & Control Memory
Output
arbiter
UTOPIA
transmit
port 0
Output interface
UTOPIA
receive
port 1
Input port interface
UTOPIA
receive
port 0
Test
interface
Input payload
separator
Cell Buffer Memory
UTOPIA
transmit
port 1
UTOPIA
transmit
port 2
UTOPIA
transmit
port 3
TEST
Data Sheet S14237EJ2V0DS00
3
µPD98412
PIN CONFIGURATION
(1) 8-bit 12-PHY polling mode/15-PHY polling mode
JTAG
JCK
IOCS_B
32
AD [31:0]
UWE_B
R/W_B
MCS_B
HTOE_B
HTWE_B
2 18
HTD [31:0]
HTP [3:0]
JDI
JDO
RESET_B
SWCLK
32 4
Microprocessor Interface
HTCS_B [1:0]
HTA [17:0]
Control
HTT &
Control Memory
Interface
RDY_B
INT
HCLK
JMS
JRST_B
8
RXDATA3 [7:0]
UCLK3
RXENB3_B
RXSOC3
4
8
8
4
UTOPIA
Interface 1
4
8
TXSOC2
TXCLAV2
TXADDR2 [3:0]
RXCLAV3
RXADDR3 [3:0]
RXADDR2 [3:0]
RXCLAV2
TXADDR3 [3:0]
TXCLAV3
TXSOC3
TXENB3_B
TXDATA3 [7:0]
NEASCOT-X15
µ PD98412
RXDATA1 [7:0]
UCLK1
RXENB1_B
RXSOC1
TXDATA0 [7:0]
TXENB0_B
TXSOC0
TXCLAV0
TXADDR0 [3:0]
RXCLAV1
RXADDR1 [3:0]
RXADDR0 [3:0]
RXCLAV0
TXADDR1 [3:0]
TXCLAV1
TXSOC1
TXENB1_B
TXDATA1 [7:0]
2
18 92
Cell Buffer
Interface
4
Data Sheet S14237EJ2V0DS00
4
4
UTOPIA
Interface 2
RXSOC2
RXENB2_B
UCLK2
RXDATA2 [7:0]
CBOE_B
CBA [17:0]
CBD [91:0]
UTOPIA
Interface 3
8
TXENB2_B
CBCS_B [1:0]
CBWE_B
4
TXDATA2 [7:0]
8
8
4
4
RXSOC0
RXENB0_B
UCLK0
RXDATA0 [7:0]
8
UTOPIA
Interface 0
µPD98412
(2) 16-bit multiplexed status polling mode
JTAG
JCK
IOCS_B
32
AD [31:0]
UWE_B
R/W_B
MCS_B
HTOE_B
HTWE_B
2 18
HTD [31:0]
HTP [3:0]
JDI
JDO
RESET_B
SWCLK
32 4
Microprocessor Interface
HTCS_B [1:0]
HTA [17:0]
Control
HTT &
Control Memory
Interface
RDY_B
INT
HCLK
JMS
JRST_B
NEASCOT-X15
µ PD98412
UTOPIA
Interface 1
5
16
TXDATA0 [15:0]
TXENB0_B
TXSOC0
TXCLAV0
TXADDR0 [4:0]
RXCLAV1
RXADDR1 [4:0]
RXADDR0 [4:0]
RXCLAV0
TXADDR1 [4:0]
TXCLAV1
TXSOC1
TXENB1_B
TXDATA1 [15:0]
2
CBOE_B
CBA [17:0]
CBD [91:0]
5
RXDATA1 [15:0]
UCLK1
RXENB1_B
RXSOC1
CBCS_B [1:0]
CBWE_B
16
16
5
5
UTOPIA
Interface 0
RXSOC0
RXENB0_B
UCLK0
RXDATA0 [15:0]
16
18 92
Cell Buffer
Interface
Data Sheet S14237EJ2V0DS00
5
µPD98412
(3) 16-bit 2-group weighted polling mode
TXDATA0 [15:0]
Group B
TXCLAV0B
TXADDR0B [3:0]
NEASCOT-X15
µ PD98412
TXADDR1A [3:0]
RXADDR0A [3:0]
RXCLAV0A
4
RXENB0A_B
TXCLAV1A
RXSOC0
TXENB1A_B
16
4
Group A
TXENB0B_B
UCLK0
TXSOC1
TXDATA1 [15:0]
RXDATA0 [15:0]
TXADDR1B [3:0]
TXCLAV1B
RXADDR0B [3:0]
RXCLAV0B
2
CBOE_B
CBA [17:0]
CBD [91:0]
RXENB0B_B
CBCS_B [1:0]
CBWE_B
TXENB1B_B
18 92
Cell Buffer
Interface
6
4
Group A
Group B
4
Group A
UTOPIA Interace 1
TXSOC0
RXSOC1
RXENB1B_B
16
Data Sheet S14237EJ2V0DS00
16
4
UTOPIA Interace 0
RXDATA1 [15:0]
RXCLAV1B
RXADDR1B [3:0]
4
TXENB0A_B
UCLK1
4
IOCS_B
TXCLAV0A
TXADDR0A [3:0]
Group B
Group A
RXCLAV1A
RXADDR1A [3:0]
RXENB1A_B
16
R/W_B
MCS_B
INT
HCLK
JMS
JRST_B
4
RDY_B
Group B
JCK
32
AD [31:0]
UWE_B
HTOE_B
HTWE_B
JDO
JTAG
2 18
HTD [31:0]
HTP [3:0]
JDI
RESET_B
SWCLK
32 4
Microprocessor Interface
HTCS_B [1:0]
HTA [17:0]
Control
HTT &
Control Memory
Interface
µPD98412
(4) 16-bit 1-group weighted polling mode
JTAG
JCK
IOCS_B
32
AD [31:0]
UWE_B
R/W_B
MCS_B
HTOE_B
HTWE_B
2 18
HTD [31:0]
HTP [3:0]
JDI
JDO
RESET_B
SWCLK
32 4
Microprocessor Interface
HTCS_B [1:0]
HTA [17:0]
Control
HTT &
Control Memory
Interface
RDY_B
INT
HCLK
JMS
JRST_B
NEASCOT-X15
µ PD98412
UTOPIA
Interface 1
5
16
TXDATA0 [15:0]
TXENB0_B
TXSOC0
TXCLAV0 [3:0]
TXADDR0 [4:0]
RXCLAV1 [3:0]
RXADDR1 [4:0]
RXADDR0 [4:0]
RXCLAV0 [3:0]
TXADDR1 [4:0]
TXCLAV1 [3:0]
TXSOC1
TXENB1_B
TXDATA1 [15:0]
2
CBOE_B
CBA [17:0]
CBD [91:0]
5
RXDATA1 [15:0]
UCLK1
RXENB1_B
RXSOC1
CBCS_B [1:0]
CBWE_B
16
16
5
5
UTOPIA
Interface 0
RXSOC0
RXENB0_B
UCLK0
RXDATA0 [15:0]
16
18 92
Cell Buffer
Interface
Data Sheet S14237EJ2V0DS00
7
µPD98412
PIN CONFIGURATION (BOTTOM VIEW)
• 576-pin tape BGA (40 × 40)
µPD98412N7-H6
59
88
171
29
198
275
300
371
28
27
394
459
26
480
539
30
25
558
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
09
08
07
576
520
06
501 500
438
05
417 416
348
04
325 324
03
225 224
250
144
117 116
30
AK AJ AH AG AF AE AD AC AB AA
1
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
Note
Index area
Note The index area is shown in Top View.
8
Data Sheet S14237EJ2V0DS00
02
01
µPD98412
PIN NAME
1.
Power
4.
JTAG
VDD
: Supply Voltage
JDI
: JTAG Data Input
GND
: Ground
JDO
: JTAG Data Output
JCK
: JTAG Data Clock
JMS
: JTAG Mode Select
JRST_B
: JTAG Reset
2.
Memory Interface
HTA17 - HTA0
: HTT Memory Address
HTD31 - HTD0
: HTT Memory Data Bus
HTP3 - HTP0
: HTT Memory Data Bus Parity
5.
Other
HTCS1_B, HTCS0_B : HTT Memory Chip Select
SWCLK
: System Clock
HTWE_B
: HTT Memory Write Enable
RESET_B
: Hardware Reset
HTOE_B
: HTT Memory Output Enable
IC
: Internal Connected
CBA17 - CBA0
: Cell Buffer Memory Address
CG
: Connect Ground
CBD91 - CBD0
: Cell Buffer Memory Data Bus
PU
: Pull-up
CBCS1_B, CBCS0_B: Cell Buffer Memory Chip Select
CBWE_B
: Cell Buffer Memory Write Enable
CBOE_B
: Cell Buffer Memory Output Enable
3.
CPU Interface
IOCS_B
: I/O Chip Select
MCS_B
: Memory Chip Select
RDY_B
: I/O Ready, Memory Ready
INT
: Interrupt Request
HCLK
: Host Clock
AD31 - AD00 : Address and Data
R/W_B
: Read/Write
UWE_B
: Upper Word Enable
Data Sheet S14237EJ2V0DS00
9
µPD98412
6.
UTOPIA
(1) 8-bit 12-PHY Polling Mode/15-PHY Polling Mode
UCLK0
: UTOPIA Clock
RXADDR33-RXADDR30
RXADDR03-RXADDR00
: Receive Address
: Receive Address
RXDATA307-RXDATA300 : Receive Data Bus
RXDATA007-RXDATA000 : Receive Data Bus
RXSOC3
: Receive Start of Cell
RXSOC0
: Receive Start of Cell
RXENB3_B
: Receive Enable Data
RXENB0_B
: Receive Enable Data
RXCLAV3
: Receive Cell Buffer
TXADDR33-TXADDR30
: Transmit Address
Transfers
RXCLAV0
: Receive Cell Buffer
Available
TXADDR03-TXADDR00
Transfers
: Transmit Address
Available
TXDATA307-TXDATA300 : Transmit Data Bus
TXDATA007-TXDATA000 : Transmit Data Bus
TXSOC3
: Transmit Start of Cell
TXSOC0
: Transmit Start of Cell
TXENB3_B
: Transmit Enable Data
TXENB0_B
: Transmit Enable Data
TXCLAV0
: Transmit Cell Buffer
Transfers
Transfers
TXCLAV3
: Transmit Cell Buffer
Available
Available
UCLK1
: UTOPIA Clock
RXADDR13-RXADDR10
: Receive Address
(2) 16-bit Multiplexed Status Polling Mode
UCLK0
: UTOPIA Clock
RXDATA107-RXDATA100 : Receive Data Bus
RXADDR04-RXADDR00
: Receive Address
RXSOC1
: Receive Start of Cell
RXDATA015-RXDATA000 : Receive Data Bus
RXENB1_B
: Receive Enable Data
RXSOC0
: Receive Start of Cell
RXENB0_B
: Receive Enable Data
Transfers
RXCLAV1
: Receive Cell Buffer
Available
TXADDR13-TXADDR10
Transfers
RXCLAV0[3]-RXCLAV0[0] : Receive Cell Buffer
: Transmit Address
Available
TXDATA107-TXDATA100 : Transmit Data Bus
TXADDR04-TXADDR00
TXSOC1
: Transmit Start of Cell
TXDATA015-TXDATA000 : Transmit Data Bus
TXENB1_B
: Transmit Enable Data
TXSOC0
: Transmit Start of Cell
TXENB0_B
: Transmit Enable Data
Transfers
TXCLAV1
: Transmit Cell Buffer
Available
: Transmit Address
Transfers
TXCLAV0[3]-TXCLAV0[0] : Transmit Cell Buffer
UCLK2
: UTOPIA Clock
RXADDR23-RXADDR20
: Receive Address
Available
UCLK1
: UTOPIA Clock
RXDATA207-RXDATA200 : Receive Data Bus
RXADDR14-RXADDR10
: Receive Address
RXSOC2
: Receive Start of Cell
RXDATA115-RXDATA100 : Receive Data Bus
RXENB2_B
: Receive Enable Data
RXSOC1
: Receive Start of Cell
RXENB1_B
: Receive Enable Data
RXCLAV2
: Receive Cell Buffer
TXADDR23-TXADDR20
: Transmit Address
Transfers
Available
Transfers
RXCLAV1[3]-RXCLAV1[0] : Receive Cell Buffer
Available
TXDATA207-TXDATA200 : Transmit Data Bus
TXADDR14-TXADDR10
TXSOC2
: Transmit Start of Cell
TXDATA115-TXDATA100 : Transmit Data Bus
TXENB2_B
: Transmit Enable Data
TXSOC1
: Transmit Start of Cell
TXENB1_B
: Transmit Enable Data
Transfers
TXCLAV2
: Transmit Cell Buffer
TXCLAV1[3]-TXCLAV1[0] : Transmit Cell Buffer
Available
UCLK3
10
: Transmit Address
Available
: UTOPIA Clock
Data Sheet S14237EJ2V0DS00
µPD98412
(3) 16-bit 2-Group Weighted Polling Mode
UCLK0
(4) 16-bit 1-Group Weighted Polling Mode
: UTOPIA Clock
UCLK0
: UTOPIA Clock
RXADDR0A3-RXADDR0A0 : Receive Address
RXADDR04-RXADDR00
: Receive Address
RXADDR0B3-RXADDR0B0 : Receive Address
RXDATA015-RXDATA000 : Receive Data Bus
RXDATA015-RXDATA000 : Receive Data Bus
RXSOC0
RXENB0_B
RXSOC0
: Receive Start of Cell
RXENB0A_B, RXENB0B_B : Receive Enable Data
Transfers
RXCLAV0A, RXCLAV0B
Transfers
RXCLAV0
: Receive Cell Buffer
Available
: Receive Cell Buffer
Available
TXADDR04-TXADDR00
TXADDR0A3-TXADDR0A0 : Transmit Address
: Receive Start of Cell
: Receive Enable Data
: Transmit Address
TXDATA015-TXDATA000 : Transmit Data Bus
TXADDR0B3-TXADDR0B0 : Transmit Address
TXSOC0
: Transmit Start of Cell
TXDATA015-TXDATA000
: Transmit Data Bus
TXENB0_B
: Transmit Enable Data
TXSOC0
: Transmit Start of Cell
TXCLAV0
: Transmit Cell Buffer
UCLK1
: UTOPIA Clock
RXADDR14-RXADDR10
: Receive Address
TXENB0A_B, TXENB0B_B : Transmit Enable Data
Transfers
Transfers
Available
TXCLAV0A, TXCLAV0B
: Transmit Cell Buffer
UCLK1
: UTOPIA Clock
Available
RXADDR1A3-RXADDR1A0 : Receive Address
RXADDR1B3-RXADDR1B0 : Receive Address
RXDATA115-RXDATA100 : Receive Data Bus
RXSOC1
RXENB1_B
Transfers
RXDATA115-RXDATA100 : Receive Data Bus
RXSOC1
: Receive Start of Cell
RXENB1A_B, RXENB1B_B : Receive Enable Data
Transfers
RXCLAV1A, RXCLAV1B
RXCLAV1
Available
TXADDR1A3-TXADDR1A0 : Transmit Address
: Transmit Data Bus
TXSOC1
: Transmit Start of Cell
: Transmit Address
TXDATA115-TXDATA100 : Transmit Data Bus
TXSOC1
: Transmit Start of Cell
TXENB1_B
: Transmit Enable Data
TXCLAV1
: Transmit Cell Buffer
TXADDR1B3-TXADDR1B0 : Transmit Address
TXDATA115-TXDATA100
: Receive Cell Buffer
Available
TXADDR14-TXADDR10
: Receive Cell Buffer
: Receive Start of Cell
: Receive Enable Data
Transfers
Available
TXENB1A_B, TXENB1B_B : Transmit Enable Data
Transfers
TXCLAV1A, TXCLAV1B
: Transmit Cell Buffer
Available
Data Sheet S14237EJ2V0DS00
11
µPD98412
PIN LAYOUT
(1/15)
Multiplexed Status
Polling Mode
2-Group Weighted
Polling Mode
1-Group Weighted
Polling Mode
I/O
AD30
←
←
←
I/O
B01
GND
←
←
←
3
C01
AD24
←
←
←
I/O
4
D01
AD20
←
←
←
I/O
5
E01
AD16
←
←
←
I/O
6
F01
GND
←
←
←
7
G01
AD10
←
←
←
I/O
8
H01
AD06
←
←
←
I/O
9
J01
GND
←
←
←
10
K01
AD01
←
←
←
I/O
11
L01
HTA17
←
←
←
O
12
M01
HTA13
←
←
←
O
13
N01
HTA09
←
←
←
O
Pin No.
Address
1
A01
2
12
12-PHY Polling Mode/
15-PHY Polling Mode
14
P01
GND
←
←
←
15
R01
HTA06
←
←
←
O
16
T01
HTA02
←
←
←
O
17
U01
HTCS0_B
←
←
←
O
18
V01
HTD31
←
←
←
I/O
19
W01
HTD29
←
←
←
I/O
20
Y01
VDD
←
←
←
21
AA01
HTD24
←
←
←
I/O
22
AB01
HTD21
←
←
←
I/O
23
AC01
HTD17
←
←
←
I/O
24
AD01
HTP1
←
←
←
I/O
25
AE01
VDD
←
←
←
26
AF01
GND
←
←
←
27
AG01
HTD06
←
←
←
I/O
28
AH01
HTD05
←
←
←
I/O
29
AJ01
HTD01
←
←
←
I/O
30
AK01
PU
←
←
←
I
31
AK02
VDD
←
←
←
32
AK03
GND
←
←
←
33
AK04
JCK
←
←
←
I
34
AK05
RXDATA307
RXDATA115
RXDATA115
RXDATA115
I
35
AK06
VDD
←
←
←
36
AK07
RXDATA301
RXDATA109
RXDATA109
RXDATA109
37
AK08
GND
←
←
←
38
AK09
RXCLAV3
RXCLAV1[2]
RXCLAV1B
CG
39
AK10
VDD
←
←
←
40
AK11
TXADDR33
IC
TXADDR1B3
IC
Data Sheet S14237EJ2V0DS00
I
I
O
µPD98412
(2/15)
Pin No.
Address
12-PHY Polling Mode/
15-PHY Polling Mode
Multiplexed Status
Polling Mode
2-Group Weighted
Polling Mode
1-Group Weighted
Polling Mode
I/O
41
AK12
CG
TXCLAV1[3]
CG
CG
I
42
AK13
TXDATA307
TXDATA115
TXDATA115
TXDATA115
O
43
AK14
VDD
←
←
←
44
AK15
TXDATA304
TXDATA112
TXDATA112
TXDATA112
O
45
AK16
TXDATA300
TXDATA108
TXDATA108
TXDATA108
O
46
AK17
RXDATA104
RXDATA104
RXDATA104
RXDATA104
I
47
AK18
RXDATA100
RXDATA100
RXDATA100
RXDATA100
I
48
AK19
UCLK1
UCLK1
UCLK1
UCLK1
I
49
AK20
RXCLAV1
RXCLAV1[0]
RXCLAV1A
RXCLAV1
I
50
AK21
RXADDR12
RXADDR12
RXADDR1A2
RXADDR12
O
51
AK22
TXADDR12
TXADDR12
TXADDR1A2
TXADDR12
O
52
AK23
TXCLAV1
TXCLAV1[0]
TXCLAV1A
TXCLAV1
I
53
AK24
TXDATA107
TXDATA107
TXDATA107
TXDATA107
O
54
AK25
TXDATA103
TXDATA103
TXDATA103
TXDATA103
O
55
AK26
CBD87
←
←
←
I/O
56
AK27
CBD84
←
←
←
I/O
57
AK28
VDD
←
←
←
58
AK29
GND
←
←
←
59
AK30
CBD77
←
←
←
60
AJ30
GND
←
←
←
I/O
61
AH30
VDD
←
←
←
62
AG30
CBD68
←
←
←
I/O
63
AF30
CBD64
←
←
←
I/O
64
AE30
VDD
←
←
←
65
AD30
CBD58
←
←
←
I/O
66
AC30
CBD54
←
←
←
I/O
67
AB30
VDD
←
←
←
68
AA30
CBD49
←
←
←
I/O
69
Y30
CBD47
←
←
←
I/O
70
W30
CBCS1_B
←
←
←
O
71
V30
CBA17
←
←
←
O
72
U30
VDD
←
←
←
73
T30
CBA14
←
←
←
O
74
R30
CBA10
←
←
←
O
75
P30
CBA06
←
←
←
O
76
N30
CBA02
←
←
←
O
77
M30
CBA00
←
←
←
O
78
L30
VDD
←
←
←
79
K30
CBD39
←
←
←
I/O
80
J30
CBD35
←
←
←
I/O
Data Sheet S14237EJ2V0DS00
13
µPD98412
(3/15)
Pin No.
14
Address
12-PHY Polling Mode/
15-PHY Polling Mode
Multiplexed Status
Polling Mode
2-Group Weighted
Polling Mode
1-Group Weighted
Polling Mode
I/O
81
H30
VDD
←
←
←
82
G30
CBD29
←
←
←
I/O
83
F30
CBD25
←
←
←
I/O
84
E30
GND
←
←
←
85
D30
CBD18
←
←
←
86
C30
VDD
←
←
←
87
B30
VDD
←
←
←
88
A30
CBD11
←
←
←
89
A29
VDD
←
←
←
90
A28
CBD05
←
←
←
I/O
I/O
I/O
91
A27
CBD01
←
←
←
I/O
92
A26
RXDATA005
RXDATA005
RXDATA005
RXDATA005
I
93
A25
RXDATA003
RXDATA003
RXDATA003
RXDATA003
I
94
A24
VDD
←
←
←
95
A23
RXCLAV0
RXCLAV0[0]
RXCLAV0A
RXCLAV0
I
96
A22
VDD
←
←
←
97
A21
TXADDR03
TXADDR03
TXADDR03
TXADDR03
O
98
A20
TXADDR01
TXADDR01
TXADDR01
TXADDR01
O
99
A19
TXSOC0
TXSOC0
TXSOC0
TXSOC0
O
100
A18
TXDATA005
TXDATA005
TXDATA005
TXDATA005
O
101
A17
GND
←
←
←
102
A16
TXDATA001
TXDATA001
TXDATA001
TXDATA001
O
103
A15
RXDATA205
RXDATA013
RXDATA013
RXDATA013
I
104
A14
RXDATA201
RXDATA009
RXDATA009
RXDATA009
I
105
A13
RXENB2_B
IC
RXENB0B_B
IC
O
106
A12
RXCLAV2
RXCLAV0[2]
RXCLAV0B
CG
I
107
A11
RXADDR21
IC
RXADDR0B1
IC
O
108
A10
TXADDR22
IC
TXADDR0B2
IC
O
109
A09
TXCLAV2
TXCLAV0[2]
TXCLAV0B
CG
I
110
A08
GND
←
←
←
111
A07
TXDATA203
TXDATA011
TXDATA011
TXDATA011
O
112
A06
VDD
←
←
←
113
A05
GND
←
←
←
114
A04
R/W_B
←
←
←
I
115
A03
UWE_B
←
←
←
I
116
A02
CG
←
←
←
I
117
B02
AD29
←
←
←
I/O
118
C02
AD27
←
←
←
I/O
119
D02
VDD
←
←
←
120
E02
AD19
←
←
←
Data Sheet S14237EJ2V0DS00
I/O
µPD98412
(4/15)
Pin No.
Address
12-PHY Polling Mode/
15-PHY Polling Mode
Multiplexed Status
Polling Mode
2-Group Weighted
Polling Mode
1-Group Weighted
Polling Mode
I/O
121
F02
AD15
←
←
←
I/O
122
G02
AD11
←
←
←
I/O
123
H02
AD09
←
←
←
I/O
124
J02
AD05
←
←
←
I/O
125
K02
AD04
←
←
←
I/O
126
L02
AD00
←
←
←
I/O
127
M02
HTA14
←
←
←
O
128
N02
HTA10
←
←
←
O
129
P02
VDD
←
←
←
130
R02
HTA05
←
←
←
O
131
T02
HTA01
←
←
←
O
132
U02
HTWE_B
←
←
←
O
133
V02
HTD30
←
←
←
I/O
134
W02
HTD26
←
←
←
I/O
135
Y02
HTD25
←
←
←
I/O
136
AA02
HTD22
←
←
←
I/O
137
AB02
HTD20
←
←
←
I/O
138
AC02
HTD16
←
←
←
I/O
139
AD02
HTD13
←
←
←
I/O
140
AE02
HTD10
←
←
←
I/O
141
AF02
HTD07
←
←
←
I/O
142
AG02
HTD02
←
←
←
I/O
143
AH02
GND
←
←
←
144
AJ02
GND
←
←
←
145
AJ03
CBD91
←
←
←
I/O
146
AJ04
JDO
←
←
←
O
147
AJ05
VDD
←
←
←
148
AJ06
RXDATA306
RXDATA114
RXDATA114
RXDATA114
I
149
AJ07
RXDATA302
RXDATA110
RXDATA110
RXDATA110
I
150
AJ08
RXDATA300
RXDATA108
RXDATA108
RXDATA108
I
151
AJ09
RXENB3_B
IC
RXENB1B_B
IC
O
152
AJ10
VDD
←
←
←
153
AJ11
RXADDR30
RXADDR14
RXADDR1B0
RXADDR14
O
154
AJ12
TXADDR30
TXADDR14
TXADDR1B0
TXADDR14
O
155
AJ13
TXENB3_B
IC
TXENB1B_B
IC
O
156
AJ14
GND
←
←
←
157
AJ15
TXDATA303
TXDATA111
TXDATA111
TXDATA111
O
158
AJ16
RXDATA107
RXDATA107
RXDATA107
RXDATA107
I
159
AJ17
RXDATA103
RXDATA103
RXDATA103
RXDATA103
I
160
AJ18
VDD
←
←
←
Data Sheet S14237EJ2V0DS00
15
µPD98412
(5/15)
12-PHY Polling Mode/
15-PHY Polling Mode
Multiplexed Status
Polling Mode
2-Group Weighted
Polling Mode
1-Group Weighted
Polling Mode
I/O
Pin No.
Address
161
AJ19
VDD
←
←
←
162
AJ20
GND
←
←
←
163
AJ21
TXADDR13
TXADDR13
TXADDR1A3
TXADDR13
O
164
AJ22
TXADDR10
TXADDR10
TXADDR1A0
TXADDR10
O
165
AJ23
TXENB1_B
TXENB1_B
TXENB1A_B
TXENB1_B
O
166
AJ24
TXDATA104
TXDATA104
TXDATA104
TXDATA104
O
167
AJ25
TXDATA101
TXDATA101
TXDATA101
TXDATA101
O
168
AJ26
CBD85
←
←
←
I/O
169
AJ27
VDD
←
←
←
170
AJ28
CBD80
←
←
←
I/O
171
AJ29
CBD76
←
←
←
I/O
172
AH29
CBD74
←
←
←
I/O
173
AG29
GND
←
←
←
174
AF29
CBD67
←
←
←
I/O
175
AE29
CBD63
←
←
←
I/O
176
AD29
CBD59
←
←
←
I/O
177
AC29
CBD57
←
←
←
I/O
178
AB29
CBD53
←
←
←
I/O
179
AA29
CBD52
←
←
←
I/O
180
Y29
CBD48
←
←
←
I/O
181
W29
CBD44
←
←
←
I/O
182
V29
CBOE_B
←
←
←
O
183
U29
GND
←
←
←
184
T29
CBA13
←
←
←
O
185
R29
CBA09
←
←
←
O
186
P29
CBA05
←
←
←
O
16
187
N29
CBA01
←
←
←
O
188
M29
CBD41
←
←
←
I/O
189
L29
CBD40
←
←
←
I/O
190
K29
CBD36
←
←
←
I/O
191
J29
CBD34
←
←
←
I/O
192
H29
CBD30
←
←
←
I/O
193
G29
CBD26
←
←
←
I/O
194
F29
CBD23
←
←
←
I/O
195
E29
CBD19
←
←
←
I/O
196
D29
GND
←
←
←
197
C29
CBD14
←
←
←
I/O
198
B29
CBD10
←
←
←
I/O
199
B28
CBD08
←
←
←
I/O
200
B27
CBD02
←
←
←
I/O
Data Sheet S14237EJ2V0DS00
µPD98412
(6/15)
1-Group Weighted
Polling Mode
I/O
←
←
I/O
RXDATA004
RXDATA004
I
RXDATA000
RXDATA000
I
RXENB0_B
RXENB0A_B
RXENB0_B
O
RXADDR03
RXADDR03
RXADDR0A3
RXADDR03
O
B21
RXADDR02
RXADDR02
RXADDR0A2
RXADDR02
O
B20
TXADDR02
TXADDR02
TXADDR0A2
TXADDR02
O
208
B19
TXCLAV0
TXCLAV0[0]
TXCLAV0A
TXCLAV0
I
209
B18
TXDATA006
TXDATA006
TXDATA006
TXDATA006
O
210
B17
TXDATA002
TXDATA002
TXDATA002
TXDATA002
O
12-PHY Polling Mode/
15-PHY Polling Mode
Multiplexed Status
Polling Mode
Pin No.
Address
201
B26
CBD00
←
202
B25
RXDATA004
RXDATA004
203
B24
RXDATA000
RXDATA000
204
B23
RXENB0_B
205
B22
206
207
2-Group Weighted
Polling Mode
211
B16
TXDATA000
TXDATA000
TXDATA000
TXDATA000
O
212
B15
RXDATA204
RXDATA012
RXDATA012
RXDATA012
I
213
B14
RXDATA200
RXDATA008
RXDATA008
RXDATA008
I
214
B13
RXSOC2
RXLLAV0[3]
CG
CG
I
215
B12
GND
←
←
←
216
B11
TXADDR23
IC
TXADDR0B3
IC
O
217
B10
CG
TXCLAV0[3]
CG
CG
I
218
B09
TXENB2_B
IC
TXENB0B_B
IC
O
219
B08
TXDATA204
TXDATA012
TXDATA012
TXDATA012
O
220
B07
TXDATA200
TXDATA008
TXDATA008
TXDATA008
O
221
B06
IOCS_B
←
←
←
I
222
B05
CG
←
←
←
I
223
B04
CG
←
←
←
I
224
B03
IC
←
←
←
O
225
C03
AD28
←
←
←
I/O
226
D03
AD26
←
←
←
I/O
227
E03
AD22
←
←
←
I/O
228
F03
AD18
←
←
←
I/O
229
G03
AD14
←
←
←
I/O
230
H03
VDD
←
←
←
231
J03
AD08
←
←
←
232
K03
VDD
←
←
←
233
L03
GND
←
←
←
234
M03
HTA15
←
←
←
O
235
N03
HTA11
←
←
←
O
236
P03
HTA07
←
←
←
O
237
R03
HTA03
←
←
←
O
238
T03
HTA00
←
←
←
O
239
U03
HTOE_B
←
←
←
O
240
V03
VDD
←
←
←
Data Sheet S14237EJ2V0DS00
I/O
17
µPD98412
(7/15)
Multiplexed Status
Polling Mode
2-Group Weighted
Polling Mode
1-Group Weighted
Polling Mode
GND
←
←
←
HTD23
←
←
←
VDD
←
←
←
AB03
GND
←
←
←
245
AC03
HTD14
←
←
←
I/O
246
AD03
HTD11
←
←
←
I/O
247
AE03
HTP0
←
←
←
I/O
248
AF03
HTD03
←
←
←
I/O
249
AG03
HTD00
←
←
←
I/O
250
AH03
IC
←
←
←
O
251
AH04
CBD90
←
←
←
I/O
252
AH05
JDI
←
←
←
I
253
AH06
JMS
←
←
←
I
254
AH07
RXDATA305
RXDATA113
RXDATA113
RXDATA113
I
255
AH08
GND
←
←
←
256
AH09
GND
←
←
←
257
AH10
RXSOC3
RXCLAV1[3]
CG
CG
I
258
AH11
RXADDR31
IC
RXADDR1B1
IC
O
259
AH12
TXADDR31
IC
TXADDR1B1
IC
O
260
AH13
TXSOC3
IC
IC
IC
O
261
AH14
TXDATA305
TXDATA113
TXDATA113
TXDATA113
O
262
AH15
TXDATA301
TXDATA109
TXDATA109
TXDATA109
O
263
AH16
RXDATA106
RXDATA106
RXDATA106
RXDATA106
I
264
AH17
RXDATA102
RXDATA102
RXDATA102
RXDATA102
I
265
AH18
GND
←
←
←
266
AH19
RXADDR13
RXADDR13
RXADDR1A3
RXADDR13
267
AH20
RXADDR10
RXADDR10
RXADDR1A0
RXADDR10
O
268
AH21
TXADDR11
TXADDR11
TXADDR1A1
TXADDR11
O
269
AH22
TXSOC1
TXSOC1
TXSOC1
TXSOC1
O
270
AH23
TXDATA105
TXDATA105
TXDATA105
TXDATA105
O
271
AH24
TXDATA102
TXDATA102
TXDATA102
TXDATA102
O
272
AH25
CBD86
←
←
←
I/O
273
AH26
CBD81
←
←
←
I/O
274
AH27
CBD79
←
←
←
I/O
275
AH28
CBD75
←
←
←
I/O
276
AG28
CBD73
←
←
←
I/O
277
AF28
CBD69
←
←
←
I/O
278
AE28
CBD66
←
←
←
I/O
279
AD28
CBD62
←
←
←
I/O
280
AC28
GND
←
←
←
Pin No.
Address
241
W03
242
Y03
243
AA03
244
18
12-PHY Polling Mode/
15-PHY Polling Mode
Data Sheet S14237EJ2V0DS00
I/O
I/O
O
µPD98412
(8/15)
Pin No.
Address
12-PHY Polling Mode/
15-PHY Polling Mode
Multiplexed Status
Polling Mode
2-Group Weighted
Polling Mode
1-Group Weighted
Polling Mode
I/O
I/O
281
AB28
CBD56
←
←
←
282
AA28
GND
←
←
←
283
Y28
VDD
←
←
←
284
W28
CBD45
←
←
←
I/O
285
V28
CBWE_B
←
←
←
O
286
U28
CBA15
←
←
←
O
287
T28
CBA11
←
←
←
O
288
R28
CBA08
←
←
←
O
289
P28
CBA04
←
←
←
O
290
N28
VDD
←
←
←
291
M28
GND
←
←
←
292
L28
CBD37
←
←
←
293
K28
VDD
←
←
←
294
J28
CBD31
←
←
←
I/O
295
H28
CBD27
←
←
←
I/O
296
G28
CBD24
←
←
←
I/O
297
F28
CBD20
←
←
←
I/O
298
E28
CBD15
←
←
←
I/O
299
D28
CBD13
←
←
←
I/O
300
C28
CBD09
←
←
←
I/O
301
C27
CBD07
←
←
←
I/O
302
C26
CBD03
←
←
←
I/O
303
C25
RXDATA007
RXDATA007
RXDATA007
RXDATA007
I
304
C24
GND
←
←
←
305
C23
GND
←
←
←
306
C22
RXSOC0
RXSOC0
RXSOC0
RXSOC0
307
C21
GND
←
←
←
308
C20
VDD
←
←
←
309
C19
CG
TXCLAV0[1]
CG
CG
I
310
C18
TXDATA007
TXDATA007
TXDATA007
TXDATA007
O
311
C17
TXDATA003
TXDATA003
TXDATA003
TXDATA003
O
312
C16
RXDATA206
RXDATA014
RXDATA014
RXDATA014
I
313
C15
GND
←
←
←
314
C14
GND
←
←
←
315
C13
VDD
←
←
←
316
C12
RXADDR20
RXADDR04
RXADDR0B0
RXADDR04
O
317
C11
TXADDR20
TXADDR04
TXADDR0B0
TXADDR04
O
318
C10
TXSOC2
IC
IC
IC
O
319
C09
TXDATA205
TXDATA013
TXDATA013
TXDATA013
O
320
C08
TXDATA201
TXDATA009
TXDATA009
TXDATA009
O
Data Sheet S14237EJ2V0DS00
I/O
I
19
µPD98412
(9/15)
Pin No.
20
Address
12-PHY Polling Mode/
15-PHY Polling Mode
Multiplexed Status
Polling Mode
2-Group Weighted
Polling Mode
1-Group Weighted
Polling Mode
I/O
321
C07
CG
←
←
←
I
322
C06
RDY_B
←
←
←
O
323
C05
GND
←
←
←
324
C04
VDD
←
←
←
325
D04
VDD
←
←
←
326
E04
AD25
←
←
←
327
F04
GND
←
←
←
328
G04
AD17
←
←
←
329
H04
VDD
←
←
←
330
J04
GND
←
←
←
331
K04
AD07
←
←
←
332
L04
VDD
←
←
←
333
M04
HTA16
←
←
←
O
334
N04
HTA12
←
←
←
O
335
P04
HTA08
←
←
←
O
336
R04
HTA04
←
←
←
O
337
T04
VDD
←
←
←
338
U04
HTP3
←
←
←
339
V04
GND
←
←
←
340
W04
HTP2
←
←
←
341
Y04
GND
←
←
←
342
AA04
VDD
←
←
←
343
AB04
HTD15
←
←
←
I/O
344
AC04
HTD12
←
←
←
I/O
345
AD04
HTD08
←
←
←
I/O
346
AE04
HTD04
←
←
←
I/O
347
AF04
RESET_B
←
←
←
I
348
AG04
IC
←
←
←
O
349
AG05
CBD89
←
←
←
I/O
350
AG06
IC
←
←
←
351
AG07
JRST_B
←
←
←
352
AG08
GND
←
←
←
353
AG09
VDD
←
←
←
354
AG10
UCLK3
CG
CG
CG
I
355
AG11
RXADDR32
IC
RXADDR1B2
IC
O
356
AG12
TXADDR32
IC
TXADDR1B2
IC
O
357
AG13
TXCLAV3
TXCLAV1[2]
TXCLAV1B
CG
I
358
AG14
TXDATA306
TXDATA114
TXDATA114
TXDATA114
O
359
AG15
TXDATA302
TXDATA110
TXDATA110
TXDATA110
O
360
AG16
VDD
←
←
←
Data Sheet S14237EJ2V0DS00
I/O
I/O
I/O
I/O
I/O
I
µPD98412
(10/15)
2-Group Weighted
Polling Mode
1-Group Weighted
Polling Mode
RXDATA101
RXDATA101
RXDATA101
I
RXENB1_B
RXENB1A_B
RXENB1_B
O
RXADDR11
RXADDR11
RXADDR1A1
RXADDR11
O
AG20
GND
←
←
←
AG21
GND
←
←
←
366
AG22
TXDATA106
TXDATA106
TXDATA106
TXDATA106
367
AG23
GND
←
←
←
368
AG24
GND
←
←
←
369
AG25
CBD82
←
←
←
370
AG26
GND
←
←
←
371
AG27
VDD
←
←
←
372
AF27
CBD72
←
←
←
I/O
373
AE27
CBD70
←
←
←
I/O
374
AD27
CBD65
←
←
←
I/O
375
AC27
GND
←
←
←
376
AB27
VDD
←
←
←
377
AA27
CBD55
←
←
←
378
Y27
GND
←
←
←
379
W27
CBD46
←
←
←
I/O
380
V27
CBCS0_B
←
←
←
O
381
U27
CBA16
←
←
←
O
382
T27
CBA12
←
←
←
O
383
R27
VDD
←
←
←
384
P27
CBA03
←
←
←
385
N27
GND
←
←
←
386
M27
CBD38
←
←
←
387
L27
GND
←
←
←
388
K27
GND
←
←
←
389
J27
CBD28
←
←
←
390
H27
GND
←
←
←
391
G27
CBD21
←
←
←
I/O
392
F27
CBD16
←
←
←
I/O
393
E27
VDD
←
←
←
394
D27
GND
←
←
←
395
D26
CBD06
←
←
←
396
D25
GND
←
←
←
397
D24
RXDATA006
RXDATA006
RXDATA006
RXDATA006
398
D23
VDD
←
←
←
399
D22
UCLK0
UCLK0
UCLK0
UCLK0
I
400
D21
CG
RXCLAV0[1]
CG
CG
I
12-PHY Polling Mode/
15-PHY Polling Mode
Pin No.
Address
361
AG17
RXDATA101
362
AG18
RXENB1_B
363
AG19
364
365
Multiplexed Status
Polling Mode
Data Sheet S14237EJ2V0DS00
I/O
O
I/O
I/O
O
I/O
I/O
I/O
I
21
µPD98412
(11/15)
12-PHY Polling Mode/
15-PHY Polling Mode
Multiplexed Status
Polling Mode
2-Group Weighted
Polling Mode
1-Group Weighted
Polling Mode
I/O
Pin No.
Address
401
D20
GND
←
←
←
402
D19
TXADDR00
TXADDR00
TXADDR0A0
TXADDR00
O
403
D18
TXENB0_B
TXENB0_B
TXENB0A_B
TXENB0_B
O
404
D17
TXDATA004
TXDATA004
TXDATA004
TXDATA004
O
405
D16
RXDATA207
RXDATA015
RXDATA015
RXDATA015
I
22
406
D15
VDD
←
←
←
407
D14
UCLK2
CG
CG
CG
I
408
D13
RXADDR23
IC
RXADDR0B3
IC
O
409
D12
TXADDR21
IC
TXADDR0B1
IC
O
410
D11
GND
←
←
←
411
D10
TXDATA206
TXDATA014
TXDATA014
TXDATA014
O
412
D09
TXDATA202
TXDATA010
TXDATA010
TXDATA010
O
413
D08
GND
←
←
←
414
D07
INT
←
←
←
O
415
D06
CG
←
←
←
I
416
D05
AD31
←
←
←
I/O
417
E05
VDD
←
←
←
418
F05
VDD
←
←
←
419
G05
AD21
←
←
←
420
H05
VDD
←
←
←
421
J05
AD12
←
←
←
422
K05
VDD
←
←
←
423
L05
AD02
←
←
←
424
M05
VDD
←
←
←
425
N05
GND
←
←
←
426
P05
VDD
←
←
←
427
R05
VDD
←
←
←
428
T05
HTCS1_B
←
←
←
429
U05
VDD
←
←
←
430
V05
HTD28
←
←
←
431
W05
VDD
←
←
←
432
Y05
HTD19
←
←
←
433
AA05
VDD
←
←
←
434
AB05
GND
←
←
←
435
AC05
VDD
←
←
←
436
AD05
VDD
←
←
←
437
AE05
SWCLK
←
←
←
438
AF05
VDD
←
←
←
439
AF06
CBD88
←
←
←
440
AF07
GND
←
←
←
Data Sheet S14237EJ2V0DS00
I/O
I/O
I/O
O
I/O
I/O
I
I/O
µPD98412
(12/15)
12-PHY Polling Mode/
15-PHY Polling Mode
Multiplexed Status
Polling Mode
2-Group Weighted
Polling Mode
1-Group Weighted
Polling Mode
Pin No.
Address
441
AF08
VDD
←
←
←
442
AF09
RXDATA303
RXDATA111
RXDATA111
RXDATA111
443
AF10
VDD
←
←
←
444
AF11
GND
←
←
←
445
AF12
VDD
←
←
←
446
AF13
VDD
←
←
←
447
AF14
VDD
←
←
←
448
AF15
VDD
←
←
←
449
AF16
RXDATA105
RXDATA105
RXDATA105
RXDATA105
450
AF17
VDD
←
←
←
451
AF18
RXSOC1
RXSOC1
RXSOC1
RXSOC1
452
AF19
VDD
←
←
←
453
AF20
VDD
←
←
←
454
AF21
VDD
←
←
←
455
AF22
VDD
←
←
←
456
AF23
VDD
←
←
←
457
AF24
CBD83
←
←
←
458
AF25
VDD
←
←
←
459
AF26
VDD
←
←
←
460
AE26
GND
←
←
←
461
AD26
VDD
←
←
←
462
AC26
VDD
←
←
←
463
AB26
CBD60
←
←
←
464
AA26
VDD
←
←
←
465
Y26
CBD50
←
←
←
466
W26
VDD
←
←
←
467
V26
VDD
←
←
←
468
U26
VDD
←
←
←
469
T26
VDD
←
←
←
470
R26
CBA07
←
←
←
471
P26
VDD
←
←
←
472
N26
CBD43
←
←
←
473
M26
VDD
←
←
←
474
L26
CBD33
←
←
←
475
K26
VDD
←
←
←
476
J26
VDD
←
←
←
477
H26
VDD
←
←
←
478
G26
CBD17
←
←
←
479
F26
GND
←
←
←
480
E26
VDD
←
←
←
Data Sheet S14237EJ2V0DS00
I/O
I
I
I
I/O
I/O
I/O
O
I/O
I/O
I/O
23
µPD98412
(13/15)
Multiplexed Status
Polling Mode
2-Group Weighted
Polling Mode
1-Group Weighted
Polling Mode
VDD
←
←
←
VDD
←
←
←
E23
VDD
←
←
←
484
E22
RXDATA001
RXDATA001
RXDATA001
RXDATA001
485
E21
VDD
←
←
←
486
E20
RXADDR00
RXADDR00
RXADDR0A0
RXADDR00
487
E19
VDD
←
←
←
488
E18
VDD
←
←
←
489
E17
VDD
←
←
←
490
E16
VDD
←
←
←
491
E15
RXDATA202
RXDATA010
RXDATA010
RXDATA010
492
E14
VDD
←
←
←
493
E13
RXADDR22
IC
RXADDR0B2
IC
494
E12
VDD
←
←
←
495
E11
VDD
←
←
←
Pin No.
Address
481
E25
482
E24
483
24
12-PHY Polling Mode/
15-PHY Polling Mode
496
E10
VDD
←
←
←
497
E09
HCLK
←
←
←
498
E08
VDD
←
←
←
499
E07
VDD
←
←
←
500
E06
IC
←
←
←
501
F06
GND
←
←
←
502
G06
AD23
←
←
←
503
H06
GND
←
←
←
504
J06
AD13
←
←
←
505
K06
GND
←
←
←
506
L06
AD03
←
←
←
507
M06
GND
←
←
←
508
N06
VDD
←
←
←
509
P06
GND
←
←
←
510
R06
GND
←
←
←
511
T06
GND
←
←
←
512
U06
GND
←
←
←
513
V06
HTD27
←
←
←
514
W06
GND
←
←
←
515
Y06
HTD18
←
←
←
516
AA06
GND
←
←
←
517
AB06
HTD09
←
←
←
518
AC06
GND
←
←
←
519
AD06
VDD
←
←
←
520
AE06
GND
←
←
←
Data Sheet S14237EJ2V0DS00
I/O
I
O
I
O
I
I/O
I/O
I/O
I/O
I/O
I/O
µPD98412
(14/15)
Pin No.
Address
12-PHY Polling Mode/
15-PHY Polling Mode
Multiplexed Status
Polling Mode
2-Group Weighted
Polling Mode
1-Group Weighted
Polling Mode
521
AE07
VDD
←
←
←
522
AE08
GND
←
←
←
523
AE09
RXDATA304
RXDATA112
RXDATA112
RXDATA112
524
AE10
GND
←
←
←
525
AE11
RXADDR33
IC
RXADDR1B3
IC
526
AE12
GND
←
←
←
527
AE13
GND
←
←
←
528
AE14
GND
←
←
←
529
AE15
GND
←
←
←
530
AE16
GND
←
←
←
531
AE17
GND
←
←
←
532
AE18
CG
RXCLAV1[1]
CG
CG
533
AE19
GND
←
←
←
534
AE20
CG
TXCLAV1[1]
CG
CG
535
AE21
GND
←
←
←
536
AE22
TXDATA100
TXDATA100
TXDATA100
TXDATA100
537
AE23
GND
←
←
←
538
AE24
CBD78
←
←
←
539
AE25
GND
←
←
←
540
AD25
CBD71
←
←
←
541
AC25
GND
←
←
←
542
AB25
CBD61
←
←
←
543
AA25
GND
←
←
←
544
Y25
CBD51
←
←
←
545
W25
GND
←
←
←
546
V25
GND
←
←
←
547
U25
GND
←
←
←
548
T25
GND
←
←
←
549
R25
GND
←
←
←
550
P25
GND
←
←
←
551
N25
CBD42
←
←
←
552
M25
GND
←
←
←
553
L25
CBD32
←
←
←
554
K25
GND
←
←
←
555
J25
CBD22
←
←
←
556
H25
GND
←
←
←
557
G25
CBD12
←
←
←
558
F25
GND
←
←
←
559
F24
CBD04
←
←
←
560
F23
GND
←
←
←
Data Sheet S14237EJ2V0DS00
I/O
I
O
I
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
25
µPD98412
(15/15)
Multiplexed Status
Polling Mode
2-Group Weighted
Polling Mode
1-Group Weighted
Polling Mode
I/O
RXDATA002
RXDATA002
RXDATA002
RXDATA002
I
GND
←
←
←
F20
RXADDR01
RXADDR01
RXADDR0A1
RXADDR01
564
F19
GND
←
←
←
565
F18
GND
←
←
←
566
F17
GND
←
←
←
567
F16
GND
←
←
←
568
F15
RXDATA203
RXDATA011
RXDATA011
RXDATA011
569
F14
GND
←
←
←
570
F13
VDD
←
←
←
571
F12
GND
←
←
←
572
F11
TXDATA207
TXDATA015
TXDATA015
TXDATA015
573
F10
GND
←
←
←
574
F09
MCS_B
←
←
←
575
F08
GND
←
←
←
576
F07
GND
←
←
←
Pin No.
Address
561
F22
562
F21
563
26
12-PHY Polling Mode/
15-PHY Polling Mode
Data Sheet S14237EJ2V0DS00
O
I
O
I
µPD98412
CONTENTS
1. PIN FUNCTIONS ........................................................................................................................... 28
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
Power Supply ........................................................................................................................ 28
UTOPIA Interface .................................................................................................................. 29
Memory Interface Signals .................................................................................................... 41
Microprocessor Interface Signals ....................................................................................... 42
JTAG ...................................................................................................................................... 43
Others .................................................................................................................................... 43
Recommended Connections of Unused Pins.................................................................... 44
Pin Status at Reset ............................................................................................................... 45
2. ELECTRICAL SPECIFICATIONS ................................................................................................. 46
3. PACKAGE DRAWING .................................................................................................................. 60
4. RECOMMENDED SOLDERING CONDITIONS........................................................................... 61
Data Sheet S14237EJ2V0DS00
27
µPD98412
1. PIN FUNCTIONS
Although the µPD98412 is a device operating at 3.3 V, it can be directly connected to a PHY device, CPU, and
memory with a 5-V TTL interface.
1.1 Power Supply
Table 1-1. Power Supply
28
Pin Name
Pin No.
I/O
Function
VDD
20, 25, 31, 35, 39, 43, 57, 61, 64, 67, 72, 78, 81, 86, 87, 89, 94, 96,
112, 119, 129, 147, 152, 160, 161, 169, 230, 232, 240, 243, 283, 290,
293, 308, 315, 324, 325, 329, 332, 337, 342, 353, 360, 371, 376, 383,
393, 398, 406, 417, 418, 420, 422, 424, 426, 427, 429, 431, 433, 435,
436, 438, 441, 443, 445 - 448, 450, 452 - 456, 458, 459, 461, 462, 464,
466 - 469, 471, 473, 475 - 477, 480 - 483, 485, 487 - 490, 492, 494 496, 498, 499, 508, 519, 521, 570
—
These pins supply a
power of +3.3 V ± 5%.
GND
2, 6, 9, 14, 26, 32, 37, 58, 60, 84, 101, 110, 113, 143, 144, 156, 162,
173, 183, 196, 215, 233, 241, 244, 255, 256, 265, 280, 282, 291, 304,
305, 307, 313, 314, 323, 327, 330, 339, 341, 352, 364, 365, 367, 368,
370, 375, 378, 385, 387, 388, 390, 394, 396, 401, 410, 413, 425, 434,
440, 444, 460, 479, 501, 503, 505, 507, 509 - 512, 514, 516, 518, 520,
522, 524, 526 - 531, 533, 535, 537, 539, 541, 543, 545 - 550, 552, 554,
556, 558, 560, 562, 564 - 567, 569, 571, 573, 575, 576
—
These are ground
pins.
Data Sheet S14237EJ2V0DS00
µPD98412
1.2 UTOPIA Interface
The µPD98412 employs a UTOPIA Level2 (cell level transfer) interface between PHY layer and ATM layer.
Symbol, pim number, and function are varied depending on the polling mode.
(1) 8-bit 12-PHY polling mode/15-PHY polling mode
Table 1-2. Receive Interface Signals (1/2)
Symbol
Pin No.
I/O
Function
RXADDR03 RXADDR00
205, 206, 563, 486
O
Multi-PHY select address of receive interface 0.
RXADDR03 is the MSB.
RXDATA007 RXDATA000
303, 397, 92, 202, 93, 561,
484, 203
I
Cell data input of receive interface 0.
Cell data is input from a PHY layer device in byte units.
The µPD98412 reads the data at the rising edge of UCLK0.
RXDATA007 is the MSB.
RXSOC0
306
I
Cell transfer start signal of receive interface 0.
This signal is input from a PHY layer device in synchronization with
the first byte of cell data.
RXENB0_B
204
O
Transfer enable signal of receive interface 0.
This signal informs a PHY layer device that the µPD98412 is ready
for reception in the next clock cycle.
RXCLAV0
95
I
Cell transfer enable signal of receive interface 0.
This pin inputs a signal that indicates that no more cells will be
supplied to the µPD98412 after the current cell has been
transferred.
UCLK0
399
I
UTOPIA clock input of receive interface 0.
Data is transferred/received at the rising edge of this clock.
RXADDR13 RXADDR10
266, 50, 363, 267
O
Multi-PHY select address of receive interface 1.
RXADDR13 is the MSB.
RXDATA107 RXDATA100
158, 263, 449, 46, 159, 264,
361, 47
I
Cell data input of receive interface 1.
Cell data is input from a PHY layer device in byte units. The
µPD98412 reads the data at the rising edge of UCLK1.
RXDATA107 is the MSB.
RXSOC1
451
I
Cell transfer start signal of receive interface 1.
This signal is input from a PHY layer device in synchronization with
the first byte of cell data.
RXENB1_B
362
O
Transfer enable signal of receive interface 1.
This signal informs a PHY layer device that the µPD98412 is ready
for reception in the next clock cycle.
RXCLAV1
49
I
Cell transfer enable signal of receive interface 1.
This pin inputs a signal that indicates that no more cells will be
supplied to the µPD98412 after the current cell has been
transferred.
UCLK1
48
I
UTOPIA clock input of receive interface 1.
Data is transferred/received at the rising edge of this clock.
Data Sheet S14237EJ2V0DS00
29
µPD98412
Table 1-2. Receive Interface Signals (2/2)
Symbol
Pin No.
I/O
RXADDR23 RXADDR20
408, 493, 107, 316
O
Multi-PHY select address of receive interface 2.
RXADDR23 is the MSB.
RXDATA207 RXDATA200
405, 312, 103, 212, 568, 491,
104, 213
I
Cell data input of receive interface 2.
Cell data is input from a PHY layer device in byte units.
The µPD98412 reads the data at the rising edge of UCLK2.
RXDATA207 is the MSB.
RXSOC2
214
I
Cell transfer start signal of receive interface 2.
This signal is input from a PHY layer device in synchronization with
the first byte of cell data.
RXENB2_B
105
O
Transfer enable signal of receive interface 2.
This signal informs a PHY layer device that the µPD98412 is ready
for reception in the next clock cycle.
RXCLAV2
106
I
Cell transfer enable signal of receive interface 2.
This pin inputs a signal that indicates that no more cells will be
supplied to the µPD98412 after the current cell has been
transferred.
UCLK2
407
I
UTOPIA clock input of receive interface 2.
Data is transferred/received at the rising edge of this clock.
RXADDR33 RXADDR30
525, 355, 258, 153
O
Multi-PHY select address of receive interface 3.
RXADDR33 is the MSB.
RXDATA307 RXDATA300
34, 148, 254, 523, 442, 149,
36, 150
I
Cell data input of receive interface 3.
Cell data is input from a PHY layer device in byte units.
The µPD98412 reads the data at the rising edge of UCLK3.
RXDATA307 is the MSB.
RXSOC3
257
I
Cell transfer start signal of receive interface 3.
This signal is input from a PHY layer device in synchronization with
the first byte of cell data.
RXENB3_B
151
O
Transfer enable signal of receive interface 3.
This signal informs a PHY layer device that the µPD98412 is ready
for reception in the next clock cycle.
RXCLAV3
38
I
Cell transfer enable signal of receive interface 3.
This pin inputs a signal that indicates that no more cells will be
supplied to the µPD98412 after the current cell has been
transferred.
UCLK3
354
I
UTOPIA clock input of receive interface 3.
Data is transferred/received at the rising edge of this clock.
30
Function
Data Sheet S14237EJ2V0DS00
µPD98412
Table 1-3. Transmit Interface Signals (1/2)
Symbol
Pin No.
I/O
Function
TXADDR03 TXADDR00
97, 207, 98, 402
O
Multi-PHY select address of transmit interface 0.
TXADDR03 is the MSB.
TXDATA007 TXDATA000
310, 209, 100, 404, 311, 210,
102, 211
O
Cell data output of transmit interface 0.
Cell data is output to a PHY layer device in byte units.
The µPD98412 outputs the data at the rising edge of UCLK0.
TXDATA007 is the MSB.
(3-state buffer)
TXSOC0
99
O
Cell transfer start signal of transmit interface 0.
This signal is output to a PHY layer device in synchronization with
the first byte of cell data.
(3-state buffer)
TXENB0_B
403
O
Transfer enable signal of transmit interface 0.
This signal informs a PHY layer device that the µPD98412 outputs
data in the current clock cycle.
TXCLAV0
208
I
Cell transfer enable signal of transmit interface 0.
This pin inputs a signal that indicates that the µPD98412 is ready
to receive the next cell after transfer of the current cell is
completed.
TXADDR13 TXADDR10
163, 51, 268, 164
O
Multi-PHY select address of transmit interface 1.
TXADDR13 is the MSB.
TXDATA107 TXDATA100
53, 366, 270, 166, 54, 271,
167, 536
O
Cell data output of transmit interface 1.
The µPD98412 outputs the data at the rising edge of UCLK1.
TXDATA107 is the MSB.
(3-state buffer)
TXSOC1
269
O
Cell transfer start signal of transmit interface 1.
This signal is output to a PHY layer device in synchronization with
the first byte of cell data.
(3-state buffer)
TXENB1_B
165
O
Transfer enable signal of transmit interface 1.
This signal informs a PHY layer device that the µPD98412 outputs
data in the current clock cycle.
TXCLAV1
52
I
Cell transfer enable signal of transmit interface 1.
This pin inputs a signal that indicates that the µPD98412 is ready
to receive the next cell after transfer of the current cell is
completed.
Data Sheet S14237EJ2V0DS00
31
µPD98412
Table 1-3. Transmit Interface Signals (2/2)
Symbol
Pin No.
I/O
TXADDR23 TXADDR20
216, 108, 409, 317
O
Multi-PHY select address of transmit interface 2.
TXADDR23 is the MSB.
TXDATA207 TXDATA200
572, 411, 319, 219, 111, 412,
320, 220
O
Cell data output of transmit interface 2.
The µPD98412 outputs the data at the rising edge of UCLK2.
TXDATA207 is the MSB.
(3-state buffer)
TXSOC2
318
O
Cell transfer start signal of transmit interface 2.
This signal is output to a PHY layer device in synchronization with
the first byte of cell data.
(3-state buffer)
TXENB2_B
218
O
Transfer enable signal of transmit interface 2.
This signal informs a PHY layer device that the µPD98412 outputs
data in the current clock cycle.
TXCLAV2
109
I
Cell transfer enable signal of transmit interface 2.
This pin inputs a signal that indicates that the µPD98412 is ready
to receive the next cell after transfer of the current cell is
completed.
TXADDR33 TXADDR30
40, 356, 259, 154
O
Multi-PHY select address of transmit interface 3.
TXADDR33 is the MSB.
TXDATA307 TXDATA300
42, 358, 261, 44, 157, 359,
262, 45
O
Cell data output of transmit interface 3.
The µPD98412 outputs the data at the rising edge.
TXDATA307 is the MSB.
(3-state buffer)
TXSOC3
260
O
Cell transfer start signal of transmit interface 3.
This signal is output to a PHY layer device in synchronization with
the first byte of cell data.
(3-state buffer)
TXENB3_B
155
O
Transfer enable signal of transmit interface 3.
This signal informs a PHY layer device that the µPD98412 outputs
data in the current clock cycle.
TXCLAV3
357
I
Cell transfer enable signal of transmit interface 3.
This pin inputs a signal that indicates that the µPD98412 is ready
to receive the next cell after transfer of the current cell is
completed.
32
Function
Data Sheet S14237EJ2V0DS00
µPD98412
(2) 16-bit multiplexed status polling mode
Table 1-4. Receive Interface Signals
Symbol
Pin No.
I/O
Function
RXADDR04 RXADDR00
316, 205, 206, 563, 486
O
Multi-PHY select address of receive interface 0.
RXADDR04 is the MSB.
RXDATA015 RXDATA000
405, 312, 103, 212, 568, 491,
104, 213, 303, 397, 92, 202,
93, 561, 484, 203
I
Cell data input of receive interface 0.
Cell data is input from a PHY layer device in 16-bit units.
The µPD98412 reads the data at the rising edge of UCLK0.
RXDATA015 is the MSB.
RXSOC0
306
I
Cell transfer start signal of receive interface 0.
This signal is input from a PHY layer device in synchronization with
the first byte of cell data.
RXENB0_B
204
O
Transfer enable signal of receive interface 0.
This signal informs a PHY layer device that the µPD98412 is ready
for reception in the next clock cycle.
RXCLAV0[0] RXCLAV0[3]
95, 400, 106, 214
I
Cell transfer enable signal of receive interface 0.
This pin inputs a signal that indicates that no more cells will be
supplied to the µPD98412. Pins to be connected (RXCLAV0[0][3]) differ depending on PHY address of the connected PHY
device.
UCLK0
399
I
UTOPIA clock input of receive interface 0.
Data is transferred/received at the rising edge of this clock.
RXADDR14 RXADDR10
153, 266, 50, 363, 267
O
Multi-PHY select address of receive interface 1.
RXADDR14 is the MSB.
RXDATA115 RXDATA100
34, 148, 254, 523, 442, 149,
36, 150, 158, 263, 449, 46,
159, 264, 361, 47
I
Cell data input of receive interface 1.
Cell data is input from a PHY layer device in 16-bit units.
The µPD98412 reads the data at the rising edge of UCLK1.
RXDATA115 is the MSB.
RXSOC1
451
I
Cell transfer start signal of receive interface 1.
This signal is input from a PHY layer device in synchronization with
the first byte of cell data.
RXENB1_B
362
O
Transfer enable signal of receive interface 1.
This signal informs a PHY layer device that the µPD98412 is ready
for reception in the next clock cycle.
RXCLAV1[0] RXCLAV1[3]
49, 532, 38, 257
I
Cell transfer enable signal of receive interface 1.
This pin inputs a signal that indicates that no more cells will be
supplied to the µPD98412 after the current cell has been
transferred. Pins to be connected (RXCLAV1[0]-[3]) differ
depending on PHY address of the connected PHY device.
UCLK1
48
I
UTOPIA clock input of receive interface 1.
Data is transferred/received at the rising edge of this clock.
Data Sheet S14237EJ2V0DS00
33
µPD98412
Table 1-5. Transmit Interface Signals
Symbol
Pin No.
I/O
Function
TXADDR04 TXADDR00
317, 97, 207, 98, 402
O
Multi-PHY select address of transmit interface 0.
TXADDR04 is the MSB.
TXDATA015 TXDATA000
572, 411, 319, 219, 111, 412,
320, 220, 310, 209, 100, 404,
311, 210, 102, 211
O
Cell data output of transmit interface 0.
Cell data is output to a PHY layer device in 16-bit units.
The µPD98412 outputs the data at the rising edge of UCLK0.
TXDATA015 is the MSB.
(3-state buffer)
TXSOC0
99
O
Cell transfer start signal of transmit interface 0.
This signal is output to a PHY layer device in synchronization with
the first byte of cell data.
(3-state buffer)
TXENB0_B
403
O
Transfer enable signal of transmit interface 0.
This signal informs a PHY layer device that the µPD98412 outputs
data in the current clock cycle.
TXCLAV0[0] TXCLAV0[3]
208, 309, 109, 217
I
Cell transfer enable signal of transmit interface 0.
This pin inputs a signal that indicates that the µPD98412 is ready
to receive the next cell after transfer of the current cell is
completed. Pins to be connected (TXCLAV0[0]-[3]) differ
depending on PHY address of the connected PHY device.
TXADDR14 TXADDR10
154, 163, 51, 268, 164
O
Multi-PHY select address of transmit interface 1.
TXADDR14 is the MSB.
TXDATA115 TXDATA100
42, 358, 261, 44, 157, 359,
262, 45, 53, 366, 270, 166,
54, 271, 167, 536
O
Cell data output of transmit interface 1.
The µPD98412 outputs the data at the rising edge of UCLK1.
TXDATA115 is the MSB.
(3-state buffer)
TXSOC1
269
O
Cell transfer start signal of transmit interface 1.
This signal is output to a PHY layer device in synchronization with
the first byte of cell data.
(3-state buffer)
TXENB1_B
165
O
Transfer enable signal of transmit interface 1.
This signal informs a PHY layer device that the µPD98412 outputs
data in the current clock cycle.
TXCLAV1[0] TXCLAV1[3]
52, 534, 357, 41
I
Cell transfer enable signal of transmit interface 1.
This pin inputs a signal that indicates that the µPD98412 is ready
to receive the next cell after transfer of the current cell is
completed. Pins to be connected (TXCLAV1[0]-[3]) differ
depending on PHY address of the connected PHY device.
34
Data Sheet S14237EJ2V0DS00
µPD98412
(3) 16-bit 2-group weighted polling mode
Table 1-6. Receive Interface Signals (1/2)
Symbol
Pin No.
I/O
Function
RXADDR0A3 RXADDR0A0
205, 206, 563, 486
O
Multi-PHY select address of receive interface 0, group A.
RXADDR0A3 is the MSB.
RXADDR0B3 RXADDR0B0
408, 493, 107, 316
O
Multi-PHY select address of receive interface 0, group B.
RXADDR0B3 is the MSB.
RXENB0A_B
204
O
Transfer enable signal of receive interface 0, group A.
This signal informs a PHY layer device that the µPD98412 is ready
for reception in the next clock cycle.
RXENB0B_B
105
O
Transfer enable signal of receive interface 0, group B.
This signal informs a PHY layer device that the µPD98412 is ready
for reception in the next clock cycle.
RXCLAV0A
95
I
Cell transfer enable signal of receive interface 0, group A.
This pin inputs a signal that indicates that no more cells will be
supplied to the µPD98412 after the current cell has been
transferred.
RXCLAV0B
106
I
Cell transfer enable signal of receive interface 0, group B.
This pin inputs a signal that indicates that no more cells will be
supplied to the µPD98412 after the current cell has been
transferred.
RXDATA015 RXDATA000
405, 312, 103, 212, 568, 491,
104, 213, 303, 397, 92, 202,
93, 561, 484, 203
I
Cell data input of receive interface 0.
Cell data is input from a PHY layer device in 16-bit units.
The µPD98412 reads the data at the rising edge of UCLK0.
RXDATA015 is the MSB.
RXSOC0
306
I
Cell transfer start signal of receive interface 0.
This signal is input from a PHY layer device in synchronization with
the first byte of cell data.
UCLK0
399
I
UTOPIA clock input of receive interface 0.
Data is transferred/received at the rising edge of this clock.
Data Sheet S14237EJ2V0DS00
35
µPD98412
Table 1-6. Receive Interface Signals (2/2)
Symbol
Pin No.
I/O
Function
RXADDR1A3 RXADDR1A0
266, 50, 363, 267
O
Multi-PHY select address of receive interface 1, group A.
RXADDR1A3 is the MSB.
RXADDR1B3 RXADDR1B0
525, 355, 258, 153
O
Multi-PHY select address of receive interface 1, group B.
RXADDR1B3 is the MSB.
RXENB1A_B
362
O
Transfer enable signal of receive interface 1, group A.
This signal informs a PHY layer device that the µPD98412 is ready
for reception in the next clock cycle.
RXENB1B_B
151
O
Transfer enable signal of receive interface 1, group B.
This signal informs a PHY layer device that the µPD98412 is ready
for reception in the next clock cycle.
RXCLAV1A
49
I
Cell transfer enable signal of receive interface 1, group A.
This pin inputs a signal that indicates that no more cells will be
supplied to the µPD98412 after the current cell has been
transferred.
RXCLAV1B
38
I
Cell transfer enable signal of receive interface 1, group B.
This pin inputs a signal that indicates that no more cells will be
supplied to the µPD98412 after the current cell has been
transferred.
RXDATA115 RXDATA100
34, 148, 254, 523, 442, 149,
36, 150, 158, 263, 449, 46,
159, 264, 361, 47
I
Cell data input of receive interface 1.
Cell data is input from a PHY layer device in 16-bit units.
The µPD98412 reads the data at the rising edge of UCLK1.
RXDATA115 is the MSB.
RXSOC1
451
I
Cell transfer start signal of receive interface 1.
This signal is input from a PHY layer device in synchronization with
the first byte of cell data.
UCLK1
48
I
UTOPIA clock input of receive interface 1.
Data is transferred/received at the rising edge of this clock.
36
Data Sheet S14237EJ2V0DS00
µPD98412
Table 1-7. Transmit Interface Signals (1/2)
Symbol
Pin No.
I/O
Function
TXADDR0A3 TXADDR0A0
97, 207, 98, 402
O
Multi-PHY select address of transmit interface 0, group A.
TXADDR0A3 is the MSB.
TXADDR0B3 TXADDR0B0
216, 108, 409, 317
O
Multi-PHY select address of transmit interface 0, group B.
TXADDR0B3 is the MSB.
TXENB0A_B
403
O
Transfer enable signal of transmit interface 0, group A.
This signal informs a PHY layer device that the µPD98412 outputs
data in the current clock cycle.
TXENB0B_B
218
O
Transfer enable signal of transmit interface 0, group B.
This signal informs a PHY layer device that the µPD98412 outputs
data in the current clock cycle.
TXCLAV0A
208
I
Cell transfer enable signal of transmit interface 0, group A.
This pin inputs a signal that indicates that the µPD98412 is ready
to receive the next cell after transfer of the current cell is
completed.
TXCLAV0B
109
I
Cell transfer enable signal of transmit interface 0, group B.
This pin inputs a signal that indicates that the µPD98412 is ready
to receive the next cell after transfer of the current cell is
completed.
TXDATA015 TXDATA000
572, 411, 319, 219, 111, 412,
320, 220, 310, 209, 100, 404,
311, 210, 102, 211
O
Cell data output of transmit interface 0.
Cell data is output to a PHY layer device in 16-bit units.
The µPD98412 outputs the data at the rising edge of UCLK0.
TXDATA015 is the MSB.
(3-state buffer)
TXSOC0
99
O
Cell transfer start signal of transmit interface 0.
This signal is output to a PHY layer device in synchronization with
the first byte of cell data.
(3-state buffer)
Data Sheet S14237EJ2V0DS00
37
µPD98412
Table 1-7. Transmit Interface Signals (2/2)
Symbol
Pin No.
I/O
Function
TXADDR1A3 TXADDR1A0
163, 51, 268, 164
O
Multi-PHY select address of transmit interface 1, group A.
TXADDR1A3 is the MSB.
TXADDR1B3 TXADDR1B0
40, 356, 259, 154
O
Multi-PHY select address of transmit interface 1, group B.
TXADDR1B3 is the MSB.
TXENB1A_B
165
O
Transfer enable signal of transmit interface 1, group A.
This signal informs a PHY layer device that the µPD98412 outputs
data in the current clock cycle.
TXENB1B_B
155
O
Transfer enable signal of transmit interface 1, group B.
This signal informs a PHY layer device that the µPD98412 outputs
data in the current clock cycle.
TXCLAV1A
52
I
Cell transfer enable signal of transmit interface 1, group A.
This pin inputs a signal that indicates that the µPD98412 is ready
to receive the next cell after transfer of the current cell is
completed.
TXCLAV1B
357
I
Cell transfer enable signal of transmit interface 1, group B.
This pin inputs a signal that indicates that the µPD98412 is ready
to receive the next cell after transfer of the current cell is
completed.
TXDATA115 TXDATA100
42, 358, 261, 44, 157, 359,
262, 45, 53, 366, 270, 166,
54, 271, 167, 536
O
Cell data output of transmit interface 1.
Cell data is output to a PHY layer device in 16-bit units.
The µPD98412 outputs the data at the rising edge of UCLK1.
TXDATA115 is the MSB.
(3-state buffer)
TXSOC1
269
O
Cell transfer start signal of transmit interface 1.
This signal is output to a PHY layer device in synchronization with
the first byte of cell data.
(3-state buffer)
38
Data Sheet S14237EJ2V0DS00
µPD98412
(4) 16-bit 1-group weighted polling mode
Table 1-8. Receive Interface Signals
Symbol
Pin No.
I/O
Function
RXADDR04 RXADDR00
316, 205, 206, 563, 486
O
Multi-PHY select address of receive interface 0.
RXADDR04 is the MSB.
RXDATA015 RXDATA000
405, 312, 103, 212, 568, 491,
104, 213, 303, 397, 92, 202,
93, 561, 484, 203
I
Cell data input of receive interface 0.
Cell data is input from a PHY layer device in 16-bit units.
The µPD98412 reads the data at the rising edge of UCLK0.
RXDATA015 is the MSB.
RXSOC0
306
I
Cell transfer start signal of receive interface 0.
This signal is input from a PHY layer device in synchronization with
the first byte of cell data.
RXENB0_B
204
O
Transfer enable signal of receive interface 0.
This signal informs a PHY layer device that the µPD98412 is ready
for reception in the next clock cycle.
RXCLAV0
95
I
Cell transfer enable signal of receive interface 0.
This pin inputs a signal that indicates that no more cells will be
supplied to the µPD98412 after the current cell has been
transferred.
UCLK0
399
I
UTOPIA clock input of receive interface 0.
Data is transferred/received at the rising edge of this clock.
RXADDR14 RXADDR10
153, 266, 50, 363, 267
O
Multi-PHY select address of receive interface 1.
RXADDR14 is the MSB.
RXDATA115 RXDATA100
34, 148, 254, 523, 442, 149,
36, 150, 158, 263, 449, 46,
159, 264, 361, 47
I
Cell data input of receive interface 1.
Cell data is input from a PHY layer device in 16-bit units.
The µPD98412 reads the data at the rising edge of UCLK1.
RXDATA115 is the MSB.
RXSOC1
451
I
Cell transfer start signal of receive interface 1.
This signal is input from a PHY layer device in synchronization with
the first byte of cell data.
RXENB1_B
362
O
Transfer enable signal of receive interface 1.
This signal informs a PHY layer device that the µPD98412 is ready
for reception in the next clock cycle.
RXCLAV1
49
I
Cell transfer enable signal of receive interface 1.
This pin inputs a signal that indicates that no more cells will be
supplied to the µPD98412 after the current cell has been
transferred.
UCLK1
48
I
UTOPIA clock input of receive interface 1.
Data is transferred/received at the rising edge of this clock.
Data Sheet S14237EJ2V0DS00
39
µPD98412
Table 1-9. Transmit Interface Signals
Symbol
Pin No.
I/O
Function
TXADDR04 TXADDR00
317, 97, 207, 98, 402
O
Multi-PHY select address of transmit interface 0.
TXADDR04 is the MSB.
TXDATA015 TXDATA000
572, 411, 319, 219, 111, 412,
320, 220, 310, 209, 100, 404,
311, 210, 102, 211
O
Cell data output of transmit interface 0.
Cell data is output to a PHY layer device in 16-bit units.
The µPD98412 outputs the data at the rising edge of UCLK0.
TXDATA015 is the MSB.
(3-state buffer)
TXSOC0
99
O
Cell transfer start signal of transmit interface 0.
This signal is output to a PHY layer device in synchronization with
the first byte of cell data.
(3-state buffer)
TXENB0_B
403
O
Transfer enable signal of transmit interface 0.
This signal informs a PHY layer device that the µPD98412 outputs
data in the current clock cycle.
TXCLAV0
208
I
Cell transfer enable signal of transmit interface 0.
This pin inputs a signal that indicates that the µPD98412 is ready
to receive the next cell after transfer of the current cell is
completed.
TXADDR14 TXADDR10
154, 163, 51, 268, 164
O
Multi-PHY select address of transmit interface 1.
TXADDR14 is the MSB.
TXDATA115 TXDATA100
42, 358, 261, 44, 157, 359,
262, 45, 53, 366, 270, 166,
54, 271, 167, 536
O
Cell data output of transmit interface 1.
The µPD98412 outputs the data at the rising edge of UCLK1.
TXDATA115 is the MSB.
(3-state buffer)
TXSOC1
269
O
Cell transfer start signal of transmit interface 1.
This signal is output to a PHY layer device in synchronization with
the first byte of cell data.
(3-state buffer)
TXENB1_B
165
O
Transfer enable signal of transmit interface 1.
This signal informs a PHY layer device that the µPD98412 outputs
data in the current clock cycle.
TXCLAV1
52
I
Cell transfer enable signal of transmit interface 1.
This pin inputs a signal that indicates that the µPD98412 is ready
to receive the next cell after transfer of the current cell is
completed.
40
Data Sheet S14237EJ2V0DS00
µPD98412
1.3 Memory Interface Signals
The µPD98412 has two types of memory interfaces. One of them is used to store a cell header translation table
and an address pointer to the cell buffer to the HTT & control memory, and the other is used to store cell data to the
cell buffer memory. Table 1-10 shows the interface signals of the HTT & control memory. Table 1-11 shows the
interface signals of the cell buffer memory.
Table 1-10. HTT & Control Memory Interface Signals
Symbol
Pin No.
I/O
Function
HTA17 HTA00
11, 333, 234, 127, 12, 334, 235, 128,
13, 335, 236, 15, 130, 336, 237, 16,
131, 238
O
Address output
HTD31 HTD00
18, 133, 19, 430, 513, 134, 135, 21,
242, 136, 22, 137, 432, 515, 23, 138,
343, 245, 139, 344, 246, 140, 517, 345,
141, 27, 28, 346, 248, 142, 29, 249
I/O
Data I/O bus (32-bit/word units)
(w/pull-down resistor)
HTP3 HTP0
338, 340, 24, 247
I/O
Parity I/O (w/pull-down resistor)
HTCS1_B,
HTCS0_B
428, 17
O
Chip select signal
HTWE_B
132
O
Write enable signal
HTOE_B
239
O
Output enable signal
Table 1-11. Cell Buffer Memory Interface Signals
Symbol
Pin No.
I/O
Function
CBA17 CBA00
71, 381, 286, 73, 184, 382, 287, 74,
185, 288, 470, 75, 186, 289, 384, 76,
187, 77
O
Address output
CBD91 CBD00
145, 251, 349, 439, 55, 272, 168, 56,
457, 369, 273, 170, 274, 538, 59, 171,
275, 172, 276, 372, 540, 373, 277, 62,
174, 278, 374, 63, 175, 279, 542, 463,
176, 65, 177, 281, 377, 66, 178, 179,
544, 465, 68, 180, 69, 379, 284, 181,
472, 551, 188, 189, 79, 386, 292, 190,
80, 191, 474, 553, 294, 192, 82, 389,
295, 193, 83, 296, 194, 555, 391, 297,
195, 85, 478, 392, 298, 197, 299, 557,
88, 198, 300, 199, 301, 395, 90, 559,
302, 200, 91, 201
I/O
Data bus (92-bit/word units)
(w/pull-down resistor)
CBCS1_B,
CBCS0_B
70, 380
O
Chip select signal
CBWE_B
285
O
Write enable signal
CBOE_B
182
O
Output enable signal
Data Sheet S14237EJ2V0DS00
41
µPD98412
1.4 Microprocessor Interface Signals
The µPD98412 supports a 32-bit address/data multiplexed synchronous bus type microprocessor interface.
Table 1-12. Microprocessor Interface Signal
Symbol
Pin No.
I/O
Function
IOCS_B
221
I
I/O chip select signal
MCS_B
574
I
Memory chip select signal
INT
414
O
Interrupt request signal
HCLK
497
I
Microprocessor bus clock (8 to 33 MHz)
AD31 - AD0
416, 1, 117, 225, 118, 226, 326, 3, 502,
227, 419, 4, 120, 228, 328, 5, 121, 229,
504, 421, 122, 7, 123, 231, 331, 8, 124,
125, 506, 423, 10, 126
R/W_B
114
I
Read/write select signal
UWE_B
115
I
High-order word enable signal
RDY_B
322
O
Ready signal (3-state buffer)
42
I/O
Address/data bus
Data Sheet S14237EJ2V0DS00
µPD98412
1.5 JTAG
Table 1-13. JTAG Interface Signals
Symbol
Pin No.
I/O
Function
JDI
252
I
JTAG serial data input
JDO
146
O
JTAG serial data output (normally open)
(3-state buffer)
JCK
33
I
JTAG serial clock input
JMS
253
I
JTAG mode select signal
JRST_B
351
I
JTAG reset signal
1.6 Others
Table 1-14. Other Interface Signals
Symbol
Pin No.
I/O
Function
SWCLK
437
I
System clock input (8 to 40 MHz)
RESET_B
347
I
Hardware reset signal (Schmitt input buffer)
CG
116, 222, 223, 321, 415
I
Always connect to GND.
PU
30
I
Always pull up to VDD.
IC
224, 250, 348, 350, 500
O
Internally connected (always open).
Data Sheet S14237EJ2V0DS00
43
µPD98412
1.7 Recommended Connections of Unused Pins
Table 1-15. Recommended Connections of Unused Pins
Pin Name
I/O
Recommended Connections
RXDATA***
I
Connect to GND.
RXSOC*
I
Connect to GND.
RXCLAV*
I
Connect to GND.
UCLK*
I
Connect to GND.
TXCLAV*
I
Connect to GND.
HTD31 - HTD00
I/O (w/pull-down resistor)
Open.
HTP3 - HTP0
I/O (w/pull-down resistor)
Open.
CBD91 - CBD00
I/O (w/pull-down resistor)
Open.
IOCS_B
I
Pull up to VDD.
MCS_B
I
Pull up to VDD.
I/O
Pull up to VDD.
R/W_B
I
Pull up to VDD.
UWE_B
I
Pull up to VDD.
JDI
I
Connect to GND.
JCK
I
Connect to GND.
JMS
I
Connect to GND.
JRST_B
I
Connect to GND.
All output pins
O
Open.
AD31 - AD00
44
Data Sheet S14237EJ2V0DS00
µPD98412
1.8 Pin Status at Reset
Table 1-16. Pin Status at Reset
Pin Name
I/O
Pin Status at Reset
RXADDR*
O
High level
RXENB*_B
O
High level
TXADDR*
O
High level
TXDATA***
O (3-state buffer)
Hi-Z
TXSOC*
O (3-state buffer)
Hi-Z
TXENB*_B
O
High level
HTA17 - HTA00
O
Low level
HTCS1_B, HTCS0_B
O
High level
HTWE_B
O
High level
HTOE_B
O
High level
HTP3 - HTP0
I/O (w/pull-down resistor)
Low level
HTD31 - HTD00
I/O (w/pull-down resistor)
Low level
CBD91 - CBD00
I/O (w/pull-down resistor)
Low level
CBA17 - CBA00
O
Low level
CBOE_B
O
High level
CBWE_B
O
High level
CBCS1_B, CBCS0_B
O
High level
INT
O
Low level
RDY_B
AD31 - AD00
JDO
O (3-state buffer)
Hi-Z
I/O
Hi-Z
O (3-state buffer)
Hi-Z
Data Sheet S14237EJ2V0DS00
45
µPD98412
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter
Symbol
Supply voltage
Test Conditions
VDD
Rating
Unit
−0.5 to +4.6
V
Input voltage
VI
VI < VDD + 3.0 V
−0.5 to +6.6
V
Output voltage
VO
VO < VDD + 3.0 V
−0.5 to +6.6
V
Storage temperature
Tstg
−65 to +150
°C
Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of
the product may be impaired. The absolute maximum ratings are values that may physically
damage the product(s). Be sure to use the product(s) within the ratings.
Capacitance
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
CI
Frequency = 1 MHz
−
10
20
pF
Output capacitance
CO
Frequency = 1 MHz
−
10
20
pF
Input/output capacitance
CIO
Frequency = 1 MHz
−
10
20
pF
MIN.
TYP.
MAX.
Unit
3.135
3.300
3.465
V
Recommended Operating Condition
Parameter
Symbol
Test Conditions
Supply voltage
VDD
Low-level input voltage
VIL
Other than RESET_B
signal
0
−
0.8
V
High-level input voltage
VIH
Other than RESET_B
signal
2.0
−
5.5
V
Negative trigger voltage
VN
RESET_B signal
0.6
1.8
V
Positive trigger voltage
VP
RESET_B signal
1.2
2.4
V
Hysteresis voltage
VH
0.3
1.5
V
Operating temperature
TA
−40
+85
°C
46
Data Sheet S14237EJ2V0DS00
−
µPD98412
DC Characteristics (TA = −40 to +85 °C, VDD = 3.3 V ±5%)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Output leakage current
IOZ
VO = VDD or GND
−
−
±10
µA
Input leakage current
ILI1
VI = VDD or GND, Note 1
−
−
±10
µA
ILI2
VI = VDD
Note 2 (50 kΩ pull-down)
25
120
220
µA
IOL1
VOL = 0.4 V, Note 3
6.0
−
−
mA
Low-level output leakage current
IOL2
VOL = 0.4 V, Note 4, 5
9.0
−
−
mA
IOL3
VOL = 0.4 V, Note 6
12.0
−
−
mA
IOH1
VOH = 2.4 V, Note 3
−3.0
−
−
mA
IOH2
VOH = 2.4 V, Note 4
−4.0
−
−
mA
IOH2
VOH = 2.4 V, Note 5 (UTOPIA)
−6.0
−
−
mA
IOH3
VOH = 2.4 V, Note 6
−5.0
−
−
mA
Low-level output leakage voltage
VOL
IOL = 0 mA
−
−
0.1
V
High-level output leakage voltage
VOH1
IOH = 0 mA, Note 7
VDD − 0.2
−
−
V
VOH2
IOH = 0 mA, Note 8
VDD − 0.4
−
−
V
−
Note 9
1300
mA
High-level output leakage current
Operating current
IDD
VI = VDD or GND
Notes 1. RXDATA***, RXSOC*, RXCLAV*, UCLK*, TCLAV*, AD31-AD00, MCS_B, IOCS_B, R/W_B, UWE_B,
HCLK, JDI, JCK, JMS, JRST_B, SWCLK, RESET_B pins
2. HTD31-HTD00, HTP3-HTP0, CBD91-CBD00 pins
3. INT, JDO pins
4. HTA17-HTA00, HTWE_B, HTOE_B, CBA17-CBA00, CBCS0_B, CBWE_B, CBOE_B, HTCS1_B,
HTCS0_B, CBCS1_B, HTD31-HTD00, HTP3-HTP0, CBD91-CBD00 pins
5. RXADDR**, TXADDR**, RXENB*_B, TXENB*_B, TXDATA***, TXSOC* pins
6. RDY_B, AD31-AD00 pins
7. INT, JDO, RXADDR**, TXADDR**, RXENB*_B, TXENB*_B, TXDATA***, TXSOC*, HTCS1_B,
HTCS0_B, CBCS1_B, HTA17-HTA00, HTWE_B, HTOE_B, CBA17-CBA00, CBCS0_B, CBWE_B,
CBOE_B, RDY_B, AD31-AD00 pins
8. HTD31-HTD00, HTP3-HTP0, CBD91-CBD00 pins
9. The approximate TYP. value of the operating current (IDD) depends on the throughput of switching.
For example with the following conditions, it is calculated as shown below.
Conditions: 8-bit UTOPIA interface × 4 ports, SWCLK = 40 MHz, UCLK0 to UCLK3 = 50 MHz
Calculation formula: IDD (TYP.) = 267 × t + 600 mA, t (throughput): 0 − 1.5 [Unit: Gbps]
Data Sheet S14237EJ2V0DS00
47
µPD98412
AC Test Output Waveform
2.2 V
2.0 V
2.0 V
Test point
0.8 V
0.8 V
0.4 V
AC Characteristics (TA = −40 to +85 °C, VDD = 3.3 V ±5%)
(1) Control Signal
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SWCLK cycle time
tCYSL
25
125
ns
SWCLK high-level width
tWSKH
10.5
−
ns
SWCLK low-level width
tWSKL
10.5
−
ns
SWCLK rise time
tSKR
−
2
ns
SWCLK fall time
tSKF
−
2
ns
RESET_B low-level width
tWRSL
16
−
tCYSK
Control Signal
tCYSK
tWSKH
tWSKL
SWCLK
in
tSKR
tSKF
RESET_B
in
tWRSL
48
Data Sheet S14237EJ2V0DS00
µPD98412
(2) Processor interface (32-bit mode, read/write)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
HCLK cycle time
tCYHK
30
125
ns
HCLK high-level width
tWHKH
12
−
ns
HCLK low-level width
tWHKL
12
−
ns
HCLK rise time
tHKR
−
3
ns
HCLK fall time
tHKF
−
3
ns
HCLK ↑→ INT output delay time
tDHKIT
Load capacitance 30 pF
1
17
ns
HCLK ↑→ RDY_B output delay
time
tDHKRY
Load capacitance 70 pF
1
17
ns
HCLK ↑→ RDY_B float output
delay time
tFHKRY
Load capacitance 70 pF
1
17
ns
HCLK ↑→ AD output delay time
tDHKAD
Load capacitance 70 pF
1
17
ns
HCLK ↑→ AD float output delay
time
tFHKAD
Load capacitance 70 pF
1
17
ns
AD setup time (vs. HCLK ↑)
tSADHK
8
−
ns
AD hold time (vs. HCLK ↑)
tHHKAD
1
−
ns
IOCS_B setup time (vs. HCLK ↑)
tSIOHK
8
−
ns
IOCS_B hold time (vs. HCLK ↑)
tHHKIO
1
−
ns
IOCS_B recovery time
tIORV
Note
−
ns
MCS_B setup time (vs. HCLK ↑)
tSMHK
8
−
ns
MCS_B hold time (vs. HCLK ↑)
tHHKM
1
−
ns
MCS_B recovery time
tMRV
Note
−
ns
UWE_B setup time (vs. HCLK ↑)
tSUWHK
8
−
ns
UWE_B hold time (vs. HCLK ↑)
tHHKUW
1
−
ns
R/W_B setup time (vs. HCLK ↑)
tSRWHK
8
−
ns
R/W_B hold time (vs. HCLK ↑)
tHHKRW
1
−
ns
Note
(1) When HCLK cycle time (tCYHK) < 4 × SWCLK cycle time (tCYSK):
IOCS_B recovery time (tIORV) = MCS_B recovery time (tMRV) = tCYHK
(2) When HCLK cycle time (tCYHK) ≥ 4 × SWCLK cycle time (tCYSK):
IOCS_B recovery time (tIORV) = MCS_B recovery time (tMRV) = tCYHK × 2
Data Sheet S14237EJ2V0DS00
49
µPD98412
Processor interface (32-bit mode, read)
tCYHK
tWHKH tWHKL
HCLK
in
tHKR tHKF tSADHK tHHKAD
AD31 - AD00
in/out
tFHKAD
tDHKAD
data
address
address
tSIOHK
tHHKIO
tIORV
tSMHK
tHHKW
tMRV
IOCS_B
in
MCS_B
in
tSUWHK
tHHKUW
UME_B
in
tSRWHK
tHHKRW
R/W_B
in
tDHKRY
tDHKRY
RDY_B
out
(Hi-Z)
(Hi-Z)
HCLK
in
INT
out
50
tDHKIT
Data Sheet S14237EJ2V0DS00
tFHKRY
tDHKIT
µPD98412
Processor interface (32-bit mode, write)
tCYHK
tWHKH tWHKL
HCLK
in
tHKR tHKF tSADHK tHHKAD
AD31 - AD00
in/out
address
tSADHK
tHHKAD
data
Don’t care
tSIOHK
tHHKIO
tIORV
tSMHK
tHHKW
tMRV
IOCS_B
in
MOS_B
in
tSUWHK
tHHKUW
UME_B
in
tSRWHK
tHHKRW
R/W_B
in
tDHKRY tDHKRY
RDY_B
out
(Hi-Z)
Data Sheet S14237EJ2V0DS00
tFHKRY
(Hi-Z)
51
µPD98412
(3) HTT & control memory interface
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
tCYSK − 2
ns
tSHDHA
9
ns
HTD, HTP hold time (vs. HTA)
tHHAHD
1
ns
HTCS_B cycle time
tCYHC
tCYSK − 2
ns
HTD, HTP setup time
(vs. HTCS_B)
tSHDHC
9
ns
HTD, HTP hold time
(vs. HTCS_B)
tHHCHD
1
ns
HTOE_B cycle time
tCYHO
tCYSK − 2
ns
HTD, HTP setup time
(vs. HTOE_B)
tSHDHO
9
ns
HTD, HTP hold time
(vs. HTOE_B)
tHHOHD
1
ns
HTWE_B low-level width
tWHWL
Load capacitance 50 pF
tWSKL − 1.5
ns
Data → HTWE_B ↑ output delay
time
tDHDHW
Load capacitance 50 pF
tWSKL − 3
ns
HTWE_B ↑→ Data float output
delay time
tFHWHD
Load capacitance 50 pF
0
ns
HTA → HTWE_B ↓ output delay
time
tDHAHW
Load capacitance 50 pF
tWSKH − 5
ns
HTCS_B ↓→ HTWE_B ↑ output
delay time
tDHCHW
Load capacitance 50 pF
tCYSK − 6
ns
HTOE_B ↑→ HTWE_B ↑ output
delay time
tDHOHW
Load capacitance 50 pF
tCYSK − 6
ns
HTWE_B ↑→ HTA output delay
time
tDHWHA
Load capacitance 50 pF
0
ns
HTWE_B ↑→ HTCS_B ↑ output
delay time
tDHWHC
Load capacitance 50 pF
0
ns
HTWE_B ↑→ HTOE_B ↓ output
delay time
tDHWHO
Load capacitance 50 pF
0
ns
HTD float → HTOE_B ↓ output
delay time
tDHDHO
Load capacitance 50 pF
0
ns
HTOE_B ↑→ Data output delay
time
tDHOHD
Load capacitance 50 pF
tWSKH − 3
ns
HTA cycle time
tCYHA
HTD, HTP setup time (vs. HTA)
52
Load capacitance 50 pF
Load capacitance 50 pF
Load capacitance 50 pF
Data Sheet S14237EJ2V0DS00
µPD98412
HTT & control memory interface (read)
(SWCLK)
in
tCYHA
HTA17 - HTA00
out
address
tSHDHA
HTD31 - HTD00,
HTP3-HTP0
in/out
(Hi-Z)
tHHAHD
(Hi-Z)
data
tCYHC
HTCS1_B,
HTCS0_B
out
tCYHO
tSHDHC
tHHCHD
tSHDHO
tHHOHD
HTOE_B
out
HTWE_B
out
HTT & control memory interface (write)
(SWCLK)
in
tCYHA
HTA17 - HTA00
out
address
tDHAHW
HTD31 - HTD00,
HTP3 - HTP0
in/out
HTCS1_B,
HTCS0_B
out
tDHWHA
(Hi-Z)
Valid
tDHDHW
tDHOHD
(Hi-Z)
tFHWHD
tDHDHO
tDHCHW
tDHWHC
tDHDHW
tDHWHO
HTOE_B
out
HTWE_B
out
tWHWL
Data Sheet S14237EJ2V0DS00
53
µPD98412
(4) Cell buffer memory interface
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
tCYSK − 2
ns
tSCDCA
9
ns
CBD hold time (vs. CBA)
tHCACD
1
ns
CBCS_B cycle time
tCYCC
tCYSK − 2
ns
CBD setup time (vs. CBCS_B)
tSCDCC
9
ns
CBD hold time (vs. CBCS_B)
tHCCCD
1
ns
CBOE_B cycle time
tCYCO
tCYSK − 2
ns
CBD setup time (vs. CBOE_B)
tSCDCO
9
ns
CBD hold time (vs. CBOE_B)
tHCOCD
1
ns
CBWE_B low-level width
tWCWL
Load capacitance 50 pF
tWSKL − 1.5
ns
Data → CBWE_B ↑ output delay
time
tDCDCW
Load capacitance 50 pF
tWSKL − 3
ns
CBWE_B ↑→ Data float output
delay time
tFCWCD
Load capacitance 50 pF
0
ns
CBA → CBWE_B ↓ output delay
time
tDCACW
Load capacitance 50 pF
tWSKH − 5
ns
CBCS_B ↓→ CBWE_B ↑ output
delay time
tDCCCW
Load capacitance 50 pF
tCYSK − 6
ns
CBOE_B ↑→ CBWE_B ↑ output
delay time
tDCOCW
Load capacitance 50 pF
tCYSK − 6
ns
CBWE_B ↑→ CBA output delay
time
tDCWCA
Load capacitance 50 pF
0
ns
CBWE_B ↑→ CBCS_B ↑ output
delay time
tDCWCC
Load capacitance 50 pF
0
ns
CBWE_B ↑→ CBOE_B ↓ output
delay time
tDCWCO
Load capacitance 50 pF
0
ns
CBD float → CBOE_B ↓ output
delay time
tDCDCO
Load capacitance 50 pF
0
ns
CBOE_B ↑→ Data output delay
time
tDCOCD
Load capacitance 50 pF
tWSKH − 3
ns
CBA cycle time
tCYCA
CBD setup time (vs. CBA)
54
Load capacitance 50 pF
Load capacitance 50 pF
Load capacitance 50 pF
Data Sheet S14237EJ2V0DS00
µPD98412
Cell buffer memory interface (read)
(SWCLK)
in
tCYCA
CBA17 - CBA00
out
address
tSCDCA
CBD91 - CBD00
in/out
(Hi-Z)
tHCACD
(Hi-Z)
data
tCYCC
CBCS1_B,
CBCS0_B
out
tCYCO
tSCDCC
tHCCCD
tSCDCO
tHCOCD
CBOE_B
out
CBWE_B
out
Cell buffer memory interface (write)
(SWCLK)
in
tCYCA
CBA17 - CBA00
out
address
tDCACW
CBD91 - CBD00,
in/out
tDCWCA
(Hi-Z)
Valid
tDCDCW
CBCS1_B,
CBCS0_B
out
tDCOCD
(Hi-Z)
tFCWCD
tDCDCO
tDCCCW
tDCWCC
tDCOCW
tDCWCO
CBOE_B
out
CBWE_B
out
tWCWL
Data Sheet S14237EJ2V0DS00
55
µPD98412
(5) UTOPIA interface (reception)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
125
ns
UCLK cycle time
tCYRK
20
UCLK high-level width
tWRKH
8
ns
UCLK low-level width
tWRKL
8
ns
UCLK rise time
tRKR
2
ns
UCLK fall time
tRKF
2
ns
UCLK ↑→ RXADDR output delay
time
tDRKA
Load capacitance 50 pF
1
14
ns
UCLK ↑→ RXENB_B output
delay time
tDRKE
Load capacitance 50 pF
1
14
ns
RXCLAV setup time (vs. UCLK ↑)
tSCARK
4
ns
RXCLAV hold time (vs. UCLK ↑)
tHRKCA
1
ns
RXDATA setup time (vs. UCLK ↑)
tSDRK
4
ns
RXDATA hold time (vs. UCLK ↑)
tHRKD
1
ns
RXSOC setup time (vs. UCLK ↑)
tSSCRK
4
ns
RXSOC hold time (vs. UCLK ↑)
tHRKSC
1
ns
56
Data Sheet S14237EJ2V0DS00
µPD98412
UTOPIA interface (reception) (n = 0 - 3)
8-bit mode
tCYRK
tWRKH tWRKL
UCLKn
in
tRKR
RXADDRn3 RXADDRn0
out
RXCLAVn
in
tDRKA
tRKF
“F(h)”
N
“F(h)”
tSCARK
(Hi-Z)
N+1
(Hi-Z)
tDRKE
“F(h)”
tHRKCA
tSCARK
N+2
tHRKCA
(Hi-Z)
(Hi-Z)
tDRKE
RXNBn_B
out
tSDRK
RXDATAn7 RXDATAn0
in
P47
(Hi-Z)
P48
tHRKD
H1
tHRKSC
tSSCRK
H2
tHRKSC
H3
tSSCRK
(Hi-Z)
RXSOCn
in
16-bit mode
tCYRK
tWRKH tWRKL
UCLKn
in
tRKR
RXADDRn4 RXADDRn0
out
RXCLAVn
in
tDRKA
tRKF
“1F(h)”
N
“1F(h)”
tSCARK
(Hi-Z)
N+1
tHR KCA
tSCARK
(Hi-Z)
(Hi-Z)
tDRKE
“1F(h)”
N+2
tHRKCA
(Hi-Z)
tDRKE
RXENBn_B
out
tSDRK
RXDATAn15 RXDATAn8
in
P45
RXDATAn7 RXDATAn0
in
P46
RXSOCn
in
(Hi-Z)
P47
H1
tSDRK
(Hi-Z)
P48
tHRKSC
tHRKD
H3
tHRKD
H2
tSSCRK
H4
tHRKSC
tSSCRK
(Hi-Z)
Data Sheet S14237EJ2V0DS00
57
µPD98412
(6) UTOPIA interface (transmission)
Parameter
Symbol
MAX.
Unit
UCLK ↑→ TXADDR output delay
time
tDTKA
Load capacitance 50 pF
1
14
ns
UCLK ↑→ TXENB_B output
delay time
tDTKE
Load capacitance 50 pF
1
14
ns
UCLK ↑→ TXDATA output delay
time
tDTKD
Load capacitance 50 pF
1
14
ns
UCLK ↑→ TXDATA float output
delay time
tFTKD
Load capacitance 50 pF
1
14
ns
UCLK ↑→ TXSOC output delay
time
tDTKSC
Load capacitance 50 pF
1
14
ns
UCLK ↑→ TXSOC float output
delay time
tFTKSC
Load capacitance 50 pF
1
14
ns
TXCLAV setup time (vs. UCLK ↑)
tSCATK
4
ns
TXCLAV hold time (vs. UCLK ↑)
tHTKCA
1
ns
58
Test Conditions
Data Sheet S14237EJ2V0DS00
MIN.
TYP.
µPD98412
UTOPIA interface (transmission) (n = 0 - 3)
8-bit mode
UCLKn
in
tDTKA
TXADDRn3 TXADDRn0
out
TXCLAVn
in
"F(h)"
N
"F(h)"
tSCATK
(Hi-Z)
0
tSCATK
tHTKCA
(Hi-Z)
tDTKE
"F(h)"
1
tHTKCA
(Hi-Z)
(Hi-Z)
tDTKE
TXENBn_B
out
tFTKD
TXDATAn7 TXDATAn0
out
tDTKD
(Hi-Z)
P48
tFTKSC
H2
H1
H3
H4
tDTKSC
tDTKSC
(Hi-Z)
TXSOCn
out
16-bit mode
UCLKn
in
tDTKA
TXADDRn4 TXADDRn0
out
TXCLAVn
in
“1F(h)”
N
“1F(h)”
tSCATK
(Hi-Z)
0
tHTKCA
tSCATK
(Hi-Z)
(Hi-Z)
tDTKE
tDTKE
tFTKD
tDTKD
“1F(h)”
1
tHTKCA
(Hi-Z)
TXENBn_B
out
TXDATAn15 TXDATAn8
out
P47
TXDATAn7TXDATAn0
out
P48
(Hi-Z)
tFTKD
tFTKSC
H1
H3
H2
H4
tDTKD
tDTKSC
tDTKSC
TXSOCn
out
Data Sheet S14237EJ2V0DS00
59
µPD98412
3. PACKAGE DRAWING
A
A
B
A1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Q
R
S
T
B W
D
A2
AJ AG AE AC AA W U R N L J G E C A
AK AH AF AD AB Y V T P M K H F D B
X
C
Y
Index area
J
H
A
B
G
S
F
L
φM
M
S A B
φP
M
S
detail of A part
E
detail of B part
(Z)
K S
N
ITEM
A
MILLIMETERS
40.00±0.20
A1
23.00 MAX.
A2
23.00 MAX.
B
C
39.60±0.15
39.60±0.15
D
E
F
40.00±0.20
1.585
1.27 (T.P.)
G
0.60±0.10
H
0.80 +0.20
−0.10
J
1.40 +0.30
−0.20
K
0.15
L
φ 0.75±0.15
M
0.30
N
P
0.25 MIN.
0.10
Q
R
3.0
2.0
S
2.0
T
W
3.0
22.73
X
22.73
Y
C 0.40
Z
0.20
S576N7-127-H6-1
60
Data Sheet S14237EJ2V0DS00
µPD98412
4. RECOMMENDED SOLDERING CONDITIONS
Solder this product under the following recommended conditions.
For details of the recommended soldering conditions, refer to information document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended, consult NEC.
Surface-mount type
• µPD98412N7-H6: 576-pin tape BGA (40 × 40)
Soldering Method(s)
Soldering Conditions
Recommended
Conditions Symbol
Infrared reflow
Package peak temperature: 235 °C, Time: 30 sec max. (210 °C min.),
Note
Number of times: three times max., Number of days: 7 (after that,
prebaking is necessary at 125 °C for 10 hours)
IR35-107-3
Partial heating
Pin temperature: 300 °C max. (per device side), Time: 3 sec max. (per
device side)
−
Note Number of days in storage after the dry pack has been opened. The storage conditions are at 25 °C, 65%
RH MAX.
Data Sheet S14237EJ2V0DS00
61
µPD98412
[MEMO]
62
Data Sheet S14237EJ2V0DS00
µPD98412
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S14237EJ2V0DS00
63
µPD98412
NEASCOT-X15 is a trademark of NEC Corporation.
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8