DATA SHEET MOS INTEGRATED CIRCUIT µPD98411 ATM QUAD SONET FRAMER The µPD98411 NEASCOT-P40 is one of ATM-LAN LSIs and provides the functions of the TC sublayer of the SONET/SDH-base physical layer of the ATM protocol specified by the ATM Forum. Its main functions include a transmission function to map an ATM cell passed from an ATM layer to the payload of 155M-bps SONET STS3c/SDH STM-1 frame and transmit the cell to the PMD (Physical Media Dependent) sublayer of the physical layer, and a reception function to separate the overhead and ATM cell from the data string received from the PMD device and transmit the ATM cell to the ATM layer. The µPD98411 NEASCOT-P40 combines these transmission /reception functions into a port function that is realized as a single 4-port LSI chip. This LSI is ideally suited for use in the ATM hubs, ATM switches, and other equipment used to configure an ATM network. In addition, the µPD98411 also has a clock recovery function for each port to extract synchronous clock for reception of receive data from the bit stream, and a clock synthesis function to generate a clock for transmission. For the details of functional description, refer to the following user's manual. µPD98411 User's Manual : S12736E FEATURES • Incorporates an ATM user network interface TC sublayer function for four channels. • Conforms to ATM FORUM UNI v3.1. • Incorporates four clock recovery PLLs and one clock synthesizer PLL. • Conforms to ATM FORUM UTOPIA Level 2 v1.0. • • ATM layers can be selected from the multi-PHY interface (up to 800 Mbps) in several different modes. Single 16-bit 1TCLAV/1RCLAV (Cell Available signal mode) Single 8-bit Direct Status Indication mode Dual 8-bit Multiplexed Status Polling mode A management interface can be set to either of two modes. RD-WR-RDY style (Intel-compatible mode) DS-R/W-ACK style (Motorola-compatible mode) • The line-side PMD interface accepts a P-ECL level input. • Supports a loopback function. • Supports a pseudo error generation frame transmission function. • Incorporates one general input port per channel and three output ports (each able to drive an LED) per channel. • Supports JTAG boundary scan test (IEEE 1149.1). The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S12953EJ4V0DS00 (4th edition) Date Published January 1999 NS CP(K) Printed in Japan NEC Corporation 1997,1999 µPD98411 • Incorporates a wide range of operation, administration, and maintenance (OAM) functions. Transmission Alarm Condition and Failure Detection Line Quality Monitoring APS Insertion of B1-byte computation Line AIS/Path AIS Insertion of B2-byte computation Line RDI/Path RDI Insertion of B3-byte computation Automatic transmission of a Line REI Automatic transmission of a Path REI Reception Alarm Condition and Failure Detection Notification of Degraded Line Quality External input signal change B1 error B1 error counter LOS B2 error B2 error counter OOF B3 error B3 error counter LOF Line REI Line REI counter LOP Path REI Path REI counter OCD Frequency justification Frequency justification counter LCD FIFO overflow HEC processing dropped cell counter Line AIS/Path AIS FIFO overflow dropped cell counter Line RDI/Path RDI Received idle cell counter APS Valid cell counter • 0.35-µm CMOS process • Low power consumption; +3.3 V single-voltage power supply ORDERING INFORMATION Part Number µPD98411GN-MMU 2 Line Quality Monitor Counter Package 240-pin plastic QFP (fine pitch) (32 × 32 mm) Data Sheet S12953EJ4V0DS00 µPD98411 APPLICATIONS The following are examples of the application using the µPD98411. • ATM Switches NIC OC-12 SONET Framer µPD98411 155 ATM Interface Backbone Network µPD98411 NIC SWITCH µPD98411 NIC µPD98411 UTOPIA Level2 CPU Data Sheet S12953EJ4V0DS00 3 µPD98411 SYSTEM CONFIGURATION 1) µPD98411 System Application OSC (19.44M) Status PMD I/F (PECL) Optical Module Multimode Fiber Optical Module µ PD98411 ATM Layer Device Tx UTOPIA I/F (NEASCOT-P40) Equalizer Components RJ-45 Connector Magnetics Shielded Twist Pair Rx UTOPIA I/F Equalizer Components RJ-45 Connector Magnetics Management I/F Processor 2) Connection to 5-V transceiver/receiver The following show an example of connecting the µPD98411 to a 5-V optical transceiver. Since the µPD98411 operates on 3.3 V, a coupling circuit should be added if it is to be connected to a 5-V device. 3.3V µPD98411 Port0 5V 0.1µF 510Ω 510Ω 110Ω 110Ω 82Ω 82Ω 430Ω 430Ω GND 5V optical transceiver 0.1µF×4 RDIT0 RDIC0 TDOT0 TDOC0 RSDT RSDC TXDT TXDC 5V 820Ω 820Ω 91Ω 91Ω 130Ω 130Ω 1.1kΩ 1.1kΩ VCCR VCCT VEER VEET 0.1µF GND SD0 GND PECL->TTL translator MC10H350 by Motorola, etc. 4 Data Sheet S12953EJ4V0DS00 GND SD µPD98411 3) UTOPIA Interface The UTOPIA interface transfers transmit/receive cell data to a device in the upper ATM layer. The interface between the µPD98411 and the ATM layer conforms to “MPHY Data Path Operation” of the “UTOPIA Level 2 version 1.0 June ’95” standard. Bus Mode The way to indicate Cell Available state Dual eight-bit bus. In this mode, an 8-bit data bus is used for two ports. Ports 0 and 1 transfer signals using one eight-bit bus, while ports 2 and 3 transfer signals using another eight-bit bus. The ports operate independently. PMD µPD98411 One TCLAV & one RCLAV signal mode The one TCLAV & one RCLAV signal mode outputs the TCLAV and RCLAV signal status information for four ports of the µPD98411 by multiplexing them into a single signal. µPD98411 UTOPIA Port0 Port0 8-bit Port1 TCLAV ATM layer device RCLAV Port1 TDI Port2 8-bit ATM layer Port2 8 or 16-bit RDO device Port3 Port3 Single eight-bit bus. In this mode, cell data for all four ports is transferred through an eight-bit bus. The maximum transfer rate is 400 Mbps (8 bits x 50 MHz). PMD µPD98411 ATM layer Device TADD RADD Direct Status Indication Mode µPD98411 has four TXCLAV and RXCLAV status signals, one pair of TXCLAV and RXCLAV for each port. Status signals and cell transfers are independent of each other. No address information is needed to obtain status information. UTOPIA Port0 Port0 Port1 Port1 8-bit device Port2 µPD98411 ATM layer Port2 Port3 TCLAV3-TCLAV0 RCLAV3-RCLAV0 TDI ATM layer Device 8 or 16-bit RDO Port3 Single sixteen-bit bus. In this mode, cell data for all four ports is transferred through a sixteen-bit bus. The maximum transfer rate is 800 Mbps (16 bits x 50 MHz). TADD RADD Multiplexed Status Polling Mode When six or more µPD98411s are connected to one ATM layer, ATM layer obtain the status information of all the connected ports in the 53 clock cycles in which it transmits or receives a PMD µPD98411 single data cell. Because a minimum of two clock cycles are UTOPIA required to obtain the TCLAV/RCLAV signal status of a port by Port0 ATM layer polling. Therefore every port address is allocated in a fixed manner to one of the four status signals and to one of eight Port1 16-bit Port2 ATM layer device port groups. Port3 Data Sheet S12953EJ4V0DS00 5 Conforms to UTOPIA level 2 multi-PHY PECL serial interface interface of 400 to 800 Mbps PMD interface (PECL IN/OUT) Clock Recovery S/P Rx framer block Rx timing generation Descramble BIP generation Overhead extraction Rx ATM cell processor block Cell descramble Cell synchronization Idle cell drop P/S Tx framer block Scramble Tx timing generation BIP generation Overhead setup Tx ATM cell processor block HEC generation Cell scramble HEC compare/control Cell mapping Idle cell insertion BLOCK DIAGRAM 6 155.52 MHz RX FIFO (8 cells) TX FIFO (8 cells) Port0 Clock P/S recovery S/PTX FramerRx Block framer block Clock P/S recovery Tx ATM Cells Block RxOperate ATM cell processor block S/PTX Framer Block Rx framer block P/S RX FIFO Rx ATM cell processor block Rx framer block Tx FIFO 6 Cells Tx ATM Cells Block RxOperate ATM cell processor block Tx framer block ATM layer interface Port2 S/P PMD interface (PECL IN/OUT) Port1 PMD interface (PECL IN/OUT) PMD interface (PECL IN/OUT) Data Sheet S12953EJ4V0DS00 Clock Recovery Tx ATM cell processor block RX FIFO Tx FIFO 6 Cells RX FIFO TX FIFO Port3 Clock Synthesizer JTAG OAM sequencer Mode registers Test registers Performance registers Interrupt cause registers Tx/Rx overhead registers Management interface Address: 9 bits Data: 8 bits µPD98411 CPU Bus Interface µPD98411 JDO JRSTB JDI JMS JCK FUNCTIONAL PIN GROUPS +3.3 V VDD GND RDIT0/RDIC0 (differential input) TDOT0/TDOC0 (differential input) RDIT1/RDIC1 (differential input) TDOT1/TDOC1 (differential input) PMD interface JTAG boundary scan interface RDIT2/RDIC2 (differential input) TDOT2/TDOC2 (differential input) RDIT3/RDIC3 (differential input) TDOT3/TDOC3 (differential input) TFKT/TFKC (differential input) REFCLK RCLK1 RCLK2 RENBL1_B RENBL2_B RCLAV0 RCLAV1 RCLAV2 RCLAV3 RADD1[4:0] RADD2[4:0] RSOC1 RSOC2 RDO[15:0] RPR1 RPR2 UTOPIA interface (Rx) REFCLK-2nd CSSEL TCLK1 TCLK2 TENBL1_B TENBL2_B TCLAV0 TCLAV1 TCLAV2 TCLAV3 TADD1[4:0] TADD2[4:0] TSOC1 TSOC2 TDI[15:0] TPR1 TPR2 RXFP TXFP TFSS RCL TCL XLFC MADD[8:0] MDATA[7:0] CS_B DS/RD_B RW/WR_B ACK/RDY_B CMD0 BMODE CMD1 RESET_B CMD2 PHINT0_B CMD3 External alarm signal input PHINT1_B PALM0[2:0] PHINT2_B PALM1[2:0] PHINT3_B SD0 SD1 SD2 PALM2[2:0] SD3 Management interface UTOPIA interface (Tx) Alarm signal output PALM3[2:0] SD signal input Data Sheet S12953EJ4V0DS00 7 µPD98411 PIN CONFIGURATION 240-pin plastic QFP (fine pitch) (32 × 32 mm) (Top View) Remark1. 2. 8 IC: internal connect pin. Leave the IC pins open. In this document, xxx_B stands for active low pin. Data Sheet S12953EJ4V0DS00 µPD98411 PIN ARRANGEMENT TABLE (1/2) Number Pin Name Number 1 GND 40 2 GND 41 3 RDO[11] 42 4 RDO[12] 5 6 7 Pin Name Number Pin Name Number Pin Name VDD 79 TDOC1 118 SD2 GND 80 GND 119 SD3 MD[3] 81 VDD 120 VDD 43 MD[2] 82 GND-PE1 121 GND RDO[13] 44 MD[1] 83 GND-PE1 122 GND RDO[14] 45 MD[0] 84 RDIC1 123 IC RDO[15] 46 VDD 85 RDIT1 124 TCL 8 VDD 47 BMODE 86 VDD-PE1 125 TXFP 9 RCLAV1 48 IC 87 IC 126 RXFP 10 RCLAV0 49 RCL 88 VDD-PE2 127 TFSS 11 GND 50 GND 89 TDOT2 128 CMD3 12 RCLK1 51 VDD-PEC 90 TDOC2 129 CMD2 13 RENBL1_B 52 TFKC 91 GND-PE2 130 CMD1 14 VDD 53 TFKT 92 GND-PE2 131 CMD0 15 RADD1[0] 54 GND-PEC 93 RDIC2 132 VDD 16 RADD1[1] 55 CSSEL 94 RDIT2 133 PALM3[2] 17 RADD1[2] 56 GND-CS 95 VDD-PE2 134 PALM3[1] 18 RADD1[3] 57 VDD-CS 96 IC 135 PALM3[0] 19 RADD1[4] 58 REFCLK 97 VDD-PE3 136 PALM2[2] 20 GND 59 JCK 98 TDOT3 137 PALM2[1] 21 VDD 60 GND 99 TDOC3 138 PALM2[0] 22 ACK/RDY_B 61 VDD 100 VDD 139 GND 23 RW/WR_B 62 GND 101 GND 140 VDD 24 DS/RD_B 63 REFCLK-2nd 102 GND-PE3 141 PALM1[2] 25 CS_B 64 JDO 103 GND-PE3 142 PALM1[1] 26 MADD[8] 65 JDI 104 RDIC3 143 PALM1[0] 27 MADD[7] 66 JMS 105 RDIT3 144 PALM0[2] 28 MADD[6] 67 JRST_B 106 VDD-PE3 145 PALM0[1] 29 MADD[5] 68 VDD-PE0 107 GND 146 PALM0[0] 30 MADD[4] 69 TDOT0 108 IC 147 VDD 31 MADD[3] 70 TDOC0 109 IC 148 GND 32 MADD[2] 71 GND-PE0 110 IC 149 PHINT3_B 33 MADD[1] 72 GND-PE0 111 IC 150 PHINT2_B 34 MADD[0] 73 RDIC0 112 IC 151 PHINT1_B 35 GND 74 RDIT0 113 IC 152 PHINT0_B 36 MD[7] 75 VDD-PE0 114 IC 153 RESET_B 37 MD[6] 76 XLFC 115 IC 154 GND 38 MD[5] 77 VDD-PE1 116 SD0 155 TADD2[0] 39 MD[4] 78 TDOT1 117 SD1 156 TADD2[1] Data Sheet S12953EJ4V0DS00 9 µPD98411 (2/2) Number Pin Name Number Pin Name Number 157 TADD2[2] 179 GND 158 TADD2[3] 180 GND 159 TADD2[4] 181 VDD 10 Pin Name Number Pin Name 201 VDD 223 RCLAV2 202 TDI[13] 224 GND 203 TDI[14] 225 RCLK2 160 VDD 182 TADD1[0] 204 TDI[15] 226 RENBL2_B 161 GND 183 TADD1[1] 205 TPR1 227 VDD 162 TENBL2_B 184 TADD1[2] 206 TSOC1 228 RADD2[0] 163 TCLK2 185 TADD1[3] 207 GND 229 RADD2[1] 164 VDD 186 TADD1[4] 208 VDD 230 RADD2[2] 165 TCLAV3 187 VDD 209 RSOC2 231 RADD2[3] 166 TCLAV2 188 GND 210 RPR2 232 RADD2[4] 167 GND 189 TENBL1_B 211 RDO[0] 233 GND 168 TDI[0] 190 TCLK1 212 RDO[1] 234 VDD 169 TDI[1] 191 GND 213 RDO[2] 235 RSOC1 170 TDI[2] 192 TCLAV1 214 VDD 236 RPR1 171 TDI[3] 193 TCLAV0 215 RDO[3] 237 RDO[8] 172 TDI[4] 194 VDD 216 RDO[4] 238 RDO[9] 173 VDD 195 TDI[8] 217 RDO[5] 239 RDO[10] 174 TDI[5] 196 TDI[9] 218 RDO[6] 240 VDD 175 TDI[6] 197 TDI[10] 219 RDO[7] 176 TDI[7] 198 TDI[11] 220 VDD 177 TPR2 199 TDI[12] 221 GND 178 TSOC2 200 GND 222 RCLAV3 Data Sheet S12953EJ4V0DS00 µPD98411 PIN NAME ACK/RDY_B : Acknowledge/Ready REFCLK : System Clock BMODE : Bus Mode REFCLK-2nd : 2nd Reference Cock CMD3-CMD0 : Command Signal RENBL2_B, : Receive Data Enable CS_B : Chip Select RENBL1_B CSSEL : Clock Source Select RESET_B : System Reset DS/RD_B : Data Strobe/Read RPR2, RPR1 : Receive Data Path Parity GND : Ground RSOC2, RSOC1 : Receive Start Of Cell GND-CS : Ground for Analog PLL Block RW/WR_B : Management Interface Read/Write GND-PE3, : Ground for Rx PECL Block RxFP : Receive Frame Pulse GND-PE2, SD3-SD0 : Signal Detect GND-PE1, TADD2[4:0], : Transmit Address GND-PE0 TADD1[4:0] GND-PEC : Ground for TFKT/C PECL Block TCL JCK : JTAG Clock TCLAV3-TCLAV0 : Transmit Cell Available Signals : Internal Transmit System Clock JDI : JTAG Data Input TCLK2, TCLK1 : Transmit DATA transferring Clock JDO : JTAG Data Output TDI15-TDI0 : Transmit Data Input from the ATM JMS : JTAG Mode Select JRST_B : JTAG Reset TDOC3-TDOC0 MADD[8:0] : Management Interface Address TDOT3-TDOT0 : Transmit Data Output True TENBL2_B, : Transmit Data Enable Layer Bus : Transmit Data Output Complement MD[7:0] : Management Interface Data Bus TENBL1_B PALM3[2:0], : Physical Alarm Output Signals TFKC : Transmit Reference Clock Complement TFKT : Transmit Reference Clock True TFSS : Transmit Frame Set Signal TPR2,TPR1 : Transmit Data Path Parity TSOC2,TSOC1 : Transmit Start Of Cell PHINT2_B, TxFP : Transmit Frame Pulse PHINT1_B, VDD : Supply Voltage PHINT0_B, VDD-CS : Supply Voltage for Analog PLL Block VDD-PE3, : Supply Voltage for Rx PECL Block PALM2[2:0], PALM1[2:0], PALM0[2:0] PHINT3_B, RADD2[4:0], : Physical Interrupt : Receive Address RADD1[4:0] VDD-PE2, : Internal Receive System Clock VDD-PE1, RCLAV3-RCLAV0 : Receive Cell Available Signals VDD-PE0 RCLK2, RCLK1 : Receive Data Transferring Clock VDD-PEC RDIC3-RDIC0 : Receive Data Input Complement RDIT3-RDIT0 : Receive Data Input True RDO[15:0] : Receive Data Output RCL : Supply Voltage for TFKT/C PECL Block XLFC Data Sheet S12953EJ4V0DS00 : Tx Loop Filter Capacity 11 µPD98411 CONTENTS 1. PIN FUNCTIONS ……………………………………………………………………………….... 13 1.1 PMD Interface ………………………………………………………………………………………………... 13 1.2 UTOPIA Interface ………………………………………………………………………………………….… 15 1.3 Management Interface ……………………………………………………………………………………… 19 1.4 Alarm Signal Input/output …………………………………………………………………………………… 20 1.5 JTAG Boundary Scan ………………………………………………………………………………………. 20 1.6 Power Supply and Ground ……………««««««««««««««««««««««««««1 21 1.7 Others ………………………………………………………………………………………………………… 21 1.8 Disipation of Unused Pins ………………………………………………………………………………….. 22 1.9 Initial State of Pins ………………………………………………………………………………………….. 23 1.10 Correspondence between UTOPIA Interface Modes and Pins Used …………………………….……. 24 2. ELECTRICAL CHARACTERISTICS …………………………………………………………….. 25 3. PACKAGE DRAWING ……………………………………………………………………………... 33 4. RECOMMENDED SOLDERING CONDITIONS ………………………………………………… 34 12 Data Sheet S12953EJ4V0DS00 µPD98411 1. PIN FUNCTIONS 1.1 PMD Interface Pin Name (1/3) Pin No. I/O Level I/O 105, 94, P-ECL I RDIT0 85, 74 True(+) RDIC3- 104, 93, P-ECL RDIC0 84, 73 Complement(-) TDOT3- 98, 89, P-ECL TDOT0 78, 69 True(+) TDOC3- 99, 90, P-ECL TDOC0 79, 70 Complement(-) 119-116 CMOS RDIT3- SD3-SD0 Function Receive serial data input. Refers to the differential input of the P-ECL level. I O Transmit serial data output. Refers to the differential output of the P-ECL level. To the transmit O clock. I Line signal detection signal input. Refers to the pins for inputting the SD (Signal Detect) signal of line transceivers (such as optical modules). If this signal goes low, this port detects LOS. High: Normal REFCLK 58 CMOS I Low: LOS state System clock (19.44MHz) input. Used as the source clock for the internal synthesizer PLL/clock recovery PLL and register operation. REFCLK-2nd 63 CMOS I Second system clock (19.44MHz) input. Refers to the pin for inputting the second source clock of the internal synthesizer PLL. This pin is not used if it is unnecessary to switch the source clock of the synthesizer PLL. The CSSC register (address 076H) specifies which of REFCLK and REFCLK-2nd clocks to use as the source block. The REFCLK input is selected as the default. Even when REFCLK-2nd is used as the source clock of the synthesizer PLL, REFCLK is used for register operation as well; therefore, it is necessary to input the clock. REFCLK REFCLK_2nd Transmit synthesizer PLL clock 155.52MHz transmit clock Register REF_cnt bit RXFP 126 CMOS O Receive frame pulse output (8kHz). The pulse signal is output synchronously with the start of the receiving frame. The pulse signal is 1 cycle of the RCL clock in length. The internal FPMSK register (address: 07CH) is used to select which of the four ports will output the pulse synchronous to the receiving frame. No port is selected as the default; therefore, using the default will result in no output. Data Sheet S12953EJ4V0DS00 13 µPD98411 (2/3) Pin Name XLFC Pin No. I/O Level I/O 76 Analog O Function Loop filter capacity connection pin. Refers to the pin connecting the loop filter of the synthesizer PLL. Leave the pin open. TXFP 125 CMOS O Transmitting end frame pulse signal output (8KHz). Outputs a pulse signal synchronous with the start of the transmission frame and equivalent to the 1 cycle of the TCL clock in length. The setting of the internal FPMSK register (address: 07CH) selects which of the four ports should output the pulse synchronous with the transmitting frame. No port is selected as the default value; therefore, using the default will result in no output. TFSS 127 CMOS I Frame transmission disable signal input. If High is input to this pin, the output data strings of all ports are fixed to either to 0 or 1 and frame transmission stops. If Low is input, transmission restarts from the start (the 1st A1 byte) of the frame. Transmission starts with the output of a transmission synchronously with the rising edge of the TCL clock 9 cycles after the last rising edge of the TCL clock at which TFSS was detected as being high. RCL 49 CMOS O Receive system clock output (19.44MHz). Each port uses the 155.52MHz receive clock divided by eight for internal receive processing; and this pin outputs this clock. Which port's system clock is output is selected by setting the relevant value of the RCMSK register (address: 07BH). By using the default value, the clock of port 0 is selected. During resetting or when no port is selected, Low is output. Also, this pin can output REFCLK-2nd clock. 14 Data Sheet S12953EJ4V0DS00 µPD98411 # # # # # # # # # # # (3/3) Pin Name TCL Pin No. I/O Level I/O 124 CMOS O Function Transmission system clock output (19.44 MHz). Each port uses the 155.52MHz transmit clock divided by eight for internal transmit processing; and this pin outputs this clock. Which port's system clock is output is selected by setting the relevant value of the TCMSK register (address: 07AH). During resetting or when no port is selected, Low is output. TFKT 53 P-ECL I Externally generated 155.52MHz transmit clock input. Refers to the pin for inputting the externally generated transmit True(+) clock (155.52MHz) when not using the internally mounted TFKC 52 P-ECL I Complement(-) CSSEL 55 synthesizer PLL. This pin is enabled by setting the CSSEL pin to High. CMOS I TFKT/TFKC pin enable signal input. This pin inputs the enable signal of the TFKT/TFKC pin when inputting a 155.52MHz clock from outside the chip at the TFKT/TFKC pin. High: TFKT/TFKC pin enable Low: TFKT/TFKC pin disable 1.2 UTOPIA Interface The pin used for each UTOPIA interface signal varies with the mode selected by the internal MltUt register (at address 079H). Please refer the table “Correspondence between UTOPIA Interface Modes and Pins Used”. (1/4) Pin Name RDO[15:8] Pin No. I/O Level I/O 7-3 CMOS O 239-237 RDO[7:0] 3-state Function Receive data buses. These 16-bit data bus pins transfer receive data to the ATM 219-215 layer device. Output is made synchronous with the startup of 213-211 the RCLK clock. The pins used varies depending on the UTOPIA interface mode selected by the MltUt register (address: 079H). • Single 8-bit bus: RDO[7:0] • Single 16-bit bus: RDO[15:0] • Dual 8-bit bus: RDO[15:8]/RDO[7:0] RCLK2 225 RCLK1 12 CMOS I Receive clock input. These pins accept receive data transfer clocks of up to 50MHz. The pin to be used varies depending on the UTOPIA interface mode selected by the MltUt register (address: 079H). • Single 8-bit bus: RCLK2 • Single 16-bit bus: RCLK1 • Dual 8-bit bus: RCLK1/RCLK2 Data Sheet S12953EJ4V0DS00 15 µPD98411 (2/4) Pin Name Pin No. I/O Level I/O RSOC2 209 CMOS O RSOC1 235 3-state Function Receive cell starting location signal output. These pins output a signal which indicates the location of the first byte with regard to the ATM layer device. The pin to be used varies depending on the UTOPIA interface mode selected by the MltUt register (address: 079H). • Single 8-bit bus: RSOC2 • Single 16-bit bus: RSOC2 • Dual 8-bit bus: RSOC1/RSOC2 RENBL2_B 226 RENBL1_B 13 CMOS I Receive enable signal input. These pins input a signal which indicates that the corresponding ATM layer device is capable of accepting receive data. The pin to be used varies depending on the UTOPIA interface mode selected by the MltUt register (address: 079H). • Single 8-bit bus: RENBL2_B • Single 16-bit bus: RENBL1_B • Dual 8-bit bus: RENBL1_B/RENBL2_B RCLAV3 222 CMOS O RCLAV2 223 RCLAV1 9 data exists in the receive FIFO. RCLAV0 10 In 1TCLAV&1RCLAV mode, the RCLAV signal of each port is 3-state Receive cell transferable signal output. This signal informs the ATM layer device that 1 cell or more of internally multiplexed to be output as a signal. Of the four signals of RCLAV0 to RCLAV3, the pin and operation of the signal which is used vary depending on the UTOPIA interface mode selected by the MltUt register (address: 079H). • Single 8-bit bus: RCLAV2 • Single 16-bit bus: RCLAV1 • Dual 8-bit bus: RCLAV1/RCLAV2 In Direct Status Indication (DSI) mode, the four signals of RCLAV0 to RCLAV3 are allocated to each of the ports to identify their FIFO statuses. RCLAV0 corresponds to Port 0, and RCLAV3 to Port 3. RADD2[4:0] 232-228 RADD1[4:0] 19-15 CMOS I Receiving end PHY address input. These pins input the address which selects the port. Different pins are used depending on the UTOPIA interface mode selected by the MltUt register (address: 079H). • Single 8-bit bus: RADD2[4:0] • Single 16-bit bus: RADD1[4:0] • Dual 8-bit bus: RADD1[4:0]/RADD2[4:0] 16 Data Sheet S12953EJ4V0DS00 µPD98411 (3/4) Pin Name Pin No. I/O Level I/O RPR2 210 CMOS O RPR1 236 Function Parity bit output pins. Odd parity bits are generated and output from these pins with respect to the data output from RDO15-RDO0. The pin to be used varies depending on the UTOPIA interface mode selected by the MltUt register (address: 079H). • Single 8-bit bus: RPR2 • Single 16-bit bus: RPR2 • Dual 8-bit bus: RPR1/RPR2 TDI[15:8] TDI[7:0] 204-202 CMOS I Transmit data buses. 199-195 These data buses input transmit data from the ATM layer device 176-174 at the rising edge of the TCLK clock. 172-168 The pin to be used varies depending on the UTOPIA interface mode selected by the MltUt register (address: 079H). • Single 8-bit bus: TDI[15:8] • Single 16-bit bus: TDI[15:0] • Dual 8-bit bus: TDI[15:8]/TDI[7:0] TCLK2 163 TCLK1 190 CMOS I Transmit clock input. These pins input clocks of up to 50MHz for transmit data transfer. The pin to be used varies depending on the UTOPIA interface mode selected by the internal MltUt register (address: 079H). • Single 8-bit bus: TCLK1 • Single 16-bit bus: TCLK2 • Dual 8-bit bus: TCLK1/TCLK2 TSOC2 178 TSOC1 206 CMOS I Transmit cell starting location signal input. These pins input a signal which indicates the location of the first byte of the transmit cell. The pin to be used varies depending on the UTOPIA interface mode selected by the MltUt register (address: 079H). • Single 8-bit bus: TSOC1 • Single 16-bit bus: TSOC1 • Dual 8-bit bus: TSOC1/TSOC2 TENBL2_B 162 TENBL1_B 189 CMOS I Transmit enable signal input. These pins input a signal which indicates that the ATM layer device is outputting valid transmit data to TDI[15]-TDI[0]. The pin to be used varies depending on the UTOPIA interface mode selected by the internal MltUt register (address: 079H). • Single 8-bit bus: TENBL1_B • Single 16-bit bus: TENBL2_B • Dual 8-bit bus: TENBL1_B/TENBL2_B Data Sheet S12953EJ4V0DS00 17 µPD98411 (4/4) Pin Name Pin No. I/O Level I/O TCLAV3 165 CMOS O TCLAV2 166 TCLAV1 192 space of at least 1 cell is available in the transmit FIFO. TCLAV0 193 In 1TCLAV&1RCLAV mode, the TCLAV signal of each port is 3-state Function Transmit cell acceptable signal output. The signal informs the ATM layer device that unused storage internally multiplexed to be output as a signal. Of the four signals of TCLAV0 to TCLAV3, the pin to be used varies depending on the UTOPIA interface mode selected by the MltUt register (address: 079H). • Single 8-bit bus: TCLAV1 • Single 16-bit bus: TCLAV2 • Dual 8-bit bus: TCLAV1/TCLAV2 In Direct Status Indication (DSI) mode, the four pins TCLAV0 to TCLAV3 are allocated to each of the ports signal by signal, and indicate the FIFO statuses of each port. TCLAV0 corresponds to Port 0; and TCLAV3 to Port 3. TADD2[4:0] 159-155 TADD1[4:0] 186-182 CMOS I Transmission PHY address input. These pins input the address of the port to be selected. The pins used vary depending on the UTOPIA interface mode selected by the MltUt register (address: 079H). • Single 8-bit bus: TADD1[4:0] • Single 16-bit bus: TADD2[4:0] • Dual 8-bit bus: TADD1[4:0]/TADD2[4:0] TPR2 177 TPR1 205 CMOS I Parity bit input pins. These pins input the odd parity bit input from TD0[15]-TDO[0]. The pin to be used varies depending on the UTOPIA interface mode selected by the MltUt register (address: 079H). • Single 8-bit bus: TPR1 • Single 16-bit bus: TPR1 • Dual 8-bit bus: TPR1/TPR2 18 Data Sheet S12953EJ4V0DS00 µPD98411 1.3 Management Interface Pin Name BMODE Pin No. I/O Level I/O 47 CMOS I Function Mode selection input. This pin input is used to select the mode of the management interface. BMODE=: 1: Selects <RD_B, WR_B, RDY_B> as the pin function. 0: Selects <DS_B, R/W_B, ACK_B> as the pin function. MADD[8:0] 26-34 CMOS I Address input. 9-bit addresses for inputting internal register addresses. MD[7:0] 36-39 CMOS 42-45 CS_B 25 I/O 8-bit data buses for reading/writing internal register data. 3-state CMOS I Chip select signal input. When at low level, access to internal registers is enabled. DS/RD_B 24 CMOS I Data strobe signal input or read signal input. The function of this pin varies depending on the management interface mode selected for the BMODE pin input. BMODE =0: Functions as data strobe signal DS_B BMODE =1: Function as RD_B selecting the read access RW/WR_B 23 CMOS I Read/write signal input or write signal input. The function of this pin varies depending on the management interface mode selected for the BMODE pin input. When BMODE=0, the pin functions as Read/Write control signal R/W_B. R/W_B= High: Read cycle Low: Write cycle When BMODE=1, the pin functions as WR_B selecting Write for internal registers. ACK/RDY_B 22 CMOS O 3-state Data acknowledge signal output or ready signal output. Outputs acknowledge and ready signals which accept the Read/Write cycle for internal registers. PHINT3_B- 149-152 CMOS O PHINT0_B Interrupt signal output. These signals inform the host that an interrupt factor has occurred. Two modes are available for this purpose: one which indicates an interrupt factor for four ports using the PHINT0_B signal and the other which uses four pins PHINT0-PHINT3 to indicate an individual interrupt for each port. Port 0 corresponds to the PHINT0_B pin; and Port 3 to PHINT3_B. RESET_B 153 CMOS I System reset signal input. Initializes the µPD98411. This input signal should be kept low for 1µs or more. Especially, in case of the power on, abovementioned pulse width must be kept after the supply voltage reaches equal to or more than 90% at least. When the RESET_B signal is input, the clock must be input at REFCLK pin. Data Sheet S12953EJ4V0DS00 19 µPD98411 1.4 Alarm Signal Input/output Pin Name Pin No. I/O Level I/O CMD0-CMD3 128-131 CMOS I Function General-purpose input signal. Refers to the general-purpose input pins which input the status signals, etc. from external peripheral devices. The signal level of these pins can also be reflected in the status bits of internal registers, and changes in these bits can be used identify interrupt factors. Each port is equipped with a pin: CMD0 corresponds to Port 0 and CMD3 to Port 3. PALM3[2:0] 133-135 PALM2[2:0] 136-138 CMOS O PHY layer alarm detection signal output. These pins output the signal to notify that the port detected the PALM1[2:0] 141-143 alarm or the defect (LOS, OOF, LOF, LOP, OCD, LCD, Line AIS, PALM0[2:0] 144-146 Path AIS, Line RDI, Path RDI) or that the level of the CMD pin input was changed. Additionary, it is possible to use as the general output ports which reflects state of the bit of the internal register,too. The events to be indicated are selected by seting to AMPR, AMR1, AMR2 registers. 1.5 JTAG Boundary Scan Pin Name JDI Pin No. I/O Level I/O 65 CMOS I Function Refers to the boundary scan data input. When unused, connect this to ground. JDO 64 CMOS O 3-state JCK 59 CMOS I Refers to the boundary scan data output. When unused, leave this open. Refers to the boundary scan clock input. When unused, connect this to ground. JMS 66 CMOS I Refers to the boundary scan mode select signal input. When unused, connect this to ground. JRST_B 67 CMOS I Refers to the boundary scan reset signal input. When unused, connect this to ground. 20 Data Sheet S12953EJ4V0DS00 µPD98411 1.6 Power Supply and Ground Pin Name VDD Pin No I/O Function 8, 14, 21, 40, 46, 61, 81, -- Low-speed section logic power supply (+3.3V±5%) and ground. 100, 120, 132, 140, 147, 160, 164, 173, 181, 187, 194, 201, 208, 214, 220, 227, 234, 240 GND 1 ,2, 11, 20, 35, 41, 50, -- 60, 62, 80, 101, 107, 121, 122, 139, 148, 154, 161, 167, 179, 180, 188, 191, 200, 207, 221, 224, 233 VDD-PEC 51 -- TFKT/TFKC input high-speed part power supply (+3.3V±5%) GND-PEC 54 -- and ground. Noise from this power supply affects the jitter characteristic. Eliminate noise through countermeasures such as filters. VDD-CS 57 -- Transmit clock synthesizer PLL power supply (+3.3V±5%) and GND-CS 56 -- ground. Noise from this power supply affects the jitter characteristic. Eliminate noise through countermeasures such as filters. VDD-PE3 97, 106 VDD-PE2 88, 95 power supply (+3.3V±5%). VDD-PE1 77, 86 Noise from this power supply affects the jitter characteristic. VDD-PE0 68, 75 Eliminate noise through countermeasures such as filters. GND-PE3 102, 103 GND-PE2 91, 92 ground. GND-PE1 82, 83 Noise from this power supply affects the jitter characteristic. GND-PE0 71, 72 Eliminate noise through countermeasures such as filters. 1.7 -- Each port high-speed section, receive clock recovery section Each port high-speed section, receive clock recovery section Others Pin Name IC -- Pin No. I/O Level I/O 48, 87, 96, CMOS -- 108-115 Function These refer to the internal circuit connection test pins. Be sure to leave them open. 123 Data Sheet S12953EJ4V0DS00 21 µPD98411 1.8 Disipation of Unused Pins Take the following actions with pins that are unused in certain modes. Pin Name RCLK2, RCLK1 Measure Connect them to ground. RENBL2_B, RENBL1_B RADD2[4:0], RADD1[4:0] TDI[15:0] TCLK2, TCLK1 TSOC2, TSOC1 TENBL2_B, TENBL1_B TADD2[4:0], TADD1[4:0] TPR2, TPR1 RDO[15:0] Leave them open. RSOC2, RSOC1 RPR2, RPR1 RCLAV3-RCLAV0 TCLAV3-TCLAV0 22 CMD3-CMD0 Connect them to ground. SD3-SD0 Pull them up. TFKT/TFKC Pull up TFKT and connect TFKC to ground. TFSS Connect it to ground. XLFC Leave it open. REFCLK-2nd Connect it to ground Each of output pins Leave them open. Data Sheet S12953EJ4V0DS00 µPD98411 1.9 Initial State of Pins Pin Name During Resetting After Resetting Hi-Z Hi-Z PHINT3_B-PHINT0_B H H PALM3[2:0]-PALM0[2:0] L L RXFP L L TXFP L L TCL L L RCL L L Hi-Z Hi-Z ACK/RDY_B H H TDOT3-TDOT0 L L TDOC3-TDOC0 H H RDO[15:0] RSOC2, RSOC1 RCLAV3-RCLAV0 TCLAV3-TCLAV0 RPR2, RPR1 MD[7:0] Data Sheet S12953EJ4V0DS00 23 µPD98411 1.10 Correspondence between UTOPIA Interface Modes and Pins Used Mode Dual 2 TCLAV/2 RCLAV MSL[3:0] 0001 Pins Used (_B is omitted) Tx 8-bit Direct Status Indication Using 4 TCLAV/ 4 RCLAV signals (two-state outputs) 0101 1001 Multiplexed Status Polling Using 4 TCAV/ 4 RCLAV signals (three-state outputs) 1101 TCLK2, TDI[7:0], TADD2, TPR2, TENBL2_B, TCLAV2, TSOC2 Rx Port 0/1 RCLK1, RDO[15:8], RADD1, RPR1, RENBL1_B, RCLAV1, RSOC1 Port 2/3 RCLK2, RDO[7:0], RADD2, RPR2, RENBL2_B, RCLAV2, RSOC2 Tx Port 0/1 TCLK1, TDI[15:8], TADD1, TPR1, TENBL1_B, TCLAV0-TCLAV1, TSOC1 Port 2/3 TCLK2, TDI[7:0], TADD2, TPR2, TENBL2_B, TCLAV2-TCLAV3, TSOC2 Port 0/1 RCLK1, RDO[15:8], RADD1, RPR1, RENBL1_B, RCLAV0-RCLAV1, RSOC1 Port 2/3 RCLK2, RDO[7:0], RADD2, RPR2, RENBL2_B, RCLAV2-RCLAV3, RSOC2 Port 0/1 TCLK1, TDI[15:8], TADD1, TPR1, TENBL1_B, TCLAV1, TSOC1 Port 2/3 TCLK2, TDI[7:0], TADD2, TPR2, TENBL2_B, TCLAV2, TSOC2 Port 0/1 RCLK1, RDO[15:8], RADD1, TPR1, RENBL1_B, RCLAV1, RSOC1 Port 2/3 RCLK2,RDO[7:0], RADD2, TPR2, RENBL2_B, RCLAV2, RSOC2 Port 0/1 TCLK1, TDI[15:8], TADD1, TPR1, TENBL1_B, TCLAV0-TCLAV1, TSOC1 Port 2/3 TCLK2, TDI[7:0], TADD2, TPR2, TENBL2_B, TCLAV2-TCLAV3, TSOC2 Port 0/1 RCLK1, RDO[15:8], RADD1, RPR1, RENBL1_B, RCLAV0-RCLAV1, RSOC1 Port 2/3 RCLK2, RDO[7:0], RADD2, RPR2, RENBL2_B, RCLAV2-RCLAV3, RSOC2 Tx Rx Tx Rx Single 1 TCLAV/1 RCLAV 0010 8-bit Single Direct Status Indication Using 4 TCLAV/ 4 RCLAV signals (two-state outputs) 0110 Multiplexed Status Polling Using 4 TCLAV/ 4 RCLAV signals (three-state outputs) 1010 Multiplexed Status Polling Using 4 TCAV/ 4 RCLAV signals (three-state outputs) 1110 1 TCLAV/1 RCLAV 0011 16-bit 24 Direct Status Indication Using four TCLAV/four RCLAV signals (two-state outputs) 0111 Multiplexed Status Polling Using one TCLAV/one RCLAV signal (three-state outputs) 1011 Multiplexed Status Polling Using four TCLAV/four RCLAV signals (three-state outputs) 1111 TCLK1, TDI[15:8], TADD1, TPR1, TENBL1_B, TCLAV1, TSOC1 Port 2/3 Rx Multiplexed Status Polling Using 2 TCLAV/ 2 RCLAV signals (three-state outputs) Port 0/1 Tx TCLK1, TDI[15:8], TADD1, TPR1, TENBL1_B, TCLAV1, TSOC1 Rx RCLK2, RDO[7:0], RADD2, RPR2, RENBL2_B, RCLAV2, RSOC2 Tx TCLK1, TDI[15:8], TADD1, TPR1, TENBL1_B, TCLAV0-TCLAV3, TSOC1 Rx RCLK2, RDO[7:0], RADD2, RPR2, RENBL2_B, RCLAV0-RCLAV3, RSOC2 Tx TCLK1, TDI[15:8], TADD1, TPR1, TENBL1_B, TCLAV1, TSOC1 Rx RCLK2, RDO[7:0], RADD2, RPR2, RENBL2_B, RCLAV2, RSOC2 Tx TCLK1, TDI[15:8], TADD1, TPR1, TENBL1_B, TCLAV0-TCLAV3, TSOC1 Rx RCLK2, RDO[7:0], RADD2, RPR2, RENBL2_B, RCLAV0-RCLAV3, RSOC2 Tx TCLK2, TDI[15:0], TADD2, TPR1, TENBL2_B, TCLAV2, TSOC1 Rx RCLK1, RDO[15:0], RADD1, RPR2, RENBL1_B, RCLAV1, RSOC2 Tx TCLK2, TDI[15:0], TADD2, TPR1, TENBL2_B, TCLAV0-TCLAV3, TSOC1 Rx RCLK1, RDO[15:0], RADD1, RPR2, RENBL1_B, RCLAV0-RCLAV3, RSOC2 Tx TCLK2, TDI[15:0], TADD2, TPR1, TENBL2_B, TCLAV2, TSOC1 Rx RCLK1, RDO[15:0], RADD1, RPR2, RENBL1_B, RCLAV1, RSOC2 Tx TCLK2, TDI[15:0], TADD2, TPR1, TENBL2_B, TCLAV0-TCLAV3, TSOC1 Rx RCLK1, RDO[15:0], RADD1, RPR2, RENBL1_B, RCLAV0-RCLAV3, RSOC2 Data Sheet S12953EJ4V0DS00 µPD98411 2. ELECTRICAL CHARACTERISTICS Note The ‘Š’ mark shows the characteristics which was changed from previous version. Absolute Maximum Ratings Parameter Supply voltage Input/output voltage Symbol Unit -0.5 to +4.6 V -0.5 to +6.6 and VDD+3.0 V -0.5 ~ +4.6 and VDD+0.5 V VDD VI/VO Pins except on P-ECL VIA/VOA P-ECL pins Š Rating Conditions Operating temperature Topt -40 to +85 °C Storage temperature Tstg -65 to +150 °C Caution If even one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the values at which the product can be used without physical damage. Be sure not to exceed or fall below these values when using the product. Capacitance Parameter Symbol Conditions MIN. TYP. MAX. Unit Input capacitance CI Frequency = 1MHz 6 10 pF Output capacitance CO Frequency = 1MHz 6 10 pF I/O capacitance CIO Frequency = 1MHz 6 10 pF MIN. TYP. MAX. Unit 3.3 VDD x 1.05 V +85 °C Recommended Operating Conditions Parameter Š Š Symbol Conditions Supply voltage VDD VDD x 0.95 Operating ambient TA -40 temperature Low-level input voltage High-level input voltage Š Š P-ECL differential input voltage VIL Pins except on P-ECL VILA P-ECL pins VIH Pins except on P-ECL VIHA VIDIFF 0 0.8 V VDD –2.82 VDD -1.50 V 2.2 5.25 V P-ECL pins VDD –1.49 VDD –0.4 V P-ECL pins 0.1 2.41 V Data Sheet S12953EJ4V0DS00 25 µPD98411 Š DC Characteristics (VDD = 3.3 ±5% V, TA = -40 to +85 °C) Symbol Parameter Conditions MIN. TYP. MAX. Unit Off-state output current IOZ VI = VDD or GND 10 µA Input leakage current IIL Pins except on P-ECL 10 µA 10 µA 56.4 KΩ VI = VDD or GND P-ECL pins IILA Š Internal Pull-down RPL 59,65,66,67 pins VOLA P-ECL pins 5.4 30 resistance Low-level output voltage VDD -2.175 VDD -1.975 VDD -1.755 V VDD -1.14 V RL = 50Ω, VT = VDD -2V VOHA High-level output voltage P-ECL pins VDD -0.92 VDD -0.69 RL = 50Ω, VT = VDD -2V Low-level output current IOL High-level output current IOH Supply current IDD Š Š VOL = 0.4V, VDD = 3.3V 9.0 mA -9.0 mA Pins except on P-ECL VOH = 2.4V, VDD = 3.3V Pins except on P-ECL During normal operation 500 800 mA Š AC Characteristics (VDD = 3.3 ±5% V, TA = -40 to +85 °C) The propagation delay time is defined as follows: 0.7VDD Input pin 0.5VDD 0.3VDD Output pin 0.5VDD tPD AC Testing Load Circuit AC Test Device Under Test Š CL Š Remark 26 CL=30pF CL Include Jig Capacitance In case of CL=50pF, the operating condition changes to TA = 0 to +70 °C. Data Sheet S12953EJ4V0DS00 µPD98411 Management Interface a) Internal Register Read Symbol Parameter Conditions MIN. TYP. MAX. Unit Address setting time (vs. DS_B↓[RD_B↓]) tSADDS 10 ns CS_B setting time (vs. DS_B↓[RD_B↓]) tSCSDS 5 ns R/W_B[WR_B] setting time tSRWDS 5 ns Address hold time (vs. DS_B↑[RD_B↑]) tHADDS 4 ns CS_B hold time (vs. DS_B↑[RD_B↑]) tHCSDS 0 ns R/W_B[WR_B] hold time tHRWDS 0 ns (vs. DS_B↓[RD_B↓]) (vs. DS_B↑[RD_B↑]) Š DS_B↓[RD_B↓] → ACK_B[RDY_B] tVAKDS Load capacitance: 30 pF 15 ns 25 ns output delay Š DS_B↓[RD_B↓] → data output delay tVDADS Load capacitance: 30 pF Š DS_B↑[RD_B↑] → ACK_B[RDY_B] tIAKDS Load capacitance: 30 pF 10 70 ns 15 70 ns 10 ns float delay Š DS_B↑[RD_B↑] → data float delay tIDADS Load capacitance: 30 pF Š ACK_B↓ → data output delay tDDAAK Load capacitance: 30 pF DS_B[RD_B] pulse width tWDS 51.44 ns DS_B ↑[RD_B↑] →DS_B ↓[RD_B↓] tDSINT 51.44 ns recovery time tTCLK is the cycle of the TCLK. ( i ) BMODE=”0” MADD[8:0] tHADDS tSADDS CS_B tSCSDS tHCSDS MD[7:0] tVDADS tDDAAK tIDADS DS_B /RD_B tDSINT tWDS RW_B /WR_B tSRWDS tHRWDS ACK_B /RDY_B tVAKDS tIAKDS ( ii )BMODE=”1” MADD[8:0] tSADDS CS_B tHADDS tSCSDS tHCSDS MD[7:0] tVDADS tDDAAK tIDADS DS_B /RD_B tDSINT tW DS RW_B /WR_B tSRWDS tHRWDS ACK_B /RDY_B tVAKDS Data Sheet S12953EJ4V0DS00 tIAKDS 27 µPD98411 b) Internal Register Write Parameter Conditions Symbol MIN. TYP. MAX. Unit Address setting time (vs. DS_B↓[RD_B↓]) tSADDS 10 ns CS_B setting time (vs. DS_B↓[WR_B↓]) tSCSDS 5 ns R/W_B[RD_B] setting time tSRWDS 5 ns Data setting time (vs. DS_B↑[WR_B↑]) tSDADS 15 ns Address hold time (vs. DS_B↑[WR_B↑]) tHADDS 4 ns CS_B hold time (vs. DS_B↑[WR_B↑]) tHCSDS 0 ns R/W_B[RD_B] hold time tHRWDS 0 ns (vs. DS_B↓[WR_B↓]) (vs. DS_B↑[WR_B↑]) Š Data hold time (vs. DS_B↑[WR_B↑]) tHDADS DS_B↓[RD_B↓] → ACK_B[RDY_B] tVAKDS Load capacitance: 30 pF 15 ns tIAKDS Load capacitance: 30 pF 10 ns 4 ns output delay Š DS_B↑[RD_B↑] → ACK_B[RDY_B] float delay DS_B [RD_B] pulse width tWDS 51.44 ns DS_B ↑[RD_B↑] →DS_B ↓[RD_B↓] tDSINT 51.44 ns recovery time tTCLK is the cycle of the TCLK. ( i )BMODE=”0” MADD[8:0] tSADDS tHADDS CS_B tHCSDS tSCSDS MD[7:0] tSDADS tHDADS DS_B /RD_B tDSINT tWDS RW_B /WR_B tHRWDS tSRWDS ACK_B /RDY_B tVAKDS tIAKDS ( ii ) BMODE=”1” MADD[8:0] tHADDS tSADDS CS_B tSCSDS tHCSDS MD[7:0] tSDADS RW_B/WR_B tHDADS tDSINT tWDS DS_B/RD_B tSRWDS ACK_B/RDY_B tHRWDS tVAKDS tIAKDS 28 Data Sheet S12953EJ4V0DS00 µPD98411 OAM Interface Parameter Š Symbol REFCLK↑ → PALM3[2:0] -PALM0 tDARRL Conditions MIN. TYP. Load capacitance: 30 pF MAX. Unit 25 ns 25 ns [2:0] delay REFCLK↑ → PHINT3- PHINT 0 tDRFINT delay REFCLK tDARRL tDARRL tDRFINT tDRFINT PALM3[2:0]PALM0[2:0] REFCLK PHINT3_B-PHINT0_B Control Signal Interface Parameter Symbol TFSS setting time (vs. TCL↑) tSTFTL Conditions MIN. TYP. MAX. 20 Unit ns TFSS hold time (vs. TCL↑) tHTFTL Š TCL↑ → TxFP delay tDTFTL Load capacitance: 30 pF 25 ns Š RCL↑ → RxFP delay tDRFRL Load capacitance: 30 pF 25 ns CMD setting time (vs. REFCLK) tSCMRF 20 ns CMD hold time (vs. REFCLK) tHCMRF 5 ns SD setting time (vs. REFCLK) tSSDRF 20 ns SD hold time (vs. REFCLK) tHSDRF 5 ns 5 ns TCL tDTFTL tDTFTL TFSS tSTFTL tHTFTL TXFP RCL tDRFRL tDRFRL RXFP REFCLK CMD3-CMD0 tSCMRF tHCMRF SD3-SD0 tSSDRF Data Sheet S12953EJ4V0DS00 tHSDRF 29 µPD98411 UTOPIA Interface (transmission side) Symbol Parameter MIN. Conditions TYP. MAX. Unit TCLK cycle time tCYTK 20 125 ns TCLK high-level width tWTKH 0.4xtCYTK 0.6x tCYTK ns TCLK low-level width tWTKL 0.4xtCYTK 0.6x tCYTK ns Š TCLK↑ → TCLAV↑↓ delay tDCATK Load capacitance: 30 pF 1 14 ns Š TCLK↑ → TCLAV output delay tVCATK Load capacitance: 30 pF 1 14 ns Š TCLK↑ → TCLAV data float delay tICATK Load capacitance: 30 pF 1 20 ns TDI[0]-TDI[7] setting time tSDITK 4 ns TDI[0]-TDI[7] hold time (vs. TCLK↑) tHDITK 1 ns TSOC setting time (vs. TCLK↑) tSSOTK 4 ns TSOC hold time (vs. TCLK↑) tHSOTK 1 ns TPR setting time (vs. TCLK↑) tSPRTK 4 ns TPR hold time (vs. TCLK↑) tHPRTK 1 ns TADD0- TADD 7 setup time tSADTK 4 ns tHADTK 1 ns TENBL_B setting time (vs. TCLK↑) tSENTK 4 ns TENBL_B hold time (vs. TCLK↑) tHENTK 1 ns (vs. TCLK↑) (vs. TCLK↑) TADD0- TADD7 hold time (vs. TCLK↑) tCYTK tWTKH tWTKL TCLK tSADTK TADD2[4:0] TADD1[4:0] tDCATK tHADTK tDCATK tICATK TCLAV3-TCLAV0 tVCATK TENBL2_B, TENBL1_B tSSOTK tHSOTK tSDITK tHDITK tSPRTK tHPRTK TSOC2,TSOC1 TDI[7:0] TPR2,TPR1 30 Data Sheet S12953EJ4V0DS00 tSENTK tHENTK µPD98411 UTOPIA Interface (reception side) Symbol Parameter MIN. Conditions TYP. MAX. Unit RCLK cycle time tCYRK 20 125 ns RCLK high-level width tWRKH 0.4xtCYRK 0.6xtCYRK ns RCLK low-level width tWRKL 0.4xtCYRK 0.6xtCYRK ns Š RCLK↑ → RCLAV↑↓ delay tDCARK Load capacitance: 30 pF 1 14 ns Š RCLK↑ → RCLAV output delay tVCARK Load capacitance: 30 pF 1 14 ns Š RCLK↑ → RCLAV data float delay tICARK Load capacitance: 30 pF 1 20 ns Š RCLK↑ →RDO ↑↓ delay tDDORK Load capacitance: 30 pF 1 14 ns Š Š RCLK↑→RDO output delay tVDORK Load capacitance: 30 pF 1 14 ns RCLK↑→RDO data float delay tIDORK Load capacitance: 30 pF 1 20 ns Š RCLK↑ → RSOC↑↓ delay tDSORK Load capacitance: 30 pF 1 14 ns RCLK↑ → RSOC output delay tVSORK Load capacitance: 30 pF 1 14 ns RCLK↑ → RSOC data float delay tISORK Load capacitance: 30 pF 1 20 ns RCLK↑ → RPR↑↓ delay tDPRRK Load capacitance: 30 pF 1 14 ns Š RCLK↑ → RPR output delay tVPRRK Load capacitance: 30 pF 1 14 ns Š RCLK↑ → RPR data float delay tIPRRK Load capacitance: 30 pF 1 20 RADD setting time (vs. RCLK↑) tSADRK 4 ns RADD hold time (vs. RCLK↑) tHADRK 1 ns RENBLB setting time (vs. RCLK↑) tSENRK 4 ns RENBLB hold time (vs. RCLK↑) tHENRK 1 ns Š Š Š ns tCYRK tWRKH RCLK tWRKL tSADRK tHADRK RADD2[4:0], RADD1[4:0] RCLAV3-RCLAV0 tDCARK RENBL2_B, RENBL1_B tSENRK tDCARK tICARK tVCARK tHENRK RSOC2,RSOC1 tDSORK tDSORK tISORK tVSORK tIDORK tVDORK tDDORK tDDORK tIPRRK tVPRRK tDPRRK tDPRRK RDO[15:0] RPR2,RPR1 Data Sheet S12953EJ4V0DS00 31 µPD98411 PMD Interface (transmission side) Symbol Parameter Note Conditions MIN. TYP. MAX. Unit 51.4403 +20ppm ns 0.6xtCYRF ns 0.6xtCYRF ns REFCLK cycle time tCYRF -20ppm REFCLK high-level width tWRFH 0.4xtCYRF REFCLK low-level width tWRFL 0.4xtCYRF TFKT(C) cycle time tCYSF -0.005UI Note 6.43 +0.005UI ns To get the transmit source clock which is a jitter below 0.01UI, the basis signal which has at least equal or more than 40-ppm precision must be inputted. (i) When using Clock Synthesizer tCYFR tWRFH tWRFL REFCLK TDOT3-TADT0 (TDOC3-TDOC0) (ii) When using external serial clock tCYSF TFKT (TFKC) TDOT3-TDOT0 (TDOC3-TDOC0) PMD Interface (reception side) Parameter RDIT(C) setting time (vs. TFKT(C)) RDIT(C) hold time (vs. TFKT(C)) Symbol tSDISC tHDISC Conditions When using external PLL When using external PLL TFKT (TFKC) tSDISC tHDISC RDIT3-RDIT0 (RDIC3-RDIC0) 32 Data Sheet S12953EJ4V0DS00 MIN. 1.0 4.0 TYP. MAX. Unit ns ns µPD98411 3. PACKAGE DRAWING 240-PIN PLASTIC QFP (FINE PITCH) (32x32) A B 180 181 121 120 detail of lead end S C D R Q 240 1 F G 61 60 H I J M P K M N S L S NOTE ITEM Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 34.6±0.2 B 32.0±0.2 C 32.0±0.2 D 34.6±0.2 F 1.25 G 1.25 H 0.22 +0.05 −0.04 I 0.10 J 0.5 (T.P.) K 1.3±0.2 L 0.5±0.2 M 0.17 +0.03 −0.07 N P 3.2±0.1 0.10 Q 0.4±0.1 R 3 +7 −3 S 3.8 MAX. P240GN-50-LMU, MMU, SMU-4 Data Sheet S12953EJ4V0DS00 33 µPD98411 4. RECOMMENDED SOLDERING CONDITIONS The conditions listed below shall be met when soldering this product. For more details, refer to our document “Semiconductor Device Mounting Technology Manual (C10535E)”. Please consult with our sales offices in case other soldering process is used, or in case the soldering is done under different conditions. Surface-mount devices •µPD98411GN-MMU: 240-pin plastic QFP (fine pitch) (32 x 32 mm) Soldering process Infrared ray reflow Soldering conditions Peak package’s surface temperature :235° C or below, Reflow time : 30 seconds or below (210 °C or higher), Number of reflow profess : 1, Symbol IR35-363-1 Note Partial heating method Note Exposure limit :3 days (36 hours pre-backing is required at 125C° afterwards) Terminal temperature :300 °C or below, Flow time : 3 seconds or below (Per one side of the device). Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25 °C and relative humidity at 65% or less. 34 Data Sheet S12953EJ4V0DS00 -- µPD98411 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S12953EJ4V0DS00 35 µPD98411 NEASCOT-P40 is a trademark of NEC corporation. The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. 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Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8