DATA SHEET MOS INTEGRATED CIRCUIT µPD98402A LOCAL ATM SONET FRAMER The µPD98402A is one of the ATM-LAN LSIs and incorporates the TC sublayer function in the SONET/SDHbased physical layer of the ATM protocol. The main functions of the µPD98402A include a transmit function for mapping ATM cells received from the ATM layer onto the payload block of the SONET STS-3c/SDH STM-1 frame and sending them to PMD (Physical Media Dependent) in the physical layer, and a receive function for separating the overhead block and ATM cells from the data string received from the PMD sublayer and sending the ATM cells to the ATM layer. Futhermore, the µPD98402A is compliant with the ATM Forum UNI Recommendations. FEATURES • Provision of TC sublayer function of ATM protocol physical layer • Support of SONET STS-3c frame/SDH STM-1 frame format • Provision of stop mode for cell scramble/descramble and frame scramble/descramble • Disposal/transitory selection of unassigned cells is possible. • Compliant with UTOPIA interface • Incorporation of internal loopback function at PMD and ATM layer turns • PMD interface 155.52 Mbps serial interface 19.44 MHz parallel interface • Provided with registers for writing/reading overhead information SOH (section overhead): C1 (1st to 3rd) bytes, F1 byte LOH (line overhead): K2 byte POH (pass overhead): F2 byte, C2 byte • CMOS process • +5 V single power supply The information in this document is subject to change without notice. Document No. S10835EJ1V0DS00 (1st edition) Date Published December 1995 P Printed in Japan © 1995 µPD98402A • Incorporation of OAM (Operation And Maintenance) function Transmitting side Receiving side Transmission of various alarms • Detection of alarms and error signals • Transmission by generation of sources LOS (Loss Of Signal) Line RDI (FERF), Path RDI (FERF) OOF (Out Of Frame) Line FEBE, Path FEBE LOF (Loss Of Frame) • Transmission by command instruction LOP (Loss Of Pointer) Line AIS, Path AIS LOC (Loss Of Cell delineation) Line FEBE, Path FEBE Line RDI (FERF), Path RDI (FERF) Line AIS, Path AIS • Detection and display of quality deterioration sources B1 error, B2 error, B3 error, Line FEBE, Path FEBE • Incorporation of counter for counting number of performance monitoring errors B1 byte error counter B2 byte error counter B3 byte error counter Line FEBE error counter Path FEBE error counter 2 µPD98402A ORDERING INFORMATION Part Number Package µPD98402AGM-KED160-pin plastic QFP (FINE PITCH) (24 × 24 mm) APPLICATION EXAMPLES The followings are examples of the terminal equipment and the ATM Hub application using the µPD98402A. NIC APPLICATION DATA I/F (UTOPIA) CONTROL MEMORY mPD98402A PHY CHIP mPD98401A SAR CHIP CLOCK RECOVERY CHIP Rx PMD TO HUB Tx PMD CNT I/F 155.52MHz HOST BUS I/F SYNTHESIZER HOST BUS HUB APPLICATION (NIC SIDE) DATA I/F SWITCH SYSTEM (UTOPIA) mPD98402A PHY CHIP CLOCK RECOVERY CHIP Rx PMD TO NIC CNT I/F Tx PMD 155.52MHz SYNTHESIZER CONTROLLER CONTROLLER BUS 3 4 Test Block BIP Generator (Rx) Scrambler Mode Register Tx Timing Generator Tx Overhead Controller + Descrambler INT Cause Registers OAM Sequencer Rx Overhead Controller Cell Scrambler Cell Delineation HEC Verification HEC Correction Performance Registers + Rx Timing Generator Idle Cell Insert Tx FIFO 4 Cell Idle Cell Drop Rx FIFO 4 Cell C2 F2 F1 K2 C1(#1~#3) Rx Overhead Registers F1 K2 C2 F2 Tx Overhead Registers C1(#1~#3) HEC Generator Cell Descrambler Loop Back RESET VDD GND Loop Back BIP Generator (Tx) Parallel fiSerial SONET Framing A1, A2 ATM Layer Interface TDO TJI TCK TMS TRST TFC RPC RPD0-RPD7 TPC TPD0-TPD7 RCIC, RCIT PSEL RDIC, RDIT RCL Serialfi Parallel OOF TFKC, TFKT RxFP TCOC, TCOT TDOC, TDOT OE PHINT CE ACK R/W A0—A5 D0—D7 TSOC TCLK TDI0—TDI7 TENBL FULL RDO0—RDO7 RENBL EMPTY RSOC RCLK µPD98402A BLOCK DIAGRAM Management Interface RAL TAL LOS TFSS TCL TxFP PMD Interface µPD98402A FUNCTIONAL PIN GROUPS PMD Interface 8 GND VDD RESET TFSS RxFP TCL RDIT TxFP RDIC RCL Control RDO0-RDO7 RCIC RCLK RCIT RSOC TDOC RENBL TDOT EMPTY TCOC TDI0-TDI7 TCOT TCLK TFKC TSOC TFKT TENBL 8 8 ATM Layer Interface FULL TPD0-TPD7 TPC 8 TFC D0-D7 RPD0-RPD7 A0-A5 R/W RPC CE PSEL 8 6 Management Interface ACK RAL PHINT TAL OE TRST TMS TJI OOF TCK LOS TDO OAM Interface JTAG boundary scanNote pin Note This function can be supported at the customer’s request. 5 µPD98402A PIN CONFIGURATION GND GND RDO7 RDO6 RDO5 RDO4 RDO3 RDO2 RDO1 RDO0 VDD GND RCLK GND RENBL RSOC EMPTY FULL TSOC TEMBL GND TCLK GND VDD TDI7 TDI6 TDI5 TDI4 TDI3 TDI2 TDI1 TDI0 GND PHINT CE OE ACK R/W GND GND 160-pin plastic QFP (FINE PITCH) (24 × 24 mm) (Top View) 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 µ PD98402AGM-KED VDD TCK TDO TJI TMS TRST RAL TAL LOS OOF IC IC IC IC IC IC IC IC IC VDD GND IC IC IC IC IC IC IC TFSS RxFP TxFP TCL VDD GND TPD0 TPD1 TPD2 TPD3 TPD4 VDD GND GND TPD5 TPD6 TPD7 TPC GND TFC TFKT TFKC GND VDD TCOT TCOC VDD GND VDD TDOT TDOC VDD GND RCIT RCIC GND RDIT RDIC RPC GND RPD7 RPD6 RPD5 GND RPD4 RPD3 RPD2 RPD1 RPD0 PSEL GND GND 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Remarks 1. IC : Internally Connected. Leave open. 2. CG : Connect to GND. 6 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 VDD A5 A4 A3 A2 A1 A0 GND D7 D6 D5 D4 D3 GND D2 D1 D0 RESET CG GND VDD IC IC IC IC IC GND IC IC IC IC IC IC IC IC RCL IC IC IC VDD µPD98402A A0-A5 : Address Bus ACK CE : Read/write Cycle Receive Acknowledge : Chip Enable D0–D7 EMPTY : Data Bus : Output Buffer Empty FULL GND : Buffer Full : Ground LOS OE : Loss of Signal : Output Enable OOF PHINT : Out of Frame : Physical Interrupt PSEL RAL : PMD I/F Select : Receive Alarm RCIC RCIT : Receive Clock Input Complement : Receive Clock Input True RCL RCLK : Internal Receive System Clock : Receive Data Transferring Clock from the ATM Layer Device RDIC RDIT : Receive Data Input Complement : Receive Data Input True RDO0-RDO7 : Receive Data Output RENBL : Receive Data Enable RESET RPC : System Reset : Receive Parallel Data Clock RPD0-RPD7 : Receive Parallel Data RSOC : Receive Start Address of ATM Cell R/W RxFP : Read/write Control : Receive Frame Pulse TAL TCK : Transmit Alarm : Test Clock TCL TCLK : Internal Transmit System Clock : Transmit Data Transferring Clock from the ATM Layer Device TCOC TCOT : Transmit Clock Output Complement : Transmit Clock Output True TDI0-TDI7 TDO : Transmit Data Input from the ATM Layer : Test Data Output TDOC TDOT : Transmit Data Output Complement : Transmit Data Output True TENBL TFC : Transmit Data Enable : Transmit Reference Clock TFKC TFKT : Transmit Reference Clock Complement : Transmit Reference Clock True TFSS TJI : Transmit Frame Set Signal : Test JTAG Data Input TPC : Transmit Parallel Data Clock TPD0-TPD7 : Transmit Parallel Data TMS TRST : Test Mode Select : Test Reset TSOC TxFP : Transmit Start Address of ATM Cell : Transmit Frame Pulse VDD : Supply Voltage 7 µPD98402A 1. PIN FUNCTIONS • PMD Interface Pin No. I/O I/O Level RDIC Symbol 66 I Pseudo ECL Complement (–) These pins are used to input receive serial data when serial interface mode is used (PSEL pin input = low level). Ground Function RDIT 65 I Pseudo ECL True (+) them when Parallel interface mode is used. RCIC 63 I Pseudo ECL Complement (–) These pins are used to input the receive system clock when serial interface mode is used (PSEL pin input = low level). RCIT 62 I Pseudo ECL True (+) Clocks are input in synchronization with receive data. Ground them when parallel interface mode is used. TDOC 59 O Pseudo ECL Complement (–) TDOT 58 O Pseudo ECL True (+) These pins are used to output transmit serial data when serial interface mode is used (PSEL pin input = low level). They are open-drain pins. Terminate them with VDD –2 V via a 50 Ω resistor. To be undefined after reset. TCOC 54 O Pseudo ECL Complement (–) These pins are used to output transmit clocks when serial interface mode is used (PSEL pin input = low level). Transmit clocks to be input to the TFKC/TFKT pins are output passing TCOT 53 O Pseudo ECL True (+) through internal gates. They are open-drain pins. Terminate them with VDD –2 via a 50 Ω resistor. To be undefined after reset. TFKC 50 I Pseudo ECL Complement (–) These pins are used to input transmit system clocks when serial interface mode is used (PSEL pin input = low level). Transmit data output from the TDOC/TDOT pins is output in TFKT 49 I Pseudo ECL True (+) synchronization with clocks that are input to these pins. Ground them when parallel interface mode is used. 77-73, 71-69 I TTL These pins are used to input receive parallel data when parallel interface mode is used (PSEL pin input = high level). Leave them open when serial interface mode is used. 67 I TTL This pin is used to input the receive system clock when parallel interface mode is used (PSEL pin input = high level). Input clocks synchronous with the receive data. Leave it open when serial interface mode is used. 35-39, 43-45 O CMOS These pins are used to output transmit parallel data when parallel interface mode is used (PSEL pin input = high level). Leave them open when serial interface mode is used. TPC 46 O CMOS This pin is used to output transmit clocks when parallel interface mode is used (PSEL pin input = high level). Transmit clocks to be input to the TFC pin are output passing through internal gates. Leave it open when serial interface mode is used. TFC 48 I TTL This pins is used to input transmit system clocks when parallel interface mode is used (PSEL pin input = high level). Transmit data output from pins TPD0 to TPD7 are output in synchronization with the clocks input to this pin. Leave it open when serial interface mode is used. PSEL 78 I CMOS This pin is used to select the mode for PMD interface serial/ parallel interface. Low level: Serial interface mode High level: Parallel interface mode RPD0-RPD7 RPC TPD0-TPD7 8 µPD98402A • Power supply Symbol Pin No. I/O Function VDD 1, 20, 33, 40, 52, 55, 57, 60, 81, 100, 120, 137, 150 – Supply voltage, 5 V ±5 % GND 21, 34, 41, 42, 47, 51, 56, 61, 64, 68, 72, 79, 80, 94, 101, 107, 113, 121, 122, 128, 138, 140, 147, 149, 159, 160 – Ground • ATM Layer Interface Symbol Pin No. I/O I/O Level RDO0-RDO7 151-158 O CMOS Connected to 8-bit data bus to output the receive data to the ATM Layer device. Output is synchronized with the RCLK rising up. To be undefined after reset. RCLK 148 I TTL Input pin of the receive data transferring clock from the ATM Layer device. RSOC 145 O CMOS RENBL 146 I TTL Receive enable signal. Input pin of the signal indicating that the ATM layer device can receive data. EMPTY 144 O CMOS Output buffer empty signal. This signal indicates that there is no data to be transferred to the receive FIFO of the µPD98402A. To be inactive after reset. 129-136 I TTL 8-bit data bus to input the transmit data from the ATM Layer device. Reading a data on the bus is synchronized with the TCLK rising-up. TCLK 139 I TTL Input pin of the transmit data transferring clock from the ATM layer device. TSOC 142 I TTL Transmit cell start address signal. Input pin of the signal indicating the start byte of the transmit ATM cell input from the ATM Layer device to the µPD98402A. TENBL 141 I TTL Transmit enable signal. This signal indicates that the ATM Layer device is transmitting the valid data to the TDI0-TDI7. FULL 143 O CMOS TDI0-TDI7 Function Receive cell start address signal. To the ATM Layer device, this signal indicates the start address byte of the receive ATM cell. To be undefined after reset. Input buffer full signal. When 4 bytes remain as the acceptable bytes of transmit FIFO at last, this signal changes to active. To be inactive after reset. 9 µPD98402A • Management Interface Pin No. I/O I/O Level Function D0-D7 Symbol 104-106 108-112 I/O CMOS 8-bit data bus for data transfer between the control processor and the internal register of the µPD98402A. A0-A5 114-119 I TTL Address bus. Used for setting the internal register address of the µPD98402A. R/W 123 I TTL Read/write control signal. Low level: Write cycle High level: Read cycle CE 126 I TTL Chip enable signal. At low level, internal register access is to be enable. ACK 124 O CMOS Read/write cycle receive acknowledge or ready signal. After reset, this signal indicates inactive level. PHINT 127 O CMOS Signal which indicates the interrupt cause occurrence to the processor. After reset, this signal indicates inactive level. OE 125 I TTL Output enable. When this signal is set to low level, the µPD98402A outputs data to the control bus. Even if the CE signal is inactive, when this signal is at low level, the µPD98402A drives the control bus. • OAM Interface Pin No. I/O I/O Level Function LOS Symbol 9 O CMOS Loss of signal detection. Output high level when receive serial data input is "0" for 50 µs continuously or optical input stop signal (RAL) is input. When 2 consecutive frames of valid synchronous pattern is detected, or when input of the optical input stop signal is released, low level is output. To be inactive after reset. OOF 10 O CMOS Out of frame detection. When 4 consecutive frames of wrong synchronous pattern are detected, high level is output. When 2 consecutive frames of normal synchronous pattern are detected, low level is output. To be inactive after reset. RAL 7 I TTL Receive alarm. Inputs receiver-side optical input stop signal by the optical module. Low level: Normal High level: Optical input stopped. TAL 8 I TTL Transmit alarm. Inputs transmit-side optical output stop signal output by the optical module. Low level: Normal High level: Optical output stopped. 10 µPD98402A • Control Pin No. I/O I/O Level Function TFSS Symbol 29 I TTL This is the transmit frame setting signal input pin. It allows synchronization timing of transmit frame output to be set. The µPD98402A samples this input signal by the internal transmit system clock (TCL). Initial output of the transmit frame is restarted 9 clocks into TCL clock cycle after a high level is latched at TCL rise. RESET 103 I TTL This is the system reset signal input pin. It initializes the µPD98402A. It is necessary to input a reset signal with a pulse width of 2 cycles or more of the clock that has the longest cycle among the following clocks input to the µPD98402A. ATM layer : TCLK, RCLK clock cycles PMD layer : 1/8 cycle of TFKT/TFKC, RCIC/RCIT clocks, TFC, RPC clock cycles Immediately after a reset, no read/write is possible to registers during 5 clocks of the TCL clock (19.44 MHz). TCL 32 O CMOS This pin is used to output an internal transmit system clock. The µPD98402A outputs as the internal transmit system clock, the TFKT/TFKC input clock (155.52 MHz) scaled by 8 in serial interface mode, and the TFC input clock (19.44 MHz) in parallel interface mode. RCL 85 O CMOS This pin is used to output an internal receive system clock. The µPD98402A outputs as the internal receive system clock, the RCIC/RCIT input clock (155.52 MHz) scaled by 8 in serial interface mode, and the RFC input clock (19.44 MHz) in parallel interface mode. TxFP 31 O CMOS This is a frame pulse signal on the transmitting side. It outputs pulses synchronous with the transmit frame start. To be inactive after reset. RxFP 30 O CMOS This is a frame pulse signal on the receiving side. It outputs pulses synchronous with the receive frame start. To be inactive after reset. • JTAG boundary scan pins (This function can be supported at the customer’s request.) Symbol Pin No. I/O I/O Level Function TJI 4 I TTL TDO 3 O CMOS TCK 2 I TTL This is a pin for JTAG boundary scan. Pull it up or ground it in normal operation. TMS 5 I TTL This is a pin for JTAG boundary scan. Pull it up or ground it in normal operation. TRST 6 I TTL This is a pin for JTAG boundary scan. Ground it in normal operation. This is a pin for JTAG boundary scan. Pull it up or ground it in normal operation. This is a pin for JTAG boundary scan. Leave it open in normal operation. 11 µPD98402A • Recommended Connection for Unused Pins Pin 12 Recommended connection TDOC, TDOT, TCOC, TCOT, ACK, LOS, OOF, TCL, TxFP, RxFP leave open RAL, TAL, TFSS connect to GND µPD98402A 2. ELECTRICAL SPECIFICATION Absolute maximum ratings Parameters Symbol Ratings Unit V DD –0.5 to +6.5 V VI/VO –0.5 to VDD +0.5 V Operating ambient temperature TA 0 to +70 °C Storage temperature Tstg –65 to +150 °C Supply voltage Input/output voltage Caution Conditions Exposure to absolute maximum ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. The device should be operated within the limits specified under DC and AC characteristics. Capacitance Parameters Symbol Input capacitance CI Output capacitance CO Input/output capacitance CIO Conditions MIN. f = 1 MHz TYP. MAX. Unit 10 20 pF 10 20 pF 10 20 pF TYP. MAX. Unit Recommended operating conditions Parameters Supply voltage Operating ambient temperature Low level input voltage High level input voltage Notes 1. Symbol Conditions MIN. V DD 4.75 5.25 V TA 0 +70 °C VIL1 Note1 0 +0.8 VIL2 Note2 V DD–2 V DD–1.5 VIL3 Note3 0 0.3 VDD VIH1 Note1 2.2 VDD VIH2 Note2 V DD–1.1 VDD VIH3 Note3 0.7 V DD VDD V V TTL input pin 2. Pseudo ECL input pin 3. CMOS input pin 13 µPD98402A DC Characteristics (VDD = 5 V ±0.25 V, TA = 0 to +70 °C) Parameters Off-state output current Symbol Conditions MIN. TYP. MAX. Unit µA I OZ VI = V DD or GND Note1 — 10 ILI1 VI = V DD or GND Note2 — 10 ILI2 Note 3 — 10 Input leak current VOH1 IOH = –0.5 mA Note4 0.7 VDD — VOH2 Note 5 V DD–0.9 V DD–0.4 V OL1 IOL = 6.0 mA Note4 — 0.4 V OL2 Note 5 V DD–2.0 V DD–1.7 — 300 High level output voltage V Low level output voltage Supply current Notes 1. 14 3-state data bus 2. TTL input pin 3. Pseudo ECL input pin 4. CMOS output pin 5. Pseudo ECL output pin µA V I DD Normal operation mA µPD98402A AC Characteristics (1) Management Interface Internal Register Read/Write Parameters Symbol Conditions MIN. A0-A5 setup time (to CE↓) tSCC1 5 R/W setup time (to CE↓) tSCC2 5 A0-A5 hold time (to CE↓) tHCC1 3 R/W hold time (to CE↓) tHCC2 3 CE↓→ACK↓ delay time (read) tDCNAR CE↓→ACK↓ delay time (write) CE↑→ACK↑ delay time CE↓→ data output delay time tDCNAW tDCPA tDCD TYP. MAX. Unit ns ns Load capacitor 15 pF At parallel data input 3× tCYPPR 4.5 × tCYPPR Load capacitor 15 pF At serial data input 3× (tCYPSR × 8) 4.5 × (tCYPSR × 8) Load capacitor 15 pF At parallel data input 2× tCYPPR 3.5 × tCYPPR Load capacitor 15 pF At serial data input 2× (tCYPSR × 8) 3.5 × (tCYPSR × 8) Load capacitor 15 pF At parallel data input 1× tCYPPR 2.5 × tCYPPR Load capacitor 15 pF At serial data input 1× (tCYPSR × 8) 2.5 × (tCYPSR × 8) Load capacitor 15 pF At parallel data input 2× tCYPPR 3.5 × tCYPPR Load capacitor 15 pF At serial data input 2× (tCYPSR × 8) 3.5 × (tCYPSR × 8) ns ns ns ns OE↓→ data output delay time tDOD Load capacitor 15 pF — 9.4 ns OE↑→ data floating output delay time tFOD Load capacitor 15 pF — 10 ns D0-D7 setup time (to CE↓) tSDC 5 — ns D0-D7 hold time (to CE↓) tHCD 3 — ns CE low-level width tCEBW 3.5 × tCYPPR — 3.5 × (tCYPSR × 8) — 2.5 × tCYPPR — 2.5 × (tCYPSR × 8) — At parallel data input At serial data input OE low-level width tOEBW At parallel data input At serial data input Remarks 1. 2. ns ns For tCYPPR, refer to (6) PMD parallel interface timing. For tCYPSR, refer to (7) PMD serial interface timing. 15 µPD98402A Management Interface Internal Register Read (a) Case 1 When the host uses ACK signal tHCC1 tSCC1 A0-A5 R/W tHCC2 tSCC2 tCEBW CE tDCPA tOEBW OE tDCNAR ACK tDOD Valid D0-D7 tDCD (b) Case 2 tFOD When the host does not use ACK signal tSCC1 tHCC1 tSCC2 tHCC2 A0-A5 R/W tCEBW CE tOEBW OE Valid D0-D7 tDOD 16 tFOD µPD98402A Internal Register Write tSCC1 tHCC1 A0-A5 tHCC2 R/W CE tSCC2 ACK tDCPA tDCNAW D0-D7 Valid tSDC tHCD “H” OE (2) OAM Interface Parameters Symbol Conditions MIN. TYP. MAX. Unit TCL↑→LOS delay time tDCLS load capacitor = 15 pF 5 30 ns RCL↑→OOF delay time tDCOF load capacitor = 15 pF –5 +7 ns OAM Interface TCL RCL tDCLS LOS tDCOF OOF 17 µPD98402A (3) Control Signal Interface Parameters Symbol Conditions load capacitor = 15 pF MIN. TYP. MAX. Unit 0 +5 ns TCL↑→TPC delay time tDTCP TFSS setup time (to TCL↑) tSFSC 10 — ns TFSS hold time (to TCL↑) tHCFS 5 — ns TCL↑→TxFP delay time tDCFP load capacitor = 15 pF 0 +20 ns RCL↑→RxFP delay time tDCRP load capacitor = 15 pF –5 +20 ns Control Signal Interface TPC tDTCP TCL tDCFP TFSS TxFP tSFSC tHCFS RCL RxFP tDCRP 18 tDCRP tDCFP µPD98402A (4) SAR Interface (Transmitter Side) Parameters Symbol Conditions MIN. TYP. MAX. Unit TCLK cycle time tCYST 30 125 ns TCLK high level width tSTH 12 110 ns TCLK low level width tSTL 12 110 ns TCLK↑→FULL↓ delay time tFD 5 17 ns load capacitor = 15 pF TDI0-TDI7 setup time (to TCLK↑) tSTDK1 5 — ns TSOC setup time (to TCLK↑) tSTDK2 12 — ns TENBL setup time (to TCLK↑) tSTDK3 5 — ns TDI0-TDI7 hold time (to TCLK↑) tHKTD1 3 — ns TSOC hold time (to TCLK↑) tHKTD2 3 — ns TENBL hold time (to TCLK↑) tHKTD2 3 — ns SAR Interface (Transmitter Side) tCYST TCLK tSTH tSTL FULL tFD tSTDK2 tSTDK3 tHKTD3 TENBL tHKTD2 tSTDK1 TSOC TDI0-TDI7 P48 H1 Invalid H2 tHKTD1 H3 19 µPD98402A (5) SAR Interface (Receiver Side) Parameters Symbol Conditions MIN. TYP. MAX. Unit RCLK cycle time tSYCR 30 125 ns RCLK high level width tSRH 12 110 ns RCLK low level width tSRL 12 110 ns RCLK↑→EMPTY↑↓delay time tED 5 17 ns RENBL setup time (to RCLK↑) tSREK 12 — ns RENBL hold time (to RCLK↑) tHKRE 3 — ns RCLK↑→RSOC↑↓ delay time tRSD load capacitor = 15 pF 0 17 ns RCLK↑→RDO0-RDO7 delay time tRDD load capacitor = 15 pF 0 17 ns load capacitor = 15 pF SAR Interface (Receiver Side) tSYCR RCLK tSRH tSRL EMPTY tHKRE tSREK tED tED RENBL tRSD tRSD RSOC tRDD RDO0-RDO7 20 P48 tRDD H1 H2 H3 µPD98402A (6) PMD Parallel Interface Parameters Symbol Conditions MIN. TYP. MAX. Unit RPC cycle time tCYPPR 50 — ns RPC high level width tPPRH 20 — ns RPC low level width tPPRL 20 — ns TFC cycle time tCYPPT 50 — ns TFC high level width tPPTH 20 — ns TFC low level width tPPTL 20 — ns RPD0-RPD7 setup time (to RPC↑) tSPDC 5 — ns RPD0-RPD7 hold time (to RPC↑) tHPCD 3 — ns TFC↑→TPC↑ delay time tDFPCP load capacitor = 15 pF 3 25 ns TFC↓→TPC↓ delay time tDFPCN load capacitor = 15 pF 3 25 ns TPC↑→TPD0-TPD7 delay time tDPCD load capacitor = 15 pF –3.0 +1.0 ns PMD Parallel Interface Receive Side tCYPPR tPPRH tPPRL RPC RPD0-RPD7 tSPDC tHPCD Transmit Side tDFPCP tCYPPT tDFPCN tPPTH tPPTL TFC TPC TPD0-TPD7 tDPCD 21 µPD98402A (7) PMD Serial Interface Parameters Symbol Conditions MIN. TYP. MAX. Unit RCIT (RCIC) cycle time tCYPSR 6.4 — ns TFKT (TFKC) cycle time tCYPST 6.4 — ns Serial data setup time tSSDC 1.0 — ns Serial data hold time tHSCD 1.0 — ns Serial clock delay time (rising) tDFSCP Load capacitor 15 pF — 8 ns Serial clock delay time (falling) tDFSCN Load capacitor 15 pF — 8 ns Transmit serial data delay time tDSCD Load capacitor 15 pF — 3 ns PMD Serial Interface Receive Side tCYPSR RCIC, RCIT RDIC, RDIT tSSDC tHSCD Transmit Side tDFSCP tDFSCN tCYPST TFKC, TFKT TCOC, TCOT TDOC, TDOT tDSCD 22 µPD98402A 3. PACKAGE DRAWING 160 PIN PLASTIC QFP (FINE PITCH) ( 24) A B 120 121 81 80 detail of lead end C D S R Q 160 1 41 40 F G H I J M K P M N NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. L ITEM MILLIMETERS A 26.0±0.2 INCHES 1.024 +0.008 –0.009 B 24.0±0.2 0.945±0.008 C 24.0±0.2 0.945±0.008 D 26.0±0.2 1.024 +0.008 –0.009 F 2.25 0.089 G 2.25 0.089 H 0.22 +0.05 –0.04 0.009±0.002 I 0.10 0.004 J 0.5 (T.P.) K 1.0±0.2 0.020 (T.P.) 0.039 +0.009 –0.008 L 0.5±0.2 0.020 +0.008 –0.009 M 0.17 +0.03 –0.07 0.007 +0.001 –0.003 N 0.10 0.004 P 2.7 0.106 Q 0.125±0.075 0.005±0.003 R 5°±5° 5°±5° S 3.0 MAX. 0.119 MAX. S160GM-50-3ED, JED, KED-2 23 µPD98402A 4. RECOMMENDED SOLDERING CONDITIONS For the µPD98402A, soldering must be performed under the following conditions. For details of recommended conditions for surface mounting, refer to information document “Semiconductor Device Mounting Technology Manual” (IEI-1207). For other soldering methods, please consult with NEC sales personnel. • µPD98402AGM-KED: 160-pin plastic QFP (FINE PITCH) (24 × 24 mm) Soldering Method Soldering Conditions Symbol Infrared reflow Package peak temperature: 235 °C, time: 30 sec. max. (over 210 °C), count: twice or less, restriction days: 3Note (after that, 125 °C pre-baking for 20 hours is necessary) Precautions: (1) Reflow a second time should be started when the device temperature has returned to its normal state after the first reflow. (2) Avoid flux cleaning with water after the first reflow. IR35-203-2 Pin partial heating Pin temperature: 300 °C max., time: 3 seconds max. (per side) Note This means the number of days after unpacking the dry pack. Storage conditions are 25 °C and 65 % RM max. 24 — µPD98402A [MEMO] 25 µPD98402A [MEMO] The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: “Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M4 94.11 26