COP404C ROMless CMOS Microcontrollers General Description Features The COP404C ROMless Microcontroller is a member of the COPSTM family, fabricated using double-poly, silicon gate CMOS (microCMOS) technology. The COP404C contains CPU, RAM, I/O and is identical to a COP444C device except the ROM has been removed and pins have been added to output the ROM address and to input the ROM data. The COP404C can be configured, by means of external pins, to function as a COP444C, a COP424C, or a COP410C. Pins have been added to allow the user to select the various functional options that are available on the family of mask-programmed CMOS parts. The COP404C is primarily intended for use in the development and debug of a COP program for the COP444C/445C, COP424C/425C, and COP410C/411C devices prior to masking the final part. The COP404C is also appropriate in low volume applications or when the program might be changing. Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Accurate emulation of the COP444C, COP424C and COP410C Lowest Power Dissipation (50 mW typical) Fully static (can turn off the clock) Power saving IDLE state and HALT mode 4 ms instruction time, plus software selectable clocks 128 c 4 RAM, addresses 2k c 8 ROM True vectored interrupt, plus restart Three-level subroutine stack Single supply operation (2.4V to 5.5V) Programmable read/write 8-bit timer/event counter Internal binary counter register with MICROWIRETM serial I/O capability General purpose and TRI-STATEÉ outputs LSTTL/CMOS compatible MICROBUSTM compatible Software/hardware compatible with other members of the COP400 family MICROBUSTM and MICROWIRETM are trademarks of National Semiconductor Corporation. TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. Block Diagram TL/DD/5530 – 1 FIGURE 1. Block Diagram C1995 National Semiconductor Corporation TL/DD/5530 RRD-B30M105/Printed in U. S. A. COP404C ROMless CMOS Microcontrollers April 1992 Absolute Maximum Ratings Supply Voltage Voltage at any pin 6V Operating temperature range b 0.3V to VCC a 0.3V Total Allowable Source Current Total Allowable Sink Current 25 mA 25 mA DC Electrical Characteristics Parameter Operating Voltage Power Supply Ripple (Notes 4, 5) Storage temperature range Lead temperature (soldering, 10 sec.) Conditions Min Max Units 2.4 5.5 0.1 VCC V V 120 700 3000 mA mA mA 20 6 mA mA 0.1 VCC V V 0.2 VCC V V peak to peak VCC e 2.4V, tc e 64 ms VCC e 5.0V, tc e 16 ms VCC e 5.0V, tc e 4 ms (Tc is instruction cycle time) HALT Mode Current (Note 2) VCC e 5.0V, FIN e 0 kHz, TA e 25§ C VCC e 2.4V, FIN e 0 kHz, TA e 25§ C Input Voltage Levels RESET, D0 (clock input) CKI Logic High Logic Low All other inputs (Note 7) Logic High Logic Low 0.9 VCC 0.7 VCC VCC e 4.5V, VIN e 0 Hi-Z input leakage 30 330 mA b1 a1 mA 7 pF 0.4 V V 0.2 V V 330 80 mA mA mA mA mA mA 5 mA 100 pF .7 1.6 mA mA a 2.5 mA Input capacitance (Note 4) Output Voltage Levels LSTTL Operation Logic High Logic Low CMOS Operation Logic High Logic Low Output current levels Sink (Note 6) Source (Standard option) Source (Low current option) Standard outputs VCC e 5.0V g 10% IOH eb100 mA IOL e 400 mA IOH eb10 mA IOL e 10 mA 2.7 VCCb0.2 VCC e 4.5V, VOUT e VCC VCC e 2.4V, VOUT e VCC VCC e 4.5V, VOUT e 0V VCC e 2.4V, VOUT e 0V VCC e 4.5V, VOUT e 0V VCC e 2.4V, VOUT e 0V 1.2 0.2 0.5 0.1 30 6 Allowable Sink/Source current per pin (Note 6) Allowable Loading on CKOH Current needed to over-ride HALT (Note 3) To continue To halt 300§ C 0§ CsTas70§ C unless otherwise specified Supply Current (Note 1) Input Pull-up current 0§ to a 70§ C b 65§ C to a 150§ C VCC e 4.5V, VIN e 2VCC VCC e 4.5V, VIN e 7VCC TRI-STATE leakage current b 2.5 Note: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. 2 COP404C AC Electrical Characteristics 0§ CsTAs70§ C unless otherwise specified Min Max Units Instruction Cycle Time (tc) Parameter VCCt4.5V 4.5VlVCCt2.4V 4 16 DC DC ms ms Operating CKI Frequency VCCt4.5V 4.5VlVCCt2.4V DC DC 1.0 250 MHz kHz Duty Cycle (Note 4) f1 e 4 MHz 40 60 % Rise Time (Note 4) Fall Time (Note 4) f1 e 4 MHz external clock 60 40 ns ns Instruction Cycle Time using D0 as a RC Oscillator DualClock Input (Note 4) R e 30k, VCC e 5V C e 82 pF 16 ms INPUTS: (See Fig. 3 ) tSETUP tHOLD OUTPUT PROPAGATION DELAY IP7 ± IP0, A10±A8, SKIP tPD1, tPD0 AD/DATA tPD1, tPD0 ALL OTHER OUTPUTS tPD1, tPD0 MICROBUS TIMING Read Operation (Fig. 4 ) Conditions G Inputs SI Input VCCt4.5V IP Input All Others VCCt4.5V 4.5VlVCCt2.4V * 8 Tc/4 a .7 0.3 1.0 1.7 0.25 1.0 ms ms ms ms ms ms VOUT e 1.5V, CL e 100 pF, RL e 5K VCCt4.5V 4.5VlVCCt2.4V 1.94 7.75 ms ms VCCt4.5V 4.5VlVCCt2.4V 375 1.5 ns ms VCCl4.5V 4.5VlVCCt2.4V 1.0 4.0 ms ms CL e 50 pF, VCC e 5V g 5% Chip select stable before RD btCSR 65 Chip select hold time for RD btRCS 20 ns ns RD pulse width btRR 400 ns Data delay from RD btRD 375 ns RD to data floating btDF (Note 4) 250 ns Write Operation (Fig. 5 ) Chip select stable before WR btCSW 65 Chip select hold time for WR btWCS 20 ns WR pulse width btWW 400 ns Data set-up time for WR btDW 320 ns Data hold time for WR btWD 100 ns INTR transition time from WR btWI ns 700 ns Note 1: Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI and all other pins pulled up to VCC with 20k resistors. See current drain equation on page 16. Note 2: Test conditions: All inputs tied to VCC; L lines in TRI-STATE mode and tied to Ground; all outputs tied to Ground. Note 3: When forcing HALT, current is only needed for a short time (approx. 200 ns) to flip the HALT flip-flop. Note 4: This parameter is only sampled and not 100% tested. Variation due to the device included. Note 5: Voltage change must be less than 0.1 VCC in a 1 ms period. Note 6: SO output sink current must be limited to keep VOL less than 0.2 VCC to prevent entering test mode. Note 7: MB, TIN, DUAL, SEL10, SEL20, input levels at VCC or VSS. 3 Connection Diagram Pin Descriptions Dual-In-Line Package Pin VCC VSS CKI RS CKOI L0 ± L7 G0 ± G3 D1 ± D3 D0 IN0 ± IN3 SO SI SK IP0 ± IP7 A8, A9, A10 SKIP AD/DATA MB CKOH DUAL TIN SEL10 SEL20 UNUSED TL/DD/5530–2 Order Number COP404CN See NS Package Number N48A Description Most positive voltage Ground Clock input Reset input General purpose input 8 TRI-STATE I/O 4 general purpose I/O 3 general purpose outputs Either general purpose output or Dual-Clock RC input 4 general purpose inputs Serial data output Serial data input Serial data clock output I/O for ROM address and data 3 address outputs Skip status output Clock output MICROBUS select input Halt I/O pin Dual-Clock select input Timer input select pin (should be connected to GND) COP410C emulation select input COP424C emulation select input Ground FIGURE 2 The internal architecture is shown in Figure 1 . Data paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implementing the instruction set of the device. Positive logic is used. When a bit is set, it is a logic ‘‘1’’, when a bit is reset, it is a logic ‘‘0’’. pushes the next PC address into the stack. Each return pops the stack back into the PC register. DATA MEMORY Data memory consists of a 512-bit RAM, organized as 8 data registers of 16 c 4-bit digits. RAM addressing is implemented by a 7-bit B register whose upper 3 bits (Br) select 1 of 8 data registers and lower 4 bits (Bd) select 1 of 16 4-bit digits in the selected data register. While the 4-bit contents of the selected RAM digit (M) are usually loaded into or from, or exchanged with, the A register (accumulator), it may also be loaded into or from the Q latches or T counter or loaded from the L ports. RAM addressing may also be performed directly by the LDD and XAD instructions based upon the immediate operand field of these instructions. The Bd register also serves as a source register for 4-bit data sent directly to the D outputs. PROGRAM MEMORY Program Memory consists of a 2048-byte external memory (typically PROM). Words of this memory may be program instructions, constants or ROM addressing data. ROM addressing is accomplished by a 11-bit PC register which selects one of the 8-bit words contained in ROM. A new address is loaded into the PC register during each instruction cycle. Unless the instruction is a transfer of control instruction, the PC register is loaded with the next sequential 11-bit binary count value. Three levels of subroutine nesting are implemented by a three level deep stack. Each subroutine call or interrupt 4 Timing Diagrams TL/DD/5530 – 3 FIGURE 3. Input/Output Timing TL/DD/5530 – 4 FIGURE 4. MICROBUS Read Operation Timing TL/DD/5530 – 5 FIGURE 5. MICROBUS Write Operation Timing 5 Functional Description EN is an internal 4-bit register loaded by the LEI instruction. The state of each bit of this register selects or deselects the particular feature associated with each bit of the EN register: 0. The least significant bit of the enable register, EN0, selects the SIO register as either a 4-bit shift register or a 4bit binary counter. With EN0 set, SIO is an asynchronous binary counter, decrementing its value by one upon each low-going pulse (‘‘1’’ to ‘‘0’’) occurring on the SI input. Each pulse must be at least two instruction cycles wide. SK outputs the value of SKL. The SO output equals the value of EN3. With EN0 reset, SIO is a serial shift register left shifting 1 bit each instruction cycle time. The data present at SI goes into the least significant bit of SIO. SO can be enabled to output the most significant bit of SIO each cycle time. The SK outputs SKL ANDed with the instruction cycle clock. 1. With EN1 set, interrupt is enabled. Immediately following an interrupt, EN1 is reset to disable further interrupts. 2. With EN2 set, the L drivers are enabled to output the data in Q to the L I/O port. Resetting EN2 disables the L drivers, placing the L I/O port in a high-impedance input state. 3. EN3, in conjunction with EN0, affects the SO output. With EN0 set (binary counter option selected) SO will output the value loaded into EN3. With EN0 reset (serial shift register option selected), setting EN3 enables SO as the output of the SIO shift register, outputting serial shifted data each instruction time. Resetting EN3 with the serial shift register option selected disables SO as the shift register output; data continues to be shifted through SIO and can be exchanged with A via an XAS instruction but SO remains set to ‘‘0’’. INTERNAL LOGIC The processor contains its own 4-bit A register (accumulator) which is the source and destination register for most I/O, arithmetic, logic, and data memory access operations. It can also be used to load the Br and Bd portions of the B register, to load and input 4 bits of the 8-bit Q latch or T counter, L I/O ports data, to input 4-bit G, or IN ports, and to perform data exchanges with the SIO register. A 4-bit adder performs the arithmetic and logic functions, storing the results in A. It also outputs a carry bit to the 1-bit C register, most often employed to indicate arithmetic overflow. The C register in conjunction with the XAS instruction and the EN register, also serves to control the SK output. The 8-bit T counter is a binary up counter which can be loaded to and from M and A using CAMT and CTMA instructions. This counter is operated as a time-base counter. When the T counter overflows, an overflow flag will be set (see SKT and IT instructions below). The T counter is cleared on reset. A functional block diagram of the timer/ counter is illustrated in Figure 10a . Four general-purpose inputs, IN3–IN0, are provided. IN1, IN2 and IN3 may be selected (by pulling MB pin low) as Read Strobe, Chip Select, and Write Strobe inputs, respectively, for use in MICROBUS application. The D register provides 4 general-purpose outputs and is used as the destination register for the 4-bit contents of Bd. In the dual clock mode, D0 latch controls the clock selection (see dual oscillator below). The G register contents are outputs to a 4-bit general-purpose bidirectional I/O port. G0 may be selected as an output for MICROBUS applications. The Q register is an internal, latched, 8-bit register, used to hold data loaded to or from M and A, as well as 8-bit data from ROM. Its contents are outputted to the L I/O ports when the L drivers are enabled under program control. With the MICROBUS option selected, Q can also be loaded with the 8-bit contents of the L I/O ports upon the occurrence of a write strobe from the host CPU. The 8 L drivers, when enabled, output the contents of latched Q data to the L I/O port. Also, the contents of L may be read directly into A and M. As explained above, the MICROBUS option allows L I/O port data to be latched into the Q register. The SIO register functions as a 4-bit serial-in/serial-out shift register for MICROWIRETM I/O and COPS peripherals, or as a binary counter (depending on the contents of the EN register). Its contents can be exchanged with A. The XAS instruction copies C into the SKL latch. In the counter mode, SK is the output SKL; in the shift register mode, SK outputs SKL ANDed with the clock. INTERRUPT The following features are associated with interrupt procedure and protocol and must be considered by the programmer when utilizing interrupts. a. The interrupt, once recognized as explained below, pushes the next sequential program counter address (PC a 1) onto the stack. Any previous contents at the bottom of the stack are lost. The program counter is set to hex address 0FF (the last word of page 3) and EN1 is reset. b. An interrupt will be recognized only on the following conditions: 1. EN1 has been set. 2. A low-going pulse (‘‘1’’ to ‘‘0’’) at least two instruction cycles wide has occurred on the IN1 input. 3. A currently executing instruction has been completed. TABLE I. ENABLE REGISTER MODES Ð BITS EN0 AND EN3 EN0 EN3 0 0 Shift Register SIO 0 1 Shift Register 1 1 0 1 Binary Counter Binary Counter SI Input to Shift Register Input to Shift Register Input to Counter Input to Counter 6 SO SK Serial out 0 1 If SKL e 1, SK e clock If SKL e 0, SK e 0 If SKL e 1, SK e clock If SKL e 0, SK e 0 SK e SKL SK e SKL 0 Functional Description (Continued) functioning and timing relationships between the signal lines affected by this option are as specified for the MICROBUS interface, and are given in the AC electrical characteristics and shown in the timing diagrams (Figures 4 and 5 ). Connection of the COP404C to the MICROBUS is shown in Figure 6 . 4. All successive transfer of control instructions and successive LBIs have been completed (e.g. if the main program is executing a JP instruction which transfers program control to another JP instruction, the interrupt will not be acknowledged until the second JP instruction has been executed). c. Upon acknowledgement of an interrupt, the skip logic status is saved and later restored upon popping of the stack. For example, if an interrupt occurs during the execution of an ASC (Add with Carry, Skip on Carry) instruction which results in carry, the skip logic status is saved and program control is transferred to the interrupt servicing routine at hex address 0FF. At the end of the interrupt routine, a RET instruction is executed to pop the stack and return program control to the instruction following the original ASC. At this time, the skip logic is enabled and skips this instruction because of the previous ASC carry. Subroutines should not be nested within the interrupt service routine, since their popping of the stack will enable any previously saved main program skips, interfering with the orderly execution of the interrupt routine. d. The instruction at hex address 0FF must be a NOP. e. An LEI instruction may be put immediately before the RET instruction to re-enable interrupts. INITIALIZATION The external RC network shown in Figure 7 must be connected to the RESET pin for the internal reset logic to initialize the device upon power-up. The RESET pin is configured as a Schmitt trigger input. If not used, it should be connected to VCC. Initialization will occur whenever a logic ‘‘0’’ is applied to the RESET input, providing it stays low for at least three instruction cycle times. Upon initialization, the PC register is cleared to 0 (ROM address 0) and the A, B, C, D, EN, IL, T and G registers are cleared. The SKL latch is set, thus enabling SK as a clock output. Data Memory (RAM) is not cleared upon initialization. The first instruction at address 0 must be a CLRA (clear A register). MICROBUS INTERFACE With MB pin tied to Ground, the COP404C can be used as a peripheral microprocessor device, inputting and outputting data from and to a host microprocessor (mP). IN1, IN2 and IN3 general purpose inputs become MICROBUS compatible read-strobe, chip-select, and write-strobe lines, respectively. IN1 becomes RD Ð a logic ‘‘0’’ on this input will cause Q latch data to be enabled to the L ports for input to the mP. IN2 becomes CS Ð a logic ‘‘0’’ on this line selects the COP404C and the mP peripheral device by enabling the operation of the RD and WR lines and allows for the selection of one of several peripheral components. IN3 becomes WR Ð a logic ‘‘0’’ on this line will write bus data from the L ports to the Q latches for input to the COP404C. G0 becomes INTR a ‘‘ready’’ output, reset by a write pulse from the mP on the WR line, providing the ‘‘handshaking’’ capability necessary for asynchronous data transfer between the host CPU and the COP404C. This option has been designed for compatibility with National’s MICROBUS - a standard interconnect system for 8-bit parallel data transfer between MOS/LSI CPUs and interfacing devices. (See MICROBUS National Publication). The TL/DD/5530 – 8 FIGURE 7. Power-Up Circuit TIMER The timer is operated as a time-base counter. The instruction cycle frequency generated from CKI passes through a 2-bit divide-by-4 prescaler. The output of this prescaler increments the 8-bit T counter thus providing a 10-bit timer. The prescaler is cleared during execution of a CAMT instruction and on reset. For example, using a 1MHz crystal, the instruction cycle frequency of 250 kHz (divide by 4) increments the 10-bit timer every 4 mS. By presetting the counter and detecting overflow, accurate timeouts between 16 mS (4 counts) and 4.096 mS (1024 counts) are possible. Longer timeouts can be achieved by accumulating, under software control, multiple overflows. HALT MODE The COP404C is a FULLY STATIC circuit; therefore, the user may stop the system oscillator at any time to halt the chip. The chip may also be halted by two other ways (see Figure 8 ): Ð Software HALT: by using the HALT instruction. Ð Hardware HALT: by using the HALT I/O port CKOH. It is an I/O flip-flop which is an indicator of the HALT status. An external signal can over-ride this pin to start and stop the chip. By forcing CKOH high the TL/DD/5530 – 7 FIGURE 6. MICROBUS Option Interconnect 7 D0 oscillator (the instruction cycle time equals the D0 oscillation frequency divided by 4) by setting the D0 latch high or the CKI oscillator by resetting D0 latch low. Functional Description (Continued) chip will stop as soon as CKI is high and CKOH output will stay high to keep the chip stopped if the external driver returns to high impedance state. Note that even in dual clock mode, the counter, if used as a time-base counter, is always connected to the CKI oscillator. For example, the user may connect up to a 1 MHz RC circuit to D0 for faster processing and a 32 kHz external clock to CKI for minimum current drain and time keeping. Note: CTMA instruction is not allowed when the chip is running from D0 clock. Once in the HALT mode, the internal circuitry does not receive any clock signal and is therefore frozen in the exact state it was in when halted. All information is retained until continuing. The chip may be awakened by one of two different methods: Ð Continue function: by forcing CKOH low, the system clock will be re-enabled and the circuit will continue to operate from the point where it was stopped. CKOH will stay low. Ð Restart: by forcing the RESET pin low (see Initialization) The HALT mode is the minimum power dissipation state. Note: if the user has selected dual-clock (DUAL pin tied to Ground) AND is forcing an external clock on D0 pin AND the COP404C is running from the D0 clock, the HALT mode - either hardware or software - will NOT be entered. Thus, the user should switch to the CKI clock to HALT. Alternatively, the user may stop the D0 clock to minimize power. Figures 10a and 10b show the timer and clock diagrams with and without Dual-Clock. Oscillator Options TL/DD/5530 – 9 There are two basic clock oscillator configurations available as shown by Figure 9. R C 15k 82 pF 30k 82 pF 60k 100 pF Note: 15ksRs150k Ð CKI oscillator: CKI is configured as a LSTTL compatible input external clock signal. The external frequency is divided by 4 to give the instruction cycle time. Ð Dual oscillator. By tying DUAL pin to Ground, pin D0 is now a single pin RC controlled Schmitt trigger oscillator input. The user may software select between the Cycle Time 4b9 ms 8b16 ms 16b32 ms VCC t 4.5V t 4.5V 2.4b4.5V 50 pFsCs150 pF FIGURE 9. Dual-Oscillator Component Values TL/DD/5530 – 10 FIGURE 8. HALT Mode 8 Functional Description (Continued) TL/DD/5530 – 11 FIGURE 10a. Clock and Timer Block Diagram without Dual-Clock TL/DD/5530 – 12 Figure 10b. Clock and Timer Block Diagram with Dual-Clock 9 External Memory Interface COP404C Instruction Set The COP404C is designed for use with an external Program Memory. This memory may be implemented using any devices having the following characteristics: 1. random addressing 2. LSTTL or CMOS-compatible TRI-STATE outputs 3. LSTTL or CMOS-compatible inputs 4. access time e 1. 0 ms max. Table II is a symbol table providing internal architecture, instruction operand and operation symbols used in the instruction set table. Table III provides the mnemonic, operand, machine code data flow, skip conditions and description of each instruction. Table II. Instruction Set Table Symbols Symbol Definition Internal Architecture Symbols A 4-bit Accumulator B 7-bit RAM address register Br Upper 3 bits of B (register address) Bd Lower 4 bits of B (digit address) C 1-bit Carry register D 4-bit Data output port EN 4-bit Enable register G 4-bit General purpose I/O port IL two 1-bit (IN0 and IN3) latches IN 4-bit input port L 8-bit TRI-STATE I/O port M 4-bit contents of RAM addressed by B PC 11-bit ROM address program counter Q 8-bit latch for L port SA 11-bit Subroutine Save Register A SB 11-bit Subroutine Save Register B SC 11-bit Subroutine Save Register C SIO 4-bit Shift register and counter SK Logic-controlled clock output SKL 1-bit latch for SK output T 8-bit timer Typically, these requirements are met using bipolar PROMs or MOS/CMOS PROMs, EPROMs or E2PROMs. During operation, the address of the next instruction is sent out on A10, A9, A8 and IP7 through IP0 during the time that AD/DATA is high (logic ‘‘1’’ e address mode). Address data on the IP lines is stored into an external latch on the high-tolow transition of the AD/DATA line; A10, A9 and A8 are dedicated address outputs, and do not need to be latched. When AD/DATA is low (logic ‘‘0’’ e data mode), the output of the memory is gated onto IP7 through IP0, forming the input bus. Note that AD/DATA output has a period of one instruction time, a duty cycle of approximately 50%, and specifies whether the IP lines are used for address output or data input. A simplified block diagram of the external memory interface is shown in Figure 11. Instruction operand symbols d 4-bit operand field, 0 – 15 binary (RAM digit select) r 3-bit operand field, 0 – 7 binary (RAM register select) a 11-bit operand field, 0 – 2047 y 4-bit operand field, 0 – 15 (immediate data) RAM(x) RAM addressed by variable x ROM(x) ROM addressed by variable x Operational Symbols a Plus b Minus –l Replaces k – l is exchanged with e Is equal to b TL/DD/5530–13 A FIGURE 11. External Memory Interface to COP404C Z : 10 one’s complement of A exclusive-or range of values Instruction Set (Continued) TABLE III. COP404C Instruction Set Mnemonic Operand Hex Code Machine Language Code (Binary) Data Flow Skip Conditions Description ARITHMETIC INSTRUCTIONS ASC 30 l0011l0000l ADD ADT AISC 31 4A 5b l0011l0001l l0011l0001l l0101l y l CASC 10 l0001l0000l CLRA COMP NOP RC SC XOR 00 40 44 32 22 02 l0000l0000l l0100l0000l l0100l0100l l0011l0010l l0010l0010l l0000l0010l y A a C a RAM(B) x A Carry x C A a RAM(B) x A A a 1010 x A Aay x A A a RAM(B) a C x A Carry x C 0xA AxA None ‘‘0’’ x C ‘‘1’’ x C A Z RAM(B) x A Carry None None None None None None Add with Carry, Skip on Carry Add RAM to A Add Ten to A Add Immediate. Skip on Carry (y i 0) Compliment and Add with Carry, Skip on Carry Clear A Ones complement of A to A No Operation Reset C Set C Exclusive-OR RAM with A None None Jump Indirect (note 2) Jump None Jump within Page (Note 3) None Jump to Subroutine Page (Note 4) None Jump to Subroutine None Always Skip on Return Return from Subroutine Return from Subroutine then Skip None HALT processor None IDLE till timer overflows then continues None Copy A, RAM to T None None Copy T to RAM, A Copy A, RAM to Q None Copy Q to RAM, A None None Load RAM into A, Exclusive-OR Br with r Load A with RAM pointed to direct by r,d Load Q Indirect (Note 2) None Reset RAM Bit None None Carry Carry TRANSFER OF CONTROL INSTRUCTIONS JID JMP a JP a FF 6b Ð Ð l1111l1111l l0110l0la10:8l l a7:0 l l1l a6:0 l Ð JSRP a Ð (pages 2,3 only) or l11l a5:0 l (all other pages) l10l a5:0 l JSR a 6b Ð 48 49 l0110l1la10:8l l a7:0 l l0100l1000l l0100l1001l 33 38 33 39 l0011l0011l l0011l1000l l0011l0011l l0011l1001l RET RETSK HALT IT ROM (PC10:8 A,M) a x PC a x PC6:0 a x PC5:0 x PC7:0 PC a 1 x SA x SB x SC 00010 x PC10:6 a x PC5:0 PC a 1 x SA x SB x SC a x PC SC x SB x SA x PC SC x SB x SA x PC MEMORY REFERENCE INSTRUCTIONS CAMT CTMA CAMQ CQMA LD LDD r r,d LQID RMB 0 1 2 3 33 3F 33 2F 33 3C 33 2C b5 l0011l0011l l0011l1111l l0011l0011l l0010l1111l l0011l0011l l0011l1100l l0011l0011l l0010l1100l l00l r l0101l 23 Ð BF (r e 0:3) l0010l0011l l0l r l d l l1011l1111l 4C 45 42 43 l0100l1100l l0100l0101l l0100l0010l l0100l0011l A x T7:4 RAM(B) x T3:0 T7:44 x RAM(B) T3:0 x A A x Q7:4 RAM(B) x Q3:0 Q7:4 x RAM(B) Q3:0 x A RAM(B) x A Br Z r x Br RAM(r,d) x A ROM(PC10:8,A,M) x Q SB x SC 0 x RAM(B)0 0 x RAM(B)1 0 x RAM(B)2 0 x RAM(B)3 11 None Instruction Set (Continued) TABLE III. COP404C Instruction Set (Continued) Operand Hex Code Machine Language Code (Binary) STII 0 1 2 3 y 4D 47 46 4B 7b l0100l1101l l0100l0111l l0100l0110l l0100l1011l l0111l y l X r b6 l00l r l0110l (r e 0:3) l0010l0011l l1l r l d l l00l r l0111l (r e 0:3) l00l r l0100l Mnemonic SMB XAD r,d XDS r 23 Ð b7 XIS r b4 (r e 0:3) Data Flow Skip Conditions Description 1 x RAM(B)0 1 x RAM(B)1 1 x RAM(B)2 1 x RAM(B)3 y x RAM(B) Bd a 1 x Bd RAM(B) Ý A Br Z r x Br RAM(r,d) Ý A None Set RAM Bit None RAM(B) Ý A Bdb1 x Bd Br Z r x Br RAM(B) Ý A Bd a 1 x Bd Br Z r x Br Bd decrements past 0 Bd increments past 15 Store Memory Immediate and Increment Bd Exchange RAM with A, Exclusive-OR Br with r Exchange A with RAM pointed to directly by r,d Exchange RAM with A and Decrement Bd. Exclusive-OR Br with r Exchange RAM with A and Increment Bd, Exclusive-OR Br with r A x Bd Bd x A r,d x B None None Skip until not a LBI Copy A to Bd Copy Bd to A Load B Immediate with r,d (Note 5) None None REGISTER REFERENCE INSTRUCTIONS CAB CBA LBI r,d 50 4E Ð 33 6b 12 (r e 0:3: d e 0,9:15) or l0011l0011l l1l r l d l (any r, any d) l0011l0011l l0110l y l l0001l0010l 20 21 33 21 33 01 11 03 13 01 11 03 13 41 l0010l0000l l0010l0001l l0011l0011l l0010l0001l l0011l0011l l0000l0001l l0001l0001l l0000l0011l l0001l0011l l0000l0001l l0001l0001l l0000l0011l l0001l0011l l0100l0001l 33 Ð LEI y XABR l0101l0000l l0100l1110l l00l r l(d-1)l y x EN None Load EN Immediate (Note 6) A Ý Br None Exchange A with Br (Note 7) C e ‘‘1’’ A e RAM(B) G3:0 e 0 Skip if C is True Skip if A Equals RAM Skip if G is Zero (all 4 bits) Skip if G Bit is Zero TEST INSTRUCTIONS SKC SKE SKGZ SKGBZ SKMBZ SKT 0 1 2 3 0 1 2 3 1st byte 2nd byte 12 G0 e 0 G1 e 0 G2 e 0 G3 e 0 RAM(B)0 e 0 RAM(B)1 e 0 RAM(B)2 e 0 RAM(B)3 e 0 A time-base counter carry has occured since last test Skip if RAM Bit is Zero Skip on Timer (Note 2) Instruction Set (Continued) TABLE III. COP404C Instruction Set (Continued) Mnemonic Operand Machine Language Code (Binary) Hex Code Skip Conditions Data Flow Description INPUT/OUTPUT INSTRUCTIONS ING ININ INIL INL OBD OGI y OMG XAS 33 2A 33 28 33 29 33 2E 33 3E 33 5b 33 3A 4F l0011l0011l l0010l1010l l0011l0011l l0010l1000l l0011l0011l l0010l1001l l0011l0011l l0010l1110l l0011l0011l l0011l1110l l0011l0011l l0101l y l l0011l0011l l0011l1010l l0100l1111l G xA None Input G Ports to A IN xA None Input IN Inputs to A None None Input IL Latches to A (Note 2) Input L Ports to RAM,A None Output Bd to D Outputs None Output to G Ports Immediate Output RAM to G Ports IL3, CKO, ‘‘0’’, IL0 xA L7:4 x RAM(B) L3:0 x A Bd x D y xG RAM(B) A xG Ý SIO, C x SKL None None Exchange A with SIO (Note 2) Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are numbered O to N where O signifies the least significant bit (low-order, right-most bit). For example, A3 indicates the most significant (left-most) bit of the 4-bit A register. Note 2: For additional information on the operation of the XAS, JID, LQID, INIL, and SKT instructions, see below. Note 3: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction, otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page. Note 4: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of P). A JSRP may not be used when in pages 2 or 3. JSRP may not jump to the last word in page 2. Note 5: LBI is a single-byte instruction if d e 0, 9, 10, 11, 12, 13, 14, or 15. The machine code for the lower 4 bits equals the binary value of the ‘‘d’’ data minus 1, e.g., to load the lower four bits of B(Bd) with the value 9 (10012), the lower 4 bits of the LBI instruction equal 8 (10002). To load 0, the lower 4 bits of the LBI instruction should equal 15 (11112). Note 6: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a ‘‘1’’ or ‘‘0’’ in each bit of EN corresponds with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.) Note 7: If SEL2O e 1, A If SEL2O e 0, A Ý Br (0 x A3) Ý Br (0,0 x A3, A2). Description of Selected Instructions new address is fetched and loaded into the Q latches. Next, the stack is ‘‘popped’’ (SC x SB x SA x PC), restoring the saved value of PC to continue sequential program execution. Since LQID pushes SB x SC, the previous contents of SC are lost. Note: LQID uses 2 instruction cycles if executed, one if skipped. XAS INSTRUCTION XAS (Exchange A with SIO) copies C to the SKL latch and exchanges the accumulator with the 4-bit contents of the SIO register. The contents of SIO will contain serial-in/serial-out shift register or binary counter data, depending on the value of the EN register. If SIO is selected as a shift register, an XAS instruction can be performed once every 4 instruction cycles to effect a continuous data stream. JID INSTRUCTION JID (Jump Indirect) is an indirect addressing instruction, transferring program control to a new ROM location pointed to indirectly by A and M. It loads the lower 8 bits of the ROM address register PC with the contents of ROM addressed by the 11-bit word, PC10: 8, A, M. PC10, PC9 and PC8 are not affected by JID. Note: JID uses 2 instruction cycles if executed, one if skipped. LQID INSTRUCTION LQID (Load Q Indirect) loads the 8-bit Q register with the contents of ROM pointed to by the 11-bit word PC10: PC8, A, M. LQID can be used for table lookup or code conversion such as BCD to seven-segment. The LQID instruction ‘‘pushes’’ the stack (PC a 1 x SA x SB x SC) and replaces the least significant 8 bits of the PC as follows: A x PC (7:4), RAM(B) x PC(3:0), leaving PC(10), PC(9) and PC(8) unchanged. The ROM data pointed to by the 13 Description of Selected Instructions (Continued) If using an external square wave oscillator, the following equation can be used to calculate the COP404C operating current drain: Ico e Iq a V c 40 c Fi a V c 1400 c Fi / 4 SKT INSTRUCTION The SKT (Skip On Timer) instruction tests the state of the T counter overflow latch (see internal logic, above), executing the next program instruction if the latch is not set. If the latch has been set since the previous test, the next program instruction is skipped and the latch is reset. The features associated with this instruction allow the processor to generate its own time-base for real-time processing, rather than relying on an external input signal Note: If the most significant bit of the T counter is a 1 when a CAMT instruction loads the counter, the overflow flag will be set. The following sample of codes should be used when loading the counter: CAMT ; load T counter SKT ; skip if overflow flag is set and reset it NOP where: Ico e chip operating current drain in microamps Iq e quiescent leakage current (from curve) Fi e CKI frequency in MegaHertz V e chip VCC in volts For example at 5 volts VCC and 400 kHz: Ico e 20 a 5 c 40 c .4 a 5 c 1400 c .4 / 4 Ico e 20 a 80 a 700 e 800 mA at 2.4 volts VCC and 30 kHz: Ico e 6 a 2.4 c 40 c .03 a 2.4 c 1400 c .0*/4 Ico e 6 a 2.88 a 25.2 e 34.08 mA If an IT instruction is executed, the chip goes into the IDLE mode until the timer overflows. In IDLE mode, the current drain can be calculated from the following equation: Ici e Iq a V c 40 c Fi IT INSTRUCTION The IT (idle till timer) instruction halts the processor and puts it in an idle state until the time-base counter overflows. This idle state reduces current drain since all logic (except the oscillator and time base counter) is stopped. For example, at 5 volts VCC and 400 kHz Ici e 20 a 5 c 40 c .4 e 100 mA The total average current will then be the weighted average of the operating current and the idle current: INIL INSTRUCTION INIL (Input IL Latches to A) inputs 2 latches, IL3 and IL0, CKOI and 0 into A. The IL3 and IL0 latches are set if a lowgoing pulse (‘‘1’’ to ‘‘0’’) has occurred on the IN3 and IN0 inputs since the last INIL instruction, provided the input pulse stays low for at least two instruction cycles. Execution of an INIL inputs IL3 and IL0 into A3 and A0 respectively, and resets these latches to allow them to respond to subsequent low-going pulses on the IN3 and IN0 lines. The state of CKOI is input into A2. A 0 is input into A1. IL latches are cleared on reset. Instruction Set Notes a. The first word of a program (ROM address 0) must be a CLRA (Clear A) instruction. b. Although skipped instructions are not executed, they are still fetched from the program memory. Thus program paths take the same number of cycles whether instructions are skipped or executed except for JID, and LQID. c. The ROM is organized into pages of 64 words each. The Program Counter is a 11-bit binary counter, and will count through page boundaries. If a JP, JSRP, JID, or LQID is the last word of a page, it operates as if it were in the next page. For example: a JP located in the last word of a page will jump to a location in the next page. Also, a JID or LQID located in the last word of every fourth page (i.e. hex address 0FF, 1FF, 2FF, 3FF, 4FF, etc.) will access data in the next group of four pages. Ita e Ico c To Ti a Ici c To a Ti To a Ti where: Ita e total average current Ico e operating current Ici e idle current To e operating time Ti e idle time I/O OPTIONS COP404C outputs have the following configurations, illustrated in Figure 12 . a. Standard Ð A CMOS push-pull buffer with an N-channel device to ground in conjunction with a P-channel device to VCC, compatible with CMOS and LSTTL. (Used on SO, SK, AD/DATA, SKIP, A10:8 and D outputs.) b. Low Current Ð This is the same configuration as a. above except that the sourcing current is much less. (Used on G outputs.) c. Standard TRI-STATE L Output Ð A CMOS output buffer similar to a. which may be disabled by program control. (Used on L outputs.) All inputs have the following configuration: d. Input with on chip load device to VCC. (Used on CKOI.) Power Dissipation The lowest power drain is when the clock is stopped. As the frequency increases so does current. Current is also lower at lower operating voltages. Therefore, for minimum power dissipation, the user should run at the lowest speed and voltage that his application will allow. The user should take care that all pins swing to full supply levels to insure that outputs are not loaded down and that inputs are not at some intermediate level which may draw current. Any input with a slow rise or fall time will draw additional current. For example, an RC oscillator on D0 will draw more current than a square wave clock input since it is a slow rising signal. e. HI-Z input which must be driven by the users logic. (Used on CKI, RESET, IN, SI, DUAL, MB, SEL10 and SEL20 inputs.) All output drivers use one or more of three common devices numbered 1 to 3. Minimum and maximum current (IOUT and VOUT) curves are given in Figure 13 for each of these devices to allow the designer to effectively use these I/O configurations. 14 a. Standard Push-Pull Output b. Low Current Push-Pull Output c. Standard TRI-STATE ‘‘L’’ Output TL/DD/5530 – 15 d. Input with Load e. Hi-Z Input FIGURE 12. Input/Output Configurations Typical Performance Characteristics Minimum Sink Current Standard Minimum Source Current Low Current Option Minimum Source Current Low Current Option Maximum Source Current Low Current Option Maximum Source Current Maximum Quiescent Current TL/DD/5530 – 16 FIGURE 13. Input/Output Characteristics 15 Emulation The COP404C may be used to exactly emulate the COP444C/445C, COP424C/425C, and COP410C/411C. However, the Program Counter always addresses 2k of external ROM whatever chip is being emulated. Figure 14 shows the interconnect to implement a hardware emulation. This connection uses a NMC27C16 EPROM as external memory. Other memory can be used such as bipolar PROM or RAM. Pins IP7 – IP0 are bidirectional inputs and outputs. When the AD/DATA clocking output turns on, the EPROM drivers are disabled and IP7 – IP0 output addresses. The 8-bit latch (MM74C373) latches the addresses to drive the memory. TL/DD/5530 – 14 FIGURE 14. COP404C Used To Emulate A COP444C 16 Emulation (Continued) When AD/DATA turns off, the EPROM is enabled and the IP7 – IP0 pins will input the memory data. A10, A9 and A8 output the most significant address bits to the memory. (SKIP output may be used for program debug if needed.) Ð CKI is divided by 4. Other divide-by are emulated by external divider. Ð CKO can be emulated as a general purpose input by using CKOI or as a Halt I/O port by using CKOH. Ð MB pin can be pulled low if the MICROBUS feature of the COP444C and COP424C is needed. Othewise it should be high. Ð DUAL pin can be pulled low if the Dual-Clock feature of the COP444C and COP424C is needed. Otherwise it should be high. Ð The SEL10 and SEL20 inputs are used to emulate the COP444C/445C, COP424C/425C, or COP410C/411C. cant address bits of the program memory should be grounded). Furthermore, the subroutine stack is decreased from 3 levels to 2 levels. The pins SEL10 and SEL20 change the internal logic of the device to accurately emulate the devices as indicated above. However, the user must remember that the COP424C/425C is a subset of the COP444C/COP445C with respect to memory size. The COP410C/411C is a subset both in memory size and in function. The user must take care not to use features and instructions which are not available on the COP410C/411C (see table IV. below) when using the COP404C to emulate the COP410C/411C. TABLE IV. FEATURES AND INSTRUCTIONS NOT AVAILABLE ON COP410C/411C. Timer ADT Dual-clock CASC Interrupt CAMT Microbus CTMA IT LDD r, d XAD r, d (except 3, 15) XABR SKT ININ INIL OGI y # When emulating the COP444C/445C, the user must configure SEL20 e 1 and SEL10 e 1. # When emulating the COP424C/425C, the user must configure SEL20 e 0 and SEL10 e 1. In this mode, the user RAM is physically halved. As in the COP424C/ 425C, the user has 64 digits (256 bits) of RAM available. Pin A10 should not be connected to the program memory (most significant address bit of the program memory should be grounded if using a 2k c 8 memory). # When emulating the COP410C/411C, the user must configure SEL20 e 0 and SEL10 e 0. In this mode, the user has 32 digits (128 bits) of RAM available organized in the same way as the COP410C/411C - 4 registers of 8 digits each. Pins A10 and A9 should not be connected to the program memory (the 2 most signifi- Option Table COP404C MASK OPTIONS The following COP444C options have been implemented in the COP404C: Option value Option 1 e 0 Option 2 e 1, 2 Option 3 e 5 Option 4 e 1 Option 5–8 e 0 Option 9 e 1 Option 10 e 1 Option 11 e 0 Option 12–15 e 0 Option 16 e 1 Option 17 e 0 Option 18 e 0 Option 19 e 1 Option 20 e 1 Option 21–24 e 1 Option 25–28 e 0 Option 29 e 1 Option 30 e 0, 1 Option 31 e 0 Option 32 e 0, 1 Option 33 e N/A 17 Comment Ground Pin Ð no option available CKO is replaced by CKOI and CKOH CKI is external clock input divided by 4 RESET is Hi-Z input L outputs are standard TRI-STATE IN1 is a Hi-Z input IN2 is a Hi-Z input VCC pin Ð no option available L outputs are standard TRI-STATE SI is a Hi-Z input SO is a standard output SK is a standard output IN0 is a Hi-Z input IN3 is a Hi-Z input G outputs are low-current D outputs are standard No internal initialization logic DUAL-CLOCK is pin selectable TIMER time-base counter MICROBUS is pin selectable 48-pin package COP404C ROMless CMOS Microcontrollers Physical Dimensions inches (millimeters) Molded Dual-In-Line Package (N) Order Number COP404CN NS Package Number N48A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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