ETC AGB64LV01-QC

™
Easy GUI Browser Chip
AGB64LV01-QC
•
•
•
•
•
•
Dedicated GUI Chip — Manages the GUI,
interacts with the user, and controls the
LCD— Frees up your Micro!
HTML-Based GUI Creation— create and edit
quickly using drag-and-drop HTML tools
Compiler Included— Converts from HTML,
JPEG, and GIF into small, quickly-executable
Amulet µHTML™ pages
Processor Independent— Easily interfaces to
most microcontrollers (8/16/32-bit and DSPs)
Replaces Traditional GUI Library— No
library porting, complex GUI programming, or
RTOS required
RS232 Interface— Up-to 115.2 Kbps
Amulet’s Easy GUI Browser Chip is a special purpose microcontroller that is optimized to execute
Amulet’s GUI kernel and component based GUI firmware. The chip is a combination LCD controller chip
and a user interface chip. This chip eliminates the
need for complex code to draw each pixel on an
LCD. The chip renders GUI pages containing
graphic images, Amulet Widgets, and other UI objects directly to the LCD. This lets your embedded
micro do its job more efficiently. Thus, the main
application can run on a smaller processor with less
RAM and ROM, and code development and maintenance time is significantly reduced.
The AGB64LV01-QC is an 80-pin FQFP ASIC
with the following built in peripherals:
• LCD Controller
•
Microprocessor
•
UART
•
Timer
•
SPI Master
The Easy GUI Browser chip has 13 dedicated
output lines for LCD control of various size subVGA displays. The chip is able to drive different
size displays because the bias voltage, which
determines the LCD driving voltage, is supplied
from an external source.
•
Supply voltage: 3.3V +10%
•
Applicable LCD duty: up to 1/256 (adjustable in single increments)
Requires:
• 3.3V Power Supply
• Serial Flash (Atmel,
1 Megabit minimum)
• Static RAM (64K-byte
minimum)
• Clock/Crystal
(up to 20 MHz)
Pin
No.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
Name
ICLK
XTAL
/IRQ2
PIXEL_D6
PIXEL_D5
PIXEL_D3
PIXEL_D1
PIXEL_D0
LINE_PULSE
PIXEL_CLK
FRAME_OUT
ADDR6
ADDR4
/WE
DATA2
DATA0
SYNC
ADDR2
ADDR0
ADDR16
ADDR14
/OE
DATA7
DATA5
ADDR12
ADDR11
ADDR9
TXD
RXD
POC1
POC3
/POC4
POC6
SCLK
MOSI
/SS0
/SS2
/SS3
/SS5
/SS7
Pin
No.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
Name
GND
/RESET
PIXEL_D7
VCC
PIXEL_D4
PIXEL_D2
GND
LCD_PWR
FRAME_CLK
GND
ADDR7
ADDR5
VCC
DATA3
DATA1
GND
ADDR3
ADDR1
GND
ADDR15
ADDR13
VCC
DATA6
DATA4
GND
ADDR10
ADDR8
GND
/POC0
POC2
VCC
/IRQ1
POC7
GND
MISO
/SS1
GND
/SS4
/SS6
VCC
Pin Description
I = Input O = Output I/O = Input and Output P = Power Supply
Pin Name
DATA7-DATA0
ADDR16-ADDR0
Type
I/O
O
WE
OE
SYNC
RESET
ICLK
XTAL
IRQ2
RXD
TXD
MISO
MOSI
SS0
SS1-SS6
SS7
POC0
POC3
POC6
POC4
POC1-POC2
IRQ1
POC7
SCLK
PIXEL_D7PIXEL_D0
O
O
O
I
I
O
I
I
O
I
O
O
O
O
I
I
I
I
I
I
I
O
O
Pin Number
45-48, 11-13, 31
40-42, 49, 51-54,
22-25, 34-37, 39
27
43
33
4
1
3
5
57
55
70
69
71
72-73, 75-78
79
58
61
65
63
59-60
64
66
67
6-7, 9-13, 15
PIXEL_CLK
O
19
LINE_PULSE
O
17
FRAME_OUT
FRAME_CLK
LCD_PWR
VCC
GND
O
O
O
P
P
21
18
16
8, 26, 44, 62, 80
2, 14, 20, 32, 38,
50, 56, 68, 74
*Frequency Setup Table.
115200 Baud Rate
Freq. POC Line
1 2 3
10Mhz 1 1 1
12Mhz 0 1 1
16Mhz 1 0 1
20Mhz 0 0 1
19200 Baud Rate
Freq. POC Line
1 2 3
10Mhz 0 1 1
12Mhz 0 1 0
16Mhz 1 0 0
20Mhz 0 0 0
Description
System Data Bus
System Address Bus
Memory Write Enable (1=read 0=write)
Memory Output Enable (0=read 1=write)
N/C
System Reset (active low)
System Clock See Diagram for connections
System Clock
Interrupt Request (active low)
UART Receive Data
UART Transmit Data
SPI Data In
SPI Data Out
SPI Flash Select
Extra Slave Selects
System Ram Test Status
System Power-Up Mode
Flash Programming Rate*
System Ram Test
Touch Panel Calibration
Crystal Selection*
Touch Panel Interrupt
N/C
SPI Clock
LCD Pixel Data. This output bus transfers data
to be displayed on the LCD. Users can specify
the bus width to be either 1, 2, 4, or 8.
Pixel Data Shift Clock (CL2). User can specify
whether to clock data in on the rising or falling
edge of PIXEL_CLK.
Pixel Data Latch Signal (CL1). This output goes
active for one clock period after all the serial data
for the current line has been shifted to the LCD.
Polarity of this signal can be specified.
Frame Signal (FLM). LCD first frame synchronization.
LCD Drive Signal (M). LCD crystal polarization clock.
Display Control Signal. LCD power (“H”=On, “L”=Off).
Power Supply Pin
Grounding Pin
DC Characteristics
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage 3.3V
Operating Temp.
Storage Temp.
Soldering Lead Temp.
soldering 10 Sec.
Symbol
VCC
Vin
Topr
Tstg
Tsol
Value
-0.3 to +6.5
3.0 to 3.6
-20 to +75
-60 to +150
210
Unit
V
V
°C
°C
°C
DC Characteristics for 3.3V
Item
TTL INPUT
Input “High” Voltage
Input “Low” Voltage
Input Leakage current
CMOS INPUT
Input “High” Voltage
Input “Low” Voltage
Input Leakage current
TTL OUTPUT
Output “High” Voltage
Output “Low” Voltage
CMOS OUTPUT
Symbol
Min
Vih
Vil
IL
2
Vih
Vil
IL
.7 x VCC
Voh
Vol
2.45
Output “High” Voltage
Output “Low” Voltage
Operating Frequency
Pull-up Resistor (Reset, RxD,
POC7, IRQ, MISO, ICLK)
Voh
Vol
F_CLK
.7 x VCC
Typ
-10
-10
10
70K
16
108K
Max
Unit
0.8
10
V
V
µA
0.3VCC
10
V
V
µA
0.45
V
V
0.3VCC
20
202K
V
V
MHz
Ohms
Current
VCC = + 3.3V +/-10%, GND = 0, TEMP= -20 TO +75C
Item
Operating Current
Operating Current
Operating Current
Operating Current
Symbol
Icc
Icc
Icc
Icc
Condition
10MHz
10MHz Reset
16MHz
16MHz Reset
Min
Typ
10
7
16
10
Max
Unit
mA
mA
mA
mA
Detailed Description
Although there is only a single Von-Neuman CPU, the CPU features task specific opcodes,
registers and memory segments for three very different types of tasks: graphics rendering, I/
O processing and general purpose computing. This architecture enables the GUI kernel
firmware to implement a highly efficient task scheduler. In addition, graphics and I/O tasks
are implemented with a minimum of CPU cycles and code space.
The Line Buffer is a parallel loaded shift register with a maximum capacity of 256 bytes. It is
responsible for periodically burst fetching a block of pixel data for each raster line from the
frame buffer. To minimize the burst period, the Line Buffer was implemented as a dual
ported synchronous SRAM block capable of reading a single byte in a single CPU clock
cycle.
To minimize external pin and component count, only a single external memory bus is implemented. Because both the CPU and Line Buffer require access to external memory, a
memory interface unit is employed to resolve arbitration and to direct flow of data and address signals.
The CPU also features a separate I/O bus linking the following on-chip peripherals to the
CPU’s I/O task: an LCD Raster Controller, Three Timers, a UART, and an SPI master with 8
slave selects.
The LCD Raster Controller is a unique peripheral. It is responsible for converting the Line
Buffer data to signals conforming to standard LCD interfaces. These include horizontal and
vertical synchs as well as a serially shifted data stream of pixel data and a shift clock.
LCD Interface Timing Diagrams
The following timing diagrams assume:
DATA WIDTH = 8-bits Max. (Adjustable in Software)
LINE_PULSE = Positive or Negative - Edge Line Pulse (Adjustable in Software)
PIXEL_CLK = Positive or Negative - Edge Pixel Clock (Adjustable in Software)
MAXBYTE = 4 bytes of data per line and with the following data in the line buffer: 20, 21, 22, 23 …
XTAL
PIXEL_CLK
Active Edge
PIXEL_DATA
0
2
1
2
3
2
LINE_PULSE
FRAME_OUT
FRAME_CLK
Interface Information, by Manufacturer/Model
Signal
PIXEL_CLK
PIXEL_D0
PIXEL_D1
PIXEL_D2
PIXEL_D3
LINE_PULSE
FRAME_OUT
FRAME_CLK
LCD_PWR
Seiko
G4 /G8
CL2
D3
D2
D1
D0
CL1
FLM
M
DISP OFF
Optrex
DMF50081
CP
D3
D2
D1
D0
LP
FLM
M
DISP OFF
Denistron
PM0149
CL2(SCP)
D0
D1
D2
D3
CL1(LP)
FLM
M
BLE
NanYa
LMBGAX032X
CP2
D3
D2
D1
D0
CP1
S
Hantronix
DM3224-1
CP
D3
D2
D1
D0
LOAD
FRAME
Pixtech
FE524M1
DCLK
D4
D3
D2
D1
HSYNC
YSYNC
DISPOFF
DON
LCD characteristic settings within the compiler let you specify different
displays either by manufacturer or by size (up to 1/4 VGA resolution),
frame frequency, and pixel clock.
SPI Interface Timing Diagram
/SS0
SCLK
MOSI
MISO
SPI Interface
•
Serial Interface Architecture
•
Minimum 1M-Bit (264 bytes/page * 512 pages)
•
One 264-byte SRAM data buffer
•
TTL I/O
Description
Amulet’s Easy GUI Browser Chip supports an Atmel flash memory device (Part # AT45DB011B-SC)
for data storage of µHTML pages. The flash memory device must be organized with a minimum of
512 pages of 264 bytes each, plus one SRAM data buffer of 264 bytes. The flash is enabled through
a chip select pin (/CS) and accessed via a three-wire serial interface consisting of a serial input (SI),
serial output (SO), and a serial clock (SCK).
Device Operation
The flash device is controlled by instructions from the Amulet Easy GUI Browser Chip. The list of
instructions which Amulet uses to interface to the flash are as follows:
Main Memory Page Read (52H)
Main Memory Page to Buffer Transfer (53H),
Buffer Write (84H)
Buffer to Main Memory Page Program (83H)
Status Register (57H).
If you decide to use a flash device other than the recommended Atmel part, the device must support
the five instructions above. Please check the Atmel datasheet for more information on the Atmel flash
device.
There are two subsystems that access memory: The CPU and the Display Line Buffer. The timing for
each subsystem is detailed below.
CPU Memory Access Timing
The CPU performs both Read and Write accesses to memory. In either case, all timing parameters for
CPU accesses are relative to the falling edge of CLK. All input signals are sampled at the falling edge of
CLK and all output signals transition after some delay relative to the falling edge of CLK. Input Hold
times are the amount of time after the falling edge of CLK that a signal must remain stable. Output Hold
times are the minimum delay that the signal will remain stable after the falling edge of CLK.
tcyc
CPU Write
CLK
tad
tah
ADDR
tds0
Label Description
Value Units
tad
tah
tds0
tdh0
tws
twh
10
5
10
5
8
3
Address Delay
Address Hold
Write Data Delay
Write Data Hold
Write Enable Delay
Write Enable Hold
nS
nS
nS
nS
nS
nS
tdh0
DATA
tws
twh
/WE
CPU Read
CLK
tad
tah
ADDR
tds1
DATA
tdh1
Label Description
Value Units
tad
tah
tds1
tdh1
10
5
5
0
Address Delay
Address Hold
Read Data Setup
Read Data Hold
nS
nS
nS
nS
Line Buffer Memory Access Timing
The Line buffer only performs Read accesses to memory. Timing parameters for Line buffer reads
are relative to both edges of CLK. All input signals are sampled at the rising edge of CLK and all
output signals transition after some delay relative to the falling edge of CLK. Input Hold times are the
amount of time after the rising of CLK that a signal must remain stable. Output Hold times are the
minimum delay that the signal will remain stable after the falling edge of CLK.
tcyc
LineBuffer Read
CLK
tad
tah
ADDR
Label Description
Value Units
tad
tah
tds2
tdh2
10
5
5
5
Address Delay
Address Hold
Read Data Setup
Read Data Hold
nS
nS
nS
nS
tds2 tdh2
DATA
Clock Options
Clock
Oscillator
ICLK
CLOCK
XTAL
Chip Mechanicals 80 PQFP (14x20x2.7mm), 3.2mm FP
Sample Application
Amulet Technologies, LLC
275 Saratoga Avenue, Suite 230
Santa Clara, CA 95050
(408) 244-0363
www.AmuletTechnologies.com
©2001 Amulet Technologies. U.S. and Foreign Patents Pending. Easy GUI and µHTML are Trademarks of Amulet Technologies.