ETC ART2815T

PD - 94529A
ART28XXT SERIES
28V Input, Three Output
ADVANCED ANALOG
HYBRID - HIGH RELIABILITY
RADIATION HARDENED DC/DC CONVERTER
Description
The ART Series of three output DC/DC converters are
designed specifically for use in the hostile radiation
environments characteristic of space and weapon systems. The extremely high level of radiation tolerance
inherent in the ART design is the culmination of extensive research, thorough analysis and testing and of
careful component specification. Many of the best circuit design features characterizing the Advanced Analog standard product line were adapted for incorporation into the ART topology. Capable of uniformly high
performance over long term exposures in radiation intense environments, this series sets the standard for
distributed power systems demanding high performance and reliability.
The ART converters are hermetically sealed in a rugged, low profile package utilizing copper core pins to
minimize resistive DC losses. Long-term hermeticity is
assured through use of parallel seam welded lid attachment along with Advanced Analog’s rugged ceramic pin-to-package seal. Axial orentation of the leads
facilitates preferred bulkhead mounting to the principal
heat-dissipating surface.
Manufactured in a facility fully qualified to MIL-PRF38534, these converters are fabricated utilizing DSSC
qualified processes, and are fully compliant to Class H
while being fully processed to the requirements specified for space. Complete PI & CI testing has been completed including Group C life test. Variations in electrical, mechanical and screening specifications can be
accommodated. Contact Advanced Analog for special
requirements.
www.irf.com
ART
Features
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
Total Dose > 100KRad (Si), 2:1margin
SEE hard to LET = 83 Mev.cm2 /mg
Designed to MIL-PRF-38534 for Space
Derated per MIL-STD-975 & MIL-STD-1547
Output Power Range 3 to 30 Watts
19 to 50 Volt Input Range
Input Undervoltage Lockout
High Electrical Efficiency > 80%
Full Performance from -55°C to +125°C
Continuous Short Circuit Protection
12.8 W / in3 Output Power Density
True Hermetic Package
External Inhibit Port
Externally Synchronizable
Fault Tolerant Design
5V, ±12 or ±15 Volts Outputs Available
1
09/09/02
ART28XXT Series
SPECIFICATIONS
Absolute Maximum/Minimum Ratings Note1 Recommended Operating Conditions Note 2
Input Voltage
Minimum Output Current
Soldering Temperature
Storage Temperature
-0.5V to 80V
5% maximum rated
current, any output
300°C for 10 seconds
-65°C to +135°C
Input Voltage Range
19V to 60V
19V to 50V for full derating
to MIL-STD-975
Output Power Range
3W to 30 W
Operating Temperature -55°C to +125°C
-55°C to +85°C for full
derating to MIL-STD-975
Electrical Performance -55°C < TCASE < +125°C, VIN=28V, CL=0 unless otherwise specified.
Parameter
Symbol
Conditions
Output power Note 5
Output current Note 5
4.95
5.05
IOUT = ±250mAdc, TC = +25°C ART2812(dual)
IOUT = ±250mAdc, TC = +25°C ART2815(dual)
±11.50
±14.50
±12.50
±15.15
POUT
IOUT
Load regulation Note 4
VRLINE
VRLOAD
19 Vdc< VIN < 50Vdc
3
30
(main)
150
3000
(dual)
75
750
(main)
-15
+15
±75 mAdc < IOUT < ±750 mAdc
(dual)
-60
+60
150 mAdc < IOUT < 3000 mAdc
(main)
-180
+180
(dual)
-300
+300
Total regulation
Input current
VRCROSS
(main)
-10
+10
(dual)
-500
+500
VR
W
mAdc
19 Vdc< VIN < 50Vdc
mV
19 Vdc< VIN < 50Vdc
mV
19 Vdc< VIN < 50Vdc
±75 mAdc < IOUT < ±750 mAdc
Cross regulation Note 8
Units
Vdc
VOUT
150 mAdc < IOUT < 3000 mAdc
Line regulation Note 3
Max
(main)
IOUT = 1.5Adc, TC = +25°C
Output voltage accuracy
Min
mV
19 Vdc< VIN < 50Vdc
All conditions of Line, Load,
(main)
Cross Regulation, Aging,
Temperature and Radiation ART2812(dual)
ART2815(dual)
4.8
5.2
±11.1
±13.9
±12.9
±16.0
V
IOUT = minimum rated, Pin 3 open
250
Pin 3 shorted to pin 2 (disabled)
8
mA
IIN
Output ripple voltage Note 6
VRIP
19 Vdc< VIN < 50Vdc
IOUT = 3000 mAdc (main), ±500 mAdc (dual)
100
mVp.p
Input ripple current Note 6
IRIP
19 Vdc< VIN < 50Vdc
IOUT = 3000 mAdc (main), ±500 mAdc (dual)
150
mAp.p
Switching frequency
FS
Sychronization input open. (pin 6)
225
275
KHz
Efficiency
Eff
IOUT = 3000 mAdc (main), ±500 mAdc (dual)
80
%
For Notes to SPECIFICATIONS, refer to page 3
2
www.irf.com
ART28XXT Series
Electrical Performance (Continued)
Parameter
Symbol
Conditions
Enable Input
open circuit voltage
drive current (sink)
voltage range
Output response to step load
changes Notes 7, 11
VTLD
Turn on overshoot
5.0
0.1
50.0
V
mA
V
310
10.0
0.25
80
KHz
V
V
V/µS
%
7.5
W
Short circuit, any output
10% Load to/from 50% load
-200
200
50% Load to/from 100% load
-200
200
mV PK
10% Load to/from 50% load
200
50% Load to/from 100% load
200
µS
TTLD
VTLN
TTLN
VOS
IOUT = 3000 mAdc
VIN = 19 V to/from 50 V
IOUT = ±500 mAdc
(main)
-350
350
(dual)
-1050
1050
IOUT = 3000 mAdc
VIN = 19 V to/from 50 V
IOUT = ±500 mAdc
(main)
500
(dual)
500
(main)
500
(dual)
1500
TDLY
IOUT = minimum and full rated
Capacitive load Notes 9, 10
CL
No effect on DC performance
ISO
mV PK
µS
IOUT = minimum and full rated
Turn on delay Note 14
Isolation
3.0
225
4.5
-0.5
40
20
PD
Recovery time from step line
changes Notes 10, 11,13
Units
External clock signal on Sync. input (pin 4)
Power dissipation, load fault
Output response to step line
changes Notes 10, 11
Max
-0.5
Synchronization Input
frequency range
pulse high level
pulse low level
pulse rise time
pulse duty cycle
Recovery time from step load
changes Notes 11, 12
Min
mV
5
20
(main)
500
(dual)
100
mS
µF
500VDC Input to Output or any pin to case
(except pin 12)
100
MΩ
Notes to SPECIFICATIONS
1.
2.
3.
4.
5.
Operation outside absolute maximum/minimum limits may cause permanent damage to the device. Extended operation at the limits may permanently
degrade performance and affect reliability.
Device performance specified in Electrical Performance table is guaranteed when operated within recommended limits. Operation outside
recommended limits is not specified.
Parameter measured from 28V to 19 V or to 50V while loads remain fixed.
Parameter measured from nominal to minimum or maximum load conditions while line remains fixed.
Up to 750 mA is available from the dual outputs provided the total output power does not exceed 30W.
6.
7.
8.
9.
Guaranteed for a bandwidth of DC to 20MHz. Tested using a 20KHz to 2MHz bandwidth.
Load current is stepped for output under test while other outputs are fixed at half rated load.
Load current is fixed for output under test while other output loads are varied for any combination of minimum to maximum.
A capacitive load of any value from 0 to the specified maximum is permitted without comprise to DC performance. A capacitive load in excess of the
maximum limit may interfere with the proper operation of the converter’s short circuit protection, causing erratic behavior during turn on.
10.
Parameter is tested as part of design characterization or after design or process changes. Thereafter, parameters shall be guaranteed to the limits
specified in the table.
11.
12.
Load transient rate of change, di/dt ≤ 2 A/µSec.
Recovery time is measured from the initiation of the transient to where VOUT has returned to within ±1% of its steady state value.
13.
14.
Line transient rate of change, dv/dt ≤ 50 V/µSec.
Turn on delay time is for either a step application of input power or a logical low to high transition on the enable pin (pin 3) while power is present at the
input.
www.irf.com
3
ART28XXT Series
Group A Tests VIN= 28Volts, CL =0 unless otherwise specified.
Test
Symbol
Output voltage accuracy
VOUT
Group A
Subgroups
Min
Max
(main)
1, 2, 3
4.95
5.05
ART2812(dual)
ART2815(dual)
1, 2, 3
1, 2, 3
±11.70
±14.50
±12.30
±15.15
1, 2, 3
3
30
(main)
1, 2, 3
150
3000
(dual)
1, 2, 3
75
500
(main)
1, 2, 3
4.8
5.2
2812(dual)
2815(dual)
1, 2, 3
1, 2, 3
±11.1
±14.0
±12.9
±15.8
Conditions unless otherwise specified
IOUT = 1.5 Adc
V
IOUT = ±250mAdc
IOUT = ±250mAdc
Output power Note 1
POUT
VIN = 19 V, 28V, 50 V
Output current
Note 1
IOUT
VIN 19 V, 28V, 50 V
Output regulation Note
4
VR
Input current
Units
IOUT = 150, 1500, 3000mAdc
VIN = 19 V, 28V, 50 V
IOUT = ±75, ±310, ±625mAdc
IOUT = ±75, ±250, ±500mAdc
W
mA
V
IOUT = minimum rated, Pin 3 open
1, 2, 3
250
Pin 3 shorted to pin 2 (disabled)
1, 2, 3
8
mA
IIN
Output ripple Note 2
VRIP
VIN = 19 V, 28V, 50 V
IOUT = 3000mA main, ±500mA dual
1, 2, 3
100
mVP-P
Input ripple Note 2
IRIP
VIN = 19 V, 28V, 50 V
IOUT = 3000mA main, ±500mA dual
1, 2, 3
150
mAP-P
Switching frequency
FS
Synchronization pin (pin 6) open
4, 5, 6
225
275
KHz
Efficiency
Eff
IOUT = 800mA main, ±500mA dual
1
2, 3
80
78
Power dissipation,
load fault
PD
Short circuit, any output
1, 2, 3
10% Load to/from 50% load
4, 5, 6
-200
200
50% Load to/from 100% load
4, 5, 6
-200
200
10% Load to/from 50% load
4, 5, 6
200
50% Load to/from 100% load
4, 5, 6
200
(main)
4, 5, 6
500
(dual)
4, 5, 6
1500
Output response to step
load changes Notes 3,
5
VTL
Recovery time from
step load changes
Notes 5, 6
TTL
Turn on overshoot
VOS
%
7.5
W
mVPK
µS
IOUT = minimum and full rated
mV
Turn on delay Note 7
TDLY
IOUT = minimum and full rated
Isolation
ISO
500VDC Input to output or any pin to case
(except pin 12)
4, 5, 6
5
1
100
20
mS
MΩ
Notes to Group A Test Table
1.
Parameter verified during dynamic load regulation tests.
2.
Guaranteed for DC to 20 MHz bandwidth. Test conducted using a 20KHz to 2MHz bandwidth.
3.
Load current is stepped for output under test while other outputs are fixed at half rated load.
4.
Each output is measured for all combinations of line and load. Only the minimum and maximum readings for each output are recorded.
5.
Load step transition time ≥ 10µS.
6.
Recovery time is measured from the initiation of the transient to where VOUT has returned to within ±1% of its steady state value.
7.
Turn on delay time is tested by application of a logical low to high transition on the enable pin (pin 3) with power present at the input.
8.
Subgroups 1 and 4 are performed at +25ºC, subgroups 2 and 5 at -55ºC and subgroups 3 and 6 at +125ºC.
4
www.irf.com
ART28XXT Series
Radiation Performance
The radiation tolerance characteristics inherent in the
ART28XXT converter are the direct result of a carefully
planned ground-up design program with specific radiation
design goals. After identification of the general circuit topology, a primary task of the design effort was selection of
appropriate elements from the list of devices for which
extensive radiation effects data was available. By imposing sufficiently large margins on those electrical parameters subject to the degrading effects of radiation, designers were able to select appropriate elements for incorporation into the circuit. Known radiation data was utilized for
input to PSPICE and RadSPICE in the generation of circuit
performance verification analyses. Thus, electrical performance capability under all environmental conditions including radiation was well understood before first application of power to the inputs.
Completion of first article fabrication, screening and standard environmental testing was followed by radiation testing to confirm design goals. All design goals were met
handily and in most cases exceeded by large margin.
These test samples were built with elements that, with the
foregoing exceptions, were not screened for radiation characteristics. Additional radiation tests on subsequent
ART28XXT manufacturing lots provide continued confirmation of the soundness of the design goals as well as
justification for the element selection criteria.
A principal design goal was a converter topology that, because of large design margins, had radiation performance
essentially independent of normal elemental lot radiation
The following table specifies guaranteed minimum radiation exposure levels tolerated while maintaining specification limits.
performance variations. In the few instances where such
margins were not assured, element lots were selected
from which die were fabricated (and characterized) as
radiation hard devices so that realization of the design
goals could be assured.
Radiation Specification Tcase = 25°C
Test
Conditions
Total Ionizing Dose
(2:1 Margin)
MIL-STD-883, Method 1019.4
Operating bias applied during exposure
Dose Rate
Temporary Saturation
Survival
MIL-STD-883, Method 1021
Neutron Fluence
MIL-STD-883, Method 1017.2
Heavy Ions
(Single event effects)
BNL Tandem Van de Graaff Generator
www.irf.com
Min
Typ
100
500
Max
Unit
KRads
(Si)
1E8
1E11
Rads
(Si)/sec
3E12
Neutron
/cm²
83
MeV•
cm²/mg
5
ART28XXT Series
ART28XXT Circuit Description
Figure I. ART Block Diagram
EMI
Filter
+Input
+Vout
Dual
Return
Under-Voltage
Detector
-Vout
Dual
Primary Bias
& Reference
Enable
+5
Short
Circuit
Return
Sync
Pulse Width
Modulator
Sample
Hold
Input
Return
Circuit Description and Application Information Operating Guidelines
The ART28XXT series of converters have been designed
using a single ended forward switched mode converter
topology. (refer to Figure I.) Single ended topologies enjoy
some advantage in radiation hardened designs in that they
eliminate the possibility of simultaneous turn on of both
switching elements during a radiation induced upset; in
addition, single ended topologies are not subject to transformer saturation problems often associated with double
ended implementations.
The design incorporates an LC input filter to attenuate
input ripple current. A low overhead linear bias regulator is
used to provide bias voltage for the converter primary
control logic and a stable, well regulated reference for the
error amplifier. Output control is realized using a wide
band discrete pulse width modulator control circuit incorporating a unique non-linear ramp generator circuit. This
circuit helps stabilize loop gain over variations in line voltage for superior output transient response. Nominal conversion frequency has been selected as 250 KHz to maximize efficiency and minimize magnetic element size.
Output voltages are sensed using a coupled inductor and
a patented magnetic feedback circuit. This circuit is relatively insensitive to variations in temperature, aging, radiation and manufacturing tolerances making it particularly well suited to radiation hardened designs. The control
logic has been designed to use only radiation tolerant components, and all current paths are limited with series resistance to limit photo currents.
Other key circuit design features include short circuit protection, undervoltage lockout and an external synchronization port permitting operation at an externally set clock
rate.
6
The circuit topology used for regulating output voltages in
the ART28XXT series of converters was selected for a
number of reasons. Significant among these is the ability
to simultaneously provide adequate regulation to each
output voltage while maintaining modest circuit complexity.
These attributes were fundamental in retaining the high
reliability and insensitivity to radiation that characterizes
device performance. Use of this topology dictates that the
user maintain a minimum load on each output as specified
in the electrical tables. Attempts to operate any output
without a load will result in peak charging to a voltage level
well above the specified voltage regulation limits, potentially in excess of ratings, and should be avoided. In most
practical applications, this lower bound on the load range
does not present a serious constraint. Output loads that
are lighter than the specified minimums will result in regulation performance exceeding the limits presented in the
specification tables. Regulation curves illustrating representative performance characteristics are shown in Figures VII, VIII and IX.
Thermal Considerations
The ART series of converters is capable of providing relatively high output power from a package of modest volume. The power density exhibited by these devices is
obtained by combining high circuit efficiency with effective
methods of heat removal from the die junctions. Good
design practices have effectively addressed this requirement inside the device. However when operating at maximum loads, significant heat generated at the die junctions
must be carried away by conduction from the base. To
maintain case temperature at or below the specified maximum of 125°C, this heat can be transferred by attachment
www.irf.com
ART28XXT Series
to an appropriate heat dissipater held in intimate contact
with the converter base-plate.
Effectiveness of this heat transfer is dependent on the
intimacy of the baseplate-heatsink interface. It is therefore suggested that a heat transferring medium possessing good thermal conductivity is inserted between the
baseplate and heatsink. A material utilized at the factory
during testing and burn-in processes is sold under the

trade name of Sil-Pad 4001. This particular product is an
insulator but electrically conductive versions are also available. Use of these materials assures optimum surface
contact with the heat dissipater by compensating for minor surface variations. While other available types of heat
conducting materials and thermal compounds provide similar effectiveness, these alternatives are often less convenient and are frequently messy to use.
A conservative aid to estimating the total heat sink surface
area (AHEAT SINK) required to set the maximum case temperature rise (∆T) above ambient temperature is given by
the following expression:
 ∆T 
A HEAT SINK ≈ 
0.85 
 80 P 
−1.43
− 594
.
Thus, a total heat sink surface area (including fins, if any)
of approximately 32 in2 in this example, would limit case
rise to 35°C above ambient. A flat aluminum plate, 0.25"
thick and of approximate dimension 4" by 4" (16 in 2 per
side) would suffice for this application in a still air environment. Note that to meet the criteria, both sides of the plate
require unrestricted exposure to the ambient air.
Inhibiting Converter Output
As an alternative to application and removal of the DC
voltage to the input, the user can control the converter
output by providing an input referenced, TTL compatible,
logic signal to the enable pin 3. This port is internally pulled
“high” so that when not used, an open connection on the
pin permits normal converter operation. When inhibited
outputs are desired, a logical “low” on this port will shut the
converter down. An open collector device capable of sinking at least 100 µA connected to enable pin 3 will work well
in this application.
A benefit of utilization of the enable input is that following
initial charge of the input capacitor, subsequent turn-on
commands will induce no uncontrolled current inrush.
Figure II. Enable Input Equivalent Circuit
where
∆T = Case temperature rise above ambient
V in
 1

− 1
P = Device dissipation in Watts = POUT 
Eff


As an example, assume that it is desired to maintain the
case temperature of an ART2815T at +65°C or less while
operating in an open area whose ambient temperature
does not exceed +35°C; then
5K
2N2907A
64K
Enable
Input
5.6 V
150K
2N2222A
186K
150K
2N2222A
150K
∆T = 65 - 35 = 35°C
Input
Return
From the Specification Table, the worst case full load efficiency for this device is 80%; therefore the maximum power
dissipation at full load is given by
Converter inhibit is initiated when
this transistor is turned off
1

P = 30 •  − 1 = 30 • (0.25) = 75
.W
.80 
and the required heat sink area is
35


A HEAT SINK = 
0.85 
 80 • 7.5 
−1.43
− 594
. = 318
. in 2
1Sil-Pad is a registered Trade Mark of Bergquist, Minneapolis, MN
www.irf.com
7
ART28XXT Series
Synchronization
Parallel Operation
When using multiple converters, system requirements may
dictate operating several converters at a common system frequency. To accommodate this requirement, the
ART28XXT type converter provides a synchronization
input port (pin 4). Circuit topology is as illustrated in Figure
III.
Although no special provision for forced current sharing
has been incorporated in the ART28XXT series, multiple
units may be operated in parallel for increased output power
applications. The 5 volt outputs will typically share to within
approximately 10% of their full load capability and the dual
(±15 volt) outputs will typically share to within 50% of their
full load. Load sharing is a function of the individual impedance of each output and the converter with the highest
nominal set voltage will furnish the predominant load current.
The sync input port permits synchronization of an ART
converter to any compatible external frequency source
operating in the band of 225 to 310 KHz. The synchronization input is edge triggered with synchronization initiated
on the negative transition. This input signal should be a
negative going pulse referenced to the input return and
have a 20% to 80% duty cycle. Compatibility requires the
negative transition time to be less than 100 ns with a minimum pulse amplitude of +4.25 volts referred to the input
return. In the event of failure of an external synchronization source, the converter will revert to its own internally
set frequency. When external synchronization is not desired, the sync in port may be left open (unconnected)
permitting the converter to operate at its’ own internally set
frequency.
Figure III. Synchronization Input Equivalent Circuit
+10V
5K
Sync
Input
2N2907A
47pf
Input Undervoltage Protection
A minimum voltage is required at the input of the converter
to initiate operation. This voltage is set to a nominal value
of 16.8 volts. To preclude the possibility of noise or other
variations at the input falsely initiating and halting converter operation, a hysteresis of approximately 1.0 volts
is incorporated in this circuit. The converter is guaranteed
to operate at 19 Volts input under all specified conditions.
Input Filter
To attenuate input ripple current, the ART28XXT series
converters incorporate a single stage LC input filter. The
elements of this filter comprise the dominant input load
impedance characteristic, and therefore determine the
nature of the current inrush at turn-on. The input filter
circuit elements are as shown in Figure IV.
Figure IV. Input Filter Circuit
10 Ω
5K
Input
Return
+ Input
3.6 µH
Output Short Circuit Protection
Protection against accidental short circuits on any output
is provided in the ART28XXT converters. This protection
is implemented by sensing primary switching current and,
when an over-current condition is detected, switching action is terminated and a restart cycle is initiated. If the
short circuit condition has not been cleared by the time the
restart cycle has completed, another restart cycle is initiated. The sequence will repeat until the short circuit condition is cleared at which time the converter will resume
normal operation. The effect is that during a shorted condition, a series of narrow pulses are generated at approximately 5% duty cycle which periodically sample the state
of the load. Thus device power dissipation is greatly reduced during this mode of operation.
8
5.4 µfd
Input
Return
www.irf.com
ART28XXT Series
Additional Filtering
Although internal filtering is provided at both input and output terminals, some applications may require additional
filtering in order to accommodate system requirements.
While the internal input filter of Figure IV. keeps input ripple
current below 100 mA p-p, an external filter may be applied
to further attenuate this ripple to a level below the CE03
limits imposed by MIL-STD-461B. Figure V. describes a
filter providing that attenuation.
It is important to be aware that when filtering high frequency noise, parasitic circuit elements can easily dominate filter performance. Therefore, it is incumbent on the
designer to exercise care when preparing a circuit layout
for such devices. Wire runs and lengths should be minimized, high frequency loops should be avoided and careful attention paid to the construction details of magnetic
circuit elements. Tight magnetic coupling will improve overall
magnetic performance and reduce stray magnetic fields.
Figure VI. External Output Filter
Figure V. External Input EMI Filter
L1
+5 V
+5V Out
L3
C1
C6
C2
+5V
Return
5V
Return
L2
+15V
+15V
Out
L4
C3
This circuit shown in Figure V has been constructed on
copper clad board using the materials listed and tested in
the laboratory.
C7
15V
Return
15V
Return
C4
C8
An external filter may also be added to the output where
circuit requirements dictate extremely low output ripple
noise. The output filter described by Figure VI has been
characterized with the ART2815T using the values shown
in the associated material list.
C5
-15V
Out
-15V
L1
7 turns AWG21 bifilar on Mag Inc. core PN YJ-41305-TC or equivalent.
L2
L3
L4
C1-C5
C6
C7, C8
7 turns AWG24 trifilar on Mag Inc. core PN YJ-41305-TC or equivalent.
4 turns AWG21 on Mag Inc. core PN MPP55048 or equivalent.
5 turns AWG21 bifilar on Mag Inc. core PN MPP55048 or equivalent.
2200pF type CKR ceramic capacitor.
170µF, 15V M39006/22-0514 Tantalum.
25µF, 50V M39006/22-0568 Tantalum.
Measurement techniques can impose a significant influence on results. All noise measurements should be measured with test leads as close to the device output pins as
physically possible. Probe ground leads should be kept to
a minimum length.
www.irf.com
9
ART28XXT Series
Performance Characteristics (Typical @ 25°C)
Figure VII.
Efficiency vs Output Power
for Three Line Voltages.
85
Efficiency (%)
80
75
70
18V
65
28V
50V
60
55
50
0
5
10
15
20
25
30
35
Output Power (Watts)
Figure VIII.
5 V Output Regulation Limits
Including all conditions of Line, Load and Cross Regulation.
Output Voltage
5.2
Upper Limit
5.1
Lower Limit
5.0
4.9
4.8
4.7
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Output Current (Amps)
10
www.irf.com
ART28XXT Series
Performance Characteristics (Typical @ 25°C) (Continued)
Figure IX.
±15 V Regulation Curves
For Three conditions of Load on the 5 Volt Output.
Output Voltage (Magnitude)
17.0
5V Load = 3.0A
5V Load = 1.5A
5V Load = 150 mA
16.0
15.0
14.0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Output Current (Each Output)
Figure X.
Cross Regulation Curves
5 Volt Output as a function of 15 Volt Load Current for Three 5 Volt Loads.
5.2
Output Voltage
5.1
5.0
4.9
4.8
5V Load = 150mA
4.7
5V Load = 1.5A
4.6
5V Load = 3.0A
4.5
0
0.1
0.2
0.3
0.4
0.5
0.6
±15 Volt Load Current
www.irf.com
11
ART28XXT Series
ART28XXT Physical & Interface Characteristics
ART28XXT Case Outline
Ø 0.136 - 6 Holes
8
0.040
Pin Dia.
9
1.950
4
11
6 x 0.200
= 1.200
2.200
5
10
1.675
3
12
2
13
1
14
0.375
0.263
0.138
0.300
1.400
0.150
2.400
0.275
0.240
2.700
3.25 Ref.
Max
Mounting
Plane
0.050
Flange
0.500
Max
Note:
1. Dimensions are in inches.
2. Base Plate Mounting Plane Flatness 0.003 maximum.
3. Unless otherwise specified, tolerances are
= ± 2°
∠
.XX
= ± .01
.XXX
= ± .005
4. Device Weight - 120 grams maximum.
Pin Designation
Pin #
1
2
3
4
5
8
9
10
11
12
13
14
12
Signal
+ V input
Input return
Enable
Sync In
No connection
No connection
- 15 Vdc output
15 Vdc output return
+ 15 Vdc output
Chassis
+ 5 Vdc output
5 Vdc output return
Part Numbering
A R T 28 15 T / E M
M odel
In p u t V o lta g e
28 = 28V
1 00 = 1 00 V
O u tp u t V o lta g e s
S cre e n in g L e v e l
N o S uffix = F lig h t
/E M = E n g in ee rin g
O u tp u ts
T = Triple
1 5 = 5 V , ± 1 5V
1 2 = 5 V , ± 1 2V
Note:
Radiation performance not specified for /EM screened device type.
www.irf.com
ART28XXT Series
Standard Process Screening for ART28XXT Series
MIL-STD-883
Requirement
/EM Limits
Method
Flight Limits
(Class K)
Temperature Range
-55°C to +125°C
-55°C to +125°C
Element Evaluation
N/A
MIL-PRF-38534
Non-destructive Bond Pull
2023
N/A
100%
Internal Visual
2017
✓
✓
Temperature Cycle
1010
✓
Cond C
Constant Acceleration
2001,
500 g
Cond A
PIND
2020
N/A
Cond A
Burn-in
1015
160 hrs @ 125°C
320 hrs @ 125°C
Interim Electrical @ 160 hrs
Final Electrical (Group A)
Read & Record Data
(2 × 160 hrs)
MIL-PRF-38534
& Specification
-55, +25, +125°C
-55, +25, +125°C
N/A
2%
PDA (25°C, interim to final)
Radiographic Inspection
2012
N/A
✓
Seal, Fine & Gross
1014
✓
Cond A, C
External Visual
2009
✓
✓
Standard Periodic & Conformance Inspections on ART28XXT Series
Inspection
Application
Quantity
Group A
Part of Screening on Each Unit
Group B
Each Inspection Lot
*5 units
Group C
First Inspection Lot or
Following Class 1 Change
10 Units
Group D
In Line (Part of Element Evaluation)
* Group B quantity for Option 2 End of Line
100%
QCI. No Group B samples reuired for Option 1, In-line.
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
ADVANCED ANALOG: 2270 Martin Av., Santa Clara, California 95050, Tel: (408) 727-0500
Visit us at www.irf.com for sales contact information.
Data and specifications subject to change without notice. 09/02
www.irf.com
13