QS5919 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER QS5919 FEATURES: DESCRIPTION • • • • • • • • • • • • The QS5919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q 0-Q4, Q 5, Q/2. Careful layout and design ensure < 500ps skew between the Q0-Q4, and Q/2 outputs. The QS5919 includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external components. Various combinations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The PLL can also be disabled by the PLL_EN signal to allow low frequency or DC testing. The LOCK output asserts to indicate when phase lock has been achieved. The QS5919 is designed for use in highperformance workstations, multi-board computers, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. 5V operation Low noise CMOS level outputs < 500ps output skew, Q0–Q 4 2xQ output, Q outputs, Q output, Q/2 output Outputs 3-state and reset while OE/RST low PLL disable feature for low frequency testing Internal loop filter RC network Functional equivalent to Motorola MC88915 Positive or negative edge synchronization (PE) Balanced drive outputs ±36mA 160MHz maximum frequency (2xQ output) Available in QSOP and PLCC packages For more information on PLL clock driver products, see Application Note AN-227. FUNCTIONAL BLOCK DIAGRAM REF_SEL LO CK SYNC 0 0 SYNC 1 1 O E/RST R D R D R FEE DBACK PE PH A S E LO O P D ETEC TO R FIL TER D R D D FREQ _SEL 0 1 1 VCO R PLL_E N R /2 D R D Q Q Q Q Q Q Q Q Q /2 Q5 Q4 Q3 Q2 Q1 Q0 INDUSTRIAL TEMPERATURE RANGE 0 2xQ JULY 2000 1 c 2000 Integrated Device Technology, Inc. DSC-5823/- QS5919 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE 4 25 Q/2 FEEDBACK 5 24 GND REF_SEL 6 23 Q3 SYNC 0 7 22 V DD SO28-9 AV DD 8 21 Q2 PE 9 20 GND 10 19 LOCK SYNC 1 11 18 PLL_EN FREQ_SEL 12 17 GND GND 13 16 Q1 Q0 14 15 V DD AGND Max. –0.5 to +7 Unit V VIN DC Input Voltage VIN –0.5 to +7 V TSTG Maximum Power QSOP Dissipation (TA = 85°C) PLCC Storage Temperature Range 655 770 –65 to +150 mW mW °C REF_SEL 6 24 GN D SYN C 0 7 23 Q3 AV DD 8 22 V DD PE 9 21 Q2 AGN D 10 20 GN D SYN C 1 11 19 LOCK PLCC Max. 6 26 Q/2 CAPACITANCE (TA = 25° C, f = 1MHz, VIN = 0V) Typ. 4 27 25 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. QSOP 28 5 (1) Symbol Rating AVDD/VDD Supply Voltage to Ground Max. 4 1 J28-1 12 13 14 15 16 PLCC TOP VIEW ABSOLUTE MAXIMUM RATINGS Typ. 3 2 FEED BAC K QSOP TOP VIEW Parameter CIN 3 2xQ OE/RST 4 Unit pF 2 17 18 PLL_EN 2xQ V DD 26 GN D 3 Q4 V DD Q1 V DD GN D 27 V DD 2 Q5 Q5 Q0 Q4 V DD 28 GN D 1 FREQ _SEL GND OE/RST PIN CONFIGURATION QS5919 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE PIN DESCRIPTION Pin Name I/O Description SYNC0 I Reference clock input SYNC1 I Reference clock input REF_SEL I Reference clock select. When 1, selects SYNC 1. When 0, selects SYNC0. FREQ_SEL I VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency. FEEDBACK I Q0 -Q4 O PLL feedback input which is connected to a user selected output pin. External feedback provides flexibility for different output frequency relationships. See the Frequency Selection Table for more information. Clock outputs Q5 O Clock output. Matched in frequency, but inverted with respect to Q. 2xQ O Clock output. Matched in phase, but frequency is double the Q frequency. Q/2 O Clock output. Matched in phase, but frequency is half the Q frequency. LOCK O OE/RST I PLL_EN I PLL lock indication signal. 1 indicates positive lock. 0 indicates that the PLL is not locked and outputs may not be synchronized to the inputs. Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1, outputs are enabled. PLL enable. Enables and disables the PLL. Useful for testing purposes. PE I VDD — When PE is LOW, outputs are synchronized with the positive edge of SYNC. When HIGH, outputs are synchronized with the negative edge of SYNC. Power supply for output buffers. AVDD — Power supply for phase lock loop and other internal circuitries. GND — Ground supply for output buffers. AGND — Ground supply for phase lock loop and other internal circuitries. OUTPUT FREQUENCY SPECIFICATIONS Industrial: TA = –40°C to +85°C, AVDD/VDD = 5.0V ± 10% Symbol Description – 55 – 70 – 100 – 133 – 160 Units FMAX_2XQ Max Frequency, 2xQ 55 70 100 133 160 MHz FMAX_Q Max Frequency, Q0 - Q4, Q5 FMAX_Q/2 Max Frequency, Q/2 27.5 35 50 66.5 80 MHz 13.75 17.5 25 33.25 40 MHz FMIN_2XQ Min Frequency, 2xQ 20 20 20 20 20 MHz FMIN_Q Min Frequency, Q0 - Q4, Q5 10 10 10 10 10 MHz FMIN_Q/2 Min Frequency, Q/2 5 5 5 5 5 MHz 3 QS5919 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE FREQUENCY SELECTION TABLE FREQ_SEL SYNC (MHz) (allowable range) (1) Min. Max Output Used for Feedback HIGH Q/2 FMIN_Q/2 FMAX _Q/2 HIGH Q0 -Q4 FMIN_Q HIGH Q5 FMIN_Q HIGH 2xQ FMIN_2XQ FMAX _2XQ LOW Q/2 FMIN_Q/2 /2 LOW Q0 -Q4 FMIN_Q /2 LOW Q5 FMIN_Q /2 FMAX _Q /2 LOW 2xQ FMIN_2XQ /2 FMAX _2XQ /2 Q/2 Output Frequency Relationships (2) Q5 Q0 - Q4 2XQ SYNC – SYNC X 2 SYNC X 2 SYNC X 4 FMAX _Q SYNC / 2 – SYNC SYNC SYNC X 2 FMAX _Q – SYNC / 2 SYNC – SYNC – SYNC X 2 SYNC / 4 – SYNC / 2 SYNC / 2 SYNC FMAX _Q/2 /2 SYNC – SYNC X 2 SYNC X 2 SYNC X 4 FMAX _Q /2 SYNC / 2 – SYNC SYNC SYNC X 2 – SYNC / 2 SYNC – SYNC – SYNC X 2 SYNC / 4 – SYNC / 2 SYNC / 2 SYNC NOTES: 1. Operation in the specified SYNC frequency range guarantees that the VCO will operate in its optimal range of 20MHz to FMAX_2XQ. Operation with Sync inputs outside specified frequency ranges may result in out-of-lock outputs. FREQ_SEL only affects VCO frequency and does not affect output frequencies. 2. The lock output pin (LOCK) may not indicate reliably for VCO frequencies below 30MHz. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = –40°C to +85°C, AVDD/VDD = 5.0V ± 10% Symbol VIH Parameter Input HIGH Voltage Conditions Guaranteed Logic HIGH Level Min. 2 Typ. — Max. — Unit V VIL Input LOW Voltage Guaranteed Logic LOW Level — — 0.8 V VOH Output HIGH Voltage IOH = −36mA VDD – 0.75 — — V IOH = −100µA VOL Output LOW Voltage VDD – 0.2 — — V VDD = Min., IOL = 36mA — — 0.45 V VDD = Min., IOL = 100µA — — 0.2 V — VH Input Hysteresis — 100 — mV IOZ Output Leakage Current VOUT = VDD or GND, VDD = Max. — — 5 µA IIN Input Leakage Current VIN = AVDD or GND, AVDD = Max. — — 5 µA IPD Input Pull-Down Current (PE) AVDD = Max., VIN = AVDD — — 100 µA POWER SUPPLY CHARACTERISTICS Symbol IDDQ Parameter Quiescent Power Supply Current ∆IDD Power Supply Current per Input HIGH IDDD Dynamic Power Supply Current (1) Test Conditions VDD = Max., OE/RST = LOW, SYNC = LOW, All outputs unloaded VDD = Max., VIN = 3.4V Typ. Max. 1.5 Unit mA 0.4 1.5 mA VDD = Max., CL = 0pF 0.2 0.4 mA/MHz NOTE: 1. Relative to the frequency of Q outputs. 4 QS5919 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE INPUT TIMING REQUIREMENTS Symbol tR, tF FI tPWC DH Description (1) Maximum input rise and fall times, 0.8V to 2V Min. — Max. 3 Unit ns Input Clock Frequency, SYNC0, SYNC1 (1) 2.5 FMAX _2XQ MHz Input clock pulse, HIGH or LOW (2) 2 — ns Duty cycle, SYNC0, SYNC1 (2) 25 75 % NOTES: 1. See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with different FEEDBACK and FREQ_SEL combinations. 2. Where pulse witdh implied by DH is less than tWPC limit, tWPC limit applies SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol tSKR Parameter (1) Output Skew Between Rising Edges, Q0-Q4 and Q/2 (2) Min. — Max. 500 Unit ps tSKF Output Skew Between Falling Edges, Q0-Q4 and Q/2 (2) — 500 ps (2,5) — 750 ps tSKALL Output Skew, All Outputs tPW Pulse Width, 2xQ output, >40MHz TCY/2 − 0.4 TCY/2 + 0.4 ns tPW Pulse Width, Q0-Q4, Q5, Q/2 outputs, 80MHz TCY/2 − 0.4 TCY/2 + 0.4 ns tJ Cycle-to-Cycle Jitter (4) − 0.15 0.15 ns − 500 0 ps (6) tPD SYNC Input to Feedback Delay tLOCK SYNC to Phase Lock — 10 ms tPZH tPZL tPHZ tPLZ tR, tF Output Enable Time, OE/RST LOW to HIGH (3) 0 14 ns Output Disable Time, OE/RST HIGH to LOW (3) 0 14 ns 0.3 2.5 ns Output Rise/Fall Times, 0.2VDD ∼ 0.8VDD NOTES: 1. See Test Loads and Waveforms for test load and termination. 2. Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade). 3. Measured in open loop mode PLL_EN = 0. 4. Jitter is characterized with Q output at 20MHz. See Frequency Selection Table for information on proper FREQ_SEL level for specified input frequencies. 5. Skew measured at selected synchronization edge. 6. tPD measured at device inputs at 1.5V, Q output at 80MHz. 5 QS5919 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE AC TEST LOADS AND WAVEFORMS VDD 300 Ω 100 Ω 7.0V O UTPUT O UTPUT 300 Ω 30pF 100 Ω TEST CIRCUIT 1 TEST CIRCUIT 2 1.0ns 1.0ns tR 3.0V VDD 2.0V 0.8V D D V th = 1.5V 0.5V D D 0.8V 0.2V D D 0V 0V tF tP W TTL INPUT TEST WAVEFORM CMOS OUTPUT WAVEFORM EN A BLE DISABLE 3V 1.5V CO NTRO L 0V IN PU T t PLZ t PZ L O UTPUT 3.5V NO R M ALLY LO W SW ITCH CLO SED 1.5V D D O UTPUT O PEN VO L 0.3V VOH tP H Z tP Z H SW ITCH 0.3V 1.5V D D NO R M ALLY 0V HIGH ENABLE AND DISABLE TIMES TEST CIRCUIT 1 is used for output enable/disable parameters. TEST CIRCUIT 2 is used for all other timing parameters. 6 QS5919 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE AC TIMING DIAGRAM SYNC tP D FEEDBACK tJ Q t SK F Q 0 -Q 4 t S KR Q /2 2xQ t SKA LL Q5 NOTES: 1. AC Timing Diagram applies to Q output connected to FEEDBACK and PE = GND. For PE = VDD, the negative edge of FEEDBACK aligns with the negative edge of SYNC input, and the negative edges of the multiplied and divided outputs align with the negative edge of SYNC. 2. All parameters except tPD are measured at 0.5VDD; tPD is measured at 1.5V. 7 QS5919 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE PLL OPERATION PLL circuit is to provide an effective zero propagation delay between the output and input signals. In fact, adding delay circuits in the feedback path, ‘propagation delay’ can even be negative! A simplified schematic of the QS5919 PLL circuit is shown below. The Phase Locked Loop (PLL) circuit included in the QS5919 provides for replication of incoming SYNC clock signals. Any manipulation of that signal, such as frequency multiplying or inversion is performed by digital logic following the PLL (see the block diagram). The key advantage of the SIMPLIFIED DIAGRAM OF QS5919 FEEDBACK Q 2xQ INPU T VCO /2 Q /2 Q /2 PHASE DETECTOR The phase difference between the output and the input frequencies feeds the VCO which drives the outputs. Whichever output is fed back, it will stabilize at the same frequency as the input. Hence, this is a true negative feedback closed loop system. In most applications, the output will optimally have zero phase shift with respect to the input. In fact, the internal loop filter on the QS5919 typically provides within 150ps of phase shift between input and output. If the user wishes to vary the phase difference (typically to compensate for backplane delays), this is most easily accomplished by adding delay circuits to the feedback path. The respective output used for feedback will be advanced by the amount of delay in the feedback path. All other outputs will retain their proper relationships to that output. 8 QS5919 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION QS XXXX X Device Type Package Q J Quarter Size Outline Package (SO28-9) Plastic Leaded Chip Carrier (J28-1) 5919 Low Skew CMOS PLL Clock Driver with Integrated Loop Filter CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. 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