QS5935 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER QS5935 FEATURES: DESCRIPTION • • • • • • • • • The QS5935 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to a reference clock input. Five outputs are available: Q0–Q4. Careful layout and design ensure <500ps skew between the Q0–Q 4. The QS5935 includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external components. The PLL can also be disabled by the PLL_EN signal to allow low frequency or DC testing. The QS5935 is designed for use in cost sensitive high-performance computing systems, workstations, multi-board computers, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. In the QSOP package, the QS5935 clock driver represents the best value in small form factor, high-performance clock management products. 5V operation Five low noise CMOS level outputs <500ps output skew, Q0–Q4 Outputs 3-state and reset while OE/RST low PLL disable feature for low frequency testing Internal loop filter RC network Balanced drive outputs ±36mA 80MHz maximum frequency Available in QSOP package FUNCTIONAL BLOCK DIAGRAM PLL_EN /2 0 1 CLK_IN Q0 Q1 PLL Q2 FEEDBAC K Q3 Q4 OE/RST INDUSTRIAL TEMPERATURE RANGE JULY 2000 1 c 2000 Integrated Device Technology, Inc. DSC-5816/- QS5935 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION Symbol Rating AVDD, VDD Supply Voltage to Ground GND 1 20 Q4 OE/RST 2 19 N/C FEEDBACK 3 18 G ND AV DD 4 17 Q3 VDD 5 16 VDD AG ND 6 15 Q2 CLK_IN 7 14 G ND VDD 8 13 PLL_EN GND 9 12 G ND 10 11 Q1 Q0 SO 20-8 DC Input Voltage VIN Max. –0.5 to +7 V 0.5 –65 to +150 W °C NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (TA = 25° C, f = 1MHz, VIN = 0V) (1) Pins CIN COUT Typ. 3 Max. 4 Unit pF 4 5 pF NOTE: 1. Capacitance is characterized but not tested. QSOP TOP VIEW PIN DESCRIPTION Pin Name Unit V –0.5 to VDD+0.5 Maximum Power Dissipation (TA = 85°C) Storage Temperature Range TSTG (1) I/O Description CLK_IN I Reference clock input FEEDBACK I External feedback provides flexibility for different output frequency relationships Q0 -Q4 O Clock outputs OE/RST I PLL_EN I VDD — Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1, outputs are enabled. When 1, PLL is enabled. When 0, PLL is disabled and the output for Q 0 -Q4 will be CLK_IN/2 in frequency. This allows the CLK_IN input to be single-stepped for system debug. Power supply for output buffers AVDD — Power supply for phase lock loop and other internal circuitries GND — Ground supply for output buffers AGND — Ground supply for phase lock loop and other internal circuitries 2 QS5935 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = –40°C to +85°C, AVDD/VDD = 5.0V ± 10% Symbol VIH Parameter Input HIGH Voltage Conditions Guaranteed Logic HIGH Level Min. 2 Typ. — Max. — Unit V VIL Input LOW Voltage Guaranteed Logic LOW Level — — 0.8 V VOH Output HIGH Voltage IOH = −36mA VDD – 0.75 — — V IOH = −100µA VDD – 0.2 — — V VDD = Min., IOL = 36mA — — 0.45 V VDD = Min., IOL = 100µA — — 0.2 V — 100 — mV — — ±5 µA — — ±5 µA VOL Output LOW Voltage VH Input Hysteresis IOZ Output Leakage Current IIN Input Leakage Current — VOUT = VDD or GND, VDD = Max., Outputs Disabled VIN = AVDD or GND, AVDD = Max. POWER SUPPLY CHARACTERISTICS Symbol IDDQ Parameter Quiescent Power Supply Current ∆IDD Power Supply Current per Input HIGH Test Conditions VDD = Max., OE/RST = LOW, CLK_IN = LOW, All outputs unloaded VDD = Max., VIN = 3.4V IDDD Dynamic Power Supply Current (1) VDD = Max., CL = 0pF Typ. — Max. 1 Unit mA 0.7 1.5 mA — 0.4 mA/MHz NOTE: 1. This value is guaranteed but not tested. SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol tSKR Parameter (1) Output Skew Between Rising Edges, Q0-Q4 (2,3) Min. — Typ. — Max. 500 Unit ps tSKF Output Skew Between Falling Edges, Q0-Q4 (2,3) — — 500 ps tPW Pulse Width, Q0-Q4 TCYC/2 − 0.4 — TCYC/2 + 0.4 ns tJ Cycle-to-Cycle Jitter (2,5) − 0.15 — +0.15 ns − 500 — +500 ps (2,6) tPD CLK_IN to Feedback Delay tLOCK CLK_IN to Phase Lock — — 10 ms tPZH tPZL tPHZ tPLZ tR, tF Output Enable Time, OE/RST LOW to HIGH (4) 0 — 14 ns Output Disable Time, OE/RST HIGH to LOW (2,4) 0 — 14 ns Output Rise/Fall Times, 0.2VDD ∼ 0.8VDD (2) — — 2.5 ns tR, tF Maximum Rise/Fall Times, 0.8V to 2V — — 3 ns FI Input Clock Frequency 10 — 80 MHz 2 — — ns 25 — 75 % tPWC Input Clock Pulse, HIGH or LOW DH Duty Cycle, CLK_IN (7) (7) NOTES: 1. See Test Loads and Waveforms for test load and termination. 2. This parameter is guaranteed by characterization but not tested. 3. Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade). 4. Measured in open loop mode PLL_EN = 0. 5. Jitter is characterized using an oscilloscope, Q output at 20MHz. Measurement is taken one cycle after jitter. 6. tPD measured at device inputs at 1.5V, Q output at 80MHz. 7. Input timing requirements are guaranteed by design but not tested. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies. 3 QS5935 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE AC TEST LOADS AND WAVEFORMS VDD 300 Ω 100 Ω 7.0V OU TP UT OU TP UT 300 Ω 30p F 100 Ω TEST CIRCUIT 1 TEST CIRCUIT 2 1.0ns 1.0ns tR 3.0V VDD 2.0V 0.8V D D V th = 1 .5V 0.5V DD 0.8V 0.2V D D 0V 0V tF tP W TTL INPUT TEST WAVEFORM CMOS OUTPUT WAVEFORM EN A BL E DISA B LE 3V 1.5V CO NTRO L 0V INPU T tPL Z t PZ L OU TP UT 3.5V NO R M AL LY LOW SW ITCH 0.5V DD CLO SED 0.3V VO L 0.3V VOH tPH Z tPZ H SW ITCH OU TP UT OP EN 0.5V D D NO R M AL LY 0V HIGH ENABLE AND DISABLE TIMES TEST CIRCUIT 1 is used for output enable/disable parameters. TEST CIRCUIT 2 is used for all other timing parameters. 4 QS5935 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE AC TIMING DIAGRAM CLK_IN tP D FE ED BA CK tJ Q tS K F Q 0 -Q 4 NOTES: 1. AC Timing Diagram applies to Q output connected to FEEDBACK . 2. All parameters are measured at 0.5VDD except for tPD, which is measured at 1.5V 5 QS5935 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION QS XXXX Device Type X Package X Process Blank Industrial (-40°C to +85°C) Q Quarter Size Outline Package (SO20-8) 5935 Low Skew CMOS PLL C lock Driver with Integrated Loop Filter CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. Turboclock is a registered trademark of Integrated Device Technology, Inc. 6