QS5930T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER QS5930T FEATURES: DESCRIPTION • • • • • • • • • • • • • The QS5930T Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to a reference clock input. Six outputs are available: Q0–Q4, Q/2. Careful layout and design ensure < 250ps skew between the Q0–Q4, and Q/2 outputs. The QS5930T includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external components. Various combinations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The PLL can also be disabled by the PLL_EN signal to allow low frequency or DC testing. The QS5930T is designed for use in cost sensitive high-performance computing systems, workstations, multi-board computers, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. In the QSOP package, the QS5930T clock driver represents the best value in small form factor, high-performance clock management products. 5V operation Q/2 output, 5 Q outputs Useful for Pentium, PowerPC, and PCI systems Internal loop filter RC network Low noise TTL level outputs <250ps rising edge output skew Balanced drive outputs ±24mA PLL bypass feature for low frequency testing Internal VCO/2 option for wider frequency range Outputs tri-state and reset while OE/RST is low ESD > 2000V Latch up > -300mA Available in QSOP package For more information on PLL clock driver products, see Application Note AN-227. FUNCTIONAL BLOCK DIAGRAM FEEDBACK SYNC O E/RST R D PH ASE LOO P DETECTO R FILTER R D D FREQ _SEL 0 1 1 VCO R PLL_EN R D 0 /2 R D R D Q Q Q Q Q Q Q Q /2 Q4 Q3 Q2 Q1 Q0 INDUSTRIAL TEMPERATURE RANGE SEPTEMBER 2000 1 c 2000 Integrated Device Technology, Inc. DSC-5849 QS5930T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER PIN CONFIGURATION INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS Symbol Rating AVDD,VDD Supply Voltage to Ground GND 1 20 Q4 OE/RST 2 19 Q/2 FEEDBACK 3 18 GND AVDD VDD 4 17 Q3 5 16 AGND 6 15 VDD Q2 SYNC 7 14 GND FREQ_SEL 8 13 PLL_EN GND 9 12 GND 10 11 Q1 Q0 Max. –0.5 to +7 Unit V –0.5 to +7 V AC Input Voltage (for pulse width ≤ 20ns) –3 V Maximum Power Dissipation (TA = 85°C) Storage Temperature Range 1 –65 to +150 W °C DC Input Voltage VIN TSTG (1) NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (TA = 25° C, f = 1MHz, VIN = 0V) Pins CIN COUT Typ. 3 Max. 4 Unit pF 7 9 pF QSOP TOP VIEW PIN DESCRIPTION Pin Name I/O Description SYNC I Reference clock input FREQ_SEL I FEEDBACK I Q0 -Q4 O VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency. HIGH is for higher frequencies, LOW is for lower frequencies. PLL feedback input which is connected to either a Q or a Q/2 output. External feedback provides flexibility for different output frequency relationships. See the Frequency Selection Table for more information. Clock outputs Q/2 O Clock output. Matched in phase, but frequency is half the Q frequency. OE/RST I PLL_EN I Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1, outputs are enabled. PLL enable. Enables and disables the PLL. Allows the SYNC input to be single-stepped for system debug. VDD — Power supply for output buffers. AVDD — Power supply for phase lock loop and other internal circuitries. GND — Ground supply for output buffers. AGND — Ground supply for phase lock loop and other internal circuitries. OUTPUT FREQUENCY SPECIFICATIONS Industrial: TA = –40°C to +85°C, AVDD/VDD = 5V ± 10% Symbol Description – 50 – 66 Units FMAX_Q Max Frequency, Q0 - Q4, 50 66 MHz FMAX_Q/2 Max Frequency, Q/2 25 33 MHz FMIN_Q Min Frequency, Q0 - Q4 28 28 MHz FMIN_Q/2 Min Frequency, Q/2 14 14 MHz 2 QS5930T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE FREQUENCY SELECTION TABLE FREQ_SEL SYNC (MHz) (allowable range) (1) Output Used for Feedback Min. Max Output Frequency Relationships Q/2 Q 0 - Q4 HIGH Q/2 14 FMAX _Q/2 SYNC SYNC X 2 HIGH Q0 -Q4 28 FMAX _Q SYNC / 2 SYNC LOW Q/2 7 FMAX _Q/2 /2 SYNC SYNC X 2 LOW Q0 -Q4 14 FMAX _Q /2 SYNC / 2 SYNC NOTE: 1. Operation in the specified SYNC frequency range guarantees that the VCO will operate in its optimal range of 28MHz to FMAX_Q x2. Operation with Sync inputs outside specified frequency ranges may result in out-of-lock outputs. FREQ_SEL only affects VCO frequency and does not affect output frequencies. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = –40°C to +85°C, AVDD/VDD = 5V ± 5% Symbol VIH Parameter Input HIGH Voltage Conditions Guaranteed Logic HIGH Level VIL Input LOW Voltage Guaranteed Logic LOW Level VOH Output HIGH Voltage IOH = −24mA IOH = −100µA 3 VOL Output LOW Voltage IOZ Output Leakage Current IIN Input Leakage Current Min. 2 Typ. — Max. — Unit V — — 0.8 V 2.4 — — V — — V VDD = Min., IOL = 24mA — — 0.55 V VDD = Min., IOL = 100µA — — 0.2 V VOUT = VDD or GND, VDD = Max., Outputs Disabled AVDD = Max., VIN = AVDD or GND — — 5 µA — — 5 µA POWER SUPPLY CHARACTERISTICS Symbol IDDQ Parameter Quiescent Power Supply Current Typ. — Power Supply Current per Input HIGH Test Conditions VDD = Max., OE/RST = LOW, SYNC = LOW, All outputs unloaded VDD = Max., VIN = 3V ∆IDD IDDD Max. 1 Unit mA 1 30 µA Dynamic Power Supply Current VDD = Max., CL = 0pF 0.2 0.3 mA/MHz Min. — Max. 3 Unit ns INPUT TIMING REQUIREMENTS Symbol tR, tF FI tPWC DH Description (1) Maximum input rise and fall times, 0.8V to 2V Input Clock Frequency, SYNC (1) 7 FMAX _Q MHz Input clock pulse, HIGH or LOW (2) 2 — ns Duty Cycle, SYNC (2) 25 75 % NOTES: 1. See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with different FEEDBACK and FREQ_SEL combinations. 2. Where pulse witdh implied by DH is less than tWPC limit, tWPC limit applies 3 QS5930T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol tSKR Parameter (1) Output Skew Between Rising Edges, Q0-Q4 (and Q/2) (2) Min. — Max. 250 Unit ps tSKF Output Skew Between Falling Edges, Q0-Q4 (and Q/2) (2) — 350 ps tPW Pulse Width, Q0-Q4, Q/2 outputs, 80MHz TCY/2 − 0.5 TCY/2 + 0.5 ns tJ Cycle-to-Cycle Jitter, FI > 33MHz tPD SYNC Input to Feedback Delay ( 5) tPZH tPZL tPHZ tPLZ tR, tF — 250 ns − 100 +400 ps Output Enable Time, OE/RST LOW to HIGH ( 3) 0 7 ns Output Disable Time, OE/RST HIGH to LOW ( 3) 0 6 ns 0.4 1.5 ns ( 4) Output Rise/Fall Times, 0.8V to 2V NOTES: 1. See Test Loads and Waveforms for test load and termination. 2. Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade). 3. Measured in open loop mode PLL_EN = 0. 4. Jitter is characterized with Q output at 20MHz. See Frequency Selection Table for information on proper FREQ_SEL level for specified input frequencies. 5. tPD measured at device inputs at 1.5V, Q output at 28MHz. 4 QS5930T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE AC TEST LOADS AND WAVEFORMS VDD 300 Ω 160 Ω 7.0V OUTPUT OUTPUT 300 Ω 30pF 68 Ω TEST CIRCUIT 1 28pF TEST CIRCUIT 2 PLL OPERATION The Phase Locked Loop (PLL) circuit included in the QS5930T provides for replication of incoming SYNC clock signals. Any manipulation of that signal, such as frequency multiplying, is performed by digital logic following the PLL (see the block diagram). The key advan- tage of the PLL circuit is to provide an effective zero propagation delay between the output and input signals. In fact, adding delay circuits in the feedback path, ‘propagation delay’ can even be negative! A simplified schematic of the QS5930T PLL circuit is shown below: SIMPLIFIED DIAGRAM OF QS5930T FEEDBACK Q INPU T Q /2 /2 VCO/2 PHASE DETECTO R The phase difference between the output and the input frequencies feeds the VCO which drives the outputs. Whichever output is fed back, it will stabilize at the same frequency as the input. Hence, this is a true negative feedback closed loop system. In most applications, the output will optimally have zero phase shift with respect to the input. In fact, the internal loop filter on the QS5930T typically provides within 150ps of phase shift between input and output. If the user wishes to vary the phase difference (typically to compensate for backplane delays), this is most easily accomplished by adding delay circuits to the feedback path. The respective output used for feedback will be advanced by the amount of delay in the feedback path. All other outputs will retain their proper relationships to that output. 5 QS5930T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION QS XXXX Device Type XX Speed X Package X Process Blank CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 Industrial (-40°C to +85°C) Q Quarter Size Outline Package -50T -66T 50MHz. max. frequency 66MHz. max. frequency 5930 Low Skew CMOS PLL Clock Driver with Integrated Loop Filter for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 6 for Tech Support: [email protected] (408) 654-6459