QS5LV931 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER FEATURES: • • • • • • • • • • • • • QS5LV931 DESCRIPTION: 3.3V operation JEDEC LVTTL compatible level Clock input is 5V tolerant Q outputs, Q/2 output <300ps output skew, Q0–Q4 Outputs 3-state and reset while OE/RST low PLL disable feature for low frequency testing Internal loop filter RC network Internal VCO/2 option Balanced drive outputs ±24mA ESD >2000V 80MHz maximum frequency Available in QSOP package The QS5LV931 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to a reference clock input. Six outputs are available: Q0–Q 4, Q/2. Careful layout and design ensure <300ps skew between the Q0–Q4, and Q/2 outputs. The QS5LV931 includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external components. Various combinations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The PLL can also be disabled by the PLL_EN signal to allow low frequency or DC testing. The QS5LV931 is designed for use in cost sensitive high-performance computing systems, workstations, multi-board computers, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. In the QSOP package, the QS5LV931 clock driver represents the best value in small form factor, high-performance clock management products. For more information on PLL clock driver products, see Application Note AN-227. FUNCTIONAL BLOCK DIAGRAM FEEDBACK SYNC O E/RST R D PH ASE LOO P DETE CTO R FILTER R D D FREQ_SEL 0 1 1 VCO R PLL_EN R D 0 /2 R D R D Q Q Q Q Q Q Q Q/2 Q4 Q3 Q2 Q1 Q0 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JANUARY 2002 1 c 2002 Integrated Device Technology, Inc. DSC-5821/2 QS5LV931 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER PIN CONFIGURATION INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) Symbol Description AVDD/VDD Supply Voltage to Ground GND 1 20 Q4 OE/RST 2 19 Q/2 FEEDBACK 3 18 GND AVDD VDD 4 17 Q3 5 16 AGND 6 15 VDD Q2 SYNC 7 14 GND FREQ_SEL 8 13 PLL_EN GND 9 12 GND 10 11 Q1 Q1 DC Input Voltage VIN Maximum Power Dissipation (TA = 85°C) TSTG Storage Temperature Range Max Unit –0.5 to +7 V –0.5 to +5.5 V 0.5 W –65 to +150 °C NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. CAPACITANCE (TA = +25°C, f = 1MHz, VIN = 0V) QSOP TOP VIEW Pins Typ. Max. Unit CIN 3 4 pF COUT 4 5 pF PIN DESCRIPTION Pin Name I/O SYNC I FREQ_SEL I Description Reference clock input VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency. HIGH is for higher frequencies, LOW is for lower frequencies. FEEDBACK I PLL feedback input which is connected to either a Q or a Q/2 output. External feedback provides flexibility for different output frequency relationships. See the Frequency Selection Table for more information. Q0 -Q4 O Clock outputs Q/2 O Clock output. Matched in phase, but frequency is half the Q frequency. OE/RST I Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1, outputs are PLL_EN I PLL enable. Enables and disables the PLL. Allows the SYNC input to be single-stepped for system debug. VDD — Power supply for output buffers AVDD — Power supply for phase lock loop and other internal circuitries GND — Ground supply for output buffers AGND — Ground supply for phase lock loop and other internal circuitries enabled. OUTPUT FREQUENCY SPECIFICATIONS Industrial: TA = –40°C to +85°C, AVDD/VDD = 3.3V ± 0.3V Symbol Description – 50 – 66 – 80 Units FMAX_Q Max Frequency, Q0 - Q4, 50 66 80 MHz FMAX_Q/2 Max Frequency, Q/2 25 33 40 MHz FMIN_Q Min Frequency, Q0 - Q4 10 10 10 MHz FMIN_Q/2 Min Frequency, Q/2 5 5 5 MHz 2 QS5LV931 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE FREQUENCY SELECTION TABLE SYNC (MHz) (allowable range) (1) Output Used for FREQ_SEL Output Frequency Relationships Feedback Min. Max Q/2 Q 0 - Q4 HIGH Q/2 FMIN_Q/2 HIGH Q0 -Q4 FMIN_Q FMAX _Q/2 SYNC SYNC X 2 FMAX _Q SYNC / 2 SYNC LOW Q/2 FMIN_Q/2 /2 LOW Q0 -Q4 FMIN_Q /2 FMAX _Q/2 /2 SYNC SYNC X 2 FMAX _Q /2 SYNC / 2 SYNC NOTE: 1. Operation in the specified SYNC frequency range guarantees that the VCO will operate in its optimal range of 20MHz to FMAX_Q x2. Operation with Sync inputs outside specified frequency ranges may result in out-of-lock outputs. FREQ_SEL only affects VCO frequency and does not affect output frequencies. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = –40°C to +85°C, AVDD/VDD = 3.3V ± 0.3V Symbol Parameter Conditions Min. Typ. Max. Unit VIH Input HIGH Voltage Guaranteed Logic HIGH Level 2 — — V VIL Input LOW Voltage Guaranteed Logic LOW Level — — 0.8 V VOH Output HIGH Voltage IOH = −24mA VDD — 0.6 — — V VDD — 0.2 — — — — 0.45 IOH = −100µA VOL Output LOW Voltage VH Input Hysteresis IOZ Output Leakage Current VDD = Min., IOL = 24mA VDD = Min., IOL = 100µA V — — 0.2 — — 100 — mV VOUT = VDD or GND, — — 5 µA — — 5 µA Typ. Max. Unit — 1 mA VDD = Max., Outputs Disabled IIN Input Leakage Current AVDD = Max., VIN = AVDD or GND POWER SUPPLY CHARACTERISTICS Symbol Parameter IDDQ Quiescent Power Supply Current VDD = Max., OE/RST = LOW, Test Conditions ∆IDD Power Supply Current per Input HIGH VDD = Max., VIN = 3V 1 30 µA IDDD Dynamic Power Supply Current per Output VDD = Max., CL = 0pF 0.2 0.3 µA/MHz SYNC = LOW, All outputs unloaded INPUT TIMING REQUIREMENTS Description (1) Symbol tR, tF FI tPWC DH Maximum input rise and fall times, 0.8V to 2V Input Clock Frequency, SYNC (1) Input clock pulse, HIGH or LOW (2) Duty Cycle, SYNC (2) Min. Max. Unit — 3 ns 2.5 FMAX _Q MHz 2 — ns 25 75 % NOTES: 1. See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with different FEEDBACK and FREQ_SEL combinations. 2. Where pulse witdh implied by DH is less than tWPC limit, tWPC limit applies 3 QS5LV931 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol Parameter (1) tSKR Output Skew Between Rising Edges, Q0-Q4 and Q/2 (2) tSKF Output Skew Between Falling Edges, Q0-Q4 and Q/2 (2) tPW Pulse Width, Q0-Q4, Q/2 outputs, 80MHz Min. Max. Unit — 300 ps — 300 ps TCY/2 − 0.4 TCY/2 + 0.4 ns tJ Cycle-to-Cycle Jitter (4) — 0.15 0.15 ns tPD SYNC Input to Feedback Delay (5) − 500 500 ps — 10 ms 0 14 ns 0 14 ns 0.3 2 ns tLOCK SYNC to Phase Lock tPZH Output Enable Time, OE/RST LOW to HIGH (3) tPZL tPHZ Output Disable Time, OE/RST HIGH to LOW (3) tPLZ tR, tF Output Rise/Fall Times, 0.8V ~ 2V NOTES: 1. See Test Loads and Waveforms for test load and termination. 2. Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade). 3. Measured in open loop mode PLL_EN = 0. 4. Jitter is characterized with Q output at 20MHz. See Frequency Selection Table for information on proper FREQ_SEL level for specified input frequencies. 5. tPD measured at device inputs at 0.5VDD, Q output at 80MHz. 4 QS5LV931 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE AC TEST LOADS AND WAVEFORMS VDD 300 Ω 100 Ω 6.0V OUTPUT OUTPUT 300 Ω 30pF 100 Ω Test Circuit 1 Test Circuit 2 1.0ns 1.0ns tR 3.0V tF 3.0V 2.0V 2.0V V th = 0.5V D D tP W 0.5V D D 0.8V 0.8V 0V 0V CMOS Input Test Waveform CMOS Output Waveform EN ABLE DISABLE 3V 0.5V D D CONTROL 0V INPU T tPLZ tPZ L OUTPUT 3.0V NOR MALLY LOW SWITCH 0.5V DD CLO SED 0.3V V OL 0.3V VO H tPHZ tPZH SWITCH OUTPUT OPEN 0.5V DD NOR MALLY 0V HIGH Enable and Disable Times TEST CIRCUIT 1 is used for output enable/disable parameters. TEST CIRCUIT 2 is used for all other timing parameters. 5 QS5LV931 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE AC TIMING DIAGRAM SYNC tP D FEEDBACK tJ Q tSK F Q 0 -Q 4 tSK ALL tS KR Q/2 NOTES: 1. AC Timing Diagram applies to Q output connected to FEEDBACK . 2. All parameters are measured at 0.5VDD. 6 QS5LV931 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE PLL OPERATION The Phase Locked Loop (PLL) circuit included in the QS5LV931 provides for replication of incoming SYNC clock signals. Any manipulation of that signal, such as frequency multiplying, is performed by digital logic following the PLL (see the block diagram). The key advantage of the PLL circuit is to provide an effective zero propagation delay between the output and input signals. In fact, adding delay circuits in the feedback path, ‘propagation delay’ can even be negative! A simplified schematic of the QS5LV931 PLL circuit is shown below. SIMPLIFIED DIAGRAM OF QS5LV931 FEEDBACK Q INPUT Q /2 /2 VCO /2 PHASE DETECTO R The phase difference between the output and the input frequencies feeds the VCO which drives the outputs. Whichever output is fed back, it will stabilize at the same frequency as the input. Hence, this is a true negative feedback closed loop system. In most applications, the output will optimally have zero phase shift with respect to the input. In fact, the internal loop filter on the QS5LV931 typically provides within 150ps of phase shift between input and output. If the user wishes to vary the phase difference (typically to compensate for backplane delays), this is most easily accomplished by adding delay circuits to the feedback path. The respective output used for feedback will be advanced by the amount of delay in the feedback path. All other outputs will retain their proper relationships to that output. 7 QS5LV931 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION QS XXXX Device Type XX Speed X Package X Process Blank Industrial (-40°C to +85°C) Q Quarter Size Outline Package 50 66 80 50MHz Max. Frequency 66MHz Max. Frequency 80MHz Max. Frequency 5LV931 3.3V Low Skew CMOS PLL Clock Driver with Integrated Loop Filter CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 8 for Tech Support: [email protected] (408) 654-6459