QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER FEATURES: • • • • • • • • • • • • • QS5LV919 DESCRIPTION: 3.3V operation JEDEC compatible LVTTL level outputs Clock inputs are 5V tolerant < 300ps output skew, Q0–Q4 2xQ output, Q outputs, Q output, Q/2 output Outputs 3-state and reset while OE/RST low PLL disable feature for low frequency testing Internal loop filter RC network Functional equivalent to MC88LV915, IDT74FCT388915 Positive or negative edge synchronization (PE) Balanced drive outputs ±24mA 160MHz maximum frequency (2xQ output) Available in QSOP and PLCC packages The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q 0-Q 4, Q5, Q/2. Careful layout and design ensure < 300 ps skew between the Q 0-Q 4, and Q/2 outputs. The QS5LV919 includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external components. Various combinations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The PLL can also be disabled by the PLL_EN signal to allow low frequency or DC testing. The LOCK output asserts to indicate when phase lock has been achieved. The QS5LV919 is designed for use in high-performance workstations, multiboard computers, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. For more information on PLL clock driver products, see Application Note AN-227. FUNCTIONAL BLOCK DIAGRAM REF_SEL LO CK SYNC 0 0 SYNC 1 1 PH A SE DETECTO R O E/RST R D FEEDBACK PE R D R D LOO P FILTER R D D FREQ _SEL 0 1 1 VCO R PLL_EN R /2 D R D Q Q Q Q Q Q Q Q Q /2 Q5 Q4 Q3 Q2 Q1 Q0 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE 0 2xQ JULY 2001 1 c 2001 Integrated Device Technology, Inc. DSC-5820/3 QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE 4 25 Q/2 FEEDBACK 5 24 GND REF_SEL 6 23 Q3 SYNC0 7 22 VDD AVDD 8 21 Q2 PE 9 20 GND AGND 10 19 LOCK SYNC1 11 18 PLL_EN FREQ_SEL 12 17 GND GND 13 16 Q1 Q0 14 15 VDD Rating Max. DC Input Voltage VIN QSOP Dissipation (TA = 85°C) PLCC 27 26 Q/2 REF_SEL 6 24 GND SYNC0 7 23 Q3 AVDD 8 22 VDD PE 9 21 Q2 AGND 10 20 GND SYNC1 11 19 LOCK Storage Temperature Range Unit –0.5 to +7 V –0.5 to +5.5 V 655 mW 770 mW –65 to +150 °C CAPACITANCE (TA = 25°C, f = 1MHz, VIN = 0V) QSOP CIN 28 25 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter 1 12 13 14 15 16 PLCC TOP VIEW VDD, AVDD Supply Voltage to Ground TSTG 2 5 ABSOLUTE MAXIMUM RATINGS (1) Maximum Power 3 FEEDBACK QSOP TOP VIEW Symbol 2xQ OE/RST 4 PLCC Typ. Max. Typ. Max. Unit 3 4 4 6 pF 2 17 18 PLL_EN 2xQ VDD 26 GND 3 Q4 VDD Q1 VDD GND 27 VDD 2 Q5 Q5 Q0 Q4 VDD 28 GND 1 FREQ_SEL GND OE/RST PIN CONFIGURATION QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE PIN DESCRIPTION Pin Name I/O SYNC 0 I Description Reference clock input SYNC 1 REF_SEL I I Reference clock input Reference clock select. When 1, selects SYNC1. When 0, selects SYNC0. FREQ_SEL FEEDBACK I I VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency. PLL feedback input which is connected to a user selected output pin. External feedback provides flexibility for different Q0 -Q4 O output frequency relationships. See the Frequency Selection Table for more information. Clock outputs Q5 2xQ O O Clock output. Matched in frequency, but inverted with respect to Q. Clock output. Matched in phase, but frequency is double the Q frequency. Q/2 LOCK O O Clock output. Matched in phase, but frequency is half the Q frequency. PLL lock indication signal. 1 indicates positive lock. 0 indicates that the PLL is not locked and outputs may not be OE/RST I synchronized to the inputs. Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When PLL_EN I 1, outputs are enabled. PLL enable. Enables and disables the PLL. Useful for testing purposes. PE I When PE is LOW, outputs are synchronized with the positive edge of SYNC. When HIGH, outputs are synchronized with the negative edge of SYNC. VDD AVDD — — Power supply for output buffers. Power supply for phase lock loop and other internal circuitries. GND — Ground supply for output buffers. AGND — Ground supply for phase lock loop and other internal circuitries. OUTPUT FREQUENCY SPECIFICATIONS Industrial: TA = –40°C to +85°C, AVDD / VDD = 3.3V ± 0.3V Symbol Description FMAX_2XQ Max Frequency, 2xQ – 55 – 70 – 100 – 133 – 160 Units 55 70 100 133 160 MHz 50 66.5 80 MHz FMAX_Q Max Frequency, Q0 - Q4, Q5 27.5 35 FMAX_Q/2 Max Frequency, Q/2 13.75 17.5 25 33.25 40 MHz FMIN_2XQ Min Frequency, 2xQ 20 20 20 20 20 MHz FMIN_Q Min Frequency, Q0 - Q4, Q5 10 10 10 10 10 MHz FMIN_Q/2 Min Frequency, Q/2 5 5 5 5 5 MHz 3 QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE FREQUENCY SELECTION TABLE SYNC (MHz) (allowable range)(1) Output Used for Output Frequency Relationships(2) FREQ_SEL Feedback Min. Max Q/2 Q5 Q 0 - Q4 2XQ HIGH Q/2 FMIN_Q/2 FMAX _Q/2 SYNC – SYNC X 2 SYNC X 2 SYNC X 4 HIGH Q0 -Q4 FMIN_Q FMAX _Q SYNC / 2 – SYNC SYNC SYNC X 2 HIGH Q5 FMIN_Q FMAX _Q – SYNC / 2 SYNC – SYNC – SYNC X 2 HIGH 2xQ(3) FMIN_2XQ 100 SYNC / 4 – SYNC / 2 SYNC / 2 SYNC LOW Q/2 FMIN_Q/2 /2 FMAX _Q/2 /2 SYNC – SYNC X 2 SYNC X 2 SYNC X 4 LOW Q0 -Q4 FMIN_Q /2 FMAX _Q /2 SYNC / 2 – SYNC SYNC SYNC X 2 LOW Q5 FMIN_Q /2 FMAX _Q /2 – SYNC / 2 SYNC – SYNC – SYNC X 2 LOW 2xQ FMIN_2XQ /2 FMAX _2XQ /2 SYNC / 4 – SYNC / 2 SYNC / 2 SYNC NOTES: 1. Operation in the specified SYNC frequency range guarantees that the VCO will operate in its optimal range of 20MHz to FMAX_2XQ. Operation with Sync inputs outside specified frequency ranges may result in out-of-lock outputs. FREQ_SEL only affects VCO frequency and does not affect output frequencies. 2. The lock output pin (LOCK) may not indicate reliably for VCO frequencies below 30MHz. 3. The 2xQ is limited to a maximum frequency (FMAX_2XQ) of 100MHz only when used as a feedback. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified Industrial: TA = -40°C to +85°C, AVDD/VDD= 3.3V ± 0.3V Symbol Parameter Conditions VIH Input HIGH Voltage Guaranteed Logic HIGH Level VIL Input LOW Voltage Guaranteed Logic LOW Level VOH Output HIGH Voltage IOH = −24mA Output LOW Voltage Typ. Max. Unit 2 — — V — — 0.8 V VDD – 0.6 — — V VDD – 0.2 — — VDD = Min., IOL = 24mA — — 0.45 VDD = Min., IOL = 100µA — — 0.2 IOH = −100µA VOL Min. V VH Input Hysteresis — — 100 — mV I OZ Output Leakage Current VOUT = VDD or GND, VDD = Max. — — ±5 µA IIN Input Leakage Current AVDD = Max., VIN = AVDD or GND — — ±5 µA IPD Input Pull-Down Current (PE) AVDD = Max., VIN = AVDD — — ± 100 µA POWER SUPPLY CHARACTERISTICS Symbol IDDQ Parameter Quiescent Power Supply Current Test Conditions Typ. VDD = Max., OE/RST = LOW, Max. Unit 1 mA SYNC = LOW, All outputs unloaded ∆IDD Power Supply Current per Input HIGH VDD = Max., VIN = 3V 1 30 µA IDDD Dynamic Power Supply Current (1) VDD = Max., CL = 0pF 0.2 0.4 mA/MHz NOTE: 1. Relative to the frequency of Q outputs. 4 QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE INPUT TIMING REQUIREMENTS Symbol tR, tF FI Description(1) Min. Max. Unit Maximum input rise and fall times, 0.8V to 2V — 3 ns Input Clock Frequency, SYNC0, SYNC1 2.5 100 MHz 2 — ns 25 75 % (1) tPWC Input clock pulse, HIGH or LOW(2) DH Input duty cycle, SYNC0, SYNC1 (2) NOTES: 1. See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with different FEEDBACK and FREQ_SEL combinations. 2. Where pulse witdh implied by DH is less than tWPC limit, tWPC limit applies SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol Min. Max. Unit tSKR Output Skew Between Rising Edges, Q0-Q4 (and Q/2 if PE = LOW)(2) — 300 ps tSKF Output Skew Between Falling Edges, Q0-Q4 (and Q/2 if PE = HIGH) — 300 ps — 500 ps TCY/2 − 0.4 TCY/2 + 0.4 ns tSKALL Parameter(1) Output Skew, All Outputs(2, 5) tPW Pulse Width, 2xQ output, >40MHz tPW Pulse Width, Q0-Q4, Q5, Q/2 outputs, 80MHz tJ Cycle-to-Cycle Jitter(4) tPD SYNC Input to Feedback Delay(6) (2) TCY/2 − 0.4 TCY/2 + 0.4 ns − 0.15 − 500 0.15 ns 0 ps tLOCK SYNC to Phase Lock — 10 ms tPZH Output Enable Time, OE/RST LOW to HIGH(3) 0 14 ns Output Disable Time, OE/RST HIGH to LOW(3) 0 14 ns 0.3 2 ns tPZL tPHZ tPLZ tR, tF Output Rise/Fall Times, 0.8V ∼ 2V NOTES: 1. See Test Loads and Waveforms for test load and termination. 2. Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade). 3. Measured in open loop mode PLL_EN = 0. 4. Jitter is characterized with Q output at 20MHz. See Frequency Selection Table for information on proper FREQ_SEL level for specified input frequencies. 5. Skew measured at selected synchronization edge. 6. tPD measured at device inputs at 0.5VDD, Q output at 80MHz. 5 QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE BOAR D V CC ANALOG V CC 10 µ F Low Freq. Bypass DIGITAL V CC 0.1 µ F High Freq. Bypass 0.1 µ F Bypass ANALOG G ND DIGITAL GND BOARD GND A separate Analog power supply is not necessary and should not be used. Following these prescribed guidelines is all that is necessary to use the QS5LV919 in a norm al digital environment. Figure 1. Recommended Analog Isolation Scheme for the QS5LV919 NOTES: 1. Figure 1 shows an analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure stable and jitter-free operation: a. All analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of long traces can cause undesirable voltage transients. b. The 10µF low frequency bypass capacitor and the 0.1µF high frequency bypass capacitor form a wide bandwidth filter that will minimize the QS5LV919's sensitivity to voltage transients from the system digital VCC supply and ground planes. If good bypass techniques are used on a board design near components which may cause digital VCC and ground noise, VCC step deviations should not occur at the QS5LV919's digital VCC supply. The purpose of the bypass filtering scheme shown in figure 1 is to give the QS5LV919 additional protection from the power supply and ground plane transients that can occur in a high frequency, high speed digital system. 2. The bypass capacitors can be ceramic chip capacitors. There should be a 0.1µF bypass capacitor between each of the other (digital) four VCC pins and the board ground plane. This will reduce output switching noise caused by the QS5LV919 outputs, in addition to reducing potential for noise in the "analog" section of the chip. These bypass capacitors should also be tied as close to the QS5LV919 package as possible. 6 QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE PLL OPERATION The Phase Locked Loop (PLL) circuit included in the QS5LV919 provides for replication of incoming SYNC clock signals. Any manipulation of that signal, such as frequency multiplying or inversion is performed by digital logic following the PLL (see the block diagram). The key advantage of the PLL circuit is to provide an effective zero propagation delay between the output and input signals. In fact, adding delay circuits in the feedback path, ‘propagation delay’ can even be negative! A simplified schematic of the QS5LV919 PLL circuit is shown below. SIMPLIFIED DIAGRAM OF QS5LV919 FEEDBACK 2xQ INPUT Q VCO /2 Q /2 Q /2 PHASE DETECTO R The phase difference between the output and the input frequencies feeds the VCO which drives the outputs. Whichever output is fed back, it will stabilize at the same frequency as the input. Hence, this is a true negative feedback closed loop system. In most applications, the output will optimally have zero phase shift with respect to the input. In fact, the internal loop filter on the QS5LV919 typically provides within 150ps of phase shift between input and output. If the user wishes to vary the phase difference (typically to compensate for backplane delays), this is most easily accomplished by adding delay circuits to the feedback path. The respective output used for feedback will be advanced by the amount of delay in the feedback path. All other outputs will retain their proper relationships to that output. 7 QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER The frequency relationship shown here is applicable to all Q outputs (Q0, Q1, Q2, Q3 and Q4). INDUSTRIAL TEMPERATURE RANGE 50 MHz signal 25 MHz feedback signal HIGH 2:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP In this application, the 2Q output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of 2Q and SYNC, thus the 2Q frequency will equal the SYNC frequency. The Q/2 output will always run at 1/4 the 2Q frequency, and the Q output will run at 1/2 the 2Q frequency. OE/ RST Q4 Q5 2Q Q/2 FEEDBACK LOW 25 MHz input Note that with 2Q as feedback, the maximum input frequency is 100MHz for FS = HIGH REF_SEL Q3 SYNC(0) QS5LV919 V CC (AN) Q2 PE FQ_SEL HIGH Q0 Q5 Q4 FEED BACK LOW 50 MHz input 25 MHz "Q" Clock Outputs GND(AN) 50 MHz feedback signal OE/ RST 12.5 MHz signal Q1 PLL_EN 2Q Q/2 12.5 MHz input HIGH HIGH REF_SEL Q3 SYNC(0) V C C (AN) QS5LV919 PE Q2 Allowable Input Frequency Range: 20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL HIGH) 10MHz to (f2Q MAX Spec)/4 (for FREQ_SEL LOW) 25 MHz "Q" Clock Outputs Figure 2b. Wiring Diagram and Frequency Relationships with Q4 Output Feedback GND(AN) FQ_SEL Q0 HIGH Q1 1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP PLL_EN In this application, the Q/2 output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of Q/2 and SYNC, thus the Q/2 frequency will equal the SYNC frequency. The Q outputs (Q0-Q4, Q5) will always run at 2X the Q/2 frequency, and the 2Q output will run at 4X the Q/2 frequency. HIGH 12.5 MHz feedback signal Allowable Input Frequency Range: 40MHz to (f2Q MAX Spec) (for FREQ_SEL HIGH) 20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL LOW) 50 MHz signal HIGH Figure 2a. Wiring Diagram and Frequency Relationships with 2Q Output Feedback OE/ RST Q5 Q4 Q/2 FEEDBACK LOW 12.5 MHz input 1:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP REF_SEL Q3 SYNC(0) V CC (AN) In this application, the Q4 output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of Q4 and SYNC, thus the Q4 frequency (and the rest of the "Q" outputs) will equal the SYNC frequency. The Q/2 output will always run at 1/2 the Q frequency, and the 2Q output will run at 2X the Q frequency. 2Q QS5LV919 Q2 PE 25 MHz "Q" Clock Outputs GND(AN) FQ_SEL Q0 HIGH Q1 PLL_EN HIGH Allowable Input Frequency Range: 10MHz to ( f2Q MAX Spec)/4 (for FREQ_SEL HIGH) 5MHz to (f2Q MAX Spec)/8 (for FREQ_SEL LOW) Figure 2c. Wiring Diagram and Frequency Relationships with Q2 Output Feedback 8 QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER CM MU CMMU CPU CMMU CM MU CMMU CM MU CMMU CPU CMMU CM MU CMMU INDUSTRIAL TEMPERATURE RANGE CPU CARD QS5LV919 CLOCK @f PLL 2f SYS TEM CLO CK SO URCE CPU CARD QS5LV919 PLL 2f DISTRIBUTE CLO CK @ f CLOCK @ 2f at point of use QS5LV919 PLL MEMORY CO NTROL 2f ME MO RY CAR DS CLO CK @ 2f at point of use Figure 3. Multiprocessing Application Using the QS5LV919 for Frequency Multiplication and Low Board-to-Board skew QS5LV919 System Level Testing Functionality These relationships can be seen in the block diagram. A recommended test configuration would be to use SYNC0 or SYNC1 as the test clock input, and tie PLL_EN and REF_SEL together and connect them to the test select logic. When the PLL_EN pin is LOW, the PLL is bypassed and the QS5LV919 is in low frequency "test mode". In test mode (with FREQ_SEL HIGH), the 2Q output is inverted from the selected SYNC input, and the Q outputs are divideby-2 (negative edge triggered) of the SYNC input, and the Q/2 output is divideby-4 (negative edge triggered). With FREQ_SEL LOW the 2Q output is divideby-2 of the SYNC, the Q outputs divide-by-4, and the Q/2 output divide-by-8. This functionality is needed since most board-level testers run at 1 MHz or below, and the QS5LV919 cannot lock onto that low of an input frequency. In the test mode described above, any test frequency test can be used. 9 QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE AC TEST LOADS AND WAVEFORMS VDD 300 Ω 100 Ω 7.0V OUTPUT OUTPUT 300 Ω 30pF 100 Ω TEST CIRCUIT 1 TEST CIRCUIT 2 1.0ns 1.0ns tR tF 3.0V 3.0V 2.0V 2.0V V th = 0.5V DD 0.5V D D 0.8V 0.8V 0V 0V tP W LVTTL INPUT TEST WAVEFORM LVTTL OUTPUT WAVEFORM EN ABLE DISABLE 3V 0.5V D D CONTROL 0V INPU T tPLZ tPZ L OUTPUT 3.0V NOR MALLY LOW SWITCH 0.5V D D CLO SED 0.3V V OL 0.3V V OH tPHZ tPZ H SWITCH OUTPUT 0.5V DD OPEN NOR MALLY 0V HIGH ENABLE AND DISABLE TIMES TEST CIRCUIT 1 is used for output enable/disable parameters. TEST CIRCUIT 2 is used for all other timing parameters. 10 QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE AC TIMING DIAGRAM SYNC tP D FEEDBACK tJ Q tSK F Q 0 -Q 4 tS KR Q/2 2xQ t SKA LL Q5 NOTES: 1. AC Timing Diagram applies to Q output connected to FEEDBACK and PE = GND. For PE = VDD, the negative edge of FEEDBACK aligns with the negative edge of SYNC input, and the negative edges of the multiplied and divided outputs align with the negative edge of SYNC. 2. All parameters are measured at 0.5VDD. 11 QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION QS XXXX Device Type XX Speed X Package X Process Blank Industrial (-40°C to +85°C) Q J Quarter Size Outline Package Plastic Leaded Chip Carrier 55 70 100 133 160 55MHz Max. Frequency 70MHz Max. Frequency 100MHz Max. Frequency 133MHz Max. Frequency 160MHz Max. Frequency 5LV919 Low Skew CMOS PLL Clock Driver with Integrated Loop Filter CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 12 for Tech Support: [email protected] (408) 654-6459