SLUS528A – MARCH 2002 – REVISED AUGUST 2002
FEATURES
D 12-V, –12-V, 3.3-V, 5-V Main Power Switching
D
D
D
D
D
D
D
D
D
D
D
D
D
and Auxiliary 3.3-V Power Switching
12-V, –12-V And Auxiliary 3.3-V Power FETs
Hot-Swap Protection and Control of All
Supplies
Overcurrent Protection for All Supplies
Isolation of Any Load Fault in One Slot from
Any Other Slot
Undervoltage Monitoring for the Main 12-V,
3.3-V, 5-V and Auxiliary 3.3-V Supplies
Power Fault Latching
Overtemperature Shutdown
Slot Status Readout with Open-Drain LED
Drivers
Mechanical Switch Inputs for Attention
Request and Electrical Interlock
Serial Interface for Power Control, Power
Status, Slot Control and Slot Status
Compatible With 33-MHz, 66-MHz, and
133-MHz Bus Speeds
Compliant To PCI And PCI-X Hot Plug
Specifications
One TPS2340A Supports Two Slots
DESCRIPTION
The TPS2340A contains main supply power
control, auxiliary supply power control, power
FETs for 12 V, –12 V and auxiliary 3.3 V supplies,
and a serial interface for communications with and
control of slots. Each TPS2340A contains supply
control and switching for two slots.
The main power control circuits start with all
supplies off and hold all supplies off until power to
the TPS2340A is valid on all positive supplies.
When power is requested via the serial interface,
the control circuit applies constant current to the
gates of the power FETs, allowing each FET to
ramp load voltage linearly. Each supply can be
programmed for a desired ramp rate by selecting
a gate capacitor for the power FET for that supply.
The power control circuits also monitor load
current and latch off that slot if the load current
exceeds a programmed maximum value. In
addition, once the 12-V, the 5-V, and the 3.3-V
FETs are fully enhanced, the load voltage is
monitored. If load voltage drops out of
specification after these FETs are fully enhanced,
the slot latches off. This provides another level of
protection from load fault.
The auxiliary power control circuit switches,
ramps, and monitors 3.3-V auxiliary power to each
slot. The auxiliary control circuit also controls data
switches that connect slot interrupts (power
management event [PME] outputs) to the main
interrupt PME bus after 3.3-V auxiliary supply is
connected. PME is disconnected when a board is
turned off or faulted.
Each TPS2340A contains power FETs for 12 V at
500 mA, –12 V at 100 mA, and auxiliary 3.3 V at
375 mA for each slot. These power FETs are
short-circuit protected, slew rate controlled, and
over-temperature protected.
The serial interface communicates with a slot
controller using a synchronous serial protocol.
The interface communicates with the slot, status
LEDs, and mechanical switches with individual,
dedicated lines. The interface operates from 3.3-V
power but inputs are 5-V tolerant. Status LED
drivers are capable of driving 24-mA LEDs via
integrated open-drain MOSFETs. Mechanical
switch inputs have internal pull-up and hysteresis
buffers. The serial interface controls slot power,
bus connection, and LED outputs, and monitors
board capability, power fault, and switch input
status.
Copyright 2002, Texas Instruments Incorporated
!" #!$% &"'
&! #" #" (" " ") !"
&& *+' &! # ", &" " "%+ %!&"
", %% #""'
www.ti.com
1
SLUS528A – MARCH 2002 – REVISED AUGUST 2002
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Input voltage range:
P12VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 15 V
M12VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –15.0 V to 0.5 V
All others . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
Output voltage range:
P12VO, 5V3VG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VP12VIN +0.5 V
P12VG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 28 V
M12VO, M12VG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VM12VIN–0.5 V to 0.5 V
Output current pulse: P12VO (DC internally limited) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 A
M12VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 A
Operating virtual temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are respect to DGND.
electrical characteristics over recommended operating temperature range, P12VINA = P12VINB =
12 V, V5IN = 5 V, DIGVCC = 3.3 V, M12VINA = M12VINB = –12 V, 3VAUXI = 3.3 V, all outputs unloaded,
TA = TJ (unless otherwise noted)
5-V/3.3-V Supply
PARAMETER
5VOC input threshold voltage
5VISA, 5VISB voltage fault threshold
TEST CONDITIONS
ROCSET = 6.04 kΩ
After P12VG and 5V3VG good
MIN
TYP
MAX
43
53
63
4.16
4.65
4.92
V
75
135
ns
5VISA, 5VISB voltage fault minimum captured pulse
5VSA input bias current
PWRENx = high
–100
5VISA, 5VISB input bias current
PWRENx = high
100
250
500
5VISA, 5VISB bleed current
PWRENx = low,
3VOC Input threshold voltage
3VISA, 3VISB voltage fault threshold
ROCSET = 6.04 kΩ
5VISx = 5 V
After P12VG and 5V3VG good
10
20
mA
63
72
mV
2.64
2.86
3.08
V
75
135
ns
PWRENx = high
–100
3VISA, 3VISB input bias current
PWRENx = high
100
3VISA, 3VISB bleed current
PWRENx = low,
250
500
5V3VGA, 5V3VGB turn-off time
C5V3VG = 0.022 µF,
5V3VG falling from 90% to 10%
www.ti.com
A
µA
5
10
20
mA
–20
–14.5
µA
200
P12VIN = 12V
2
100
–25
5V3VGA, 5V3VGB discharge current
5V3VGA, 5V3VGB good threshold
µA
A
5
3VSA, 3VSB input bias current
5VISx = 5 V
mV
53
3VISA, 3VISB voltage fault minimum captured pulse
time
5V3VGA, 5V3VGB charge current
100
UNIT
9.5
mA
11
11.5
V
1
3.5
µs
SLUS528A – MARCH 2002 – REVISED AUGUST 2002
electrical characteristics over recommended operating temperature range, P12VINA = P12VINB =
12 V, V5IN = 5 V, DIGVCC = 3.3 V, M12VINA = M12VINB = –12 V, 3VAUXI = 3.3 V, all outputs unloaded,
TA = TJ (unless otherwise noted) (continued)
12-V Supply
PARAMETER
+12
V Internal NMOS on
resistance
+12-V
on-resistance
–12-V
12 V Internal NMOS on
on-resistance
resistance
TEST CONDITIONS
PWREN = HIGH,
TA = TJ = 25°C
ID = 0.5 A
PWREN = HIGH,
ID = 0.5 A
ID = 0.1 A
PWREN = HIGH,
TA = TJ = 25°C
PWREN = HIGH,
MIN
TYP
MAX
0.18
0.3
Ω
0.4
Ω
0.5
ID = 0.1 A
0.75
UNIT
Ω
0.9
+12-V overcurrent threshold
ROCSET = 6.04 kΩ
0.83
1.00
1.17
–12-V overcurrent threshold
ROCSET = 6.04 kΩ
0.12
0.19
0.25
P12VOA, P12VOB fault threshold voltage
After P12VG and 5V3VG good
9.50
10.80
11.15
V
75
135
ns
–20
–14.5
P12VOA, P12VOB voltage fault minimum captured
pulse time
M12VGA, M12VGB gate charge current
–25
M12VGA, M12VGB gate discharge current
P12VGA, P12VGB, charge current
200
Derived from charge pump
1.0
P12VGA, P12VGB, discharge current
P12VGA, P12VGB good threshold
P12VIN = 12 V
19
8.5
PWREN = LOW to M12VO = –0.6 V,
CM12VG = 0.022 µF
M12VO bleed current
P12VO bleed current
µA
mA
20.5
22
15
20
V
ms
PWREN = HIGH to P12VO = 11.4 V,
C12PVG = 0.022 µF,
RL = 24 Ω
CP12VO = 200 µF
PWREN = LOW to P12VO = 0.6 V,
CP12VG = 0.022 µF
Turn off time
Turn-off
µA
mA
100
PWREN = HIGH to M12VO = –10.4 V,
CM12VG = 0.022 µF,
RL = 120 Ω
CM12VO = 50 µF
T rn on time
Turn-on
4.0
A
60
75
1.5
3.5
µs
1.5
3.5
µs
–20
–5
mA
5
10
MIN
TYP
MAX
1
2
input/output control
PARAMETER
TEST CONDITIONS
P12VIN supply current
P12VIN = 12 V
V5IN supply current
V5IN = 5 V
1.00
2.75
DIGVCC supply current
DIGVCC = 3.3 V
500
2000
M12VIN supply current
M12VIN –12 V
250
2000
3VAUXI supply current
3VAUXI = 3.3 V
200
2000
Overcurrent fault response time
500
960
DIGVCC start-up threshold voltage
2.60
2.80
2.95
DIGVCC stop threshold voltage
2.40
2.55
2.80
V5IN start-up threshold voltage
4.2
4.4
4.6
V5IN stop threshold voltage
3.8
4.0
4.4
10.2
10.3
11.2
9.5
9.4
10.6
P12VIN start-up threshold voltage
P12VIN stop threshold voltage
www.ti.com
UNIT
mA
µA
ns
V
3
SLUS528A – MARCH 2002 – REVISED AUGUST 2002
electrical characteristics over recommended operating temperature range, P12VINA = P12VINB =
12 V, V5IN = 5 V, DIGVCC = 3.3 V, M12VINA = M12VINB = –12 V, 3VAUXI = 3.3 V, all outputs unloaded,
TA = TJ (unless otherwise noted) (continued)
noise filter
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Ignored spike from overcurrent
250
ns
Latched spike from overcurrent
500
ns
3.3 V AUX and PME
PARAMETER
TEST CONDITIONS
3VAUXx overcurrent shutdown
3VAUXI to 3VAUXx on-resistance
MIN
TYP
MAX
0.95
1.15
1.40
A
300
425
mΩ
2.2
2.9
V
1.6
3.3
V/ms
3
5
2.5
7.0
5
10
µs
10
17
ms
I3VAUXx = –500 mA
3VAUXI undervoltage lockout
1.9
3VAUXx turn-on slew rate
UNIT
3VAUXx turn-on time from SWx
from SWx < 0.8 V,
C3VAUXx = 150 µF
3VAUXx turn-off time from SWx
from SWx > 2.0 V
3VAUXx turn-off time from Faultx
from 3VAUXx overcurrent fault detected
PMEx turn-on time from 3VAUXx
from 3VAUXx > 3.0 V,
C3VAUXx = 150 µF
PMEx turn-off time from SWx
from SWx > 2.0 V,
2
4
µs
PMEx turn-off time from Faultx
from 3VAUXx overcurrent fault detected
2
4
µs
PMEx switch on-resistance
from SWx < 0.8 V,
TA = TJ = 25°C
5
10
Ω
TYP
MAX
UNIT
0
10
MHz
0
15
6
ID = 10 mA
ms
ac switching characteristics
PARAMETER
TEST CONDITIONS
MIN
fMAX operating clock frequency
SIDO tCO clock to output time
0 ≤ TA ≤ 70°C
SIDI, SIL tSU setup to clock time
0 ≤ TA ≤ 70°C
15
SODI, tSU setup to clock time
0 ≤ TA ≤ 70°C
15
SODI, tH hold time
0 ≤ TA ≤ 70°C
0
All outputs tCO clock to output time
Recommended input rise and fall times
4
CL = 50 pF,
0 ≤ TA ≤ 70°C
BUSENx, SIDO: CL = 50 pF,
RESETx: CL = 35 pF,
All other outputs: CL = 25 pF,
0 ≤ TA ≤ 70°C,
10% to 90% of VCC, all digital inputs except
SWx, BUTTONx, PGOOD, PRSNT1x, and
PRSNT2x
www.ti.com
15
ns
20
0.2
1
SLUS528A – MARCH 2002 – REVISED AUGUST 2002
electrical characteristics over recommended operating temperature range, P12VINA = P12VINB =
12 V, V5IN = 5 V, DIGVCC = 3.3 V, M12VINA = M12VINB = –12 V, 3VAUXI = 3.3 V, all outputs unloaded,
TA = TJ (unless otherwise noted) (continued)
dc electrical characteristics
MIN
TYP
MAX
Input threshold voltage (SIL, SOC, SIDI, SORR,
SORLC, TEST, M66EN, SOLC, SOR, SODI, SIC)
PARAMETER
0.8
1.4
2.0
High–level input threshold voltage (SWA, SWB,
BUTTONA, BUTTONB, PRSNT1A, PRSNT2A,
PRSNT1B, PRSNT2B, PGOOD)
2.0
2.4
2.8
Low-level input threshold voltage (SWA, SWB,
BUTTONA, BUTTONB, PRSNT1A, PRSNT2A,
PRSNT1B, PRSNT2B)
0.8
1.2
1.6
Low-level input threshold voltage (PGOOD)
0.1
0.4
0.8
Input hysteresis (SWA, SWB, BUTTONA, BUTTONB,
PRSNT1A, PRSNT2A, PRSNT1B, PRSNT2B)
0.4
1.0
1.6
Input hysteresis (PGOOD)
1.5
2.0
2.5
2.4
2.8
High-level output voltage (BUSENA, BUSENB)
TEST CONDITIONS
Low-level output voltage (BUSENA, BUSENB)
IL = –8 mA
IL = 16 mA
Low-level output voltage (PWRLEDA, PWRLEDB,
ATTLEDA, ATTLEDB)
Low-level output voltage (all other outputs)
0.2
0.5
IL = 24 mA
0.4
0.8
IL = 4 mA
0.2
0.5
3.3 V pull-up resistor impedance
(inputs pulled up to 3.3 V)
30
200
5 V pull-up resistor impedance (inputs pulled up to 5 V)
30
200
Pull-down resistor impedance (inputs with pull-down)
30
200
PCIXCAPA, PCIXCAPB resistor for 133 MHz
Open circuit recommended
PCIXCAPA, PCIXCAPB resistor for 66 MHz
10 kΩ connection to DIGGND recommended
PCIXCAPA, PCIXCAPB resistor for 33 MHz
0 kΩ connection to DIGGND recommended
UNIT
V
kΩ
30
6
14
1
recommended operating conditions
MIN
MAX
Input voltage, P12VINA, P12VINB
10.8
13.2
Input voltage, V5IN
4.75
5.25
3.1
3.5
–13.2
–10.8
Input voltage, DIGVCC
Input voltage, M12VINA, M12VINB
Input voltage, 3VAUXI
3.1
3.5
Load current, PWRLEDA, PWRLEDB, ATTLEDA, ATTLEDB
0
24
Load current, P12VOA, P12VOB
0
500
Load current, M12VOA, M12VOB
0
100
Load current, 3VAUXA, 3VAUXB
0
375
www.ti.com
UNIT
V
mA
5
SLUS528A – MARCH 2002 – REVISED AUGUST 2002
DIGGND3
SODI
SIDO
PWRGND2
5V3VGA
3VSA
3VISA
5VISA
5VSA
ANAGND
NC
NC
NC
PCIXCAPA
V5IN
PWRLEDA
ATTLEDA
SWA
BUTTONA
SIC
PFP PACKAGE
(TOP VIEW)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
PMEO
PMEA
PMEB
3VAUXB
3VAUXA
3VAUXI
M12VOA
M12VINA
M12VGA
P12VGA
P12VOA
P12VINA
P12VINA
P12VINB
P12VINB
P12VOB
P12VGB
M12VGB
M12VINB
M12VOB
61
40
62
39
63
38
64
37
65
36
66
35
67
34
68
33
69
32
70
31
71
30
72
29
73
28
74
27
75
26
76
25
77
24
78
23
79
22
80
2 3
4 5
21
7 8 9 10 11 12 13 14 15 16 17 18 19 20
6
PWRGND1
5V3VGB
3VSB
3VISB
5VISB
5VSB
OCSET
NC
NC
NC
PCIXCAPB
PWRLEDB
ATTLEDB
SWB
BUTTONB
SIL
SOC
DIGGND2
SODO
SIDI
1
AVAILABLE OPTIONS
PACKAGE
6
TA
HTQFP (PFP)
–40°C to 85°C
TPS2340APFP
www.ti.com
SOR
SOLC
PGOOD
PRSNT1A
PRSNT2A
RESETA
M66ENA
CLKENA
BUSENA
DIGGND1
DIGVCC
BUSENB
CLKENB
M66ENB
RESETB
PRSNT2B
PRSNT1B
TEST
SORLC
SORR
SLUS528A – MARCH 2002 – REVISED AUGUST 2002
Terminal Functions
TERMINAL
I/O
NAME
NO.
3VAUXI
66
I
3VAUXA
65
O
3VAUXB
64
O
3VISA
57
I
3VISB
4
I
3VSA
58
I
3VSB
3
I
5V3VGA
59
O
5V3VGB
2
O
5VISA
56
I
5VISB
5
I
5VSA
55
I
DESCRIPTION
3.3Vaux voltage supply input. A 0.1-µF bypass capacitor to PWRGND is recommended.
3 3Vaux voltage supply outputs.
3.3Vaux
outputs A 0
0.01-µF
01 F bypass capacitor to PWRGND is recommended.
recommended
Connect to the load side of the sense resistor. See definition for 3VS. This pin has a switched FET to
ground to discharge any output load capacitance when the output is turned off.
off A 0.01-µF
0 01 µF bypass caca
pacitor to ANAGND is recommended.
Connect to the source side of the 3.3-V FET switch. This pin in conjunction with the 3VIS pin sense
3 V load by sensing the voltage drop across a sense resistor.
resistor A 0
01 µF bypass
the current to the 3
3.3-V
0.01-µF
capacitor to ANAGND is recommended.
Gate drive for the 5-V and 3.3-V FET switches. Ramp rate is programmed by external capacitance
connected from this pin
in to PWRGND. The capacitor
ca acitor is charged with a 20-µA current source and discharged with a switch. The output UV circuitry is disabled until the voltage on this pin is greater than
11 V and the voltage on P12VGx is greater than 20 V.
Connect to the load side of the sense resistor. See definition for 5VS. 5VIS is also used to sense the
out
ut voltage for the 5-V UV circuit. This pin
in has a switched FET to ground to discharge any output
out ut
output
load capacitance when the output is turned off. A 0.01-µF bypass capacitor to ANAGND is recommended.
5VSB
6
I
Connect to the source of the 5-V FET switch. This pin in conjunction with the 5VIS pin senses the
current to the 5V load by sensing the voltage drop across the sense resistor.
resistor A 0.01-µF
0 01 µF bypass capaci
capacitor to ANAGND is recommended.
ANAGND
54
–
Ground pin for the low level analog section
ATTLEDA
47
O
ATTLEDB
13
O
BUSENA
32
O
BUSENB
29
O
BUTTONA
45
I
BUTTONB
15
I
CLKENA
33
O
CLKENB
28
O
DIGVCC
30
I
DIGGND1
31
–
DIGGND2
18
–
DIGGND3
43
–
M12VGA
69
O
M12VGB
78
O
M12VINA
68
I
M12VINB
79
I
M12VOA
67
O
M12VOB
80
O
M66ENA
34
I
PCI 66MHz–capable bit for slot A. This pin has a 100-kΩ pull-up to 3VISA. This pin is typically tied to
the PCI connector.
M66ENB
27
I
PCI 66MHz–capable bit for slot B. This pin has a 100-kΩ pull-up to 3VISB. This pin is typically tied to
the PCI connector.
I
A resistor connected between this pin and ANAGND sets the overcurrent threshold of the 4 FET
switches. The +12-V and –12-V switches are set for the maximum permissible currents per the PCI
specification when a 1%, 6.04-kΩ resistor is used. A 0.1-µF bypass capacitor from OCSET to
ANAGND is recommended.
OCSET
7
ATTLEDx is a high
high-current,
current low
low-true,
true open
open-drain
drain output with a 100
100-kΩ
kΩ pull
pull-up
up resistor to V5IN
V5IN.
Output to bus enable FET switches.
Output-to-bus
switches These outputs typically enable PCI clocks to the PCI connector.
connector
PCI hot-plut attention notification (momentary) button inputs. Low indicates attention. These input have
hysteresis and a 100-kΩ
100 kΩ pull-up
pull up to DIGVCC,
DIGVCC requiring only a capacitor to ground for debouncing meme
chanical noise.
O tp t to clock enable FET switches.
Output-to-clock
s itches These outputs
o tp ts typically
t picall enable PCI clocks to the PCI connector.
connector
Power pin for the digital section, connect to 3.3 V. A 0.1-µF bypass capacitor from DIGVCC to
DIGGND is recommended.
Ground pins
ins for the digital section.
ramp rate of the 12-V switched out
output.
A capacitor
ca acitor connected from this pin
in to M12VO programs
rograms the ram
ut.
The capacitor is charged with a 20-µA current source and discharged with a switch.
–12-V input voltage to the device and the –12-V power FET. M12VINA and M12VINB must be tied
together and are internally connected by a high-resistance
high resistance path.
path The tab on the back of the package is
also connected to M12VIN. A 0.1-µF bypass capacitor from M12VIN to PWRGND is recommended.
–12-V Switched output.
out ut. This pin
in has a switched FET to ground to discharge any output
out ut load capacica acitance when the output is turned off. A 0.01-µF bypass capacitor to PWRGND is recommended.
www.ti.com
7
SLUS528A – MARCH 2002 – REVISED AUGUST 2002
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
P12VGA
70
O
Gate drive for the 12-V internal N-channel MOSFET for slot A. Connect a capacitor from this pin to
PWRGND to program the ramp rate. The capacitor is charged with a 5–µΑ current source and discharged with a switch. The output undervoltage circuitry is disabled until the voltage on this pin is
greater than 20 V and the voltage on 5V3VGA is greater than 11 V.
P12VGB
77
O
Gate drive for the 12-V internal N-channel MOSFET for slot B. Connect a capacitor from this pin to
PWRGND to program the ramp rate. The capacitor is charged with a 5-µΑ current source and discharged with a switch. The output undervoltage circuitry is disabled until the voltage on this pin is
greater than 20 V and the voltage on 5V3VGB is greater than 11 V.
72
I
73
I
75
I
74
I
P12VOA
71
O
12-V switched output for slot A. This pin has a switched FET to ground to discharge any output load
capacitance when the output is turned off. A 0.01-µF bypass capacitor to PWRGND is recommended.
P12VOB
76
O
12-V switched output fo rslot B. This pin has a switched FET to ground to discharge any output load
capacitance when the output is turned off. A 0.01-µF bypass capacitor to PWRGND is recommended.
PCIXCAPA
50
I
PCIXCAPB
11
I
P12VINA
P12VINB
12-V in
input
ut to the device and the 12-V power
ower FET for slot A. A 0.1-µF by
bypass
ass ca
capacitor
acitor from P12VINA
to PWRGND is recommended.
12-V in
input
ut to the device and the 12-V power
ower FET for slot B. A 0.1-µF by
bypass
ass ca
capacitor
acitor from P12VINB
to PWRGND is recommended.
PCI–X capable bit. To select 133-MHz PCI–X mode, leave PCIXCAPx floating. For 66-MHz PCI–X
mode, pull
ull down PCIXCAPx with one or two 10-kΩ resistors. For 33-MHz PCI 2.2 mode, ground
PCIXCAPx. This pin has a 10-kΩ pull–up resistor to DIGVCC. This pin is typically tied to the PCI connector.
PGOOD
38
I
Power good input. PGOOD has hysteresis so that it can be used as a power-on reset, driven from a
slow-rising RC. PGOOD also has a 100-kΩ pull-up to DIGVCC. A logic path in the TPS2340A prevents the input data state machine from being reset when SOR asserts. This can be corrected with an
external AND gate, which causes PGOOD to be de-asserted whenever SOR is asserted. (See Note
1.)
PMEA
62
I
PME input from slot A. These signals comply with PCI Power Management Spec 1.1. PMEA has a
200-kΩ pull-up to the appropriate switched 3VAUX for precharging. This pin is typically tied to the PCI
connector.
PMEB
63
I
PME input from slot B. These signals comply with PCI Power Management Spec 1.1. PMEB has a
200-kΩ pull-up to the appropriate switched 3VAUX for precharging. This pin is typically tied to the PCI
connector.
PMEO
61
O
PME output from the device. This signal is an open-drain output and complies with PCI Power Management Specification 1.1 PME definition.
PRSNT1A
37
I
PRSNT1B
24
I
PRSNT2A
36
I
PRSNT2B
25
I
PWRGND1
1
_
PWRGND2
60
–
PWRLEDA
48
O
PWRLEDB
12
O
PCI presence
resence detect bit 1. This in
input
ut has hysteresis and a 100-kΩ pull-up
ull-u to DIGVCC, requiring only a
capacitor to ground for debouncing mechanical noise. This pin is typically tied to the PCI connector.
PCI– resence detect bit 2. This input
PCI–presence
in ut has hysteresis and a 100-kΩ pull–up
ull–u to DIGVCC, requiring only
a capacitor to ground for debouncing mechanical noise. This pin is typically tied to the PCI connector.
Gro nd pin for the power
Ground
po er analog section.
section
In normal operation, output-to-power indicator PCI hot-plug status LED. In test mode, indicates the
state of the internal signal PWRENx
PWRENx, the power FET control signal
signal. PWRLEDx is a high-current,
high current lowlow
true open-drain output with a 100-kΩ pull-up resistor.
NOTE 1: PGOOD input: diagram:
TPS2340
PWRGOOD (FROM PLATFORM)
SOR (FROM HPC)
38 PGOOD
40
SOR
UDG–01126
8
www.ti.com
SLUS528A – MARCH 2002 – REVISED AUGUST 2002
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
RESETA
35
O
PCI RESET signal to slot A. Conforms to PCI 2.2 local bus specification for 3.3-V signaling. This pin is
typically tied to the PCI connector.
RESETB
26
O
PCI RESET signal to slot B. Conforms to PCI 2.2 local bus specification for 3.3-V signaling. This pin is
typically tied to the PCI connector.
SIC
44
I
Serial input clock. Shift serial data into device one bit position on rising edge.
SIDI
20
I
Serial input data Input. The serial shift register input from a down-stream TPS2340.
SIDO
41
I/O
SIL
16
I
Serial input load. Pulse low to synchronously parallel load external serial input shift registers on the
next rising edge of SIC.
SOC
17
I
Serial output clock. Shift serial output data into parallel output registers one bit position on rising edge.
SODI
42
I
Serial output data input. Serial output data shifted into parallel output registers.
SODO
19
I/O
SOLC
39
I
Serial output latch clock. Latch parallel register data on rising edge.
SORLC
22
I
Serial output reset latch clock. Latch parallel register data on rising edge (PCI RESET latches only).
SOR
40
I
Serial output reset. Clears parallel register data.
SORR
21
I
Serial output reset reset. Clears parallel register data (PCI RESET latches only).
SWA
46
I
Slot A switch input. Low indicates the slot is populated. This input has hysteresis and a 100-kΩ pull-up
to 3VAUXI, requiring only a capacitor to ground for debouncing mechanical noise. For testing purposes, pulling SWA to 5 V enables the slot main power and disables the slot auxilliary power, bypassing the serial interface.
Serial input data output. The serial shift register output to the PCI hot-plug controller or the up-stream
TPS2340. When PGOOD is low, SIDO is undriven and pulled up to DIGVCC with a 100-kΩ resistor.
During the rising edge of PGOOD, the TPS2340A latches SIDO as MODE0.
Serial output data output. Serial output data shifted to the down-stream TPS2340. When PGOOD is
low, SODO is undriven and pulled up to DIGVCC with a 100-kΩ resistor. During the rising edge of
PGOOD, the TPS2340A latches SODO as MODE1.
SWB
14
I
Slot B switch input. Low indicates the slot is populated. This input has hysteresis and a 100-kΩ pull-up
to 3VAUXI, requiring only a capacitor to ground for debouncing mechanical noise. For testing purposes, pulling SWB to 5 V enables the slot main power and disables the slot auxilliary power, bypassing the serial interface.
TEST
23
I
When asserted on the rising edge of PGOOD, device enters test modes based on the states of the
MODE pins. See In–Circuit Test section of the datasheet. When asserted after PGOOD is asserted,
maps the Pwrenx and ANDed Faultx internal signals to PWRLED and ATTLED pins for test purposes.
TEST has a 100-kΩ pull-down resistor to ground.
V5IN
49
I
5-V input to the device. A 0.1-µF bypass capacitor from V5IN to PWRGND is recommended.
www.ti.com
9
SLUS528A – MARCH 2002 – REVISED AUGUST 2002
functional block diagram
OVERCURRENT SENSE
3VAUXI 66
65 3VAUXA
AUX FAULT
LATCH
S Q
TO
SECOND
SLOT
+
2.9 V
10 ms
TURN–ON
DELAY
PMEO 61
R
+
2.2 V
SW INPUT
2.5 ms
TURN–OFF
DELAY
100 µA
OCSET 7
Q
62 PMEA
THERMAL
SHUTDOWN
CURRENT LIMIT
THRESHOLD
OVER–
CURRENT
SENSE
+
20 V
70
P12VGA
72
P12VINA
71
P12VOA
69
M12VGA
67
M12VOA
+
5V3VGA 59
10 V
3VSA 58
+
MAIN
FAULT
LATCH
3VISA 57
5VSA 55
S
Q
R
Q
OVER–
CURRENT
SENSE
+
5VISA 56
P12VO
5VIS
3VIS
OUTPUTS
GOOD
P12VIN
V5IN
DIGVCC
INPUTS
GOOD
68 M12VINA
TO
SECOND
SLOT
PWRENA
SERIAL BUS
AUXFLTA
FLTA
PWRENB
AUXFLTB
FLTB
LED OUTPUTS
SWITCH INPUTS
SERIAL TO PARALLEL CONVERTER
TO SLOT
FROM SLOT
54
ANAGND
10
1
60
PWRGND1 PWRGND2
49
30
31
V5IN
DIGVCC
DIGGND
www.ti.com
18
43
DIGGND2 DIGGND3
UDG–01011
SLUS528A – MARCH 2002 – REVISED AUGUST 2002
APPLICATION INFORMATION
Figure 1 shows three TPS2340A devices cascaded in a system to control six PCI or PCI–X hot-plug slots. A
hot-plug controller communicates with three TPS2340A devices over a nine-signal serial bus. Three signals are
used to gather status information from the slots, and six signals are used to control the slots. In this bus, seven
of the nine signals are connected in parallel. The remaining signals facilitate a cascaded bus and are comprised
of the signal pair SIDI/SIDO and SODI/SODO. The SIDO signal drives the PCI hot-plug controller serial input
data pin or the SIDI pin of another up–stream TPS2340. The SODI signal is driven by the PCI hot-plug controller
and is cascaded down to the next TPS2340A via the SODO signal.
The SIDO and SODO outputs are dual-function pins that also serve as mode-select pins upon the rising edge
of PGOOD. See Digital Circuits section for more details.
SOLC
SOLRC
SOR
SORR
SIC
SIL
PMEA PCIXCAPA
PMEB PCIXCAPB
ANALOG I/O
U1
U2
PCI
HOT–PLUG
CONTROLLER
ANALOG CONTROL
FaultA
AuxfltA
PCIXCAP1A
PCIXCAP2A
ANALOG CONTROL
PCIXCAP1A
PCIXCAP2A
PwrenA
FaultB
AuxfltB
PwrenB
SID1
SIDO/MODE0
SOD
U3
U4
SID3
SID2
SIDI
SID
SERIAL/PARALLEL CONVERTER
SODI
SODO/MODE1
INPUTS
SWA
PRTSNT2A
PRTSNT1A
BUTTONA
M66ENA
OUTPUTS
PWRLEDA
ATTLEDA
BUSENA
CLKENA
RESETA
PGOOD
PMEO
PWR_GOOD PME
TEST
INPUTS
OUTPUTS
SWB
PRTSNT2B
PRTSNT1B
BUTTONB
M66ENB
PWRLEDB
ATTLEDB
BUSENB
CLKENB
RESETB
SLOT A
SOD1
SLOTS C AND D
SOD2
SOD3
SLOTS E AND F
UDG–01015
SLOT B
Figure 1. Hot-Plug System Block Diagram
analog circuits
power controller
The functional block diagram shows the TPS2340A with detailed information on the analog functions. For clarity,
circuits for only one slot are shown in detail.
3.3-V auxiliary supply (3.3-Vaux) support
In today’s hot-plug systems, a 3.3Vaux rail remains live while the system power is shut down to allow
implementation of the PCI Power Management Specification, version 1.1. The TPS2340A provides a 3.3-Vaux
input pin that is monitored for undervoltage and generates a 3.3-Vaux supply pin for each hot-plug slot that is
monitored for overcurrent. These supply pins are switched by the slot-specific SWx slot switch inputs. When
the slot switch is opened, the slot-specific 3.3-Vaux supply is disabled to allow safe removal of the adapter card.
When the slot switch is closed (SWx grounded), the slot-specific 3.3-Vaux supply is restored.
www.ti.com
11
SLUS528A – MARCH 2002 – REVISED AUGUST 2002
APPLICATION INFORMATION
power cycling and PME
The PCI Power Management Specification defines a signal called PME (power management event) to allow
power management events to be communicated back to the system. The TPS2340A provides a slot-specific
PMEx input and a gated PMEO output pin that is monitored by the system. The gated PMEO output is controlled
by the SWx slot switch similar to the 3.3-Vaux supply pins described above, but with a delay during connection
as shown below. The purpose of the delay is to ensure that 3.3-Vaux power is stable to the slot before connecting
the PMEx signal. (If the device were to observe the PMEx signal while 3.3-Vaux power was still ramping up, a
false trigger could result.)
The 3.3-Vaux circuitry provides short-circuit fault detection. In the event of a fault, the slot 3.3-Vaux and PME
signals are immediately disconnected. The fault state is latched internally in the TPS2340A and is cleared by
opening the SWx slot switch or by the removal of the 3.3-Vaux power supplying the TPS2340.
10 ms
TYP
2.5 ms
TYP
10 ms
TYP
SWx
3VAUXx
PME ENABLE
Auxfltx
UDG–01016
Figure 2. 3.3Vaux and PME Gating
When SWx is closed, 3VAUXx power is immediately applied to the slot with controlled slew rate, minimizing
inrush current into 3VAUXx bypass capacitors. After 3VAUXx power is above threshold, a delay timer starts.
At the end of the delay timer cycle, the PMEx switches close, allowing connection of the PMEx signal to the
PMEO output. When multiple TPS2340A devices are used in a system, the PMEO output pins can be connected
to the same node, creating a wired–OR PME bus that can be connected to a system interrupt input.
When SWx is opened or if there is a power fault on channel x, the PMEx switch for that channel is immediately
opened and the 3VAUXx power for that channel is removed. Although these events happen at approximately
the same time, the 3VAUXx power should remain high until the PMEx switch is open so that falling 3VAUXx
power doesn’t cause a nuisance PMEx interrupt. To insure that 3VAUXx remains high during a power fault,
3VAUXx should have a bypass capacitance of at least 20 µF. If the capacitor is not available on the inserted
card, it should be provided on the system board.
12
www.ti.com
SLUS528A – MARCH 2002 – REVISED AUGUST 2002
APPLICATION INFORMATION
fault handling
When PGOOD is asserted (main power is valid), the serial interface is available for use. At this time, Auxflt and
Faultx (i.e. Faultx = Pwrfltx • Auxflt) signals are present in the registers and can be read back over the serial
interface.
When PGOOD is deasserted (main power is not valid), the serial interface is inactive, so the TPS2340A provides
an alternate path for observing the Auxfltx signals. In this case, Auxfltx is presented on the ATTLEDx open-drain
output, so 3Vaux faults can be observed. Systems that do not require Auxfltx indications when main power is
off should use main power to supply current to the attention LEDs.
In addition, when TEST is asserted after PGOOD has changed from 0 to 1, the AND of Pwrfltx and Auxfltx is
present on the ATTLEDx open-drain output, so the attention LEDs can be used to report any faults on each
channel.
After PGOOD is asserted with TEST deasserted and the voltage on the SWx pin is greater than VDIGVCC but
less than VV5IN, ATTLEDx follows the fault status of the main power fault (Pwrfltx). If the SWx input is pulled
to VV5IN potential, that slot becomes immediately enabled independent of serial interface status and ATTLEDx
follows the fault status of the main power fault (Pwrfltx).
Table 1. Fault Reporting Using ATTLED
PGOOD
TEST
< VDIGVCC
SWx
0
x
Auxfltx
ATTLEDx
< VDIGVCC
1
1
Pwrfltx • Auxfltx
> VDIGVCC, < VV5IN
= VV5IN
1
0
Pwrfltx
x
x
Pwrfltx
PCI–XCAP resolution
Add-in cards indicate their PCI-X mode and frequency capabilities by connection of the PCI-XCAP pin. The
TPS2340A utilizes a three-level comparator to resolve the PCI-XCAP input so as to decode operating mode
and generate the PCI-XCAP2 and PCI-XCAP1 internal signals. With PCI-XCAP open, the TPS2340A selects
PCI-X 133-MHz operation. PCI-X 66-MHz operation is selected by a 10-kΩ pull-down resistor on PCI-XCAP.
With PCI-XCAP grounded, conventional PCI-2.2 operation is selected. This decoding conforms to the standard
PCI-X specification for PCI-XCAP resolution.
Table 2. PCI-XCAP Pin State Resolution
PCI-XCAP
PCI-XCAP2
PCI-XCAP1
GND
0
0
Conventional PCI 2.2 operation
10-kΩ Pull-down Resistor
0
1
PCI-X 66-MHz operation
Open Circuit
1
1
PCI-X 133-MHz operation
www.ti.com
DESCRIPTION
13
SLUS528A – MARCH 2002 – REVISED AUGUST 2002
APPLICATION INFORMATION
thermal shutdown
Under normal operating conditions, the power dissipation in the TPS2340A is low enough that junction
temperature (TJ) is not more than 15°C above air temperature. However, in the case of a load that exceeds PCI
specifications but remains under the TPS2340A current-limit threshold, power dissipation can be higher. To
prevent any damage from an out-of-specification load or severe rise in ambient temperature, the TPS2340A
contains two independent thermal shutdown circuits, one for each slot’s main supplies.
The highest power dissipation in the TPS2340A is from the 12-V power FET so the TPS2340A temperature
sense elements are integrated closely with these FETs. These sensors indicate when the temperature at these
transistors exceeds approximately 150°C, either due to average TPS2340A power dissipation, 12-V power FET
power dissipation, or a combination of both.
When excessive junction temperature is detected on one slot, that slot fault latch is set and remains set until
junction temperature drops by approximately 10°C and the slot is turned off, then on again through the serial
interface. The other slot is not affected by this event. Also, 3.3-Vaux is not affected by thermal events.
digital circuits
The TPS2340A implements two independent slots of hot-plug power management. In addition, the TPS2340A
contains digital circuits to allow communication between these two slots and the system’s hot-plug controller.
Also, the TPS2340A contains inputs for connection to mechanical switches and outputs for driving indicator
LEDs to directly communicate with users and service.
This digital logic implements a serial-to-parallel converter that accepts data from the serial interface and
presents that data to each slot. Data from the serial interface drives the Pwrenx internal main power control
signal. Additional data from the serial interface includes BUSENx and CLKENx outputs to activate bus switches,
RESETx outputs to allow reset to each slot, and ATTLEDx and PWRLEDx outputs to indicate slot status to
users.
The serial-to-parallel converter also accepts data from the slot and sends that data back on the serial interface.
Data to the serial interface includes SWx and BUTTONx switch state, PRSNTnx bits, M66ENx and PCI–XCAPx
bits to indicate board type, and internal fault signals Auxfltx and Faultx.
When the digital circuits are operating in normal mode, the serial interface is enabled and controls the slots. The
TPS2340A also operates in various test modes, allowing board testing and system development.
Each TPS2340A controls two PCI/PCI–X slots. For systems requiring more than two slots, additional
TPS2340A devices can be cascaded without requiring an additional hot-plug controller. To maintain system
reliability and data integrity at full speed, bus length is often limited to six PCI slots. When higher speed PCI–X
protocols are active, bus length may be limited to even fewer active slots. However, the TPS2340A is not limited
in cascade capability or bus length.
14
www.ti.com
SLUS528A – MARCH 2002 – REVISED AUGUST 2002
APPLICATION INFORMATION
power on configuration
Table 3. lists the various modes of operation and the proper pin states that are necessary to achieve these
modes. The shaded rows indicate test modes.
Table 3. Power On Configuration
PGOOD
↑
↑
↑
↑
↑
↑
TEST
0
1
1
1
0
0
SODO/MODE1
1
0
0
1
0
X
SIDO/MODE0
1
0
1
X
X
0
1
1
SODO
SIDO
1
0
SODO
NOTE: X = Don’t care, x = slot A or B
SIDO
OPERATING MODE
Operational mode
NAND tree test mode
Tri–state test mode (all pins tri–stated)
Reserved
Reserved
Reserved
Normal operation, but Pwrenx driven on PWRLEDx, Faultx
driven on ATTLEDx.
Normal operation
operational mode functional description
When both mode pins are 1 and the test pin is 0, on the rising edge of PGOOD, the TPS2340A enters operational
mode. In this mode, the PCI hot-plug controller is able to address multiple TPS2340A ICs and multiple slots.
Input status for all slots is grouped into four channels that can be requested by the PCI hot-plug controller.
channel selection
The PCI hot-plug controller indicates to the TPS2340A which channel to read back via signaling on the SIL pin.
The SIL pin asserts low for one SIC clock to indicate a start bit, followed by three SIC clocks of channel address
information in the order of channel address LSB followed by channel address MSB and a reserved bit. So as
an example, if the hot-plug controller desires to read non-interrupt capable input data from the TPS2340A
(channel 01 binary), the SIL sequence is shown in Table 3.
Table 4. Input Channel Selection Example – Channel 01 Selected
CLOCK
SIL STATUS
0
Start bit (low)
1
Channel address LSB (high)
2
Channel address MSB (low)
3
Reserved (high)
4 – 47
High
www.ti.com
15
SLUS528A – MARCH 2002 – REVISED AUGUST 2002
APPLICATION INFORMATION
operational mode input channel address grouping
Table 5. lists the functions assigned to the channel addresses.
Table 5. Operational Mode Channel Address Grouping
CHANNEL
ADDRESS
FUNCTIONAL CHANNEL GROUP
00
Interrupt capable inputs
01
Non–interrupt capable inputs
10
Diagnostic data #1
11
Diagnostic data #2
As devices are cascaded, SIDI pin data is received from devices down-stream and passes through the device,
shift-register style, to eventually reach the SIDO pin and the PCI hot-plug controller. The data contained in each
input channel group is described in Tables 6, 7, 8, and 9.
Table 6. Channel 00 Data Group – Interrupt Capable Inputs
BIT
NUMBER
0
Slot A SW (1 = interlock A open)
1
Slot A button state (1 = button A pushed)
2
Slot A power fault state (PwrfltA & AuxfltA)
3
Slot A PRSNT2
4
Slot A PRSNT1
5
Reserved
6
Reserved
7
Reserved
8
Slot B SW
9
Slot B button state
10
Slot B power fault state (PwrfltB & AuxfltB)
11
Slot B PRSNT2
12
Slot B PRSNT1
13
Reserved
14
Reserved
15
Reserved
16…47
16
FUNCTION
SIDI pin data for slots C, D, E and F follows
www.ti.com
SLUS528A – MARCH 2002 – REVISED AUGUST 2002
APPLICATION INFORMATION
Table 7. Channel 01 Data Group – Non–Interrupt Capable Inputs
BIT
NUMBER
FUNCTION
0
Slot A M66EN
1
Slot A PCI–XCAP1
2
Slot A PCI–XCAP2
3
Slot A Aux Power Fault state (AuxfltA)
4
Reserved
5
Reserved
6
Reserved
7
Reserved
8
Slot B M66EN
9
Slot B PCI–XCAP1
10
Slot B PCI–XCAP2
11
Slot B Aux Power Fault state (AuxfltB)
12
Reserved
13
Reserved
14
Reserved
15
Reserved
16…47
SIDI pin data for slots C, D, E and F follows
Table 8. Channel 10 Data Group – Diagnostic Channel #1
BIT
NUMBER
FUNCTION
0
Device Present
1 = Power controller is present
0 = Power controller is not installed
1
Slot A Pwren state
2
Slot A CLKEN state (0 = clock enabled)
3
Slot A BUSEN state (0 = bus enabled)
4
Slot A PCIRST state (0 = reset asserted)
5
Slot A PWRLED state (1 = power LED on)
6
Slot A ATTLED state (1 = attention LED on)
7
Reserved
8
Device Present
1 = Power controller is present
0 = Power controller is not installed
9
Slot B Pwren state
10
Slot B CLKEN state
11
Slot B BUSEN state
12
Slot B PCIRST state
13
Slot B PWRLED state
14
Slot B ATTLED state
15
Reserved
16…47
SIDI pin data for slots C, D, E and F follows
www.ti.com
17
SLUS528A – MARCH 2002 – REVISED AUGUST 2002
Table 9. Channel 11 Data Group – Diagnostic Channel #2
BIT
NUMBER
FUNCTION
0
Slot A latched Mode 0 bit state. This bit is latched at PGOOD
1
Slot A latched Mode 1 bit state. This bit is latched at PGOOD.
2
Must be set to 1.
3
Reserved
4
Reserved
5
Reserved
6
Reserved
7
Reserved
8
Slot B latched Mode 0 bit state. This bit is latched at PGOOD.
9
Slot B latched Mode 1 bit state. This bit is latched at PGOOD.
10
Must be set to 1.
11
Reserved
12
Reserved
13
Reserved
14
Reserved
15
Reserved
16…47
SIDI pin data for slots C, D, E and F follows
Figure 3. illustrates the input scan chain timing for operational mode.
Channel 00, IRQ Input Status
SIC
C0
C1
RD
SIL#
U2 SIDO
SW–A
BTN–A
FLT–A
P2–A
P1–A
SW–B
BTN–B
FLT–B
P2–B
P1–B
SW–C
BTN–C
U3 SIDO
SW–C
BTN–C
FLT–C
P2–C
P1–C
SW–D
BTN–D
FLT–D
P2–D
P1–D
SW–E
BTN–E
U4 SIDO
SW–E
FLT–E
FLT–E
P2–E
P1–E
SW–F
FLT–F
FLT–F
P2–F
P1–F
SIDIx
SIDIy
1
2
3
4
si_bit
0
5
6
7
8
9
10
11
12
13
14
15
16
17
Channel 01, Non–IRQ Input Status
SIC
C0
C1
RD
SIL#
U2 SIDO
M66–A
PX1–A
PX2–A
AFLT–A
M66–B
PX1–B
PX2–B AFLT–B
M66–C
PX1–C
U3 SIDO
M66–C
PX1–C
PX2–C
AFLT–C
M66–D
PX1–D
PX2–D
AFLT–D
M66–E
PX1–E
U4 SIDO
M66–E
PX1–E
PX2–E
AFLT–E
M66–F
PX1–F
PX2–F
AFLT–F
SIDIx
SIDIy
1
2
3
8
9
16
17
1
PWR–A
CLK–A
BUS–A
RST#–A PLED–A ALED–A
1
PWR–B
CLK–B
BUS–B
RST#–B PLED–B ALED–B
U3 SIDO
1
PWR–C
CLK–C
BUS–C
RST#–C PLED–C ALED–C
1
PWR–D
CLK–D
BUS–D
U4 SIDO
1
PWR–E
CLK–E
BUS–E
RST#–E PLED–E ALED–E
1
PWR–F
CLK–F
BUS–F
1
2
3
8
9
si_bit
0
4
5
6
7
10
11
12
13
14
15
Channel 10, Diagnostic Data
SIC
C0
C1
RD
SIL#
U2 SIDO
si_bit
0
4
5
6
7
Figure 3. Serial Input Data Timing
18
www.ti.com
10
11
1
PWR–C
RST#–D PLED–D ALED–D
1
PWR–D
RST#–F PLED–F ALED–F
SIDIx
SIDIy
16
17
12
11
13
15
SLUS528A – MARCH 2002 – REVISED AUGUST 2002
APPLICATION INFORMATION
Similar to input data, serial output data has been ordered to facilitate cascading TPS2340A devices. Assuming
a six-slot implementation, as input data arrives in the order of slot A first, followed by data for slots B through
F, output data is delivered in reverse order, slot F data first, then data for slots E through A. For a PCI hot-plug
controller that supports 6 slots, 48 bits (8 per slot) are shifted out by the controller any time a slot control state
needs to be changed. At the conclusion of a shift-out process, output data for slots A and B is contained in the
device (electrically) closest to the PCI hot-plug controller. Output data for each slot is delivered in the bit order
described in Table 10.
Table 10. Operational Mode Output Data Bit Order
BIT
NUMBER
FUNCTION
0
Slot F Pwren state (1 = turn on power)
1
Slot F CLKEN state (1 = enable the clock)
2
Slot F BUSEN state (1 = enable the bus)
3
Slot F PCIRST state (0 = assert PCIRST)
4
Slot F PWRLED state (1 = turn on power LED)
5
Slot F ATTLED state (1 = turn on attention LED)
6
Reserved
7
Reserved
8
Slot E Pwren state
9
Slot E CLKEN state
10
Slot E BUSEN state
11
Slot E PCIRST state
12
Slot E PWRLED state
13
Slot E ATTLED state
14
Reserved
15
Reserved
16…47
SODO pin data for slots D, C, B and A follows
The output data for the six slots is shifted out using the SOC clock. After the appropriate data pattern is
established in the shift registers, this data is parallel clocked into registers via latch clocks. These registers drive
the output pins and controls. The SOLC pin serves as the latch clock for the Pwrenx, BUSENx, CLKENx,
PWRLEDx, and ATTLEDx outputs.
The SORLC pin serves as the latch clock for the RESETx pins. Two latch clocks are used so that the PCI bus
timing requirements between REQ64, TRDY, DEVSEL, and STOP and the slot’s RST signal can be more easily
controlled by the hot-plug controller.
If a fault occurs, as indicated by the assertion of the Faultx signal (where Faultx = Pwrfltx and Auxfltx), the
RESETx pin asynchronously asserts and the CLKENx and BUSENx pins are asynchronously deasserted.
www.ti.com
19
SLUS528A – MARCH 2002 – REVISED AUGUST 2002
APPLICATION INFORMATION
SOC
SOLC
SODI
PWREN CLKEN BUSEN RESET
PLED
ALED
Rsvd
Rsvd
PWREN CLKEN
ALED
Rsvd
Rsvd
PWREN CLKEN BUSEN RESET
Slot F
so_bit
0
1
2
3
PLED
ALED
Rsvd
Rsvd
45
46
47
Slot A
4
5
6
7
8
9
37
38
39
40
41
42
43
44
SOC
tSOC/2
SODI
tSU
tH
SOLC
PWRLEDx
ATTLEDx
BUSENx
CLKENx
tCO
SORLC
RESETx
tCO
UDG–01013
Figure 4. Serial Output Data Timing
20
www.ti.com
SLUS528A – MARCH 2002 – REVISED AUGUST 2002
APPLICATION INFORMATION
package information
The TPS2340A dissipates very little heat under normal operating conditions. However, when the TPS2340A
is used with a load that exceeds PCI specifications either due to a fault or a specification violation, power
dissipation increases as the square of load current. To allow reliable operation with high power dissipation, the
TPS2340A is packaged in a PowerPADt molded quad flat pack with heat-conducting tab on the underside. This
package offers thermal resistance from junction to case of approximately 8°C/W. In a typical layout, thermal
resistance from junction to ambient is approximately 35°C/W.
For optimum heat conduction and system reliability, the heat-conducting tab should be soldered directly to a
10-mm square copper area on the circuit board tied to M12VIN voltage potential. To increase heat conduction,
add plated vias to the copper area directly under the part and connect these vias to copper planes around 100%
of their perimeter. These vias conduct heat away from the top layer of the circuit board and into other layers and
should not use thermal reliefs (also known as thermals or webs). To prevent solder wicking into the vias, the
vias should either be drilled to a size small enough to allow complete filling of the vias during hole plating or
should be covered by solder mask on the back of the circuit board.
The TPS2340A TQFP–80 package conforms to JEDEC MS–026. For more information on the PowerPAD
package, consult TI PowerPAD Technical Brief (SLMA002).
device testability
Table 11. Test Mode Configuration
PGOOD
↑
1
↑
↑
↑
TEST
0
0
1
1
1
SODO/MODE1
MODE1
SODO
0
0
1
SIDO/MODE0
MODE0
SIDO
0
1
X
OPERATING MODE
Normal operation mode, latch MODE inputs
Normal operation mode, drive SODO and SIDO
NAND tree test mode
Tri–state test mode (all pins tri-stated)
Reserved
Normal operation, but Pwrenx driven on PWRLEDx, Faultx
1
1
SODO
SIDO
driven on ATTLEDx.
NOTE: X = Don’t care, x = slot A or B; shaded cells signify test modes.
When TEST is asserted after PGOOD is asserted, the device enters a run-time test mode. When this test mode
is enabled, the slot-specific PWRLEDx output asserts when the slot’s internal Pwrenx signal is asserted.
Similarly, the ATTLEDx output asserts when the corresponding ANDed slot Faultx signal is asserted.
www.ti.com
21
SLUS528A – MARCH 2002 – REVISED AUGUST 2002
APPLICATION INFORMATION
NAND tree test
All bi-directional pins are tri-stated for input mode during the NAND Tree test except SIDO. All inputs except
TEST should be forced low then forced high, one signal at a time, in the order listed below. The TEST pin is the
last signal in the chain and is forced high then low. The NAND result is driven on the SIDO output pin as shown
in the timing diagram in Figure 5.
Table 12. NAND Tree Order
NAND TREE ORDER
22
PIN NO.
1
SIDI
20
2
SODO
19
3
SWA
46
4
SWB
14
5
PRSNT1A
37
6
PRSNT1B
24
7
PRSNT2A
36
8
PRSNT2B
25
9
BUTTONA
45
10
BUTTONB
15
11
M66ENA
34
12
M66ENB
27
13
PCI–XCAPA
50
14
PCI–XCAPB
11
15
SODI
42
16
SOC
17
17
SOR
40
18
SORR
21
19
SOLC
39
20
SORLC
22
21
BUSENA
32
22
BUSENB
29
23
CLKENA
33
24
CLKENB
28
25
RESETA
35
26
RESETB
26
27
PWRLEDA
48
28
PWRLEDB
12
29
ATTLEDA
47
30
ATTLEDB
13
31
SIL
16
32
SIC
44
33
TEST
23
www.ti.com
mode1_reg = 0
nand_test = 0
highz = 0
TEST = 0
PGOOD = 1
SIDO = 0
SIDI = z
SODO = 0
SWA = z
SWB = z
PRSNT1A = z
PRSNT1B = z
PRSNT2A = z
PRSNT2B = z
BUTTONA = z
BUTTONB = z
M66ENA = z
M66ENB = z
PCIXCAP1A = z
PCIXCAP1B = z
SODI = z
SOC = x
SOLC = x
SORLC = x
BUSENA = 1
BUSENB = 1
CLKENA = 1
CLKENB = 1
RESETA = 0
PWRLEDA = 1
PWRLEDB = 1
23
RESETB = 0
SLUS528A – MARCH 2002 – REVISED AUGUST 2002
SOR = x
SORR = x
APPLICATION INFORMATION
Figure 5. NAND Tree Representative Waveforms
www.ti.com
The TPS2340A is initialized by a low-to-high transition of the PGOOD pin. The following table indicates the
electrical power-on state of each slot’s output pins.
mode0_reg = 0
SLUS528A – MARCH 2002 – REVISED AUGUST 2002
Table 13. NAND Tree Order
OUTPUT PIN
POWER-ON
STATE
PWRLEDx
1
ATTLEDx
1
BUSENx
1
CLKENx
1
RESETx
0
The TPS2340A supports tri-state and NAND–tree test functions.
package dimensions
This package has an exposed copper heat-conducting pad on the bottom of the mold. This pad is approximately
6 mm2, with maximum dimensions 6.07 mm × 6.07 mm
COPPER
HEAT
CONDUCTING
SURFACE
6.07 mm
9.5 mm
Figure 6. PowerPAD Package Details Bottom View
24
www.ti.com
SLUS528A – MARCH 2002 – REVISED AUGUST 2002
PFP (S-PQFP-G80)
PowerPAD PLASTIC QUAD FLATPACK
0,27
0,17
0,50
60
0,08 M
41
40
61
Thermal Pad
(see Note D)
80
21
1
0,13 NOM
20
Gage Plane
9,50 TYP
12,20
SQ
11,80
0,25
0,15
0,05
14,20
SQ
13,80
0°–ā7°
0,75
0,45
1,05
0,95
Seating Plane
0,08
1,20 MAX
4146925/A 01/98
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MS-026
www.ti.com
25
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third–party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated