SLUS564B − JULY 2003 − REVISED DECEMBER 2003
FEATURES
D Wide Input Voltage Range: 4.5-V to 28-V
D Selectable Dual and DDR Modes
D Selectable Fixed Frequency Voltage Mode
D Integrated Selectable Output Discharge
D Advanced Power Good Logic Monitors both
D
D
D
D
D
D
D
D
D
Channels
Selectable Autoskip Mode
Integrated Boot Strap Diodes
180° Phase Shift Between Channels
Integrated 5-V, 60-mA Regulator
Input Feedforward Control
1% Internal 0.85-V Reference
RDS(on) Overcurrent Detection (4200 ppm/°C)
Integrated OVP, UVP and Power Good Timers
30-pin TSSOP Package
DESCRIPTION
The TPS51020 is a multi-function dualsynchronous step-down controller for notebook
system power. The part is specifically designed
for high performance, high efficiency applications
where the loss associated with a current sense
resistor is unacceptable. The TPS51020 utilizes
feed forward voltage mode control to attain high
efficiency without sacrificing line response.
Efficiency at light load conditions can be
maintained high as well by incorporating autoskip
operation. A selectable, Suspend to RAM (STR)
supported, DDR option provides a one chip
solution for all switching applications from
5-V/3.3-V supply to a complete DDR termination
solution.
ORDERING INFORMATION
TA
PLASTIC TSSOP (DBT)
−40°C to 85°C
APPLICATIONS
D Notebook Computers System Bus and I/O
D DDR I or DDR II Termination
TPS51020DBT
TPS51020DBTR (T&R)
VIN
SIMPLIFIED
APPLICATION
DIAGRAM
VO1
1
INV1
2 COMP1
TPS51020
3 SSTRT1
4 SKIP
VIN
VO1
5
VO1_VDDQ
6 DDR
7 GND
8 REF_X
9 ENBL1
10 ENBL2
VO2
VREG5
VO2
11 VO2
VBST1 30
29
LL1
OUT1_D
OUTGND1
28
27
26
TRIP1
25
VIN
24
TRIP2
VREG5
REG5_IN
OUTGND2
12 PGOOD
OUT2_D
13 SSTRT2
LL2
14 COMP2
OUT2_U
15 INV2
VO1
OUT1_U
VBST2
VIN
23
22
21
VREG5
EXT_5V
20
19
18
17
VO2
16
UDG−03144
VIN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
!"#$%&" ' ()##*& %' "! +),-(%&" .%&*/
#".)(&' ("!"#$ &" '+*(!(%&"' +*# &0* &*#$' "! *1%' '&#)$*&'
'&%.%#. 2%##%&3/ #".)(&" +#"(*''4 ."*' "& *(*''%#-3 (-).*
&*'&4 "! %-- +%#%$*&*#'/
Copyright 2003, Texas Instruments Incorporated
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1
SLUS564B − JULY 2003 − REVISED DECEMBER 2003
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range unless otherwise noted. All voltage values are with respect to the network ground terminal unless
otherwise noted. (1)
TPS51020
Input voltage range
Ouput voltage range
VBST1, VBST2
−0.3 to 35
VBST1, VBST2 (with respect to LL )
−0.3 to 7
VIN, TRIP1, TRIP2, ENBL1, ENBL2, DDR
−0.3 to 30
SKIP, INV1, INV2
−0.3 to 7
OUT1_U, OUT2_U
−1 to 35
OUT1_U, OUT2_U (with respect to LL )
−0.3 to 7
LL1, LL2
−1 to 30
REF_X
−0.3 to 15
PGOOD, VO1_VDDQ, VO2, OUT1_D, OUT2_D, COMP1, COMP2, VREG5,
SSTRT1, SSTRT2
−0.3 to 7
OUTGND1, OUTGND2
Output current range
UNIT
V
−0.3 to 0.3
VREG5
70
REF_X
7
Operating free-air temperature range, TA
−40 to 85
Storage temperature range, Tstg
−55 to 150
Junction temperature range, TJ
−40 to 125
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
mA
°C
300
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
Supply voltage, VIN
4.5
28
Supply voltage, VBST1, VBST2
4.5
33
ENBL1, ENBL2, DDR, TRIP1, TRIP2
−0.1
28
OUT1_U, OUT2_U
−0.8
33
OUT1_U, OUT2_U (with respect to LL )
−0.1
5.5
LL1, LL2
−0.8
28
REF_X
−0.1
12
SSTRT1, SSTRT2, COMP1, COMP2
−0.1
5.5
SKIP, INV1, INV2
−0.1
5.5
PGOOD VO1_VDDQ, VO2
−0.1
5.5
OUT1_D, OUT2_D, VREG5
−0.1
5.5
I/O Voltage
Source current
VREG5
60
REF_X
5
UNIT
V
mA
Operating free-air temperature, TA
−40
85
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under ”recommended operating conditions” is
not implied. Exposure to Absolute Maximum Rated conditions for extended periods may affect device reliability
DISSIPATION RATING TABLE
2
PACKAGE
TA < 25°C
POWER RATING
DERATING
FACTOR ABOVE TA = 25°C
TA = 85°C
POWER RATING
30-pin DBT
874 mW
7.0 mW/°C
454 mW
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SLUS564B − JULY 2003 − REVISED DECEMBER 2003
TSSOP (0.5 mm)
DBT PACKAGE
(TOP VIEW)
INV1
COMP1
SSTRT1
SKIP
VO1_VDDQ
DDR
GND
REF_X
ENBL1
ENBL2
VO2
PGOOD
SSTRT2
COMP2
INV2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VBST1
OUT1_U
LL1
OUT1_D
OUTGND1
TRIP1
VIN
TRIP2
VREG5
REG5_IN
OUTGND2
OUT2_D
LL2
OUT2_U
VBST2
ELECTRICAL CHARACTERISTICS
TA = −40°C to 85°C, 4.5 V < VIN < 20 V, CVIN = 0.1 µF, CVREG5 = 2.2 µF, CREF_X = 0.01 µF, PGOOD = 0.2 V, ENBLx = DDR = VIN,
INVx = COMPx, RSSTRTx = OPEN, TRIP1 = TRIP2 = VIN, LLx = GND, VBSTx = LLx+5, C(OUTx_U, OUTx_D)=1 nF, REG5_IN = 0V, GND =
OUTGNDx = 0 V, VO1_VDDQ = VO2 = 0 V (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.4
2.2
350
550
0.05
1.00
UNIT
INPUT CURRENTS
IVIN
VIN supply current
REG5V_IN = OPEN,
OSC = OFF
TRIPx = VIN,
IVIN(STBY)
VIN standby current
ENBLx = 0 V,
REG5V_IN = OPEN,
DDR = VIN,
OSC = OFF
IVIN(SHDN)
VIN shutdown current
ENBLx = DDR = 0 V,
REG5V_IN = OPEN
IVIN(REG5)
VIN supply current, REG5_IN as 5-V input
current
REG5V_IN = 5 V,
OSC = OFF
200
500
REG5_IN input supply current
REG5V_IN = 5 V,
OSC = OFF
1.0
1.7
VBST supply current
IREG5
IVBSTx
ENBLx = DDR = VIN
0.05
1.00
IVBSTx
VBST shutdown current
VREG5 INTERNAL REGULATOR
ENBLx = DDR = 0 V
0.05
1.00
VVREG5
VLD5
VREG5 voltage
IOUT = 0 A
0 mA ≤ IOUT ≤ 50 mA,
5.0
5.2
VLN5
VTHL
Line regulation
VHYS(UV)
VTH(SW)
UVLO hysteresis
VHYS(SW)
Switchover hysteresis
Load regulation
UVLO threshold voltage
Switchover voltage
IOUT = 20 mA,
High to low
REG_IN voltage
4.8
VIN = 12 V
7 V≤VIN ≤ 28 V
µA
mA
µA
A
V
0.6% 2.5%
0.4% 2.0%
3.45
3.65
3.85
V
100
200
300
mV
4.2
4.5
50
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mA
4.8
V
250
mV
3
SLUS564B − JULY 2003 − REVISED DECEMBER 2003
ELECTRICAL CHARACTERISTICS (continued)
TA = −40°C to 85°C, 4.5 V < VIN < 20 V, CVIN = 0.1 µF, CVREG5 = 2.2 µF, CREF_X = 0.01 µF, PGOOD = 0.2 V, ENBLx = DDR = VIN,
INVx = COMPx, RSSTRTx = OPEN, TRIP1 = TRIP2 = VIN, LLx = GND, VBSTx = LLx+5, C(OUTx_U, OUTx_D)=1 nF, REG5_IN = 0V, GND =
OUTGNDx = 0 V, VO1_VDDQ = VO2 = 0 V (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
REF_X REFERENCE VOLTAGE
VREF10
VLD10
10-V reference voltage
VLN10
Line regulation
VREFVTT
VTT reference voltage
Load regulation
VREFVTT
VTT reference load regulation
POWERGOOD COMPARATORS
VTHDUAL(PG) PGOOD threshold (dual mode)
VTHDDR(PG) PGOOD threshold (DDR)
TPG(del)
PGOOD delay time
VIN = 14 V,
0 mA ≤ IOUT ≤ 2 mA,
IOUT = 0 A
VIN = 18 V
8.5
10.0
11.0
-12%
-20%
IOUT = 100 µA,
14 V≤VIN ≤28 V
DDR = 0 V wrt VO1_VDDQ input divided by 2
VVO1 = 2.5 V
V
5%
1.5%
0 mA ≤ IO ≤ 3 mA
0.75%
Undervoltage PGOOD
765
786
808
Overvoltage PGOOD
892
920
945
Undervoltage PGOOD,
VO1_VDDQ = 2.5 V
1.12
1.14
1.16
Overvoltage PGOOD,
VO1_VDDQ = 2.5 V
1.28
1.31
1.33
mV
V
INVx > undervoltage PGOOD,
Delay time from SSTRTx > 1.5 V to PGOOD
going high
2048
clks
DIGITAL CONTROL INPUTS
VIH
VIL
High-level input voltage, logic
DDR, ENBL1, ENBL2, SKIP
Low-level input voltage, logic
DDR, ENBL1, ENBL2, SKIP
2.2
0.3
IINLEAK
Logic input leakage current
VO1_VDDQ and VO2
DDR, ENBL1, ENBL2, SKIP= 5 V
RVOUT
VVOUTOK
VOx sink impedance
VOx low restart voltage
VVOUTx = 0.5 V, fault engaged
Fault condition removed, restart
VVO2LEAK
RVOUT
VOx input leakage current
DDR= VIN,
VO1_VDDQ input impedance
DDR= 0
0.25
V
|1.0|
µA
6
10
Ω
0.32
0.40
V
|1.0|
µA
VOx = 5 V
1.5
MΩ
UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVPDUAL
VOVPDDR
TOVP(del)
VUVPDUAL
VUVPDDR
TUVP(del)
OVP trip output threshold (dual)
Sensed at INVx
945
970
1010
OVP trip output threshold (DDR)
OVP propagation delay time(1)
VO1_VDDQ = 2.5 V
1.31
1.36
1.41
UVP trip output threshold (dual)
Sensed at INVx
510
553
595
UVP trip output threshold (DDR)
VO1_VDDQ = 2.5 V
750
813
875
V
µs
20
UVP propagation delay time
mV
4096
mV
clks
OVERCURRENT and INPUT VOLTAGE UVLO PROTECTION
ITRIPSNK
ITRIPSRC
TRIPx sink current
TRIPx source current
VTRIPx = VIN − 100 mV,
VTRIPx = 100 mV,
TCITRIP
TRIP current temperature coeficient(1)
TA = 25°C
VOCPHI
VOCPLO
High-level OCP comparator offset voltage(1)
Low-level OCP comparator offset voltage(1)
VVINUVLO
VVINHYS
VIN UVLO trip threshold
4
REF5V_IN = 4.8 V
VIN UVLO trip hysteresis
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TA = 25°C
TA = 25°C
11
13
15
10
13
16
µA
A
ppm/
°C
4200
0
|3.0|
0
|5.0|
mV
3.7
3.9
4.1
V
100
200
300
mV
SLUS564B − JULY 2003 − REVISED DECEMBER 2003
ELECTRICAL CHARACTERISTICS (continued)
TA = −40°C to 85°C, 4.5 V < VIN < 20 V, CVIN = 0.1 µF, CVREG5 = 2.2 µF, CREF_X = 0.01 µF, PGOOD = 0.2 V, ENBLx = DDR = VIN,
INVx = COMPx, RSSTRTx = OPEN, TRIP1 = TRIP2 = VIN, LLx = GND, VBSTx = LLx+5, C(OUTx_U, OUTx_D)=1 nF, REG5_IN = 0V, GND =
OUTGNDx = 0 V, VO1_VDDQ = VO2 = 0 V (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
0.84
0.85
0.86
V
0
|5.0|
mV
2
3
0.85-V REFERENCE CONTROL LOOP
VREFCH1
Error amplifier reference, channel 1 initial
accuracy
Measure COMP1,
TA = 25°C
COMP1= INV1,
VREFTC1
Error amplifier reference, channel 1
change with accuracy
0.5%
VREFLN1
Error amplifier reference, channel 1
change with line
0.1%
VCHMM
Channel 2 to channel 1 voltage mismatch
CONTROL LOOP: SKIP HYSTERSTIC COMPARATOR AND ZERO CURRENT COMPARATOR
VLLHYS
Skip hysteresis comparator hysteresis(1)
1
VLLOFF
VZOFF
Lload hysteresis comparator offset(1)
Zero current comparator offset(1)
THLTOLL
THLTOHL
PWM skip delay time
8
Skip to PWM delay time
1
0
1
10
18
mV
clks
CONTROL LOOP ERROR AMPLIFIER
IEASRC
IEASNK
COMPx source current
0.2
0.9
COMPx sink current
0.2
0.7
FUGB
AOL
Unity gain bandwidth(1)
Open loop gain(1)
CMRCOMP
IINVLEAK
COMPx voltage range(1)(6)
0.4
PHCH
MHz
80
dB
VREG5−3
|0.5|
Maximum duty cycle
Channel to channel phase difference(5)
OUTX_U minimum pulse width(1)
fOSC = 360 kHz
fOSC = 450 kHz(2)
PWM phase reversal only
86%
88%
84%
85%
80%
82%
TMIN
TIMERS: INTERNAL OSCILLATOR(4)
fOSC(hi)
fOSC(lo)
2.5
INVx input current
CONTROL LOOP: DUTY CYCLE, VOLTAGE RAMP, CHANNEL PHASE AND PWM DELAY PATH
fOSC = 270 kHz(3)
DCMAX
mA
Fast oscillator frequency initial accuracy(2)
RSSTRTx = OPEN
Slow oscillator frequency initial accuracy
RSSTRTx = 1MΩ or VSSTRT = 3 V
fOSC(tc)
Oscillator frequency over line and temperature Trimmed for 360 kHz
(1) Ensured by design. Not production tested.
(2) Maximum 450-kHz frequency can be achieved when both channels are enabled.
(3) 270 kHz is the default frequency during start-up for both channels.
(4) See Table 1.
(5) See PWM detailed description
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V
µA
180
°
100
ns
450
270
306
360
kHz
414
5
SLUS564B − JULY 2003 − REVISED DECEMBER 2003
ELECTRICAL CHARACTERISTICS (continued)
TA = −40°C to 85°C, 4.5 V < VIN < 20 V, CVIN = 0.1 µF, CVREG5 = 2.2 µF, CREF_X = 0.01 µF, PGOOD = 0.2 V, ENBLx = DDR = VIN,
INVx = COMPx, RSSTRTx = OPEN, TRIP1 = TRIP2 = VIN, LLx = GND, VBSTx = LLX+5, C(OUTx_U, OUTx_D)=1 nF, REG5_IN = 0V, GND =
OUTGNDx = 0 V, VO1_VDDQ = VO2 = 0 V (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.8
2.3
2.9
UNIT
TIMERS: SOFT-START RAMP GENERATOR
SSTRTx charge current
VREFTRK
VSSOK
SSTRTx at SMPS regulation point voltage(7)
1.00
1.22
1.45
SSTRTx OK to restart voltage
SSTRTx finished voltage(8)
0.23
0.29
0.35
1.4
1.5
1.6
SSTRTx frequency select voltage(9)
3.35
3.60
3.80
0.80
0.85
V
0.1
0.5
µA
3
10
VSSFIN
VSSCLP
VSSTRTx = 1 V
VSSTRTx = 0.5 V
µA
ISSQ
ISSDQ
SSTRTx discharge current
0.1
mA
V
OUTPUTS: INTERNAL BST DIODE
VFBST
(VVREF5− VVBSTx),VVREF5 = 5 V, IF = 10 mA
TA = 25°C
Forward voltage
IRBST
Reverse current
OUTPUTS: N-CHANNEL MOSFET GATE DRIVERS
VRBST= 30 V
RUSRC
OUTx_U source impedance
RDSRC
OUTx_D source impedance
3
10
RUSNK
OUTx_U sink impedance
2.5
5.0
RDSNK
OUTx_D sink impedance
2.5
5.0
TDEAD
Gate non-overlap dead time
(1) Ensured by design. Not production tested.
(2) Maximum 450-kHz frequency can be achieved only when both channels are enabled.
(3) 270 kHz is the default frequency during start-up for both channels.
(4) See Table 1.
(5) See PWM detailed description
(6) Feedforward Gain can be approximated as follows:
VRAMP= K1×VIN+B1, VOFFSET=K2×VIN×+B2 where K1=0.017, K2=0.01, B1=0.35 V, B2=0.4 V.
At the running duty cycle, the VCOMP should be approximately: V COMP + V OUT
B1 Ǔ ) (K2
ǒK1 ) VIN
100
VIN ) B2)
(7) See waveform point A in Figure 1
(8) See waveform point B in Figure 1
(9) See waveform point C in Figure 1
Table 1. Frequency Selection
SSTRT1
SSTRT2
CSSTRT only
CSSTRT only
1 MΩ || CSSTRT to GND
CSSTRT only
1 MΩ || CSSTRT to GND
CSSTRT only
FREQUENCY (kHz)
450(10)
360
360
1 MΩ || CSSTRT to GND
1 MΩ || CSSTRT to GND
270
(10)Although selection is made by placing a 1M resistor in parallel with the SSTRTx timing
capacitor, the softstart time to 0.85V is altered by about only 20%.
6
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Ω
ns
SLUS564B − JULY 2003 − REVISED DECEMBER 2003
ENBL1
ENBL1
ENBL2
ENBL2
fSW − Switching Frequency − kHz
470
fSW − Switching Frequency − kHz
470
360
270
360
270
5.0
3.6
C
1.5
1.2
A
B
0
SSTRT2
5.0
3.6
C
1.5
1.2
0
A
B
t0 t1
t2
t3
360
270
270
5.0
SSTRT1
t4
VSSTRT − Soft-Start Voltage − V
VSSTRT − Soft-Start Voltage − V
270 360
t5
SSTRT1
3.6
1.5
1.2
0
SSTRT2
5.0
3.6
1.5
1.2
0
t0 t1
t − Time
RSSTRT1 = RSSTRT2 = OPEN = 450 kHz
t2
t3
t4
t5
t − Time
RSSTRT1 = 1 MΩ, RSSTRT2 = OPEN = 360 kHz
Figure 1
Figure 2
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
COMP1
2
O
COMP2
14
O
DESCRIPTION
Error amplifier output. Connect feedback network to this pin and INVx for compensation of control loop.
DDR selection pin. If this pin is grounded, the device runs in DDR Mode. The error amplifier reference for VO2
is (VO1_VDDQ)/2, the REF_X output voltage becomes (VO1_VDDQ)/2 and skip mode is disabled for VO2,
Also, VREG5 is turned off when both ENBLx are at low in this mode. If this pin is at 2.2-V or higher, the device
runs in ordinary dual SMPS mode (dual mode), then the error amplifier reference for VO2 is connected to internal 0.85-V reference, the REF_X output voltage becomes 10 V, VREG5 is kept on regardless of ENBLx status.
CAUTION: Do not toggle DDR while ENBL1 or ENBL2 are high. (See Table 2)
DDR
6
I
ENBL1
9
I
ENBL2
10
I
TTL Enable Input. If ENBLx is greater than 2.2 V, then the VREG5 is enabled (DDR mode) and the SMPS of
that channel attempts to turn on. If both ENBL1 and ENBL2 are low then the 10-V (or (VO1_VDDQ)/2 output)
voltage as well as the oscillator are turned off. (See Table 2)
GND
7
O
Signal ground pin.
INV1
1
I
INV2
15
I
LL1
28
I/O
LL2
18
I/O
OUT1_D
27
O
OUT2_D
19
O
OUT1_U
29
O
OUT2_U
17
O
OUTGND1
26
O
OUTGND2
20
O
Error amplifier inverting input. Also input for skip comparator, and OVP/UVP comparators.
Switch-node connection for high-side driver and overcurrent protection circuitry.
Synchronous N-channel MOSFET driver output.
High-side N-channel MOSFET driver output.
Ground return for OUTx_D.
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7
SLUS564B − JULY 2003 − REVISED DECEMBER 2003
TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
PGOOD
NO.
12
I/O
DESCRIPTION
O
Power good output. This is an open drain pull-down pin for power good. It remains low during soft-start until
both outputs become within ±7.5%. If INV1 or INV2 is out of regulation, or VREG5V goes under UVLO then this
pin goes low. The internal delay timer counts 2048 clks at low to high (by design, no delay for high to low). If
ENBLx is low, and the power good output is high, then the power good signal for that channel is ignored.
REF_X
8
O
10-V N-channel MOSFET bias or (VO1_VDDQ)/2 reference output. If dual mode is selected (DDR > 2.2 V)
then this pin provides a low 10-V current (< 2 mA) bias, dropped down from VIN, for the SO – S5 switched
N-channel MOSFETs. If DDR mode is selected (DDR = GND) then this pin becomes (VO1_VDDQ)/2 capable
of 3 mA source current. This bias/reference is shut off when ENBL1 and ENBL2 are both low. (See Table 2)
REG5_IN
21
I
External 5V regulator Input. If this pin is above 4.7 V, then the 5 V circuit bias switches from the VREF5 to the
supply presented to REG5_IN.
SSTRT1
3
I
SSTRT2
13
I
SKIP
4
I
Skip mode selection pin. Ground for automatic control between PWM mode in heavy load and hysteretic operation in light load. Tie high for PWM only operation for the entire load condition. If DDR is grounded, then skip
mode is disabled for Channel 2.
TRIP1
25
I
Channel 1 overcurrent trip point voltage input. Connect a resistor between TRIP1 and the high-side N-channel
MOSFET input conversion voltage for high-side N-channel MOSFET UVP current limit shut down. Connect
resistor between TRIP1 and GND for low-side N-channel MOSFET overcurrent latch shutdown.
Channel 2 overcurrent trip point voltage input. Connect a resistor between TRIP2 and the high-side N-channel
MOSFET input conversion voltage for high-side N-channel MOSFET UVP current limit shut down with a 180°
channel phase shift. Connect resistor between TRIP2 and GND for low-side N-channel MOSFET over current
latch shut-down. The oscillator voltage ramp adjustment (the feed-forward feature) for channel 2 is disabled
when this pin is tied to ground via a resistor.
Soft-start/frequency select input. Connect a capacitor between SSTRTx and ground for adjusting the softstart
time. A constant current fed to this capacitor ramps the reference during startup. Frequency selection is described in Table 1. The soft-start capacitor is discharged upon UVLO/OVP/UVP, or when ENBLx is asserted
low.
TRIP2
23
I
VBST1
30
I
VBST2
16
I
VO1_VDDQ
5
I
11
I
VREG5
22
O
Internal, 60-mA, 5-V regulator output. DDR, ENBL1 or ENBL2 high ( > 2.2V) turns on the 5 V regulator.
VIN
24
I
High-voltage input. Typically the battery voltage. This pin serves as inputs for the VREF5 regulator, the REF_X
regulator and positive input for overcurrent comparators. Precaution should be taken for tracing between this
pin and the high-side N-channel MOSFET drain where positive node of TRIPx resistors are located.
VO2
Supply Input for high-side N-channel FET driver. Typically connected via charge pump from LLx.
Output discharge pin. Connect this pin to the SMPS output when discharge is required for power down. The
output is discharged to at least 0.3 V before the channel can start-up again. Ground this pin when discharge is
not required. When grounded, corresponding channel disables the low side N-channel MOSFET during startup until the high side N-channel FET attempts to turn on. If DDR is low, then the VO1_VDDQ pin must be connected to the VDDQ output since this pin works as the VDDQ feedback to generate the VTT reference voltage
and VO2 should be connected to GND since VTT must remain in a high-impedance state during S3 mode.
Table 2. Reference Regulator Control
8
MODE
DDR
ENBL1
ENBL2
VREF5
REF_X
OSC
DDR
LOW
DDR
LOW
LOW
LOW
LOW
HIGH
OFF
OFF
OFF
ON
OFF
ON
DDR
LOW
HIGH
LOW
ON
VO1_DDR
2
ON
DDR
LOW
HIGH
HIGH
ON
ON
HIGH
LOW
LOW
ON
VO1_DDR
2
OFF
DUAL
OFF
DUAL
HIGH
LOW
HIGH
ON
10 V
ON
DUAL
HIGH
HIGH
LOW
ON
10 V
ON
DUAL
HIGH
HIGH
HIGH
ON
10 V
ON
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SLUS564B − JULY 2003 − REVISED DECEMBER 2003
FUNCTIONAL BLOCK DIAGRAM
Shows Channel 1 (VO1_VDDQ) and the supporting circuitry.
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9
SLUS564B − JULY 2003 − REVISED DECEMBER 2003
APPLICATION INFORMATION
PWM OPERATION
The PWM control block utilizes a fixed-frequency, feed-forward, voltage-mode control scheme with a
wide-bandwidth, low-impedance output error amplifier as the voltage servo control block. This scheme allows
the highest efficiency down conversion while maintaining excellent line regulation and fast transient response.
Loop compensation is programmed by connecting a filter network between the COMPx pin and the INVx pin.
The wide bandwidth error amplifier handles conventional Type II compensation or Type III compensation when
using ceramic capacitors for the converter output. For channel one, the reference signal for the control loop is
always a precision 0.85-V internal reference, while the channel two loop reference is either the 0.85-V reference
or, in the case of DDR mode, one half the VO1_VDDQ voltage, (VO1_VDDQ)/2. The output signal of the error
amplifier appears at the COMPx pin and is compared to a buffered version of the 0.6-V oscillator ramp. When
TRIP2 pin is tied to VIN through a resistor, the voltage ramp is further modulated by the input voltage, VIN, to
maintain a constant modulator gain. If the TRIP2 pin is connected to ground through a resistor, then the voltage
ramp remains fixed regardless of VIN value.
The oscillator frequency is internally fixed and can be selected at 270 kHz, 360 kHz or 470 kHz by insertion of
a clamping resistor on the SSTRTx pin per Table 1. For example, 470 kHz can be attained when both SSTRTx
voltages exceed 3.5 V, as described in WAVEFORM1. The controller begins with 270 kHz in the first stage of
the softstart, and then increases to 470 kHz at the steady state. When 270 kHz is selected, both of SSTRTx
voltages are kept below 3.5 V so that the frequency is the same 270 kHz for the entire operation.
Two channels are operated in 180 degrees out-of-phase interleave switching mode. This interleaving helps
reduce the input current ripple requirement for the input capacitor. However, because the PWM loop determines
both the turn-off AND turn-on of the high-side MOSFET, this 180 degree operation may not be apparent by
looking at the LLx nodes only. Rather, the turn-off cycle of one channel always corresponds to the turn-on cycle
of the other channel and vise-versa. As a result, input ripple is reduced and dynamic response is improved over
a broad input voltage range.
MAXIMUM DUTY CYCLE
Because most notebook applications typically run from three to four cell Li−Ion or run from a 20-V adapter, 100%
duty cycle operation is not required. Rather, the TPS51020 is optimized for low duty ratio step-down conversion.
As a result of limiting the duty cycle, the flying BST capacitor is refreshed reliably and the low-side over current
detection circuitry is capable of detecting an overcurrent condition even if the output is stuck between the
regulation point and UVP. The maximum duty cycle for each operating frequency is 88% for 270 kHz, 85% for
360 kHz and 82% for 470 kHz.
It should be noted that if the system is operating close to maximum (or minimum) duty cycle, it may be difficult
for the converter to respond quickly during line/load transients or state changes (such as frequency switching
during soft start or PWM to SKIP mode transitions). This slow response is due to the dynamic range of the COMP
pin and is usually not a result of poor phase compensation. In the case of minimum duty cycle operation, the
slow response is due to the minimum pulse width of the converter (100 ns TYP). In this case (counter intuitively),
it may be advisable to slow down the switching frequency of the converter in order to improve response time.
10
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SLUS564B − JULY 2003 − REVISED DECEMBER 2003
APPLICATION INFORMATION
SKIP MODE OPERATION
If the SKIP pin is set HIGH, the SMPS operates in the fixed PWM mode. While a LOW signal is applied, the
controller operates in autoskip mode. In the autoskip mode, the operation changes from constant frequency
PWM mode to an energy-saving skip mode automatically by detecting the edge of discontinuous current mode.
During the skip mode, the hysteretic comparator monitors output voltage to trigger high side on at the next
coming oscillator pulse after the lower level is detected. Several sequential pulses may be seen, especially in
the intermediate load level, before output capacitor is charged up to the higher level and waits for next cycle.
In the skip mode, frequency varies with load current and input voltage.
Skip mode for SMPS_2 is disabled regardless of the SKIP pin status if DDR mode is selected (see Dual Mode
and DDR Mode section). This is because current sink capability is required for VTT, so that rectifying MOSFET
needs to be kept on when the inductor current flows inversely. SMPS_1 is still capable of skip mode operation
while DDR Mode.
CASCADE CONFIGURATION
If the TRIP2 pin is tied through a resistor to the input voltage, the TPS51020 assumes that the conversion voltage
for channel two is the VIN voltage, usually VBATT. Conversely, if TRIP2 is tied through a resistor to ground, the
controller assumes that the conversion voltage for channel two is the output voltage of channel one or some
other stable bus voltage.
DUAL MODE AND DDR MODE
TPS51020 provides one-chip solution for system power supply, such as for 5 V, 3.3 V or 1.8 V, and a dual
switcher DDR power supply. By simply selecting DDR signal and some external configuration change following
the instructions below, TPS51020 gives a complete function set required for the DDR termination supply such
as VDDQ/2 tracking VTT source/sink capability and VTT reference output.
If DDR is set high ( > 2.2 V), the TPS51020 runs in dual mode, that is, each converter produces an independent
output voltage with respect to the internal 0.85-V reference. Bypass REF_X to ground by 0.01-µF. The
VO1_VDDQ or VO2 terminal can be connected to either to their corresponding switcher output or ground,
depending on customer’s choice of using or not using the output discharge function (See Softstop). The 10-V
reference output can be used as FET switch biasing for power control during sleep states (see Figure 5). During
this dual mode, selection of autoskip mode or PWM mode made by SKIP applies to both SMPS_1 and SMPS_2.
If DDR is set low ( < 0.3V), the TPS51020 operates as a dual switcher DDR supply; VDDQ from SMPS_1 and
VTT from SMPS_2 (DDR Mode). In this mode, the reference voltage for SMPS_2 is switched to (VO1_VDDQ)/2
to track exactly half the voltage of SMPS_1, divided by internal resistors. VO1_VDDQ should be connected to
SMPS_1 output terminal to accomplish this, while VO2 connection is still flexible to the customer’s choice of
softstop. REF_X outputs the (VO1_VDDQ)/2 voltage after a buffer (5-mA max). SKIP controls only SMPS_1
and SMPS_2 is forced to operate in PWM mode so that current can be sink from the output. Power source of
SMPS_2 can either be the battery voltage (independent configuration), or the VDDQ (cascade configuration)
by user’s preference. When using the independent configuration, TRIP2 needs to be connected to the VIN node
via trip resistor. In case of cascade configuration, tie TRIP2 to GND via trip resistor (see Figure 7).
CAUTION:Do NOT toggle DDR HIGH while ENBL1 or ENBL2 is high (see Table 2). REF_X
output switches to high voltage (10 V) and be applied to VTTREF directly
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SLUS564B − JULY 2003 − REVISED DECEMBER 2003
APPLICATION INFORMATION
5-V LINEAR REGULATOR (VREG5)
The VREG5 voltage is the bias for all the low voltage circuitry in the TPS51020 as well as the DC boost voltage
for the MOSFET gate drivers. Total available current is 60 mA. Bypass this pin to GND by 4.7-µF. The under
voltage lockout (UVLO) circuit monitors the output of this regulator to protect internal circuitry from low input
voltages. If 5 V is applied to REG5_IN from either the SMPS output or an alternate 5 V, then the linear regulator
is turned off and the VREG5 pin is switched over to REG_IN. This operation enhances the efficiency of the
overall power supply system because the bulk of the quiescent current now runs from the 5-V output instead
of VIN (VBAT). In this configuration, ensure that VREG5_IN is less than or equal to VVIN.
EXTERNAL 5V INPUT (REG5_IN)
When a 5-V bus is available, VIN does not need to be connected to the battery. In this configuration, VIN should
be connected to REG5_IN.
LOW-SIDE N-CHANNEL FET DRIVER
The low-side driver is designed to drive high current low RDS(on) N-channel MOSFET(s). The maximum drive
voltage is 5.5 V. The drive capability is represented by its internal resistance, which are 3 Ω for VREG5 to
OUTx_D and 2.5 Ω for OUTx_D to OUTGNDx. A dead time is internally generated between top MOSFET off
to bottom MOSFET on, and bottom MOSFET off to top MOSFET on, in order to prevent shoot through.
The low-side driver is typically turned off during all fault modes except for OVP. When an OVP condition exists,
the low-side driver of the offending channel turns on and attempts to blow the protection fuse of the input supply.
During power up the low-side driver is kept off until the high side driver attempt to turn on once. In this fashion,
the TPS51020 can power up into a precharged output voltage, if so desired.
HIGH-SIDE N-CHANNEL FET DRIVER
The high-side driver is designed to drive high current, low RDS(on) N-channel MOSFET(s). When configured as
a floating driver, a 5-V bias voltage is delivered from VREG5 supply. The instantaneous drive current is supplied
by the flying capacitor between VBSTx and LLx pins, 0.1-µF ceramic for typical applications. The boost diodes
are integrated and are sufficient for enhancing the high-side MOSFET. However, external boost diodes can also
be added from VREG5 to each VBSTx in case higher gate-to-source votlage is required.
The drive capability is represented by its internal resistance, which are as follows: 3 Ω for VBST to OUTx_U
and 2.5 Ω for OUTx_U to LLx. The maximum voltage that can be applied between OUTx_U pin and OUTGNDx
pin is 35 V.
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SLUS564B − JULY 2003 − REVISED DECEMBER 2003
APPLICATION INFORMATION
ENABLE AND SOFT-START
Each SMPS is switched into standby mode separately by grounding the corresponding ENBLx pin. The 5-V
supply is enabled if either the DDR, ENBL1 or ENBL2 pin(s) goes high ( >2.2 V).
Softstart of each SMPS is achieved by slowly ramping the error amplifier reference voltage by following a
buffered version of the SSTRTx pin voltage. Designers can achieve their own start-up sequencing by simply
provide external timing signals since the startup times do not depend on the load current. The softstart time is
programmable by external capacitor connected from SSTRTx pin to the ground. Each SSTRTx pin sources
constant current, typically 2.3 µA. The output voltage of the SMPS ramps up from 0 V to its target regulation
voltage as the SSTRTx pin voltage increases from 0 V to 1.2 V. This gives the softstart time formula to be,
C SSTRT (Farads) +
T SSTRT (sec) 2.3
1.2
10 *6
The soft-start capacitor is discharged upon UVLO, OVP or UVP is detected as well as ENBLx is set low.
OUTPUT DISCHARGE (SOFT-STOP)
When an SMPS is turned off by ENBLx asserted low or the part enters a fault mode, both top and bottom drivers
are turned off. This may leave the output in a high impedance state that allows the voltage to persist for some
time. If this voltage is undesirable, then user can connect the output to the VO1_VDDQ or VO2 pins.
These pins turn on a 6-Ω resistor to ground during an off or fault condition. Both the VO1_VDDQ and VO2 pin
must be discharged to 0.3 V before the TPS51020 restarts. Grounding VO1_VDDQ or VO2 inhibits output
discharge for each SMPS, respectively. The TPS51020 has the flexibility of adding a resistor in series with the
VOx pin and the output voltage in order to reduce the discharge current and reduce the total power dissipation
within the device. It should be noted that when this resistor is added the discharged voltage threshold changes
according to the following equation:
V DISCHARGE +
ǒREXTERNAL ) RDS(on)Ǔ
R DS(on)
0.3
where
D REXTERNAL is the series resistor between VOx and the output
D RDS(on) = 6 Ω
When grounded, corresponding channel disables the low-side MOSFET during softstart until the high-side
MOSFET attempts to turn on. This allows the user to start up with precharged output.
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SLUS564B − JULY 2003 − REVISED DECEMBER 2003
APPLICATION INFORMATION
10-V N-CHANNEL FET BIAS or (VOUT1)/2 VTT VOLTAGE REFERENCE (REF_X)
TPS51020’s REF_X provides two functions depending on the operational mode. One is a linear regulator that
supply 10-V for FET switch biasing in the dual mode, the other is VTT reference voltage in the DDR mode.
If DDR is high ( > 2.2 V) then the REF_X output is a convenient 10-V, 2-mA (maximum) output, useful for biasing
N-channel FET switches typically used to manage S0, S3 and S5 sleep states where the main supply is switched
to many outputs. When VIN is < 12 V, REF_X approximately tracks VIN−2 V.
If DDR is low, then the REF_X output becomes the VDDQ/2 (VO1_VDDQ/2) reference. This output is capable
of 5-mA source current and is left on even if channel two (VTT switcher) is turned off. REF_X is turned off if ENBL1
and ENBL2 are both low (see Table 2).
POWERGOOD
The TPS51020 has advanced powergood logic that allows single powergood circuit to monitor both SMPS
output voltages (see Figure 3 ).
VOUT1
VOUT2
2048 c
PGOOD Delay Counter
2048 c
PGOOD
ENBL1
Resets Delay Counter
ENBL2
t0
t1
t2
Figure 3. PowerGood Timing Diagram
The PGOOD terminal is an open drain output. The PGOOD pin remains low until both power supplies have
started and have been in regulation ( ±7.5%) for 2048 clock pulses.
14
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SLUS564B − JULY 2003 − REVISED DECEMBER 2003
APPLICATION INFORMATION
If one channel is enabled in the period between T0 and T1, (the other channel’s ramp time plus delay time,) the
PGOOD delay counter restarts counting softstart finish after the last channel has finished softstart. Enabling
after T1 is ignored by PGOOD until the channel finishes its softstart. If either of the SMPS output goes out by
± 7.5% or UVLO is detected while ENBLx is high, PGOOD pulls low. If a channel is disabled while the other is
still active PGOOD maintains it’s logic state and only monitor the active channel.
PROTECTION FUNCTIONS
The TPS51020 is equipped with input undervoltage lock out (UVLO), output undervoltage protection (UVP) and
overvoltage (OVP) protection. Overcurrent is detected using RDS(on) of the external power MOSFETs and
protected by triggering UVP, or latch off in some cases. The states of output drive signal depends on which
protection was involved. Please refer to each protection description below for the detail.
When the input voltage UVLO is tripped, the TPS51020 resets and waits for the voltage to rise up over the
threshold voltage and restart the device. Alternatively, if output UVP or OVP is triggered, the device latches off
after a delay time defined by the internal fault counter counting the PWM oscillator pulses. The VREF5 and
REF_X is kept on in this latch off condition. The fault latch can be reset by toggling both of ENBLx pins in DDR
mode. The fault latch can be reset by either toggling VIN or bringing DDR, ENBL1 and ENBL2 all low. Be sure
to bring DDR high prior to ENBLx when TPS51020 is being used in dual mode.
If a false trip of the UVLO appears due to input voltage sag during turn-on of the high-side MOSFET such as
a large load transient, first consider adding several micro-farads of input capacitance close to the MOSFET’s
drain. Also consider adding a small VIN filter, ex. a 2.2-Ω resistor and a 2.2-µF, for decoupling. The trip resistors
should be connected to the same node as VIN pin of the device when this filter is applied. The filter resistor
should be as small as possible since a voltage drop across this resistor biases the OCP trip point.
UNDERVOLTAGE LOCKOUT PROTECTION
There are two undervoltage lock out protections (UVLO) in TPS51020. One is for VIN, which has a typical trip
threshold voltage 3.9 V and trip hysteresis 200 mV. The other is for VREF5, which has a typical trip threshold
voltage 3.65 V and trip hysteresis 300 mV. If either is triggered, the device resets and waits for the voltage to
rise up over the threshold voltage and restart the part. Please note this protection function DOES NOT trigger
the fault counter to latch off the part.
OVERVOLTAGE PROTECTION
For overvoltage protection (OVP), the TPS51020 monitors INVx voltage. When the INVx voltage is higher than
0.95V (+12%), the OVP comparator output goes high (after a 20-µs delay) and the circuit latches the top
MOSFET driver OFF, and bottom driver ON for the SMPS detected overvoltage. In addition, the output
discharge (softstop) function is enabled to discharge the output capacitor if VO1_DDR, VO2 is connected to
corresponding output terminal. The fault latch can be reset by either toggling VIN or bringing DDR, ENBL1 and
ENBL2 all low. Be sure to bring DDR high prior to ENBLx when TPS51020 is being used in dual mode.
UNDERVOLTAGE PROTECTION
For undervoltage protection (UVP), the TPS51020 monitors INVx voltage. When the INVx voltage is lower than
0.55 V (−35 %), the UVP comparator output goes high, and the internal FLT timer starts to count PWM oscillator
pulses. After 4096 clock pulses, the part latches off. Both top and bottom drivers are turned off at this condition.
Output discharge (soft-stop) function is enabled to discharge the output capacitor if VO1_DDR, VO2 is
connected to corresponding output terminal. The fault latch can be reset by either toggling VIN or bringing DDR,
ENBL1 and ENBL2 all low. Be sure to bring DDR high prior to ENBLx when TPS51020 is being used in dual
mode.
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SLUS564B − JULY 2003 − REVISED DECEMBER 2003
APPLICATION INFORMATION
OVERCURRENT PROTECTION
Overcurrent protection (OCP) is achieved by comparing the drain to source voltage of the high-side and low-side
MOSFET to a set point voltage. This voltage appears at the TRIPx pin and is defined by the conversion voltage,
typically VIN, minus the I × R drop of the ITRIP current flowing through the external resistor connected to the
conversion voltage. The offset of the internal comparators also plays a role in determining the overall accuracy
and set point of the OCP limit.
When the drain-to-source voltage of the synchronous MOSFET exceeds the set point voltage created by the
I × R drop (usually 20 mV to around 150 mV), the synchronous MOSFET on-time is extended into the next pulse
and the high-side MOSFET OCP comparator is enabled. If during the subsequent high-side on-time the
drain-to-source voltage of the high-side MOSFET exceeds the set point voltage, then the high-side on-time
pulse is terminated. This low-side extension/high-side termination action has the effect of decreasing the output
voltage until the UVP circuit is activated to turn off both the high-side and low-side drivers. The TPS51020 ITRIP
current has a temperature coefficient of 4200 PPM/°C.
The threshold voltage for the OCP comparator is set by I × R drop across the trip resistor. The ITRIP current is
12.5-µA (typ) at R.T. so that the OCP point is given by following formula,
R DS(on)
R TRIP +
ǒ
I OCP )
12.5
Ǔ
I RIPPLE
2
10 *6
Precaution should be taken with board layout in order to design OCP point as desired. The conversion voltage
point must avoid high current path. Any voltage difference between the conversion point and VIN input for the
TPS51020 is included in the threshold voltage. VIN plane layout should consider the other channels
high-current path as well.
A brief discussion is required for TRIP2 function. When TRIP2 is connected, via a resistor to GND, only low-side
OCP is used. This is the case for cascade configuration been selected. In this mode, UVP does not play a roll
in the shut off action and there is only a short delay between the over current trigger level been hit and the power
MOSFETs turn off. However, as with UVP, the SSTRTx pins are discharged and both SMPS goes though a
restart.
LAYOUT CONSIDERATIONS
Below are some points to consider before the layout of the TPS51020 design begins.
D Signal GND and power GND should be isolated as much as possible, with a single point connection
between them.
D All sensitive analog components such as INV, SSTRT, SKIP, DDR, GND, REF_X, ENBL and PGOOD
should be reference to signal GND and be as short as possible.
D The source of low-side MOSFET, the Schottky diode anode, the output capacitor and OUTGND should be
referenced to power GND and be as short and wide as possible, otherwise signal GND is subject to the noise
of the outputs.
D PCB trace defined as the node of LL should be as short and wide as possible.
D Connections from the drivers to the gate of the power MOSFET should be as short and wide as possible
to reduce stray inductance and the noise at the LL node.
D The drain of high-side MOSFET, the input capacitor and the trip resistor should be as short and wide as
possible. For noise reduction, a 22-pF capacitor CTRIP can be placed in parallel with the trip resistor.
16
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SLUS564B − JULY 2003 − REVISED DECEMBER 2003
APPLICATION INFORMATION
D The output voltage sensing trace and the feedback components should be as short as possible and be
isolated from the power components and traces.
D The low pass filter for VIN should be placed close to the TPS51020 and be referenced to signal GND.
D The bootstrap capacitor CBST (connected from VBST to LL) should be placed close to the TPS51020.
D VREG5 requires at least 4.7-µF bypass capacitor which should be placed close to the TPS51020 and be
referenced to signal GND.
D The discharge (VO1_VDDQ, VO2) should better have a dedicated trace to the output capacitor. In case of
limiting the discharge current, series resistors should be added.
D Ideally, all of the area directly under the TPS51020 chip should also be signal GND.
TPS51020
1 INV1
2 COMP1
VBST1 30
OUT1_U 29
Cin1
H_FET1
L01
CBST1
Rtrip1 Ctrip1
CH1 Output Voltage (+)
+
3 SSTRT1
LL1 28
L_FET1
4 SKIP
OUT1_D 27
Co1
CH1 Output Voltage (GN
5 VO1_VDDQ
OUTGND1 26
6 DDR
TRIP1 25
7 GND
VIN 24
−
Input Voltage (+)
Rvin
Signal GND
+
Cin
8 REF_X
TRIP2 23
9 ENBL1
VREG5 22
10 ENBL2
REG5_IN 21
Input Voltage (GND)
Cvinbp
−
Power GND
Cvreg5
CH2 Output Voltage (GND)
11 VO2
OUTGND2 20
12 PGOOD
OUT2_D 19
13 SSTRT2
LL2 18
14 COMP2
OUT2_U 17
−
L_FET2
Co2
CH2 Output Voltage (+)
+
15 INV2
VBST2 16
L02
CBST2
Cin2
H_FET2
Rtrips Ctrip2
Figure 4. PCB Trace Guideline
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SLUS564B − JULY 2003 − REVISED DECEMBER 2003
APPLICATION INFORMATION
VBAT
8 V to 20 V
C01a
22u
GND
C12
R101
R12
R01
100k
R101
C14
R04
49.7k 3900p
1.8k
R02
330
100k
R102
Q01
C02
6800p
2.2ux2
15
L01
C08
Q02
1
INV1
2
COMP1
3
SSTRT1
4
SKIP
5
VO1_VDDQ
6
DDR
7
GND
8
REF_X
10k
C15
100k
0.01u
(10V_REF
)
TPS51020
C04a
R09
VBST1 30
OUT1_U 29
LL1 28
C20
5V_X
Q11
R200
GND
R13
51k
C27
0
0
18k
VREG5 22
REG5_IN 21
R201
R16
18k
R14
51k
C01c
Q12
2.2u
C13
OUTGND2 20
OUT2_D 19
4.7u
GND
GND
LL2 18
OUT2_U 17
GND
Q04
VBST2 16
3.3V_OUT
C05c
C05a
R08
C03
R10
0.1u
0.01u
150u
L02
C11
2.7k
3300p
R11
330
0.01u
150u
OUTGND1 26
TRIP1 25
15 INV2
10k
GND
Q10
VIN 24
TRIP2 23
12 PGOOD
13 SSTRT2
14 COMP2
0.01u
C04c
OUT1_D 27
9 ENBL1
10 ENBL2
11 VO2
C19
5V_OUT
4u
0.1u
R03
Q13
2.2ux2
3.3V_X
4u
R15
28.8k
Q14
C22
15
R07
2200p
R202
Q03
100k
R203
51k
51k
Q15
C01a
: Sanyo 35SVPD22M
C01c, C02, C03, C27 : Taiyo Yuden GMK325BJ225MH−B
C04a, C05a
: Panasonic EEFUE0J151R
Q01, Q03
: Fairchild FDS6612A
Q02, Q04
: Fairchild FDS6690S
L01, L02
: Sumida CEP125−4R0MC−H
GND
Figure 5. Typical Application Circuit: Dual (5V/6A + 3.3V/6A) from VBAT
VBAT
8 V to 20 V
C01a
GND
C12
R12
R01
C14
R02
R101
Q01
C02
4700p
1.2k
100k
7.62k
4700p
2.2ux2
15
R04
L01
4.7k
C08
Q02
2.5V_OUT
5.6u
C04b
0.1u
R102
R03
3.9k
C15
100k
0.01u
(VO1_VDDQ/2_REF
)
1
INV1
2
COMP1
3
SSTRT1
4
SKIP
5
VO1_VDDQ
6
DDR
7
GND
8
REF_X
9 ENBL1
10 ENBL2
11 VO2
TPS51020
0.01u
C20
GND
R13
R16
18k
VIN 24
TRIP2 23
VREG5 22
R14
0
18k
REG5_IN 21
OUTGND2 20
C27
(EXT_5V)
4.7u
OUT2_U 17
16
VBST2
Q04
C05a
C05b
R08
0.1u
GND
C05c
150u
L02
C11
3.9k
150u
0.01u
2.2ux2
1.25V_OUT
5.6u
R15
19.7k
C22
15
2200p
2.2u
GND
C03
6800p
R11
1.2k
C13
C01c
0
OUT2_D 19
LL2 18
R10
0.01u
150u
150u
OUT1_D 27
OUTGND1 26
TRIP1 25
15 INV2
GND
C04c
C04a
VBST1 30
OUT1_U 29
LL1 28
12 PGOOD
13 SSTRT2
14 COMP2
C19
R07
Q03
100k
C01a
: Sanyo 35SVPD22M
C01c, C02, C03, C27
: Taiyo Yuden GMK325BJ225MH−B
C04a, C05a, C04b, C05b : Panasonic EEFUE0J151R
Q01, Q03
www.ti.com
: Fairchild FDS6612A
Q02, Q04
: Fairchild FDS6690S
L01, L02
: Sumida CEP125−5R6MC−H
Figure 6. Typical Application Circuit: DDR(2.5V/6A + 1.25V/6A) from VBAT
18
22u
SLUS564B − JULY 2003 − REVISED DECEMBER 2003
APPLICATION INFORMATION
VBAT
8 V to 20 V
C01a
GND
C12
R12
R01
C14
R02
R101
Q01
C02
4700p
1.2k
100k
7.62k
4700p
2.2ux2
15
R04
L01
4.7k
C08
Q02
2.5V_OUT
5.6u
C04b
0.1u
R102
R03
3.9k
C15
100k
0.01u
(VO1_VDDQ/2_REF
)
1
INV1
2
COMP1
3
SSTRT1
4
SKIP
5
VO1_VDDQ
6
DDR
7
GND
8
REF_X
TPS51020
9 ENBL1
10 ENBL2
11 VO2
12 PGOOD
13 SSTRT2
C19
0.01u
GND
C20
150u
GND
R13
R16
18k
VIN 24
TRIP2 23
C27
VREG5 22
REG5_IN 21
OUTGND2 20
OUT2_D 19
C01c
2.2u
C13
R14
(EXT_5V)
18k
4.7u
GND
GND
LL2 18
OUT2_U 17
16
VBST2
Q04
C05a
C05b
R08
L02
C11
3.9k
0.1u
GND
C05c
150u
150u
0.01u
150u
1.25V_OUT
5.6u
1.2k
R15
19.7k
C22
15
R07
2200p
Q03
100k
C01a
: Sanyo 35SVPD22M
C01c, C02, C27
: Taiyo Yuden GMK325BJ225MH−B
C04a, C05a, C04b, C05b,C04d
: Panasonic EEFUE0J151R
Q01, Q03
0
0
C04d
6800p
0.01u
150u
OUT1_D 27
OUTGND1 26
TRIP1 25
14 COMP2
15 INV2
C04c
C04a
VBST1 30
OUT1_U 29
LL1 28
R10
R11
22u
2.5V_OUT
: Fairchild FDS6612A
Q02, Q04
: Fairchild FDS6690S
L01, L02
: Sumida CEP125−5R6MC−H
Figure 7. Typical Application Circuit: DDR (2.5V/6A + 1.25V/3A) Cascade
www.ti.com
19
SLUS564B − JULY 2003 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
SHUTDOWN CURRENT
vs
JUNCTION TEMPERATURE
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
140
2.5
VENBLx − VDDR = 0 V
REG5V_IN = Open
IVIN(SHTDWN) − Shutdown Current − nA
IVIN − Input Supply Current − mA
VVIN = 12 V
2.0
1.5
1.0
0.5
−50
0
50
100
120
100
80
60
40
20
0
−50
150
0
TJ − Junction Temperature − °C
−2.50
25
−2.45
ISSQ − SSRTx Charge Current − µA
ITRIPSINK − TRIP1 Sink Current − µA
VTRIP − VVIN = 0.1 V
20
15
10
5
0
50
100
150
VVIN = 12 V
VSSTRTx = 1 V
−2.40
−2.35
−2.30
−2.25
−2.20
−2.15
−2.10
−50
TJ − Junction Temperature − °C
0
50
100
TJ − Junction Temperature − °C
Figure 11
Figure 10
20
150
SOFTSTART CURRENT
vs
JUNCTION TEMPERATURE
TRIP CURRENT
vs
JUNCTION TEMPERATURE
0
100
Figure 9
Figure 8
−50
50
TJ − Junction Temperature − °C
www.ti.com
150
SLUS564B − JULY 2003 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
SOFTSTART TIME
vs
SOFTSTART CAPACITANCE
500
100 k
VVIN = 12 V
fOSC − Oscillator Frequency − kHz
VVIN = 12 V
TA = 25°C
tSS − Softstart Time − µs
10 k
1k
100
10
100
10
1k
10 k
fOSC(HI)
400
fOSC(TYP)
350
300
fOSC(LO)
250
200
−50
1
1
450
100 k
0
CSSTRT − Softstart Capacitance − pF
Figure 12
150
OVERVOLTAGE PROTECTION THRESHOLD
vs
JUNCTION TEMPERATURE
900
1400
VVIN = 12 V
VOVP − Overvoltage Protection Trip Voltage − mV
VUVP − Undervoltage Protection Trip Voltage − mV
100
Figure 13
UNDERVOLTAGE PROTECTION THRESHOLD
vs
JUNCTION TEMPERATURE
850
800
DDR = LO
VVO1_VDDQ = 2.5 V
750
700
650
600
550
DDR = HI
500
−50
50
TJ − Junction Temperature − °C
0
50
100
150
TJ − Junction Temperature − °C
VVIN = 12 V
DDR = LO
VVO1_VDDQ = 2.5 V
1300
1200
1100
1000
DDR = HI
900
800
−50
0
50
100
TJ − Junction Temperature − °C
150
Figure 15
Figure 14
www.ti.com
21
SLUS564B − JULY 2003 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
VREG5 OUTPUT VOLTAGE
vs
VREG5 OUTPUT CURRENT
5.2
VVIN = 12 V
TA = 25°C
VVREG5 − VREG5 Output Voltage − V
5.1
VOUT1
50 mV/div
5.0
4.9
4.8
4.7
4.6
IOUT1
2 A/div
4.5
fOSC= 290 kHz
VIN = 20 V, VOUT1 = 2.5 V
1 A ≤ IOUT1 ≤ 6 A, 1A/ms
4.4
4.3
0
−20
−40
−60
−80
−100
t − Time − 100 ms / div
IVREG − VREG5 Output Current − mA
Figure 16
VOUT1
1 V/div
Figure 17. Load Transient Response
VOUT1
1 V/div
VOUT2
500 mV/div
VOUT2
500 mV/div
PGOOD
2 V/ div
PGOOD
2 V/ div
t − Time − 5 ms / div
t − Time − 5 ms / div
Figure 18. Simultaneous Startup
22
Figure 19. Offset Startup
www.ti.com
SLUS564B − JULY 2003 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
VVIN = 8 V
VDDQ (1 V/div)
ENBL1
5 V/div
Efficiency − %
ENBL2
5 V/div
VDDQ Disabled S5
VVIN = 20 V
VTT Disabled S3
VOUT2
2 V/div
VOUT1
2 V/div
VTT (1 V/div)
fOSC = 290 kHz
VVO1 = 5 V
t − Time − 5 ms / div
t − Time − 5 ms / div
Figure 20. Soft-Stop
Figure 21. Cascade Configuration DDR Mode
Shudown
PWM MODE EFFICIENCY
vs
OUTPUT CURRENT
100
100
AUTOSKIP MODE EFFICIENCY
vs
OUTPUT CURRENT
VVIN = 8 V
80
80
VVIN = 12 V
60
Efficiency − %
Efficiency − %
VVIN = 20 V
VVIN = 20 V
40
60
VVIN = 8 V
40
VVIN = 12 V
20
20
fOSC = 290 kHz
VVO1 = 5 V
fOSC = 290 kHz
VVO1 = 5 V
0
0.01
0.1
1
10
IOUT − Output Current − A
Figure 22
0
0.01
0.1
1
IOUT − Output Current − A
10
Figure 23
www.ti.com
23
SLUS564B − JULY 2003 − REVISED DECEMBER 2003
PWM MODE EFFICIENCY
vs
OUTPUT CURRENT
AUTOSKIP MODE EFFICIENCY
vs
OUTPUT CURRENT
100
100
VVIN = 8 V
VVIN = 8 V
80
80
Efficiency − %
Efficiency − %
VVIN = 12 V
60
40
VVIN = 20 V
VVIN = 20 V
40
0.1
fOSC = 290 kHz
VVO1 = 2.5 V
fOSC = 290 kHz
VVO1 = 2.5 V
1
10
IOUT − Output Current − A
Figure 24
24
VVIN = 12 V
20
20
0
0.01
60
0
0.01
0.1
1
IOUT − Output Current − A
Figure 25
www.ti.com
10
PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS51020DBT
ACTIVE
SM8
DBT
30
60
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS51020DBTG4
ACTIVE
SM8
DBT
30
60
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS51020DBTR
ACTIVE
SM8
DBT
30
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS51020DBTRG4
ACTIVE
SM8
DBT
30
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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