ETC TSS463D

TSS463
Vehicle Area Network Data Link Controller
with Serial Interface
1. Description
The TSS463 is a circuit which allows the transfer of all
the status information needed in a car or truck over a
single low-cost wire pair, thereby minimizing the
electrical wire usage.
14 channel register sets and 128 bytes of general purpose
RAM, used as a message storage area, and a 6-source
maskable interrupt.
It can be used to interconnect powerful functions and to
control and interface car body electronics (lights,
wipers, power window...).
The circuit operates in the RAM using DMA techniques,
controlled by the channel and control registers. This
allows virtually any microprocessor including SPI/SCI
interface to be connected with ease with the TSS463.
The TSS463 is fully compliant with the VAN ISO
standard ISO/11519-3. This standard supports a wide
range of applications such as low-cost remote controlled
switches, typically used for lamp control, up to complex,
highly autonomous, distributed systems which require
fast and secure data transfers.
Messages are encoded in enhanced Manchester code,
and an optional pulsed code for use with an optical or
radio link, at a maximum bit rate of 1 Mbit/s. The
TSS463 analyzes the messages received or transmitted
according to 6 different criteria including some higher
level checks.
The TSS463 is a microprocessor interfaced line
controller for mid to high complexity bus-masters and
listeners like dashboard controllers, car stereo or mobile
telephone CPUs.
In addition the bus interface has three separate inputs
with automatic source diagnosis and selection, allowing
for multibus listening or the automatic selection of the
most reliable source at any time if several line receivers
are connected to the same bus.
The microprocessor interface consists of a 256 byte
RAM and register area divided into 11 control registers,
2. Features
D
D
D
D
D
D
D
D
D
Fully compliant to VAN specification ISO/11519–3.
Handles all specified module types.
Handles all specified message types.
Handles retransmission of frames on contention and
errors.
3 separate line inputs with automatic diagnosis and
selection.
Normal or pulsed (optical and radio mode) coding.
VAN transfer rate: 1 Mbit/s maximum.
SPI/SCI interface.
SPI transfer rate: 4 Mbit/s maximum.
SCI transfer rate: 125 Kbit/s maximum.
Rev. C – 22 Feb. 01
D Idle and sleep modes.
D 128 bytes of general purpose RAM.
D 14 identifier registers with all bits individually
maskable.
D 6-source maskable interrupt including an
interrupt-on-reset to detect glitches on the reset pin.
D Integrated crystal or resonator oscillator with
internal baud rate generator and buffered clock
output.
D Single +5V power supply.
D 0.8 µm CMOS technology.
D SO 16 packaging.
1
TSS463
SCLK MOSI SS MISO
INT
RESET
TEST
VCC
GND
SPI/SCI logic
Status and
control
registers
address bus
data bus
control bus
status bus
128 bytes
Message
buffer
RAM
Protocol controller
state machine and
ID registers
Reception logic
CRC generator
and checker
Data serializer and
deserializer
Clock generator and
line synchronization
logic
XTAL1 XTAL2
Source diagnosis
and selection logic
CKOUT
Transmission logic
TxD
RxD0 RxD1 RxD2
Figure 1. Block Diagram
2
Rev. C – 22 Feb. 01
TSS463
I/O Type
MISO
1
16
MOSI
SS
2
15
SCLK
INT
3
14
RESET
VDD
4
13
GND
XTAL1
5
12
TxD
XTAL2
6
11
RxD0
TEST/VSS
7
10
RxD2
CKOUT
8
9
RxD1
Pin Name
Pin No
Pin Function
O 3–state
MISO
1
SPI/SCI Data Output
I trigger CMOS
SS
2
SPI/SCI Slave Select (active
low)
Open drain
INT
3
Interrupt (active low)
Power
VDD
4
+ 5 V power supply
I CMOS
XTAL1
5
Crystal oscillator or clock input
pin from 1 to 16 Mhz
O
XTAL2
6
Crystal oscillator output pin
Ground
TEST/VSS
7
Test mode input
O
CKOUT
8
Buffered clock output
I CMOS Pull
down
RxD1
9
VAN bus input 1
I CMOS Pull
down
RxD2
10
VAN bus input 2
I CMOS Pull
down
RxD0
11
VAN bus input 0
O 3–state
TxD
12
VAN bus output
Ground
GND
13
I trigger CMOS
pullup
RESET
14
Hardware Reset (active low)
I trigger CMOS
SCLK
15
SPI/SCI Clock Input
I trigger CMOS
MOSI
16
SPI/SCI Data Input
Figure 2. Pinout
Rev. C – 22 Feb. 01
3
TSS463
3. Operation
The circuit also features one single interrupt pin. This
pin can be treated as level sensitive, i.e. if there is a pending interrupt inside the circuit when another interrupt is
reset the INT pin will emit a high pulse with the same
pulse width as the internal write strobe (typically 20 ns).
The TSS463 is a microprocessor controlled line
controller for the VAN bus. It can interface to virtually
any microprocessor which includes SPI or SCI interface.
D On the first hand, the TSS463 provides one full
Motorola compatible SPI interface.
D On the other hand, it includes one full compatible
Intel UART (mode 0 only).
D And finally, one 9–bits SCI interface is also
integrated.
Remaining pins
mC
SCLK
MOSI
MISO
PORT X.Y
IRQ
General I/O
(if needed)
100K
MISO
SS
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
INT
VDD
CKOUT
MOSI
1
RESET (*)
RxD0
TEST/VSS
CKOUT
GND
TxD
XTAL1
XTAL2
RESET (*)
SCLK
VAN Bus
RxD2
RxD1
(*) The TSS463 RESET pin can either be connected to GND through a 1 µF capacitor, or to the µC RESET pin
or unconnected (inactive with internal pull–up).
Figure 3. Typical application with Motorola SPI mode
4. Pinout
The TSS463 is available in SOP 16 package. Figure 2
shows the pinout.
Leaving MISO output pin floating in high impedance
mode slightly increases standby consumption. A 100KW
pullup/pulldown resistor is recommended.
5. Microprocessor Interface
The processor controls the TSS463 by reading and
writing the internal registers of the circuit. These
registers appear to the processor as regular memory
locations.
5.1. Interface Modes
The TSS463 must be connected with an SPI or SCI serial
interface. See next paragraph to know how to switch
from one mode to another.
4
Rev. C – 22 Feb. 01
TSS463
5.1.1. Motorola SPI Mode
The first two bytes to be sent by the master (CPU) are
called «Initialization Sequence» : This sequence
provides a proper asynchronous RESET in the TSS463
and it selects the Motorola SPI, Intel SPI or the SCI serial
mode. This initialization sequence is shown on figure 4:
two 0x00 will cause an internal RESET and assert the
Motorola SPI mode, two «0xFF» will provide an internal
RESET and assert the Intel SPI mode and «9 bits to 0
followed by 0xFF or 0xFE» will generate an internal
RESET and assert the 9–bits SCI mode.
SPI 8 pulses
SCLK
MOSI
0x00
or 0xFF
0x00
0xFF
Motorola
Intel
SS
internal RESET
Internal RESET and SPI mode (Intel or Motorola)
SCI 9 pulses
SCLK
MOSI
0 . 0000 . 0000
1 . 1111 . 1111
SS
internal RESET
Internal RESET and SCI mode
Figure 4. Mode Configuration byte
The Motorola Serial Peripheral Interface (SPI) is fully
compatible to the SPI Motorola protocol. The interface
is implemented for slave–mode only (the TSS463 can
not generate SPI frames by itself).
The SPI mode interface consists of 4 pins : separate
wires are required for data and clock, so the clock is not
included in the data stream as shown on figure 5. One pin
is needed for the serial clock SCLK, two pins for data
communication MOSI and MISO and one pin for Slave
Select SS.
The SPI interface allows an interconnection of several
CPUs and peripherals on the same printed circuit board.
SPI 8 pulses
SCLK
MOSI
0x55
MISO
0x66
SS
Figure 5. SPI data stream
Rev. C – 22 Feb. 01
5
TSS463
SCLK : Serial Clock
MISO : Master In Slave Out
The master device provides the serial clock for the slave
devices. Data is transferred synchronously with this
clock in both directions. The master and the slave
devices send/receive a data byte during a eight clock
pulses sequence.
The MISO pin is configured as the slave device data
output (TSS463) and as master device data input (CPU).
When the slave device is not selected (SS = 1), this pin
is in high impedance state.
MOSI : Master Out Slave In
The SS pin is the slave chip select. It is low active. A low
state on the Slave Select input allows the TSS463 to
accept data on the MOSI pin and send data on the MISO
pin. The Slave Select signal must not toggle between
each transmitted byte and so, should be left at a low level
during the whole SPI frame. SS must be asserted to
inactive high level at the end of the SPI frame.
The MOSI pin is the master device data output (CPU)
and the slave device data input (TSS463). Data is
transferred serially from the master to the slave on this
line; most significant bit (MSB) first, least significant bit
(LSB) last.
SS : Slave Select
As mentioned earlier, if SS is not asserted, MISO pin is
in a high impedance state and incoming data is not
driven to the serial data register.
5.1.2. SPI protocol
The general format of the data communication in the SPI
frame between the TSS463 and the host is a bit–for–bit
exchange on each SCLK clock pulse. Data is arranged
in the TSS463 such that the significance of a bit is
determined by its position from the start for output and
from the end for input, most significant bit (MSB) is sent
first. Bit exchanges in multiples of 8 bits are allowed.
The Idle Clock Polarity (CPOL) and the Clock Phase
(CPHA) are not programmable: the CPOL and CPHA
values to be programmed in the master (CPU) are
CPOL=CPHA=1. This is available for all modes.
Waveforms with transmit and sample points are shown
on figure 6.
CPOL = CPHA = 1
Data Sample Points
SPI 8 pulses
SCLK
MOSI
0x55
MISO
0x66
SS
Data Transmit Points
Figure 6. CPOL and CPHA in the TSS463
At the beginning of a transmission over the serial
interface, the first byte is the address of the TSS463
register to be accessed. The next byte transmitted is the
control byte which determines the direction of the
communication. The following bytes are data bytes
(consecutive bytes are written in or read from Address,
Address+1, Address+2, ..., Address+n with n = 0 to 28).
To make sure the TSS463 is not out of synchronization,
the SPI interface will transmit datas «0xAA» and
6
«0x55» on the MISO pin during address and control
bytes time. This way, the master always ensures the
TSS463 is well–synchronized. If the TSS463 is out of
synchronization, the master can assert the SS pin
inactive to resynchronize the SPI interface or can assert
the RESET pin active or can send an initialization
sequence. When the SS pin is inactive, the SCLK is
allowed to toggle. This will have no effect on the
TSS463 SPI module.
Rev. C – 22 Feb. 01
TSS463
5.1.3. SPI control byte
The SPI control byte is transmitted by the master (CPU)
to the TSS463. It specifies whether it is a TSS463 Write
or Read.
7
6
5
DIR
1
1
4
0
3
0
2
0
1
0
0
0
Figure 7. SPI Control byte
DIR : Serial Transfer Direction
Zero : Read Operation. The data bytes will be read by the
master (CPU) from the TSS463.
One : Write Operation. The data bytes will be written by
the master (CPU) to the TSS463.
In both cases, address auto–increment mechanism will
take place when more than one data byte is read or
written. This mechanism is inhibited when address value
reaches 0xFF.
The seven following bits are reserved and must be equal
to : 1100000.
When the master (CPU) conducts a write, it sends an
address byte, a control byte and data bytes on its MOSI
line. The slave device (TSS463) will send, if
well–synchronized, «0xAA» during the address byte
and «0x55» during the control byte on its MISO line.
When the master (CPU) conducts a read , it sends an
address byte, a control byte and dummy characters
(«0xFF» for instance) on its MOSI line. In the case of a
VAN messages RAM read (VAN frame received), the
first data byte sent back by the TSS463 on its MISO pin
is the data length so the master knows how many dummy
characters it must send to read the VAN frame properly.
When the TSS463 responds back with data, it will not
take care of the MOSI line.
The master must activate and desactivate SS between
each data frame.
Synchronization bytes must be monitored carefully. For
instance, if «0xAA» and «0x55» are not monitored
correctly, then the previous transmission may be
incorrect too.
A control byte containing «0x00» or «0xFF» is
forbidden except during an « Initialization Sequence ».
5.1.4. Intel SPI Mode
The Intel SPI mode is the second type of interface. As
mentioned earlier, the TSS463 enters this mode if the
Initialization Sequence contains (first two bytes
received) «0xFF, 0xFF».
This mode is fully compatible to the Intel UART serial
interface programmed in mode 0 only. That means it is
the same as Motorola SPI mode (same CPOL and
Rev. C – 22 Feb. 01
CPHA) but with inverted communication sense (LSB
first and MSB last). The protocol is also the same.
However, from the master point of view (host
microcontroller), the hardware is different. Figure 8
shows how to connect the TSS463 and Intel type
microcontroller.
7
TSS463
General I/O
Remaining pins
optional
TxD
RxD
100k
MOSI
MISO
(if needed)
PORT X.y
PORT X.z
SS
1
16
2
15
3
14
4
13
5
12
6
11
SCLK
INT
IRQ
RESET (*)
VDD
RESET (*)
C1
GND
TxD
XTAL1
XTAL2
C2
XTAL1
RxD0
CKOUT
VAN Bus
RxD2
TEST/VSS
7
10
8
9
RxD1
(*) The RESET pin can either be connected to GND through a 1 µF capacitor, or to the µC RESET pin
or unconnected (inactive with internal pull–up).
Figure 8. Typical application with the 8051 UART in mode 0.
The master device provides the serial clock on the TxD
pin and is still connected to SCLK pin of the slave
device.
Then, the RxD replaces the MOSI and MISO pins and is
a bidirectional pin. To achieve a correct communication,
the user should add a little hardware to connect the
master RxD pin to the MOSI–MISO slave pins.
Figure 8 proposes two 3–state buffers controlled by the
master trough a general purpose I/O pin.
It is obvious that, in this Intel SPI mode, the master can
not monitor the «0xAA and 0x55» synchronization
bytes while sending the address and control bytes. It is
the only exception of this mode compared to the
Motorola SPI mode.
5.1.5. SCI Mode
The SCI mode is the third type of interface. As
mentioned earlier, the TSS463 enters this mode if the
Initialization Sequence contains (first two bytes
received) «0x00, 0xFF» .
The SCI is compatible to a 9–bits SCI protocol. The
interface is implemented for slave–mode only (the
TSS463 can not generate SCI frames by itself).
CPUs and peripherals on the same printed circuit board.
The SCI mode interface consists of 4 pins : separate
wires are required for data and clock, so the clock is not
included in the data stream as shown on figure 9. One pin
is needed for the serial clock SCLK, two pins for data
exchange MOSI and MISO and one pin for Slave Select
SS.
The SCI interface allows an interconnection of several
8
Rev. C – 22 Feb. 01
TSS463
SCI 9 pulses
SCLK
MOSI
0x55
MISO
0x66
SS
Figure 9. SCI data stream
SCLK : Serial Clock
MISO : Master In Slave Out
The master device provides the serial clock for the slave
devices. Data is transferred synchronously with this
clock in both directions. The master and the slave
devices exchange a data byte during a nine clock pulses
sequence. However, the TSS463 will only monitor 8 bits
on its MOSI line and send 9 bits on its MISO line.
The MISO pin is configured as the slave device data
output (TSS463) and as master device data input (CPU).
When the slave device is not selected (SS = 1), this pin
is in high impedance state. The value of the MSB (9th bit)
sent on the MISO pin will always be «1» and should not
be used by the master.
SS : Slave Select
MOSI : Master Out Slave In
The MOSI pin is the master device data output (CPU)
and the slave device data input (TSS463). Data is
transferred serially from the master to the slave on this
line; least significant bit (LSB) first, most significant bit
(MSB) last. The TSS463 will only monitor 8 bits starting
from the LSB to MSB–1.
The SS pin is the slave chip select. It is low active. A low
state on the Slave Select input allows the TSS463 to
accept data on the MOSI pin and send data on the MISO
pin. The Slave Select signal most not toggle between
each transmitted byte and so, should be left at a low level
during the whole SCI frame. SS must be asserted to
inactive high level at the end of the SCI frame.
As mentioned earlier, if SS is not asserted, MISO pin is
in high impedance state and incoming data is not driven
to the serial data register.
5.1.6. SCI protocol
Same as the SPI protocol described earlier except for
data arranging (LSB first and MSB last).
must monitor the 8 first bits too (9th bit always
equal to 1).
Only 8 bits are monitored by the TSS463 and master
5.1.7. SCI control byte
Same as the SPI control byte.
5.2. Clocks and speed considerations
5.2.1. SCLK and XTAL clocks
The SPI/SCI speed rate is given by the CPU producing
SCLK. XTAL clock controls the speed rate on the VAN
bus. The two clocks are asynchronous but a minimum
SPI/SCI interframe spacing must be apply according to
XTAL clock.
5.2.2. Intel and Motorola SPI modes
Within a SPI byte, the maximum speed allowed on the
MOSI line is 4 Mbits/s.
For example, when using a 1 Mhz oscillator (sufficient
Rev. C – 22 Feb. 01
to provide 62.5 kTS/s on the VAN bus) the minimum
inter–character delay is 12µs (12 oscillator periods).
Speed considerations are detailed on figure 10.
9
TSS463
4 Mbits/s max for SCLK
SCLK
MOSI
Address
Control
Data
SS
12 Xtal min
4 Xtal min
(12 µs at 1 MHz)
(4 µs at 1 MHz)
12 Xtal min
(12 µs at 1 MHz)
12 Xtal min
(12 µs at 1 MHz)
Figure 10. SPI speed considerations
5.2.3. SCI mode
Within a SCI 9–bits data, the maximum speed allowed
on the MOSI line is 125 Kbits/s. When using a 1 Mhz
oscillator,. the data transfer speed and the minimum
delay time between SCI bytes are shown on figure 11.
125 Kbits/s max for SCLK
SCLK
Start bit
MOSI
Stop bit
Address
Control
Data
SS
4 Xtal min
(4 µs at 1 MHz)
12 Xtal min
(12 µs at 1 MHz)
12 Xtal min
(12 µs at 1 MHz)
12 Xtal min
(12 µs at 1 MHz)
Figure 11. SCI speed considerations
5.3. Interrupts
If an event occurs in the TSS463, that needs the attention
of the processor, this will be signalled on the active low,
open drain interrupt request pin. Which event that create
such a request is controlled by the internal registers.
Every time the microprocessor accesses any of the
interrupt registers (addresses 0x08 to 0x0B) the INT pin
will be released momentarily. This enables the TSS463
to work with processors that have either edge or level
sensitive interrupt inputs.
5.4. Reset
The reset is applied asynchronously or synchronously
regarding XTAL clock.
5.4.1. Asynchronous Reset
It can be done either by the RESET pin (hardware
asynchronous reset) or by software (software
asynchronous reset).
The RESET pin is a CMOS trigger input with a pull-up
resistor (≈ 70 KΩ). An external 1 µF capacitor to GND
provides to RESET pin an efficient behavior.
The asynchronous software reset is made by the
«Initialization Sequence» described in paragraph 5.1.1.
10
Two «0x00» bytes provide an asynchronous software
reset and configure the TSS463 in the Motorola SPI
mode while two «0xFF» bytes provide a reset and
configure the component in the Intel SPI mode and
«0x00 followed by 0xFF » provide a reset and configure
the component in the SCI mode. The SS pin must be
asserted as shown on figure 12. The SPI/SCI logic will
monitor these two bytes and provide an internal reset
pulse asserting the TSS463 in the right mode.
Rev. C – 22 Feb. 01
TSS463
5.4.2. Synchronous Reset
A synchronous reset (regarding XTAL clock) is also
available on the TSS463 during current operation. It is
made through the GRES command bit of the Command
Register (address 0x03).
The two kinds of reset are ored and filtered. Then the
internal reset, always asserted asynchronously, enables
the internal oscillator. Then it waits for 12 clock periods
the oscillator stability.
The different blocks of the TSS463 need to be turned on
synchronously. So the release of the internal reset is
synchronous and a loose of clock can let the TSS463 in
permanent reset after applying Reset.
It is important to note that , even after a reset on the
RESET pin, the user should wait for 12 clock periods
before sending the «Initialization Sequence» in order to
select the SPI or SCI mode (because the default mode
after a hardware reset is the Motorola SPI mode).
4 XTAL min
SCLK
12 XTAL min
MOSI
0xFF
0xFF
SS
Detection of forbidden control
Reset Internal Pulse
End of Chip Select
Figure 12. Asynchronous software reset with UART Intel mode
6. Oscillator
An oscillator is integrated in the TSS463, and consists
of an inverting amplifier of which the input is XTAL1
and the output XTAL2.
A parallel resonance quartz crystal or ceramic resonator
must be connected to these pins. As can be seen from
Figure 8. , two capacitors have to be connected from the
crystal pins to ground. The values of C2 depend on the
frequency chosen and can be selected using the
nomograph given in Figure 41.
If the oscillator is not used, then a clock signal must be
fed to the circuit via the XTAL1 input.
Note, that this pin will behave as a CMOS level
compatible Schmitt trigger input.
In this case the XTAL2 output should be left
unconnected. The oscillator also features a buffered
clock output pin CKOUT. The signal on this pin is
directly buffered from the XTAL1 input, without
f(TSCLK) +
Rev. C – 22 Feb. 01
inversion.
There is one more pin used for the oscillator. The
TEST/VSS pin is in fact its ground, and unless this pin
is firmly connected to ground, with decoupling
capacitors, the oscillator will not operate correctly.
The test mode itself, i.e. when the TEST/VSS pin is held
high, is only intended for factory use, and the
functionality of this mode is not specified in any way.
Furthermore, it is subject to change without notice, the
only exception being for incoming inspection tests using
the test program.
The clock signal is then fed to the clock generator that
generates all the necessary timing signals for the
operation of the circuit. The clock generator is
controlled by a 4-bit code called the clock divider.
f(XTAL1)
n 16
11
TSS463
Table 1. Clock Divider.
Clock
Divider
Divide
by
16 MHz
KTS/s
12 MHz
Kbits/s
KTS/s
8 MHz
Kbits/s
KTS/s
Kbits/s
0000
1
1000
800
750
600
500
400
0001
2
500
400
375
300
250
200
0010
4
250
200
187.50
150
125
100
0011
8
125
100
93.75
75
62.5
50
0100
16
62.50
50
46.875
37.5
31.25
25
0101
32
31.25
25
23.438
18.75
15.625
12.5
0110
64
15.625
12.5
11.718
9.375
7.813
6.25
0111
128
7.813
6.25
5.859
4.688
3.906
3.125
1000
1.5
666.667
533.333
500
400
333.333
266.666
1001
3
333.333
266.666
250
200
166.666
133.333
1010
6
166.666
133.333
125
100
83.333
66.666
1011
12
83.333
66.666
62.50
50
41.666
33.333
1100
24
41.666
33.333
31.25
25
20.833
16.666
1101
48
20.833
16.666
15.625
12.50
10.416
8.333
1110
96
10.416
8.333
7.813
6.25
5.208
4.166
1111
192
5.208
4.166
3.906
3.125
2.604
2.083
Clock
Divider
Divide
by
6 MHz
KTS/s
4 MHz
Kbits/s
KTS/s
1 MHz
Kbits/s
KTS/s
Kbits/s
0000
1
375
300
250
200
62.50
50
0001
2
187.50
150
125
100
31.25
25
0010
4
93.75
75
62.50
50
15.625
12.5
0011
8
46.875
37.5
31.25
25
7.813
6.25
0100
16
23.438
18.75
15.625
12.5
3.906
3.125
0101
32
11.718
9.375
7.813
6.25
1.953
1.562
0110
64
5.859
4.688
3.906
3.125
166.666
133.333
0111
128
500
400
1.953
1.562
83.333
66.666
1000
1.5
250
200
166.666
133.333
41.666
33.333
1001
3
125
100
83.333
66.666
20.833
16.666
1010
6
62.50
50
41.666
33.333
10.416
8.333
1011
12
31.25
25
20.833
16.666
5.208
4.166
1100
24
15.625
12.50
10.416
8.333
2.604
2.083
1101
48
7.813
6.25
5.208
4.166
1.302
1.042
1110
96
3.906
3.125
2.604
2.083
0.651
0.521
1111
192
1.953
1.5625
1.302
1.042
0.3255
0.2605
12
Rev. C – 22 Feb. 01
TSS463
7. VAN Protocol
7.1. Line Interface
There are three line inputs and one line output available
on the TSS463. Which of the three inputs to use is either
programmable by software or automatically selected by
a diagnosis system.
The diagnosis system continuously monitors the data
received through the three inputs, and compares it with
each other and the selected bitrate. It then chooses the
most reliable input according to the results.
The data on the line is encoded according to the VAN
standard ISO/11519-3. This means that the TSS463 is
using a two level signal having a recessive (1) and a
dominant (0) state. Furthermore, due to the simple
medium used, all data transmitted on the bus is also
received simultaneously.
The VAN protocol is hence a CSMA/CD (Carrier Sense
Multiple Access Collision Detection) protocol, allowing
for continuous bitwise arbitration of the bus, and
non-destructive (for the higher priority message)
collision detection.
Arbitration field
Node a: TxD
R
D
Node b: TxD
R
D
Node c: TxD
R
D
On Bus: DATA
R
D
2
Node a loses the arbitration
Node a releases the bus
3
1
R: Recessive level
Node b wins the arbitration
Node c loses the arbitration
Node c releases the bus
D: Dominant level
Figure 13. CSMA/CD Arbitration
In addition to the VAN specification there is also a
pulsed coding of the dominant and recessive states. This
mode is intended to be used with an optical or radio link.
In this mode the dominant state for the transmitter is a
low pulse, (2x prescaled clocks at the beginning of the
bit) and the recessive state is just a high level. When
receiving in this mode it is not the state of the signal itself
Rev. C – 22 Feb. 01
which is decoded, but the edges. Also, reception is
imposed on the RxD0 input, and the diagnosis system
does not operate correctly.
In addition in this mode there is an internal loopback in
the circuit since optical transceivers are not able to
receive the signal that they themselves transmit.
13
TSS463
VAN BUS
SEQUENCE
NORMAL OR PULSED RECESSIVE
STATE
VAN BUS
SEQUENCE
NORMAL DOMINANT STATE
VAN BUS
SEQUENCE
PULSED DOMINANT STATE
NUMBER OF
PRESCALED
CLOCKS
0
2
4
6
8
10
12
14
16
Figure 14. State Encoding.
In Figure 14. the pulsed waveforms are shown. In
Figure 17. through Figure 23. the low “timeslots” (i.e.
blocks of 16 prescaled clocks) should be replaced by the
dominant waveform showed in Figure 14. , if the correct
representations for pulsed coding are to be seen.
7.2. VAN Frame
SOF
COMMAND
IDENTIFIER
FIELD
DATA FIELD
EXT RAK R/W RTR
FRAME
CHECK EOD ACK EOF
SUM
Figure 15. Van Bus Frame.
D Second, the Synchronous access module. It cannot
transmit SOF sequences, but it can initiate data
transfers and can receive messages.
D And finally, the Slave module, which can only
transmit using an in-frame mechanism and can
receive messages.
The VAN bus supports three different module (unit)
types:
D First, the Autonomous module, which is a bus master.
It can transmit Start Of Frame (SOF) sequences, it
can initiate data transfers and can receive messages.
Autonomous
Rank 0
SOF
ID
COM
DATA
FCS
EOD ACK
EOF
COM
DATA
FCS
EOD ACK
EOF
DATA
FCS
EOD ACK
EOF
Synchronous
Rank 1
ID
Rank 16
RTR
Slave
Figure 16. Hierarchical Access Methods
14
Rev. C – 22 Feb. 01
TSS463
Figure 15. shows a normal VAN bus frame. It is initiated
with a Start Of Frame (SOF) sequence shown in
Figure 17. The SOF can only be transmitted by an
autonomous module. During the preamble the TSS463
will synchronize its bit rate clock to the data received.
VAN BUS
START
SYNC
PREAMBLE
SEQUENCE
START OF FRAME
VAN BUS
END OF
DATA
SEQUENCE
NUMBER OF
PRESCALED
CLOCKS
0
16
ACK
32
48
END OF FRAME
64
80
96
112 128 144
160 176 192
Figure 17. Framing Sequences.
When the complete SOF sequence has been transmitted
or received, the circuit will start the transmission or
reception of the identifier field.
All data on the VAN bus, including the identifier and
Frame Check Sum (FCS), are transmitted using
enhanced Manchester code.
In enhanced Manchester code three NRZ bits are
transmitted first followed by one Manchester bit, then
VAN BUS
SEQUENCE
three more NRZ bits followed by one Manchester bit and
so on.
Since the high state is recessive and the low state is
dominant, the bus arbitration can be done. If a module
wants access to the bus, it must first listen to the bus
during one full End Of Frame (EOF) and one full Inter
Frame Spacing (IFS) period, to determine whether the
bus is free or not (i.e. no dominant states received).
NRZ “0”
NRZ “1”
VAN BUS
SEQUENCE
MANCHESTER “0”
VAN BUS
SEQUENCE
MANCHESTER “1”
NUMBER OF
PRESCALED
CLOCKS
0
8
16
24
32
Figure 18. Data Encoding.
Rev. C – 22 Feb. 01
15
TSS463
The IFS is defined to be a minimum of 64 prescaled
clocks periods. The TSS463, accepts an IFS of zero
prescaled clocks for the reception only of a SOF
sequence.
Once the bus has been determined as being free, the
module must now, if it is an autonomous module, emit
a SOF sequence or, if it is a synchronous access module,
wait until it detects a preamble sequence.
Up till this point there can be several modules
transmitting on the bus, and there is no possibility of
knowing if this is the case or not. Therefore the first field
in which arbitration can be performed is the identifier
field. Since the logical zeroes on the bus are dominant,
and all data is transmitted with the most significant bit
(MSB) first, the first module to transmit a logical zero
on the bus will be the prioritized module, i.e. the
message that is tagged with the lowest identifier will
have priority over the other messages.
It is, however, conceivable that two messages
transmitted on the bus will have the same identifier. The
TSS463 therefore continues the arbitration of the bus
throughout the whole frame. More, if the identifier in
transmission has been programmed for reception as
well, it transmits and receives messages simultaneously,
right up till the Frame Check Sequence (FCS). Only
then, if the TSS463 has transmitted the whole message,
does it discard the message received. Arbitration loss in
the FCS field is considered as a CRC error during
transmission.
This feature is called full data field arbitration, and it
enables the user to extend the identifier. For instance it
can be used to transmit the emitting modules address in
the first bytes of the data field, thus enabling the
identifier to specify the contents of the frame and the
data field to specify the source of the information.
The identifier field of the VAN bus frame is always 12
bits long, and it is always followed immediately by the
4-bit command field:
D The first bit of the command is the extension bit
(EXT). This bit is defined by the user on transmission
and is received and retained by the TSS463. To
conform with the standard it should be set to 1
(recessive) by the user, else the frame is ignored
without any IT generation.
D The second bit is the request ACKnowledge bit
(RAK). If this bit is a logical one, the receiving
16
module must acknowledge the transfer with an
in-frame acknowledgement in the ACK field. If it is
set to logical zero, then the ACK field must contain
an acknowledge absent sequence.
D Third we have the Read/Write bit (R/W). This bit
indicates the direction of the data in a frame.
− If set to zero it is a “write” message, i.e. data
transmitted by one module to be received by
another module.
− If it is set to one it implies a “read” message, i.e.
a request that another module should transmit
data to be received by the one that requested the
data (reply request message).
D Last in the command field is the Remote
Transmission Request bit (RTR). This bit is a logical
zero if the frame contains data and a logical one if the
frame does not contain data. In order to conform with
the standard a received frame included the
combination R/W. RTR = 01 is ignored without any
IT generation.
All the bits in the command field are automatically
handled by the TSS463, so the user need not to be
concerned for the encoding and decoding of these. The
command bits transmitted on the VAN bus are calculated
from the current status of the active message.
After the command field comes the data field. This is
just a sequence of bytes transmitted MSB first. In the
VAN standard the maximum message length is set to 28
bytes, but the TSS463 handles messages up to 30 bytes.
The next field is the FCS field. This field is a 15 bit CRC
checksum defined by the following generator
polynomial g(x) of order 15:
g(x) = x15+x11+x10+x9+x8+x7+x4+x3+x2+1
The division is done with a rest initialized to 0x7FFF,
and an inversion of the CRC bits is performed before
transmission.
However, since the CRC is calculated automatically
from the identifier, command and data fields by the
TSS463, it need not concern the user of the circuit. When
the frame check sequence has been transmitted, the
transmitting module must transmit an End Of Data
(EOD) sequence, followed by the ACKnowledge field
(ACK) and the End Of Frame sequence (EOF) to
terminate the transfer.
Rev. C – 22 Feb. 01
TSS463
VAN BUS
SEQUENCE
POSITIVE ACKNOWLEDGE
VAN BUS
SEQUENCE
ABSENT ACKNOWLEDGE
NUMBER OF
PRESCALED
CLOCKS
0
8
16
24
32
Figure 19. Acknowledge Sequences.
7.3. Frame Examples
The frames transmitted on the VAN bus are generated by
several modules, each supplying different parts of the
message. Figure 20. through Figure 23. show the four
frame types specified in the VAN standard, and what
module is generating the different fields.
D The most straightforward frame is the normal data
frame in Figure 20. Like all other frames it is
initiated with a SOF sequence. This sequence is
generated by a bus master (not shown in figure).
During this frame there is basically only one module
transmitting with the only exception being the
acknowledgement, generated by the receiving
module if requested in the RAK bit.
D The reply request frame with immediate reply in
Figure 21. is the only frame in which a slave module
can transmit data by filling it into the appropriate
field.
The only difference for the frame on the bus is that
the R/W bit has changed state compared to the
normal frame.
This is a highly interactive frame where a bus master
Rev. C – 22 Feb. 01
generates the SOF and the initiator generates the
identifier, the three first bits of the command, and the
acknowledge. The RTR bit, the data field, the frame
check, the EOD and the EOF are all generated by the
replying module.
D The reply request frame with deferred reply in
Figure 22. is basically the same frame as the reply
request frame with immediate reply, but since the
requested module does not generate the RTR bit the
requesting module will continue with the frame
check, the EOD and the EOF.
During this frame the requested module will only
generate the acknowledge, and only if this was
requested by the initiator through the RAK bit.
D Finally the deferred reply frame in Figure 23. which
is sent when a module has prepared a reply for a reply
request that has been received earlier.
This frame very closely mimics the normal data
frame with the only exception being the R/W bit that
has changed state.
17
TSS463
EOD
ACK
DATA
CRC
EOD
ACK
EOF
CRC
ACK
EOF
CRC
EOF
RECEIVING
module
FRAME
on bus
EOF
ACK
IDENTIFIER
CRC
EOD
SOF
DATA
ACK
IDENTIFIER
EOD
SOF
EXT
RAK
R/W
RTR
(*)
TRANSMITTING
module
EXT
RAK
R/W
RTR
(*)
With acknowledgment
EXT :
RAK :
R/W :
RTR :
ACK :
Recessive from Transmitter
Recessive for acknowledge from Transmitter
Dominant from Transmitter
– (*) Manchester bit
Dominant from Transmitter
Positive from Receiver because RAK is Recessive
SOF
IDENTIFIER
EXT
RAK
R/W
RTR
(*)
TRANSMITTING
module
DATA
SOF
IDENTIFIER
EXT
RAK
R/W
RTR
(*)
Without acknowledgment
DATA
RECEIVING
module
FRAME
on bus
EXT : Recessive from Transmitter
RAK : Dominant for no acknowledge from Transmitter
R/W : Dominant from Transmitter
– (*) Manchester bit
RTR : Dominant from Transmitter
ACK : Absent from Transmitter and from Receiver because RAK is Dominant
Figure 20. Normal Data Frame
18
Rev. C – 22 Feb. 01
DATA
CRC
EOD
ACK
EOF
DATA
CRC
EOD
ACK
EOF
REQUESTED
module
SOF
FRAME
on bus
EXT :
RAK :
R/W :
RTR :
ACK :
IDENTIFIER
ACK
RTR
(*)
IDENTIFIER
EXT
RAK
R/W
RTR
(*)
SOF
REQUESTING
module
EXT
RAK
R/W
RTR
(*)
TSS463
Recessive from Requestor
Recessive for acknowledge from Requestor
Recessive from Requestor
Recessive from Requestor and Dominant from Requestee
– (*) Manchester bit
Absent from Requestee and Positive from Requestor because RAK is Recessive
ACK
CRC
REQUESTED
module
FRAME
on bus
EOF
ACK
IDENTIFIER
ACK
SOF
CRC
EOD
IDENTIFIER
EOD
SOF
EXT
RAK
R/W
RTR
(*)
REQUESTING
module
EXT
RAK
R/W
RTR
(*)
Figure 21. Reply Request Frame with Immediate Reply
EXT
RAK
R/W
RTR
ACK
:
:
:
:
:
EOF
Recessive from Requestor
Recessive for acknowledge from Requestor
Recessive from Requestor
Recessive from Requestor – (*) Manchester bit
Absent from Requestor and Positive from Requestee because RAK is Recessive
Figure 22. Reply Request Frame with Deferred Reply
Rev. C – 22 Feb. 01
19
ACK
DATA
CRC
RECEIVING
module
FRAME
on bus
EOF
ACK
IDENTIFIER
CRC
EOD
SOF
DATA
ACK
IDENTIFIER
EOD
SOF
EXT
RAK
R/W
RTR
(*)
REPLYING
module
EXT
RAK
R/W
RTR
(*)
TSS463
EXT
RAK
R/W
RTR
ACK
:
:
:
:
:
EOF
Recessive from Replyer
Recessive for acknowledge from Replyer
Recessive from Replyer
– (*) Manchester bit
Dominant from Replyer
Absent from Replyer and Positive from Receiver because RAK is Recessive
Figure 23. Deferred Reply Frame
8. Diagnosis System
The purpose of the diagnosis system is to detect any
short or open circuits on either the DATA or DATA
lines and to permit, if it is possible, to carry the
communications on the non-defective line.
D the line receiver sensing DATA is connected to
RxD1,
D the line receiver sensing DATA is connected to
RxD2.
The diagnosis system is based on the assumption that
three separate line receivers are connected to the VAN
bus (c.f. Figure 3. ):
D One of the line receivers is connected in differential
mode, sensing both DATA and DATA signals, and is
connected to the RxD0 input.
D The other two line receivers are operating in single
wire mode and are sensing only one of the two VAN
bus signals:
The diagnosis system analyses and compares the data
sent over both VAN lines. So, the diagnosis system
executes a digital filtering and transition analyses. In
order to perform its investigation, three internal signals
are generated, RI (Return to Idle), SDC (Synchronous
Diagnosis Clock) and TIP (Transmission In Progress).
One of four operating modes can be chosen to manage
the results of the diagnosis system.
8.1. Diagnosis States
If the diagnosis system finds a failure on either of the
VAN bus signals, it changes from nominal to degraded
mode, and connects the line receiver not coupled to the
failing signal to the reception logic.
When the diagnosis system finds that the failing signal
20
is working again, it returns to nominal mode and
re-connects the differential line receiver to the reception
logic.
A major error occurs when both the VAN bus signals are
failed.
Rev. C – 22 Feb. 01
TSS463
NONIMAL
ÏÏ
ÏÏ
Ï
Ï
ÏÏ
ÏÏ
MAJOR
ERROR
DEGRATED
DEGRATED
DATA
DATA
ÏÏ
ÏÏ
- Failure during the frame.
- Default of transitions on the valid input between 2 consecutive SDC rising edges.
- Protocol fault
- In specified selection mode, every RI pulse when an EOF is detected or through an active SDC.
- In automatic selection mode and SDC active, no failure sampled by 2 consecutive SDC rising edges.
- General reset
Figure 24. Diagnosis States
Status bits give permanent information on the diagnosis
performed, whatever the programmed operating mode.
This is encoded over three bits: Sa, Sb and Sc.
− Sa and Sb bits indicate the four possible states of the
VAN bus
Table 1. Status bits: Sa & Sb
Sa
0
0
1
1
Sb
0
1
0
1
Communication
Mode
nominal
Fault
no fault on VAN bus
Status
differential communication on DATA and DATA
Mode
degraded on DATA
Fault
fault on DATA
Status
communication on DATA
Mode
degraded on DATA
Fault
fault on DATA
Status
communication on DATA
Mode
major error
Fault
fault on DATA and DATA
Status
no communication on DATA and DATA (attempt to communicate alternatively on
DATA then DATA every SDC period)
D Sc : As soon as one of the three inputs (RXD2,
RXD1, RXD0) differs from the others in the input
comparison analysis performs by the diagnosis
Rev. C – 22 Feb. 01
system, Sc is set.
The only ways to reset this status bit are through the
RI signal or a general reset.
21
TSS463
8.2. Internal Operations
8.2.1. Digital Filtering
If several spurious pulses occur during one bit, the
diagnosis for defective conductor may be corrupted. To
avoid such errors, digital filters are implemented.
Filtering operation is based on sampling of the
comparator output signals. A transition is taken into
account only if it is observed over five samples (1/16th
of timeslot).
8.2.2. Transition Analyses
These analyses are continuously done on the effective
edges on comparators after digital filtering.
D Asynchronous diagnosis
The asynchronous diagnosis is done by comparing
the number of edges on DATA and DATA.
If four edges are detected on one input and no edges
on the other during the same period, the second input
is considered faulty and the diagnosis mode will
change to one of the degraded modes.
D Transmission diagnosis
The transmission compares RxD1 and RxD2 inputs
(through the input comparators and the filters) with
the data transmitted on TxD output.
At a time when the transmission logic generates a
dominant - recessive transition, the inputs can give
different values. Taking into account the filtering
delay, the bus line seen as dominant is assumed to be
correct, the other one, recessive, is considered faulty.
The diagnosis mode is changed to reflect that.
D Synchronous diagnosis
The synchronous diagnosis counts the number of
edges on the data input connected to the reception
logic during one SDC period.
If there are less than four edges during one SDC
period, the diagnosis mode will change to the major
error mode.
D Protocol fault
The protocol fault is detected by counting the
number of consecutive dominant timeslots.
If eight consecutive timeslots are dominant, the
diagnosis mode will change to the major error mode.
8.3. Generation of Internal Signals
8.3.1. RI Signal (Return to Idle)
This signal is used to return to nominal mode in the three
specified selection modes (see sections 8.1. and 8.4.).
The RI signal is disabled in automatic selection mode.
detected. So, at the end of each frame, the user, regarding
the diagnosis status bit Sa, Sb & Sc, can make its own
choice.
The RI signal is a pulse generated when an EOF is
8.3.2. SDC Signal (Synchronous Diagnosis Clock)
This time base is used by diagnosis system in automatic
selection mode (see section 8.4. ) when no event is
recorded on the bus.
The SDC is generated either by a special SDC divider
connected to the timeslot clock, either manually. The
SDC clock period must be long compared to the timeslot
duration.
A typical SDC period should be greater than the
maximum frame length appearing on the VAN network.
8.3.3. TIP Signal (Transmission In Progress)
This signal must be enabled to allow the transmission
diagnosis (see section 8.2.2.).
22
The TIP turns on synchronously with the beginning of
the transmission:
− for asynchronous bus access, the beginning of SOF,
− for synchronous bus access, the beginning of the
identifier field,
− for a request of in frame reply, the RTR bit of the
command field.
Rev. C – 22 Feb. 01
TSS463
The TIP turns off synchronously with the end of the
transmission:
− after EOF
− after a losing of arbitration or a code violation
detection
− for a requestor of in frame reply, when the arbitration
is lost on RTR the bit.
This signal is not generated when the transmission logic
only sends an ACK.
8.4. Programming Modes
Four programming modes determine the way to use the
three different inputs and the diagnosis system.
− 3 specified selection modes
− 1 automatic selection mode
Table 2. Programming modes
Ma
Mb
0
0
Differential communication
0
1
Degraded communication on RxD2 (DATA)
1
0
Degraded communication on RxD1 (DATA)
1
1
Automatic selection according the diagnosis status
Rev. C – 22 Feb. 01
Operating mode
23
TSS463
9. Registers
The TSS463 memory map consists of three different
areas, the Control & Status registers, the Channel
registers and the Message data (or Mailbox).
9.1. Mapping
0x78 to 0x7F (r/w)
Channel
13
Channel 13
0x70 to 0x77 (r/w)
Channel 12
0x68 to 0x6F (r/w)
Channel 11
0x60 to 0x67 (r/w)
Channel 10
0x58 to 0x5F (r/w)
Channel 9
0x50 to 0x57 (r/w)
Channel 8
0x48 to 0x4F (r/w)
Channel 7
0x40 to 0x47 (r/w)
Channel 6
0x38 to 0x3F (r/w)
Channel 5
0x30 to 0x37 (r/w)
Channel 4
0x28 to 0x2F (r/w)
Channel 3
0x20 to 0x27 (r/w)
Channel 2
0x18 to 0x1F (r/w)
Channel 1
0x10 to 0x17 (r/w)
Channel 0
0x0C to 0x0F
Data Byte 127
0xFF
0x7F (r/w)
0x7E (r/w)
ID_Mask [3..0]
ID_Mask [11..4]
0x7C & 0x7D
Reserved
Reserved
0x7B (r/w) Message Length + Status
0x7A (r/w) DRAK + Message Address
0x79 (r/w) ID_TAG (lsb) + COM
ID_TAG (msb)
0x78 (r/w)
Channel 13 Registers
0x17 (r/w)
ID_Mask [3..0]
ID_Mask
ID_Mask [11..4]
[11..4]
0x16 (r/w)
Reserved
0x14 & 0x15
0x13 (r/w) Message Length + Status
0x12 (r/w) DRAK + Message Address
0x11 (r/w) ID_TAG [3..0] + COM
0x10 (r/w)
ID_TAG [11..4]
Channel 0 Registers
Reserved
0x8C
0x8B
0x8A
0x89
0x88
0x87
0x86
0x85
0x84
0x83
0x82
0x81
0x80
Interrupt Reset
0x0B (w)
Interrupt
Enable (0x80)
0x0A (r/w)
Interrupt
Status
(0x80)
0x09 (r)
Reserved
0x08
Last Error Status (0x00)
0x07 (r)
Last
Message Status (0x00)
0x06 (r)
Transmit
Status (0x00)
0x05 (r)
Line
Status
(0bx01xxx00)
0x04 (r)
Command
(0x00)
0x03 (w)
Diagnosis
Control
(0x00)
0x02 (r/w)
0x01 (r/w) Transmit Control (0x02)
Line Control (0x00)
0x00 (r/w)
Register
Data Byte 12
Data Byte 11
Data Byte 10
Data Byte 9
Data Byte 8
Data Byte 7
Data Byte 6
Data Byte 5
Data Byte 4
Data Byte 3
Data Byte 2
Data Byte 1
Data Byte 0
Message
Figure 16. Memory Map.
Note 1: All the non specified addresses between 0x00 and 0x7F are
considered as absent.
Note2: (r) means read only register.
(w) means write only register.
(r/w) means read/write register.
24
Note 3: Value after RESET is found after register name. If no value is
given, the register is not initialized at RESET.
Rev. C – 22 Feb. 01
TSS463
9.2. Control and Status Registers
9.2.1. Line Control Register (0x00) :
7
6
5
4
3
2
1
0
CD3
CD2
CD1
CD0
PC
0
IVTX
IVRX
D Read/write register.
D Default value after reset : 0×00
D reserved : Bit 2, this bit must not be set by the user ;
a 0 must always be written to this bit.
CD[3:0] : Clock Divider.
They control the VAN Bus rate through a Baud Rate
generator according to the formula below :
f(XTAL1)
f(TSCLK) +
n 16
IVTX : Invert TxD output
IVRX : Invert RxD inputs
The user can invert the logical levels used on either the
TxD output or the RxD inputs in order to adept to
different line drivers and receivers.
One : A one on either of these bits will invert the
respective signals.
Zero : (default at reset) The TSS463 will set TxD to
recessive state in Idle mode and consider the bus free
(recessive states on RxD inputs).
PC : Pulsed Code
One : The TSS463 will transmit and receive data using
the pulsed coding mode (i.e optical or radio link mode).
The use of this mode implies communication via the
RxD0 input and the non-functionality of the diagnosis
system.
Zero : (default at reset) The TSS463 will transmit and
receive data using the Enhanced Manchester code.
(RxD0, RxD1, RxD2 used).
9.2.2. Transmit Control Register (0x01) :
7
6
5
4
3
2
1
0
MR3
MR2
MR1
MR0
VER2
VER1
VER0
MT
D Read/Write register.
D Default value after reset : 0x02
MR[3:0] : Maximum Retries.
These bits allow the user to control the amount of retries
the circuit will perform if any errors occurred during
transmission.
Rev. C – 22 Feb. 01
25
TSS463
Table 2. Retries
MR [3:0]
Max. Nb of retries
Max. Nb of transmissions
0000
0
1
0001
1
2
0010
2
3
0011
3
4
0100
4
5
0101
5
6
0110
6
7
0111
7
8
1000
8
9
1001
9
10
1010
10
11
1011
11
12
1100
12
13
1101
13
14
1110
14
15
1111
15
16
Note : Bus contention is not regarded as an error and that
an infinite number of transmission attempts will be
performed if bus contention occurs continuously.
MT: Module type
The three different module types are supported (see
section 7.2.):
VER[2:0] = 001 : DLC Version after reset.
These bits must not be set by user. 001 must always be
written to these bits.
One: The TSS463 is at once an autonomous module
(Rank 0), an synchronous access module (Rank 1) or a
slave module (Rank 16).
Zero: The TSS463 is at once an synchronous access
module (Rank 1) or a slave module (Rank 16).
9.2.3. Diagnosis Control Register (0x02) :
7
6
5
4
3
2
1
0
SDC3
SDC2
SDC1
SDC0
Ma
Mb
ETIP
ESDC
D Read/Write register
D Default value after reset : 0×00.
The diagnosis is discussed in greater detail in section 8.
of this chapter.
D In its four high order bits the user can program the
SDC rate SDC [3:0],
D In its two medium order bits the diagnosis system
mode is controlled : M1, M0.
26
D In the two low order bits, the user controls if the SDC
and TIP are to be generated automatically ETIP,
ESDC.
SDC [3:0] : SDC divider
The input clock is the time slot clock.
Rev. C – 22 Feb. 01
TSS463
Table 3. System Diagnosis Clock Divider
SDC DIVIDER SDC [3:0]
Divide by
0000
64
0001
128
0010
256
0011
512
0100
1024
0101
2048
0110
4096
0111
8192
1000
16384
1001
32768
1010
65536
1011
131072
1100
262144
1101
524288
1110
1048576
1111
2097152
SDC calculation: (see section 8.3.2)
For each module, determine the largest interframe spacing, LIFS (*).
For the whole network, get the maximum LIFS, MAX–LIFS.
SDC period ≥ MAX–LIFS.
(*) IFS min = 4 TS
Example: For VAN frame speed rate = 62,5 KTS/s (1 TS= 16 ms), SDC ≥ 100 ms
⇒ 100 ms / 16 ms = 6250, divider chosen: 8192, SDC [3:0] = 0111.
Ma, Mb : Operating mode command bits
Table 4. Diagnosis System Command Bits
Ma
Mb
0
0
Forces the Communication on RxD0 (differential)
0
1
Forces the Communication on RxD2 (DATA)
1
0
Forces the Communication on RxD1 (DATA)
1
1
Automatic selection
ETIP : Enable Transmission In Progress
The Transmission In Progress (TIP), tells the diagnosis
system to enable transmission diagnosis.
ESDC : Enable System Diagnosis Clock
The Synchronous Diagnosis Clock (SDC), controls the
cycle time of the synchronous diagnosis.
One : Enable TIP generation
Zero : Disable TIP generation.
One : Enable SDC divider.
Zero : Disable SDC divider.
Rev. C – 22 Feb. 01
27
TSS463
9.2.4. Command Register (0x03) :
7
6
5
4
3
2
1
0
GRES
SLEEP
IDLE
ACTI
REAR
0
0
MSDC
D Write only register.
D Reserved : Bit 1, 2 these bit must not be set by the
user ; a zero must always be written to these bit.
D If the circuit is operating at low bitrates there might
be a considerable delay between the writing of this
register and the performing of the actual command
(worst case 6 timeslots). The user is therefore
recommended to verify, by reading the Line Status
Register (0x04), that the commands have been
performed.
GRES : General Reset
The Reset circuit command bit performs, if set, exactly
as if the external reset pin was asserted. This command
bit has its own auto-reset circuitry.
One : Reset active
Zero : Reset inactive
SLEEP : Sleep command (see section 14.2.).
If the user sets the Sleep bit, the circuit will enter sleep
mode. When the circuit is in sleep mode, all non-user
registers are setup to minimize power consumption.
Read/write accesses to the TSS463 via the SPI/SCI
interface are impossible, the oscillator is stopped.
IDLE : Idle command (see section 14.1.).
If the user sets the Idle bit, the circuit will enter idle
mode. In idle mode the oscillator will operate, but the
TSS463 will not transmit or receive anything on the bus,
and the TxD output will be in three state
One : Idle active
Zero : Idle inactive
ACTI : Activate command (see section 14.1.).
The Activate command will put the circuit in the active
mode, i.e it will transmit and receive normally on the
bus. When the circuit is in activate mode the TxD
three-state output is enabled.
One : Activate active
Zero : Activate inactive
REAR : Re-Arbitrate command.
This command will, after the current attempt, reset the
retry counter and re-arbitrate the messages to be
transmitted in order to find the highest priority message
to transmit.
One : Re-arbitrate active
Zero : Re-arbitrate inactive
To exit from this mode the user must apply either an
hardware reset (external RESET pin) either an
asynchronous software reset (via the SPI/SCI interface).
MSDC : Manual System Diagnosis Clock.
Rather than using the SDC divider described in section
9.2.3., the user can use the manual SDC command to
generate a SDC pulse for the diagnosis system.
One : Sleep active
Zero : Sleep inactive
This MSDC pulse should be high at least 2 time slot
clock.
28
Rev. C – 22 Feb. 01
TSS463
9.2.5. Line Status Register (0x04) :
7
6
5
4
3
2
1
0
SPG
IDG
Sc
Sb
Sa
TXG
RXG
D Read only register.
D Default value after reset : 0bx01xxx00.
D This register reports the operation mode of the
TSS463 in the Sleep an Idle bits (Command Register
located at address 0×03) as well as the diagnosis
system status bits Sa to Sc discussed in section 8.
SPG : Sleeping
IDG : Idling.
Default mode at reset
Sa, Sb and Sc : Diagnosis system status bits
D Sa and Sb
Table 5. Diagnosis System Status Bits
Sb
Sa
COMMUNICATION INDICATION
0
0
Nominal mode, differential communication
0
1
Degraded over DATA, fault on DATA
1
0
Degraded over DATA, fault on DATA
1
1
Major error, fault on DATA and DATA
D Sc : As soon as one of the three inputs (RxD2, RxD1,
RxD0) differs from the others in the input
comparison analysis performs by the diagnosis
system, Sc is set.
The only ways to reset this status bit are through the
RI signal or a general reset.
TXG : Transmitting.
If this status bit is active, it indicates that the TSS463 has
chosen an identifier to transmit, and it will continue to
make transmission attempt for this message until it
succeeds or the retry count is exceeded.
RXG : Receiving.
The receiving indicates that there is activity on the bus.
Note : For safe modification of active channel registers
both bits should be inactive (except “abort” command).
9.2.6. Transmission Status Register (0x05) :
7
6
5
4
3
2
1
0
NRT3
NRT2
NRT1
NRT0
IDT3
IDT2
IDT1
IDT0
D Read only register.
D Default value after reset : 0x00.
D The transmission Status register contains the number
of retries made up-to-date, according to the
Table 2. , and the channel currently in transmission.
NRT [3:0] : Number of retries done in transmission.
IDT [3:0] : Channel number currently in transmission.
Rev. C – 22 Feb. 01
29
TSS463
9.2.7. Last Message Status Register (0x06) :
7
6
5
4
3
2
1
0
NRTR3
NRTR2
NRTR1
NRTR0
IDTR3
IDTR2
IDTR1
IDTR0
D Read only register.
D Default value after reset : 0x00.
D This register is basically the same as the transmission
status register. It contains the last identifier number
that was successfully transmitted, received or
exceeded its retry count.
If it was a successful transmission, the number of
retries performed can be seen in this register as well.
NRTR [3:0] : Number of retries done successfully in
transmission. In case of reception NRTR[3:0] is
undefined.
IDTR [3:0] : Channel number that was successfully
transmitted, received or exceeded its retry count.
9.2.8. Last Error Status Register (0x07) :
7
6
5
BOC
BOV
4
D Read only register.
D Default value after reset : 0×00.
D The Last Error Status Register contains the error
code for the last transmission or reception attempt.
It is updated after each attempt, i.e. several error
codes can be reported during one single transmission
(with several retries).
BOC : Buffer occupied.
D when one channel configured in “Reply request”
mode has its “received” bit set when it attempts to
transmit its request.
D BOC with the link capability between two channels
sharing the same received buffer, is set when
one channel has already set its “received” bit in its
“Message length and status Channel register” and a
receive is attempt on the other one.
30
3
2
1
0
FCSE
ACKE
CV
FV
BOV : Buffer overflow.
BOV indicates that the buffer length setup in the
Channel Status Register was shorter than the number of
bytes received plus 1, and thus, some data was lost.
One : BOV active
Zero : BOV inactive
FCSE : Framing Check Sequence Error.
FCSE indicates a mismatch between the FCS received
and the FCS calculated
One : FCSE active
Zero : FCSE inactive
Rev. C – 22 Feb. 01
TSS463
ACKE : Acknowledge Error.
ACKE indicates a physical violation or collision on
ACK field of the frame when the TSS463 is producer.
One : ACKE active
Zero : ACKE inactive
RAK = 0
DLC: Producer
EOD field
ACK field
expected
ACKE = 0
received
ACKE = 1
received
ACKE = 1
received
ACKE = 1
RAK* = 1
*RAK: bit of the frame COMMAND field
EOD field
ACK field
expected
ACKE = 0
received
ACKE = 1
received
ACKE = 1
received
ACKE = 1
Figure 25. ACKE Status bit
CV : Code Violation.
CV indicates:
D either a Manchester code violation (2 identical TS on
Manchester bit), or a physical violation (transmitted
bit “dominant”, received bit “recessive”), on fields
ID, COM, DATA and CRC.
D either a physical violation or collision on field
“preamble” and the “recessive” bit of the “Star
Sync” field.
One : CV active
Zero : CV inactive
Rev. C – 22 Feb. 01
31
TSS463
FV : Frame Violation.
FV indicates a physical violation or collision on ACK
field of the frame when the TSS463 is consumer.
One : FV active
Zero : FV inactive
DLC:
Consumer
EOD field
ACK field
expected
FV = 0
received
FV = 1
received
FV = 1
received
FV = 1
EOD field
ACK field
expected
FV = 0
received
FV = 1
received
FV = 1
received
FV = 1
Figure 26. FV Status bit
9.2.9. Interrupt Status Register (0x09) :
7
6
5
RST
4
3
2
1
0
TE
TOK
RE
ROK
RNOK
D Read only register.
D Default value after reset : 0×80
RST : Reset interrupt.
RE indicates that the circuit has detected a valid reset
command via the RESET pin or the reset command bit
GRES. This interrupt cannot be disabled, since its
enable bit is set when a reset is detected.
1st TX
2nd TX
TE : Transmit error status flag (or exceeded retry).
This flag is set only when the Max number of
transmission (1+MR [3:0]) is reached with error of
transmission.
3rd TX
set TE
set CHER
set CHTx
Figure 27. Exceeded retry with MR[3..0] = 3
32
Rev. C – 22 Feb. 01
TSS463
TOK : Transmit OK status flag.
RNOK : Receive “with no RAK (RAK=0)” OK status
flag.
RE : Receive error status flag.
One : Status flag activated
Zero : No status flag.
ROK : Receive “with RAK (RAK=1)” OK status flag.
9.2.10. Interrupt Enable Register (0x0A) :
7
6
5
4
3
2
1
0
1
0
0
TEE
TOKE
REE
ROKE
RNOKE
D Read/write register.
D Default value reset : 0x80
REE : Reception Error Enable.
Note : On reset the Reset Interrupt Enable bit is set to 1
instead of 0, as is the general rule.
ROKE : Reception “with RAK” OK enable.
TEE : Transmit Error Enable
One : IT enabled.
Zero : IT disabled.
RNOKE : Reception “with no RAK” OK enable.
TOKE : Transmission OK Enable.
9.2.11. Interrupt Reset Register (0x0B) :
7
6
5
4
3
2
1
0
RSTR
0
0
TER
TOKR
RER
ROKR
RNOKR
D Write only register.
D Reserved bit : 5 and 6. This bit must not be set by
user; a zero must always be written to this bit.
RER : Receive Error status flag Reset.
RSTR : Reset Interrupt Reset.
RNOKR : Receive “with no RAK” OK status flag
Reset.
ROKR : Receive “with RAK” OK status flag Reset.
TER : Transmit Error status flag Reset.
One : Status flag reset.
Zero : Status flag unchanged.
TOKR : Transmit OK status flag Reset.
RST
TE
Internal
RESET
TOK
Flag
Write
TEE
RSTR
Rev. C – 22 Feb. 01
TER
RE
ROK
RNOK
Interrupt Status
Register
INT
Flag
Flag
Write
Write
TOKE
TOKR
REE
Flag
Flag
Write
Write
ROKE
RER
ROKR
Pin 3
RNOKE
Interrupt Enable
Register
Reset
RNOKR Interrupt
Register
33
4 TS
ÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇ
ID+COM+DATA+CRC
EOD
SOF
BUS
ACK
TSS463
6 TS
Set TXG
Set RXG
Reset RXG, TXG
1 to 2 TS
Line status register (0x04)
INT
4 TS
Write “IT Status Register”
Write “Last error Register”
Write “Last message Register”
Write “Message Status”
Write “Message Length & Status Register”
Figure 28. Update of the Status Register
9.3. Channel Registers
There is a total of 14 channel register sets, each
occupying 8 bytes for addressing simplicity, integrated
into the circuit. Each set contains two 2x8-bit registers
for the identifier tag, identifier mask and command
fields plus two 1x8-bit registers for DMA pointers and
message status.
The base_address of each set is:
(0x10 + (0x08 * channel_number)).
When the TSS463 is reseted either via the external
RESET pin or the general reset command, the channel
registers are not affected. That is, on power-up of the
circuit, all the channel registers start with random
values.
Due to this fact, the user should take care to initialize all
the channel registers before exiting from idle mode. The
easiest way to disable an channel register is to set the
received and transmitted bits to 1 in the Message Length
& Status Register.
Table 3: Channel Register Sets Map
34
Channel Number
From
To
Channel Number
From
To
6
0x40
0x47
13
0x78
0x7F
5
0x38
0x3F
12
0x70
0x77
4
0x30
0x37
11
0x68
0x6F
3
0x28
0x2F
10
0x60
0x67
2
0x20
0x27
9
0x58
0x5F
1
0x18
0x1F
8
0x50
0x57
0
0x10
0x17
7
0x48
0x4F
Rev. C – 22 Feb. 01
TSS463
Table 4: Channel Register Set Structure
Reg. Name
Offset
bit 7
bit 6
bit 5
ID_MASK
0x07
ID_MASK
0x06
(no register)
0x05
x
x
x
(no register)
0x04
x
x
x
MESS_L / STA
0x03
MESS_PTR
0x02
ID_TAG / CMD
0x01
ID_TAG
0x00
bit 4
bit 3
bit 2
bit 1
bit 0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
CHER
CHTx
CHRx
RAK
RNW
RTR
ID_M [3:0]
ID_M [11:4]
M_L [4:0]
DRACK
M_P [6:0]
ID_T [3: 0]
EXT
ID_T [11:4]
9.3.1. Identifier Tag and Command Registers:
The identifier tag and command registers is located at
the base_address and base_address + 1. It allows the user
to specify the full 12-bit identifier field of the ISO
standard and the 4-bit command.
7
6
5
4
3
2
1
0
ID_T 3
ID_T 2
ID_T 1
ID_T 0
EXT
RAK
RNW
RTR
7
6
5
4
3
2
1
0
ID_T 11
ID_T 10
ID_T 9
ID_T 8
ID_T 7
ID_T 6
ID_T 5
ID_T 4
D Read / Write registers.
ID_T [11:0]: Identifier Tag.
Upon a reception hit (i.e, a good comparison between
the identifier received and an identifier specified, taking
the comparison mask into account, as well as a status and
command indicating a message to be received), the
identifier tag bits value will be rewritten with the
identifier bits actually received.
EXT, RAK, RNW & RTR: (See section 11.).
No comparison will be done on the command bits,
Rev. C – 22 Feb. 01
base_address
+ 0x01
base_address
+ 0x00
excepted on EXT bit. The RAK, RNW and RTR bits will
be written into the first byte of the Message upon a
reception hit.
The RNW and RTR bits, as well as the status bits in the
length and status register, must be in a valid position for
reception or transmission. If not, the message
corresponding to this identifier is considered as inactive
or invalid.
The way of knowing if an acknowledge sequence was
requested or not is to check the first byte of the Message.
35
TSS463
9.3.2. Message Pointer Register:
The message pointer register at address (base_address +
0x02) is 8 bits wide. It indicates where in the Message
DATA RAM area the message buffer is located.
7
6
5
4
3
2
1
0
DRAK
M_P 6
M_P 5
M_P 4
M_P 3
M_P 2
M_P 1
M_P 0
D Read / Write register.
base_address
+ 0x02
address. If the message buffer length value is illegal (i.e.
zero), this register is redefined as being a link pointer,
thus containing the channel number of the channel that
contains the actual message pointer, message length and
received status. However, the identifier, mask, error and
transmitted status used will be that of the originally
matched channel. In any case, if a link is intended, the
three high bits of M_P [6:0] should be set to 0.
This allows several channels to use the same actual
reception buffer in Message DATA RAM, thus
diminishing the memory usage.
DRAK: Disable RAK (used in ’spy mode’).
In reception: whatever is the RAK bit of the incoming
valid frame, no ACK answer will be set. If the message
was successfully received, an IT is set (ROK or RNOK).
In transmission: no action.
One: disable active, ’spy mode’.
Zero: disable inactive, normal operation.
M_P [6:0]: Message pointer.
Since the Message DATA RAM area base address is
0x80, the value in this register is the offset from that
Note : Only 1 level of link is supported.
9.3.3. Message Length And Status Register:
The message length and status register at address
(base_address + 0x03) is also 8 bits wide. It indicates the
length of reserved for the message in the Message DATA
RAM area.
7
6
5
4
3
2
1
0
M_L 4
M_L 3
M_L 2
M_L 1
M_L 0
CHER
CHTx
CHRx
D Read / Write register.
M_L [4:0]: Message Length
The 5 high bits of this register allows the user to specify
either the length of the message to be transmitted, or the
maximum length of a message receivable in the pointed
reception buffer.
Note : The first byte in this register does not contain data,
but the length of the message received. This implies that
base_address
+ 0x03
the length value has to be equal to or greater than the
maximum length of a message to be received in this
buffer (or the length of a message to be transmitted) plus
1, thus allowing a maximum length of 30 bytes and a
minimum length of 0 byte.
If the value of this field is “illegal” (i.e 0x00) then this
message pointer is defined as being a link (see Message
pointer & register and section 15.).
M_L [4:0] = 0x00
Linked channel
M_L [4:0] = 0x01
Frame with no DATA field (*)
M_L [4:0] = 0x02
Frame with 1 DATA byte
-------
----------------------
M_L [4:0] = 0x1D
Frame with 28 DATA bytes
M_L [4:0] = 0x1E
Frame with 29 DATA bytes
M_L [4:0] = 0x1F
Frame with 30 DATA bytes
(*) Different of a reply request frame with no in-frame reply (deferred reply)..
36
Rev. C – 22 Feb. 01
TSS463
CHER: Channel error status and abort command.
As status, this bit is set by the TSS463 when error occurs
in transmission or on a received frame. The user must
reset it.
To abort the transmission defined in the channel, this bit
can bit set to 1 by the user (see section 13. and 13.3.)
CHRx: Channel received and receive enable command.
The 2 low order bits of this register contains the message
status. Together with the RNW and RTR bits of the
command register (base_address + 0x01), they define
the message type of this channel (selection 11.). As a
general rule (see section 13.3.), the status bits are only
set by the TSS463, so the user must reset them to perform
a transmission (CHTx) or/and a reception (CHRx). The
received and transmitted bits are only set if the
corresponding frame is without errors or if the retry
count has been exceeded.
CHTx: Channel transmitted and transmit enable
command.
9.3.4. Identifier Mask Registers:
The Identifier Mask registers (base_address + 0x06 and
base_address + 0x07) allow bitwise masking of the
comparison between the identifier received and the
identifier specified.
7
6
5
4
3
2
1
0
ID_M 3
ID_M 2
ID_M 1
ID_M 0
0
0
0
0
7
6
5
4
3
2
1
0
ID_M 11
ID_M 10
ID_M 9
ID_M 8
ID_M 7
ID_M 6
ID_M 5
ID_M 4
base_address
+ 0x07
base_address
+ 0x06
D Read / Write registers.
ID_M [11:0]: Identifier Mask
A value of 1 indicates comparison enabled.
A value of 0 indicates comparison disabled.
Rev. C – 22 Feb. 01
37
TSS463
10. Mailbox
The mailbox contents all the messages received or to be
transmitted. Each messages is link to a channel. The
Mailbox RAM area has 128 bytes and is mapped from
0x80 to 0xFF (see section 9.1.).
The message is pointed by the Message Pointer Register
of the channel, the length of the message is given by the
Message Length & Status Register of the channel
(sections 9.3.2. and 9.3.3.). This area is a pure RAM, it
contents a random value after reset.
The message (or message buffer) is composed of:
D 1 byte of message status (only used in receiving),
D n bytes of data. These data are the bytes of the DATA
field of the frame with the same organization.
Message Length & Status Register
CHER CHTx CHRx
received
DATA n
received
DATA 0
RAK RNW RTR M_L [4..0] = n+1
M_P + 0x80 + n + 2
M_P + 0x80
DATA 0
DATA n
FCS
ACK
received
EOD
RTR
RNW
ID [11..0]
EXT
RAK
received received received
SOF
M_P [6..0]
DRAK
Message
( M_L >= n + 2 )
M_L [4..0]
Message Pointer Register
EOF
Received DATA Frame, immediate or deffered reply
Figure 29. Message buffer structure for reception
38
Rev. C – 22 Feb. 01
TSS463
Message Length & Status Register
Message Pointer Register
CHER CHTx CHRx
M_L [4..0]
M_P [6..0]
DRAK
( M_L >= n + 2 )
Message
M_P + 0x80 + n + 2
transmitted DATA n
transmitted DATA 0
DATA 0
DATA n
FCS
ACK
M_P + 0x80
EOD
RTR
ID [11..0]
RNW
SOF
EXT
RAK
(nothing)
EOF
Transmitted DATA Frame
Figure 30. Message buffer structure for transmission
10.1. Message Status (pointed by: Message Pointer Register)
7
6
5
4
3
2
1
0
RRAK
RRNW
RRTR
RM_L4
RM_L3
RM_L2
RM_L1
RM_L0
D (no significant value in case of message to be
transmitted)
RRAK: Received RAK bit.
This bit is the RAK bit coming from the COM field of
the received frame.
RRNW: Received RNW bit.
This bit is the RNW bit coming from the COM field of
the received frame.
Rev. C – 22 Feb. 01
RRTR: Received RTR bit.
This bit is the RTR bit coming from the COM field of the
received frame.
RM_L[4:0]: Message length of the received frame.
If the DATA field of the received frame included DATA0
to DATAn, RM_L[4:0] = n+1, even if the reserved
length (Message Length & Status Register) is larger.
39
TSS463
Frame Type
Node x
Commu–
nication
Node A
I, P
C
Data Frame
Immediate
Reply
Deferred
Reply
Message Status on Node A after IT(*)
I, C
RAK
RNW
RTR
length
RAK
RNW
RTR
previous
value
RAK
RNW
RTR
previous
value
P
I, C
P
C
I, P
Data Frame
Immediate
Reply
Deferred
Reply
previous values
P
I, C
P
RAK
RNW
RTR
length
RAK
RNW
RTR
length
I, C
P: Producer
I: Initiator
C: Consumer
(*) After IT ROK or RNOK. In case of IT RE, the values can be erroneous.
Figure 31. Message Status updating
10.2. Message Data (string pointed by: Message Pointer Register + 1)
7
6
5
4
3
2
1
0
–––
–––
-– – –
–––
DATAn
–––
–––
–––
–––
DATA0
DATA0 is the first received (or transmitted) byte,
DATAn is the last one.
Note 1: If the length reserved (in the message length &
status register) for an incoming frame is 2 bytes greater
or more, the TSS463 will write the 2 bytes of the CRC
field in the message string just after DATAn.
Because the VAN frame does not content a message
length, the only way for the component to know the
40
length of the DATA field is either the message length
register value, either the EOD field detection. When the
reserved length is too large, at the moment when it
detects the EOD, the TSS463 has already written the 2
bytes of the CRC field, considering these bytes as
normal DATA.
Note 2: The Mailbox RAM area is a circular buffer. The
next location after 0xFF is 0x80.
Rev. C – 22 Feb. 01
TSS463
11. Messages Types
There are 5 basic message types defined in the TSS463.
Two of them (transmit and receive message types)
correspond to the normal frame, and the rest correspond
to the different versions of reply frames.
Transmit Message
RNW
RTR
Transmitted
Received
Initial setup
0
0
0
Don’t care
After transmission
0
0
1
Unchanged
To transmit a normal data frame on the VAN bus, the
user must program an identifier as a Transmit Message.
The TSS463 will then transmit this message on the bus
until it has succeeded or the retry count is exceeded.
Receive Message
RNW
RTR
Transmitted
Received
Initial setup
0
1
Don’t care
0
After transmission
0
1
Unchanged
1
The opposite of the transmit message type is the Receive
Message type. This message type will not generate any
frames on the bus. Instead it will listen to the bus until
a frame passes that matches its identifier, with the mask
taken into account, and then receive the data in that
frame.
The data received will be stored in the message buffer
and the length of the message received is stored in the
first byte of the message buffer.
The actual identifier received is stored in the identifier
register itself. This identifier may differ from the
identifier specified in the register due to the effect of the
mask register.
Normally this should not interfere with the next
identifier comparison since the bits that may differ are
masked via the mask register.
Reply Request Message
RNW
RTR
Transmitted
Received
Initial setup
1
1
0
0
After transmission
(Waiting for reply)
1
1
1
0
After reception
(of reply)
1
1
1
1
The Reply Request Message type is a demand to
transmit on the VAN bus a reply request. When this
message type is programmed, three things can happen.
In the first case no other modules on the bus responded
with an in-frame reply, and in this case the TSS463 will
set the message type to the after transmission state.
When this message type is programmed, the TSS463
Rev. C – 22 Feb. 01
will listen on the bus for a deferred reply frame matching
this identifier, without transmitting the reply request.
The second case is that another module on the bus replies
with an in-frame reply. In this case the message type will
pass immediately into the after reception state, without
passing the after transmission state.
41
TSS463
Reply Request Message without transmission
RNW
RTR
Transmitted
Received
Initial setup
1
1
Don’t care
0
After reception
1
1
Unchanged
1
In the third case the TSS463 has not yet started to
transmit the reply request, when another module either
requests a reply, and gets it, or transmits a deferred reply.
Warning ! This should be avoided as it may result in an
illegal message type (Illegal reply Request).
Immediate Reply Message
RNW
RTR
Transmitted
Received
Initial setup
1
0
0
0
After transmission
1
0
1
1
The immediate Reply Message will attempt to transmit
an in-frame reply, using the data in the message buffer.
Deferred Reply Message
RNW
RTR
Transmitted
Received
Initial setup
1
0
0
1
After reception
(of reply request)
1
0
1
1
Above a Deferred Reply Message is shown. This
message type will immediately transmit a deferred reply
frame.
Reply Request Detection Message
RNW
RTR
Transmitted
Received
Initial setup
1
0
1
0
After reception
1
0
1
1
Finally there is the Reply Request Detector Message
type. Its purpose is to receive a reply request frame and
notify the processor, without transmitting an in-frame
reply.
Inactive Message
RNW
RTR
Transmitted
Received
Recommended
Don’t care
Don’t care
1
1
After transmission
0
0
1
Don’t care
After reception
0
1
Don’t care
1
Illegal reply request
1
1
0
1
The table above shows all inactive messages types. The
last combination will transmit a reply request, but will
42
not receive the reply since its buffer is tagged as
occupied.
Rev. C – 22 Feb. 01
TSS463
12. Priority among the different channels
The priority handling on the VAN bus itself is already
explained in the Line interface section. The priorities for
the messages in the TSS463 is however slightly
different.
However, since the identifier 5 will become an inactive
message when it has received the frame, the next time
the same identifier is seen on the bus, the corresponding
data will be received by identifier 10.
For instance it’s possible that an identifier matches two
or more of the identifiers programmed into the registers.
In this case, it is the lowest identifier number that has
priority. i.e. if both identifier 5 and 10 match the
identifier received, it is the identifier 5 that will receive
the message.
The same is valid for messages to be transmitted, i.e. if
two or more messages are ready to be transmitted, it is
the one with the lowest identifier number that will get
priority.
Rev. C – 22 Feb. 01
43
TSS463
13. Retries, rearbitrate and abort
Retries and rearbitrate commands are located,
respectively, in the Transmit Control Register and in the
Command Register. An abort command is located in
each channel register set, in the Message Length &
Status Register (base_address + 0x03). These three
commands are available only when the TSS463 is
producer.
Activate
Ch. enabled in
Xmit mode ?
no
yes
Select the lowest
Ch. number and
load ”Max - retries”
Disable of
current Ch.
Abort activated
on current Ch. ?
yes
no
Wait for bus free
(EOF+IFS= 12 Timeslots)
Decrement
retry counter
Transmit frame
and wait for the end
Abort required
on current Ch.
rearbitrate?
abort
rearbitrate
no
yes
Retry needed ?
no
Figure 32. Transmit function
13.1. Retries
The purpose of retries feature is to provide, for the user,
the capability of retrying a transmit request in case of
failure, when a node tries to reach another node, either
on normal DATA frame or on REPLY REQUEST frame.
Status Register, a 4-bit counter is loaded with MR[3:0].
At each attempt, this counter will be count-down. To 0,
an IT TE is set in the Interrupt Status Register (0x09),
and the transmission is stopped.
The maximum of retries is programmable through
MR[3:0] of the Transmit Control Register (0x01). When
a channel is enable - bit CHTx= 0 of Message Length &
MR[3:0]=1 indicates 1 retry, hence 2 transmission
attempts will be performed (see Table 2. ). The number
of retries performed, as well as the current channel
44
Rev. C – 22 Feb. 01
TSS463
number associated, can be read in the Transmission
Status Register (0x05).
normal CSMA/CD protocol and, therefore, is not
taken into account in failure cases. So, an ’infinite’
number of attempts can be performed if bus
contention occurs continuously.
The Last Error Status Register (0x07) informs about the
trouble uncounted:
D Failure cases: - Code viol (CV error bit)
- Acknoledge error (ACKE error bit)
- CRC error (FCSE error bit)
D It should be noticed that contention is considered as
There is only one retries counter for all channels. When
the user writes the Max_Retries value, all channels start
their transmission with this parameter.
13.2. Rearbitrate
The purpose of rearbitrate feature is to postpone a
channel already in transmission in order to authorize an
higher priority (see section 12.) message to be transmit.
13.2.1. Typical example
* (not seen by application means no IT generation)
Second attempt
Xmit Ch8
Delay
Viol
(Retries - 1)
First attempt
Xmit Ch8
Set CHER & CHTx /Ch8,
and set IT TE
Ex: set FSCE status bit
Ex: FCS Error
(not seen by application)
(Load Max-retries)
D At the end of this transmission Ch5, either when
the attempt is successful or either when the
exceeded retry count is reached, the retries
counter is reloaded and the transmission is
activated for the Ch 8 again.
EOF+IFS
Xmit Ch5
First attempt
Xmit Ch8
Delay
Viol
Set CHTx/Ch5 & IT ROK
(Load Max-retries)
Ex: FCS Error
* (not seen by application)
(Activate Ch5)
Rearbitrate
(Load Max-retries)
D Max_retries = 1 (2 transmissions attempts).
D If Ch 8 is in a the retry loop and the user wants to
transmit the Ch 5 without waiting the end of the
loop, the user can use the rearbitrate command.
D Then, the TSS463 will wait the end of the current
transmission, reload the retries counter and
enable the Ch 5 to transmit.
stand-by
Delay
Viol
EOF+IFS: 8 + 4 Timeslots
Delay Viol: 12 Timeslots
Figure 33. Rearbitrate Example
Rev. C – 22 Feb. 01
45
TSS463
Set CHER & CHTx /Ch8,
and set IT TE
Ex: set FSCE status bit
Ex: FCS Error
(not seen by application)
(Retries - 1)
First attempt
Xmit Ch8
* (not seen by application means no IT generation)
Second attempt
Xmit Ch8
Delay
Viol
EOF+IFS
Xmit Ch5
First attempt
Xmit Ch8
Delay
Viol
(Load Max-retries)
Set CHTx/Ch5 & IT ROK
Idle command
(Load Max-retries)
Ex: FCS Error
* (not seen by application)
Rearbitrate
(Activate Ch5)
(Load Max-retries)
(same example section 13.2.1.).
Idle
Delay
Viol
EOF+IFS: 8 + 4 Timeslots
Delay Viol: 12 Timeslots
Figure 34. Idle and rearbitrate example
If the user sets the idle bit anywhere (after rearbitrate),
the idle mode is entered only at the end of all the transmit
attempts (for more information about idle command, see
section 14.).
13.2.2. Disable channel after rearbitrate
(Load Max-retries)
Ex: FCS Error
(not seen by application)
Disable Ch8(*)
(Activate Ch5)
Rearbitrate
(Load Max-retries)
(same example section 13.2.1.).
Delay
Viol
Ex: ACK Error
(not seen by application)
Set CHER & CHTx /Ch5,
and set IT TE
Ex: set ACKE status bit
Delay
Viol
Delay
Viol
stand-by
(Retries - 1)
KO
Second attempt Xmit Ch5
Set CHTx/Ch5 & IT TOK
First attempt
Xmit Ch5
First attempt
Xmit Ch8
OK
EOF+IFS
stand-by
EOF+IFS: 8 + 4 Timeslots
Delay Viol: 12 Timeslots
(*) The disable is applied setting the CHTx/Ch8 bit to 1.
Figure 35. Disable channel after rearbitrate example
In this case, the TSS463 completes the current attempt
(Ch8) and let the transmission go on the new channel
46
(Ch5 if validated), otherwise it stops all attempts on the
current channel.
Rev. C – 22 Feb. 01
TSS463
13.3. Abort
An abort command is dedicated to channels already
enabled in transmission or in in-frame response. For
example, this command can be used to break the retry
procedure on one channel.
channel aborted is not transmitted. When this abort
command is really done, the TSS463 set to 1 the
Transmitted bit (CHTx) of the Message Length & Status
Register.
Abort channel is done by setting the Error bit (CHER)
in the Message Length & Status Register (base_address
+ 0x02). This command is taken into account if the
The abort mechanism is integrated into the transmit
function. This mainly means, abort, priority and retries
live together in the transmit function.
Set CHTx/Ch13
IT ROK
Set orCHTx
CHER /Ch6 & or IT RE
Set CHTx/Ch6 & IT ROK
if success
Set CHTx/Ch6 & IT ROK
if success
Set CHTx/Ch4 &IT ROK
Abort Ch4 (during Xmit)
Abort Ch13 (before Xmit)
Activate
Abort Ch0 (before Xmit)
Set CHTx/Ch0
Ch’s initialization
Reset
Example: Ch0, Ch4, Ch6 & Ch13 set in Xmit ACK mode, Max-retry=2 (3 attempts).
Xmit Ch6
if previously fail
Xmit Ch6
if previously fail
Xmit Ch6
Xmit Ch4
12 Timeslots
Figure 36. Abort example
Rev. C – 22 Feb. 01
47
TSS463
14. Activate, idle and sleep modes
Sleep, idle and activate commands are located in the
Command Register (0x03). These three commands are
general commands for the TSS463.
14.1. Idle and activate commands
After reset, the TSS463 starts in idle mode. In this mode,
the oscillator operates (CKOUT pin active) but the
circuit cannot transmit or receive anything on the VAN
bus. The TxD output (pin 12) is in three state mode, a
Idle mode
pull-up resistor must be be provided externally or by the
line driver to avoid floating state on the VAN bus. To
activate the TSS463, the user must set the activate bit
(ACTI) and reset the idle bit (IDLE).
Activate mode
SOF
RxD
Activate command
after reset
SOF
TxD
8 TS
12 TS
3 TS
(max)
TS: Timeslot period
Idle mode
ACK
FCS
EOD
Activate mode
RxD
Idle command
INT
4 TS
5 TS
Figure 37. Idle and activate timings
In both cases, the idle state can be verified reading the
Line Status register (0x04).
14.2. Sleep command
If the user sets the sleep bit (SLEEP), the TSS463 enters
in sleep mode, whatever are the values of activate and
idle bits. It means that, all non-user registers are set-up
to reduce the power consumption and the internal
oscillator is immediately stopped. Then, accesses to all
registers (and to the messages) via the SPI/SCI interface
are impossible and CKOUT is not provided.
To exit from this mode the user must apply either an
48
hardware reset (external reset pin) either an
asynchronous software reset (via the SPI/SCI interface).
In an application (i.e. typical application figure 8) using
the CKOUT feature (pin 8), if the TSS463 is put in sleep
mode, the clock provided to the microcontroller is
stopped. So, the system does not run and the only way
to awake this application is an external reset.
Rev. C – 22 Feb. 01
TSS463
15. Linked channels
The linkage feature allows to channels to share the same
Message area, the message pointer and the message
length assumes this property:
D Zero value as message length (M_L [4:0] base_address + 0x03) declares the channel linked to
another channel.
D The number of this other channel is defined in the
message pointer field (M_P [6:0] - base_address +
0x02).
D The pointer and the length values for the Message
area are defined only once time, in the register set of
this other Channel.
Only one level of linkage can be created. This means,
(see Figure 38. ) a Channel k can be linked to the
Channel i but not to Channel j, already defined as linked
to Channel i.
All the others can be different between the two channels,
for example the ID_Tag.
The Channel j linked
Channel i and j
....
share the same
Message area
to the Channel i
--- Channel i ---
--- Message for Channels i & j ---
ID_Mask j (msb)
0x00
DRAK
ID_Tag j (lsb)
DATA n
CHER CHTx CHRx
i
ËËËËËËË
ËËËËËËË
ËËËËËËËËË
ËËËËËËË
ËËËËËËËËË
ËËËËËËË
ËËËËËËËËË
ËËËËËËË
ËËËËËËËËË
ËËËËËËËËË
ËËËËËËËËË
ËËËËËËËËË
ËËËËËËËËË
ËËËËËËËËË
ËËËËËËËËË
ËËËËËËËËË
EXT RAK RNW RTR
ID_Tag j (msb)
ID_Mask i (lsb)
ID_Mask i (msb)
Mess_Len = n+2 CHER CHTx
Mess_Ptr
DRAK
ID_Tag i (lsb)
CHRx
EXT RAK RNW RTR
Length = n+2
--- Channel j ---
ID_Mask j (lsb)
DATA 0
Message Status
ID_Tag i (msb)
Figure 38. Linkage mechanism
This Message area sharing permits either to optimize the
allocation of the 128 bytes of DATA, either to perform
Rev. C – 22 Feb. 01
some special communications between the different
nodes of the network.
49
TSS463
16. Absolute Maximum Ratings*
Ambient temperature under bias :
A = Automotive . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Voltage on VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to +7.0 V
Voltage on any pin to VSS . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
*NOTICE
Stresses at or above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
exceeding those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
17. DC Characteristics
TA = –40°C to 125°C ; VCC = 5 V ± 10 % ; VSS = 0 V
Symbol
Min.
Max
Unit
Test Conditions
VIL
Input Low Voltage
–0.5
0.3⋅VCC⋅min
V
VIH
Input High Voltage
0.7⋅VCC max
VCC+0.5
V
VHY
Hyteresis voltage of trigger CMOS
inputs
0.4
–
V
see Figure 2
VOL
Output Low Voltage
0.4
V
IOL = 3.2 mA, Vcc min
VOH
Output High Voltage
V
IOH = –3.2 mA, Vcc min
| IL |
Input Leakage Current
(SCLK, MOSI, SS)
5
µA
0 < VIN < VCC
| IOZ |
Output Tristate Leakage Current
(MISO)
5
µA
0 < VIN < VCC
RPU, RPD
Input pullup & pulldown resistors
kΩ
Note 5
2.4
70
CIO
I/O Buffer Capacitance
10
pF
Not tested
ICCSB
Power Supply Current
Sleep mode
50
µA
(Note 1)
ICCOP
Power Supply Current
Idle or Active mode
3
12
mA
mA
(Note 2)
(Notes 3, 4)
Notes :
50
Parameter
1. Sleep Mode ICCSB is measured according to Figure 39. , with a VSS Clock Signal.
2. Active mode ICCOP is measured at: XTAL = 1 MHz clock, VAN speed rate = 62.5 KTS/s.
3. Active mode ICCOP is measured at: XTAL = 16 MHz clock, VAN speed rate = 250 KTS/s.
4. ICC is a function of the Clock Frequency. In Figure 40. is displayed a graph showing ICC versus Clock frequency.
5. RESET, RxD0, RxD1, RxD2 inputs.
Rev. C – 22 Feb. 01
TSS463
Icc
TxD
CLOCK SIGNAL
N.C.
SS
SCLK,MOSI
Figure 39. ICC
mA
16
12
8
MHz
8
16
24
Figure 40. ICC Versus Clock Frequency
at 250 KTimeslot/s
Rev. C – 22 Feb. 01
51
TSS463
18. AC Characteristics
TA = –40°C to 125°C ; VCC = 5V ± 10% ; VSS = 0V
18.1. Microprocessor Interface
CLOAD = 200pF on SPI/SCI lines
Symbol
Characteristic
Min
Max
Unit
fOP
Operating Frequency
SPI
SCI
dc
dc
4
125
MHZ
KHZ
1
tCYC
Cycle Time
SPI
SCI
250
8
–
–
ns
ms
2
tLEAD
Enable Lead Time
4
–
XTAL Period
3
tLAG
Enable Lead Time
12
–
XTAL Period
4
tW(SCKH)
Clock (SCLK) High Time
100
–
ns
5
tW(SCKL)
Clock (SCLK) Low Time
100
–
ns
6
tSU
Data Setup Time (Inputs)
40
–
ns
7
tH
Data Hold Time (Inputs)
40
–
ns
8
tA
Slave Access Time (Time to Data Active from
High–Impedance State)
0
100
ns
9
tDIS
Slave Disable Time (Hold Time to High–Impedance State)
–
200
ns
10
tV
Data Valid (After Enable Edge)
–
60
ns
11
tHO
Data Hold Time (Outputs After Enable Edge)
0
–
ns
SS
(INPUT)
1
2
SCLK
(INPUT)
3
5
4
8
9
MISO
(OUTPUT)
ÉÉÉÉÉ
ÉÉÉÉÉ
MOSI
(INPUT)
52
6
7
ÉÉÉ
ÉÉÉ
10
11
ÉÉÉ
ÉÉÉ
ÉÉ
ÉÉ
Rev. C – 22 Feb. 01
TSS463
18.1.1. Oscillator Characteristics
C1 = Crystal load (no capacitance needed)
Figure 41. C2 Versus Frequency.
18.2. External Clock drive characteristics (XTAL1)
Symbol
Parameter
Min
Max
TCHCH
Oscillator period
60
ns
TCHCX
High Time at 16 MHz
20
ns
TCLCX
Low Time at 16 MHz
20
ns
TCLCH
Rise Time at 16 MHz
20
ns
TCHCL
Fall Time at 16 MHz
20
ns
TCHCL
XTAL1
VIH
Unit
TCLCH
VIH
VIH
VIL
VIL
TCHCX
TCLCX
TCHCH
Rev. C – 22 Feb. 01
53
TSS463
19. Packaging
SO 16
SO
MM
INCH
A
2.35
2.65
0.093
0.104
A1
0.10
0.30
0.004
0.012
B
0.35
0.49
0.014
0.019
C
0.23
0.32
0.009
0.013
D
10.10
10.50
0.398
0.413
E
7.40
7.60
0.291
0.299
e
1.27
BSC
0.050
BSC
H
10.00
10.65
0.394
0.419
h
0.25
0.75
0.010
0.029
L
0.40
1.27
0.016
0.050
8_
0_
N
16
a
0_
16
8_
20. Ordering Information
TSS463
Part Number
54
R
Conditioning
R : Tape & Reel
D : Dry Pack
Blank : Tubes
Rev. C – 22 Feb. 01