AD AD842KH

APPLICATIONS
Line Drivers
DAC and ADC Buffers
Video and Pulse Amplifiers
Available in Plastic DIP, Hermetic Metal Can,
Hermetic Cerdip, SOIC and LCC Packages and in
Chip Form
MIL-STD-883B Parts Available
Available in Tape and Reel in Accordance with
EIA-481A Standard
PRODUCT DESCRIPTION
The AD842 is a member of the Analog Devices family of wide
bandwidth operational amplifiers. This device is fabricated using
Analog Devices’ junction isolated complementary bipolar (CB)
process. This process permits a combination of dc precision and
wideband ac performance previously unobtainable in a monolithic op amp. In addition to its 80 MHz gain bandwidth, the
AD842 offers extremely fast settling characteristics, typically
settling to within 0.01% of final value in less than 100 ns for a
10 volt step.
The AD842 also offers a low quiescent current of 13 mA, a high
output current drive capability (100 mA minimum), a low input
voltage noise of 9 nV√Hz and a low input offset voltage (1 mV
maximum).
The 375 V/µs slew rate of the AD842, along with its 80 MHz
gain bandwidth, ensures excellent performance in video and
pulse amplifier applications. This amplifier is ideally suited for
use in high frequency signal conditioning circuits and wide
bandwidth active filters. The extremely rapid settling time of
the AD842 makes this amplifier the preferred choice for data
acquisition applications which require 12-bit accuracy. The
*Covered by U.S. Patent Nos. 4,969,823 and 5,141,898.
BALANCE
BALANCE 3
12
NC
–INPUT 4
11
V+
+
10
OUTPUT
V– 6
9
NC
NC 7
8
NC
+INPUT 5
TOP VIEW
NC
–IN
NC
+IN
NC
NC = NO CONNECT
19 NC
NC
13
AD842
20 BALANCE
14
NC 2
1 NC
NC 1
2 BALANCE
LCC (E) Package
Plastic DIP (N) Package
and
Cerdip (Q) Package
4
18
5
17
6
16
7
+
AD842
8
NC
+VS
NC
15 OUTPUT
14 NC
NC 11
NC 12
NC 13
DC PERFORMANCE
Input Offset Voltage: 1 mV max
Input Offset Drift: 14 ␮V/ⴗC
Input Voltage Noise: 9 nV/√Hz typ
Open-Loop Gain: 90 V/mV into a 500 ⍀ Load
Output Current: 100 mA min
Quiescent Supply Current: 14 mA max
CONNECTION DIAGRAMS
3 NC
FEATURES
AC PERFORMANCE
Gain Bandwidth Product: 80 MHz (Gain = 2)
Fast Settling: 100 ns to 0.01% for a 10 V Step
Slew Rate: 375 V/␮s
Stable at Gains of 2 or Greater
Full Power Bandwidth: 6.0 MHz for 20 V p-p
NC 9
–VS 10
a
Wideband, High Output Current,
Fast Settling Op Amp
AD842*
NC = NO CONNECT
TO-8 (H) Package
NC
BALANCE
SOIC (R-16) Package
NC
BALANCE
NC 1
V+
BALANCE 2
AD842
OUTPUT
+INPUT
V–
NC
TOP VIEW
NOTE: CAN BE TIED TO V+
NC = NO CONNECT
15 BALANCE
14 +V
S
13 NC
NC 4
+INPUT 5
+
NC
AD842
–INPUT 3
–INPUT
NC
16 NC
+
12 OUTPUT
NC 6
11 NC
–VS 7
10 NC
NC 8
TOP VIEW
9
NC
NC = NO CONNECT
AD842 is also appropriate for other applications such as high
speed DAC and ADC buffer amplifiers and other wide bandwidth circuitry.
APPLICATION HIGHLIGHTS
1. The high slew rate and fast settling time of the AD842 make
it ideal for DAC and ADC buffers amplifiers, lines drivers
and all types of video instrumentation circuitry.
2. The AD842 is a precision amplifier. It offers accuracy to
0.01% or better and wide bandwidth; performance previously
available only in hybrids.
3. Laser-wafer trimming reduces the input offset voltage of
1 mV max, thus eliminating the need for external offset
nulling in many applications.
4. Full differential inputs provide outstanding performance in
all standard high frequency op amp applications where the
circuit gain will be 2 or greater.
5. The AD842 is an enhanced replacement for the HA2542.
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
AD842–SPECIFICATIONS (@ +25ⴗC and ⴞ15 V dc, unless otherwise noted)
Model
Conditions
Min
INPUT OFFSET VOLTAGE3
AD842J/JR1
Typ
Max
0.5
TMIN–TMAX
Offset Drift
4.2
Input Offset Current
0.1
TMIN–TMAX
VCM = ± 10 V
TMIN–TMAX
OPEN-LOOP GAIN
VO = ± 10 V
RLOAD ≥ 500 Ω
TMIN–TMAX
Rise Time5
Overshoot5
Slew Rate5
Settling Time5
Differential Gain
Differential Phase
RLOAD ≥ 500 Ω
VOUT = ± 10 V
Open Loop
VOUT = 90 mV
VO = 20 V p-p
RLOAD ≥ 500 Ω
AVCL = –2
AVCL = –2
AVCL = –2
10 V Step
to 0.1%
to 0.01%
f = 4.4 MHz
f = 4.4 MHz
POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
Power Supply Rejection Ratio
TEMPERATURE RANGE
Rated Performance6
PACKAGE OPTIONS
Plastic (N-14)
Cerdip (Q-14)
SOIC (R-16)
Tape and Reel
TO-8 (H-12A)
LCC (E-20A)
Chips
8
10
0.4
0.5
3.5
0.05
100
2.0
f = 1 kHz
10 Hz to 10 MHz
FREQUENCY RESPONSE
Gain Bandwidth Product
Full Power Bandwidth4
Min
1.0
1.5
AD842S2
Typ
0.5
Max
Units
1.5
3.5
mV
mV
µV/°C
8
12
0.4
0.6
µA
µA
µA
µA
14
5
6
0.2
0.3
4.2
0.1
Differential Mode
INPUT VOLTAGE NOISE
Wideband Noise
OUTPUT CHARACTERISTICS
Voltage
Current
0.3
14
TMIN–TMAX
INPUT VOLTAGE RANGE
Common Mode
Common-Mode Rejection
1.5
2.5/3
14
INPUT BIAS CURRENT
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
AD842K
Min Typ Max
ⴞ10
86
80
ⴞ10
90
86
115
9
28
40/30
20/15
4.7
300
90
50
25
90
40
20
ⴞ10
100
100
2.0
kΩ
pF
115
V
dB
dB
9
28
nV/√Hz
µV rms
90
V/mV
V/mV
ⴞ10
100
5
5
5
V
mA
Ω
80
80
80
MHz
6
10
20
375
MHz
ns
%
V/µs
80
100
0.015
0.035
ns
ns
%
Degree
6
10
20
375
4.7
300
80
100
0.015
0.035
± 15
13/14
86
80
ⴞ10
86
80
115
9
28
ⴞ10
100
ⴞ5
TMIN–TMAX
VS = ± 5 V to ± 18 V
TMIN–TMAX
100
2.0
100
0
6
10
20
375
4.7
300
80
100
0.015
0.035
ⴞ18
ⴞ5
14/16
16/19.5
90
86
+75
AD842JN
AD842JQ
AD842JR-16
AD842JR-16-REEL
AD842JR-16-REEL7
AD842JH
± 15
13
ⴞ18
14
16
105
0
AD842KH
AD842JCHIPS
± 15
13
86
80
+75
AD842KN
AD842KQ
ⴞ5
–55
ⴞ18
14
19
100
+125
V
V
mA
mA
dB
dB
°C
AD842SQ, AD842SQ/883B
AD842SH
AD842SE/883B
AD842SCHIPS
NOTES
1
AD842JR specifications differ from those of the AD842JN, JQ and JH due to the thermal characteristics of the SOIC package.
2
Standard Military Drawing available 5962-8964201xx
2A – (SE/883B); XA – (SH/883B); CA – (SQ/883B).
3
Input offset voltage specifications are guaranteed after 5 minutes at TA = +25°C.
4
Full power bandwidth = slew rate/2 π VPEAK.
5
Refer to Figures 22 and 23.
6
“S” grade TMIN–TMAX specifications are tested with automatic test equipment at TA = –55°C and TA = +125°C.
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units.
Specifications subject to change without notice.
–2–
REV. E
AD842
ABSOLUTE MAXIMUM RATINGS 1
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Maximum internal power dissipation is specified so that T J does not exceed
+150°C at an ambient temperature of +25°C.
Thermal Characteristics:
θJC
θJA
θSA
Plastic Package
30°C/W
100°C/W
Cerdip Package
30°C/W
110°C/W
38°C/W
TO-8 Package
30°C/W
100°C/W
27°C/W
16-Lead SOIC Package 30°C/W
100°C/W
20-Lead LCC Package 35°C/W
150°C/W
Recommended Heat Sink: Aavid Engineering© #602B
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation2
Plastic (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
Cerdip (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 W
TO-8 (H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
SOIC (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
LCC (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 W
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . ± 6 V
Storage Temperature Range
Q, H, E . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
N, R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
METALIZATION PHOTOGRAPH
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
REV. E
–3–
AD842–Typical Characteristics (at +25ⴗC and V = ⴞ15 V, unless otherwise noted)
S
20
15
VIN
10
5
0
5
10
15
SUPPLY VOLTAGE – ⴞVolts
15
ⴞ VOUT
10
5
0
20
Figure 1. Input Common-Mode
Range vs. Supply Voltage
12
0
5
10
15
SUPPLY VOLTAGE – ⴞ Volts
Figure 4. Quiescent Current vs.
Supply Voltage
SHORT CIRCUIT CURRENT LIMIT – mA
QUIESCENT CURRENT – mA
16
15
14
13
12
11
10
–60 –40 –20
–4
–3
0 20 40 60 80 100 120 140
TEMPERATURE – ⴗC
0 20 40 60 80 100 120 140
TEMPERATURE – ⴗC
Figure 7. Quiescent Current vs.
Temperature
100
1k
LOAD RESISTANCE – ⍀
10k
10
1
0.1
0.01
10k
1M
10M
100k
FREQUENCY – Hz
100M
Figure 6. Output Impedance vs.
Frequency
85
300
17
5
Figure 3. Output Voltage Swing
vs. Load Resistance
Figure 5. Input Bias Current vs.
Temperature
18
10
100
–2
–60 –40 –20
20
15
10
OUTPUT IMPEDANCE – ⍀
INPUT BIAS CURRENT – ␮A
QUIESCENT CURRENT – mA
14
ⴞ 15V SUPPLIES
20
20
–5
16
10
5
10
15
SUPPLY VOLTAGE – ⴞ Volts
Figure 2. Output Voltage Swing
vs. Supply Voltage
18
25
0
0
275
250
+ OUTPUT CURRENT
225
200
175
–OUTPUT CURRENT
150
GAIN BANDWIDTH – MHz
0
30
OUTPUT VOLTAGE SWING – Volts p-p
OUTPUT VOLTAGE SWING – Volts
INPUT COMMON-MODE RANGE – Volts
20
80
75
70
125
100
–60 –40 –20 0 20 40 60 80 100 120 140
AMBIENT TEMPERATURE – ⴗC
Figure 8. Short-Circuit Current
Limit vs. Temperature
–4–
65
–60 –40 –20
0 20 40 60 80 100 120 140
TEMPERATURE – ⴗC
Figure 9. Gain Bandwidth Product
vs. Temperature
REV. E
AD842
60
60
40
40
20
500⍀ LOAD
20
100
500⍀ LOAD
95
0
0
100
1k
10k
100k
1M
FREQUENCY – Hz
10M
90
100M
Figure 10. Open-Loop Gain and
Phase Margin vs. Frequency
VS = ⴞ 15V
VCM = 1V p-p
+ 25ⴗC
100
80
60
40
0
5
10
15
SUPPLY VOLTAGE – ⴞV
100
+ SUPPLY
80
60
– SUPPLY
40
20
0
100
20
Figure 11. Open-Loop Gain vs.
Supply Voltage
1k
10k
100k
1M
FREQUENCY – Hz
10M 100M
Figure 12. Power Supply Rejection
vs. Frequency
10
30
OUTPUT VOLTAGE – Volts p-p
120
CMR – dB
POWER SUPPLY REJECTION – dB
80
105
RL = 1kV
+25ⴗC
VS = ⴞ15V
25
20
15
10
5
OUTPUT SWING FROM 0 TO ⴞV
80
120
110
OPEN-LOOP GAIN – dB
100
PHASE MARGIN – Degrees
100
OPEN-LOOP GAIN – dB
120
8
6
4
2
0.1% 0.01%
0
0.1% 0.01%
–2
–4
–6
–8
1k
10k
100k
1M
10M
FREQUENCY – Hz
100M
Figure 13. Common-Mode
Rejection vs. Frequency
–100
2ND HARMONIC
–120
–130
–140
100
3RD HARMONIC
1k
10k
FREQUENCY – Hz
100k
Figure 16. Harmonic Distortion vs.
Frequency
REV. E
100M
30
50
60
70
80
90
SETTLING TIME – ns
100 110
550
500
40
30
20
10
0
10
40
Figure 15. Output Swing and
Error vs. Settling Time
50
3V RMS
RL = 1k⍀
–90
–110
10M
FREQUENCY – Hz
Figure 14. Large Signal Frequency
Response
INPUT VOLTAGE – nV Hz
HARMONIC DISTORTION – dB
–80
–10
0
1M
SLEW RATE – V␮s
20
450
400
350
300
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
Figure 17. Input Voltage vs.
Frequency
–5–
250
–60 –40 –20
0 20 40 60 80 100 120 140
TEMPERATURE – ⴗC
Figure 18. Slew Rate vs.
Temperature
AD842
RF = 1k⍀
0.1␮F
+VS
HP3314A
FUNCTION
GENERATOR
OR
EQUIVALENT
2.2␮F
RIN =
499⍀
49.9⍀
–
AD842
+
VOUT
0.1␮F
499⍀
332⍀
2.2␮F
–VS
Figure 19a. Inverting Amplifier
Configuration (DIP Pinout)
R1 = 205⍀
Figure 19b. Inverter Large Signal
Pulse Response
Figure 19c. Inverter Small Signal
Pulse Response
Figure 20b. Noninverting Large
Signal Pulse Response
Figure 20c. Noninverting Small
Signal Pulse Response
RF = 205⍀
0.1␮F
+VS
2.2␮F
HP3314A
FUNCTION VIN
GENERATOR
OR
EQUIVALENT
100⍀
–
AD842
+
VOUT
0.1␮F
499⍀
49.9⍀
2.2␮F
–VS
Figure 20a. Noninverting Amplifier
Configuration (DIP Pinout)
–6–
REV. E
AD842
OFFSET NULLING
The input offset voltage of the AD842 is very low for a high
speed op amp, but if additional nulling is required, the circuit
shown in Figure 21 can be used.
ERROR
AMP
(ⴛ15)
TEK
7A13
TEK
7603
OSCILLOSCOPE
AD842 SETTLING TIME
TEK
7A16
Figures 22 and 24 show the settling performance of the AD842
in the test circuit shown in Figure 23.
HP6263
DDD5109
FLAT-TOP
PULSE
GENERATOR
Settling time is defined as:
The interval of time from the application of an ideal step
function input until the closed-loop amplifier output has
entered and remains within a specified error band.
499⍀
1k⍀
499⍀
1k⍀
0.1␮F
50⍀
+15V
2.2␮F
This definition encompasses the major components which comprise settling time. They include (1) propagation delay through
the amplifier; (2) slewing time to approach the final output value;
(3) the time of recovery from the overload associated with slewing and (4) linear settling to within the specified error band.
0.1␮F
2.2␮F
–15V
Figure 23. Settling Time Test Circuit
Figure 23 shows how measurement of the AD842’s 0.01% settling in 100 ns was accomplished by amplifying the error signal
from a false summing junction with a very high-speed proprietary hybrid error amplifier specially designed to enable testing
of small settling errors. The device under test was driving a
300 Ω load. The input to the error amp is clamped in order to
avoid possible problems associated with the overdrive recovery
of the oscilloscope input amplifier. The error amp gains the
error from the false summing junction by 15, and it contains a
gain vernier to fine trim the gain.
0.1␮F
2.2␮F
INPUT
–
AD842
+
OUTPUT
0.1␮F
RL
2.2␮F
–VS
Figure 24 shows the “long term” stability of the settling characteristics of the AD842 output after a 10 V step. There is no
evidence of settling tails after the initial transient recovery time.
The use of a junction isolated process, together with careful
layout, avoids these problems by minimizing the effects of transistor isolation capacitance discharge and thermally induced
shifts in circuit operating points. These problems do not occur
even under high output current conditions.
Figure 21. Offset Nulling (DIP Pinout)
Figure 22. 0.01% Settling Time
REV. E
499⍀
499⍀
Expressed in these terms, the measurement of settling time is
obviously a challenge and needs to be done accurately to assure
the user that the amplifier is worth consideration for the
application.
+VS
10k⍀
FET PROBE
TEK P6201
AD842
–7–
AD842
GROUNDING AND BYPASSING
USING A HEAT SINK
In designing practical circuits with the AD842, the user must
remember that whenever high frequencies are involved, some
The AD842 draws less quiescent power than most precision
high speed amplifiers and is specified for operation without a
heat sink. However, when driving low impedance loads, the current to the load can be 10 times the quiescent current. This will
create a noticeable temperature rise. Improved performance can
be achieved by using a small heat sink such as the Aavid Engineering #602B.
TERMINATED LINE DRIVER
The AD842 is optimized for high speed line driver applications.
Figure 25 shows the AD842 driving a doubly terminated cable
in a gain-of-2 follower configuration. The AD842 maintains a
typical slew rate of 375 V/µs, which means it can drive a ± 10 V,
6.0 MHz signal or a ± 3 V, 19.9 MHz signal.
The termination resistor, RT, (when equal to the characteristic
impedance of the cable) minimizes reflections from the far end
of the cable. A back-termination resistor (RBT, also equal to the
characteristic impedance of the cable) may be placed between
the AD842 output and the cable in order to damp any stray
signals caused by a mismatch between RT and the cable’s characteristic impedance. This will result in a “cleaner” signal. With
this circuit, the voltage on the line equals VIN because one half
of VOUT is dropped across RBT.
Figure 24. AD842 Settling Demonstrating No Settling
Tails
special precautions are in order. Circuits must be built with
short interconnect leads. Large ground planes should be used
whenever possible to provide a low resistance, low inductance
circuit path, as well as minimizing the effects of high frequency
coupling. Sockets should be avoided because the increased
interlead capacitance can degrade bandwidth.
Feedback resistors should be of low enough value to assure that
the time constant formed with the circuit capacitances will not
limit the amplifier performance. Resistor values of less than
5 kΩ are recommended. If a larger resistor must be used, a small
(<10 pF) feedback capacitor connected in parallel with the feedback resistor, RF, may be used to compensate for these stray
capacitances and optimize the dynamic performance of the
amplifier in the particular application.
Power supply leads should be bypassed to ground as close as
possible to the amplifier pins. A 2.2 µF capacitor in parallel with
a 0.1 µF ceramic disk capacitor is recommended.
The AD842 has ± 100 mA minimum output current and, therefore, can drive ± 5 V into a 50 Ω cable.
The feedback resistors, R1 and R2, must be chosen carefully.
Large value resistors are desirable in order to limit the amount
of current drawn from the amplifier output. But large resistors
can cause amplifier instability because the parallel resistance
R1储R2 combines with the input capacitance (typically 2–5 pF) to
create an additional pole. Also, the voltage noise of the AD842
is equivalent to a 5 kΩ resistor, so large resistors can significantly increase the system noise. Resistor values of 1 kΩ or 2 kΩ
are recommended.
If termination is not used, cables appear as capacitive loads and
can be decoupled from the AD842 by a resistor in series with
the output.
CAPACITIVE LOAD DRIVING ABILITY
Like all wideband amplifiers, the AD842 is sensitive to capacitive loading. The AD842 is designed to drive capacitive loads of
up to 20 pF without degradation of its rated performance. Capacitive loads of greater than 20 pF will decrease the dynamic
performance of the part although instability should not occur
unless the load exceeds 100 pF.
2.2␮F
+VS
0.1␮F
VIN
TERMINATION
RESISTOR FOR
INPUT SIGNAL
+
RST
AD842
–
50⍀ OR 75⍀
CABLE
0.1␮F
–VS
2.2␮F
RT
R1
RT = RST = CABLE CHARACTERISTIC
IMPEDANCE
R2
Figure 25. Line Driver Configuration
–8–
REV. E
AD842
OVERDRIVE RECOVERY
2.2␮F
Figure 26 shows the overdrive recovery capability of the AD842.
Typical recovery time is 80 ns from negative overdrive and
400 ns from positive overdrive.
+VS
0.1␮F
–
HP3314A
PULSE GENERATOR
OR EQUIVALENT
1␮s, ⴞ1V SQUARE
WAVE INPUT
OUTPUT
AD842
+
0.1␮F
1k⍀
50⍀
–VS
2.2␮F
Figure 27. Overdrive Recovery Test Circuit
Figure 26. Overdrive Recovery
REV. E
–9–
AD842
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.005 (0.13) MIN
0.795 (20.19)
0.725 (18.42)
8
1
PIN 1
7
0.100 (2.54)
BSC
14
8
1
7
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
0.325 (8.25)
0.300 (7.62)
0.210 (5.33)
MAX
0.130
(3.30)
0.160 (4.06)
MIN
0.115 (2.93)
0.022 (0.558) 0.070 (1.77) SEATING
PLANE
0.014 (0.356) 0.045 (1.15)
0.195 (4.95)
0.115 (2.93)
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.015 (0.381)
0.008 (0.204)
8
0.050 (1.27)
BSC
0.075
(1.91)
REF
0.100 (2.54)
0.064 (1.63)
0.2992 (7.60)
0.2914 (7.40)
0.1043 (2.65)
0.0926 (2.35)
0.095 (2.41)
0.075 (1.90)
0.358 (9.09) 0.358
(9.09)
0.342 (8.69) MAX
SQ
SQ
0.4193 (10.65)
0.3937 (10.00)
0.0291 (0.74)
ⴛ 45ⴗ
0.0098 (0.25)
8ⴗ
0.0192 (0.49) SEATING
0ⴗ
0.0125 (0.32)
0.0138 (0.35) PLANE
0.0091 (0.23)
0.015 (0.38)
0.008 (0.20)
15°
0°
0.011 (0.28)
0.007 (0.18)
R TYP
0.075 (1.91)
REF
0.088 (2.24)
0.054 (1.37)
0.200 (5.08)
BSC
0.100 (2.54) BSC
3
4
19
18 20
1
BOTTOM
VIEW
14
13
0.055 (1.40)
0.045 (1.14)
0.015 (0.38)
MIN
0.028 (0.71)
0.022 (0.56)
0.050 (1.27)
BSC
8
9
45° TYP
0.150 (3.81)
BSC
0.0500 (1.27)
0.0157 (0.40)
12-Lead Metal Can Package
(TO-8 Style)
REFERENCE PLANE
0.181 (4.60)
0.148 (3.76)
0.375 (9.53)
MIN
0.050 (1.27) MAX
0.200 (5.08)
BSC
0.100 (2.54)
BSC
0.615 (15.62)
0.592 (15.04)
0.555 (14.10)
0.545 (13.84)
0.0118 (0.30)
0.0040 (0.10)
0.150
(3.81)
MIN
0.100 0.070 (1.78) SEATING
(2.54) 0.030 (0.76) PLANE
BSC
9
1
0.320 (8.13)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
20-Terminal Leadless Ceramic Chip Carrier Package
(E-20A)
0.4133 (10.50)
0.3977 (10.00)
PIN 1
0.310 (7.87)
0.220 (5.59)
PIN 1
0.785 (19.94) MAX
16-Lead SOIC Package
(R-16)
16
0.098 (2.49) MAX
0.040 (1.02) MAX
0.045 (1.14)
0.000 (0.00)
7
0.400
(10.16)
BSC
9
10
5
11
4
0.019 (0.48)
0.016 (0.41)
0.021 (0.53)
0.016 (0.41)
8
6
12
3
2
0.037 (0.94)
0.026 (0.66)
PRINTED IN U.S.A.
14
C1195c–0–3/00 (rev. E)
14-Lead Cerdip Package
(Q-14)
14-Lead Plastic Package
(N-14)
0.200
(5.08)
BSC
1
0.036 (0.91)
0.026 (0.66)
BASE & SEATING PLANE
–10–
REV. E