Standard ICs Driver for segmented LCD module with key input function BU9768AK / BU9768AKV The BU9768AK / BU9768AKV are man-machine interface ICs with key input, designed for portable multimedia terminals and other devices. They can be used as drivers for operation mode display LCD panels on portable terminals, household products, car stereos, and other appliances. Up to 126 cells can be displayed, and up to 30 keys can be input. Also, a maximum of four outputs are possible using expansion pins. (The number of outputs for each pin can be changed using control codes.) Applications •Portable multi-media terminals, POS terminals, wireless radios, telephones, cameras, VCRs, movie projectors, car stereos, others •1)Features Drive of up to 42 segment outputs, three common outputs, and up to 126 cells is possible. 2) Up to 30 keys can be input. 3) A maximum of four pins can be used as output pins for expansion. 4) 1 / 3 duty drive. 5) A bias of 1 / 2 or 1 / 3 can be selected for the LCD display power supply. •Block diagram Kl1 Kl2 Kl3 Kl4 Kl5 KO1 (S41) Key scan buffer DO KO2 (S42) KO3 KO4 KO5 KO6 Key scan control CS Control decoder Dl Command decoder CK VDD Control register VDD1 LCD Power VDD2 Shift register VSS OSC O.S.C Divider Data latch for LCD RST Segment and common driver ··· COM1 ··· ··· COM3 S1 (EP1) ··· ··· S4 (EP4) S5 ··· S40 1 Standard ICs BU9768AK / BU9768AKV COM2 COM1 S40 S39 S38 S37 S36 S35 S34 S33 46 COM3 KO3 47 KO2(S42) KO4 48 KO1(S41) KO5 •Pin assignments 45 44 43 42 41 40 39 38 37 36 35 34 33 17 S17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 S16 18 S18 DI 64 S15 19 S19 CK 63 S14 20 S20 CS 62 S13 21 S21 DO 61 S12 22 S22 OSC 60 S11 23 S23 VSS 59 S10 24 S24 VDD2 58 S9 25 S25 VDD1 57 S8 26 S26 VDD 56 S7 27 S27 RST 55 S6 28 S28 Kl5 54 S5 29 S29 Kl4 53 S4(EP4) 30 S30 Kl3 52 S3(EP3) 31 S31 Kl2 51 S2(EP2) 32 S32 Kl1 50 S1(EP1) KO6 49 Fig.1 2 Standard ICs BU9768AK / BU9768AKV •Pin descriptions Pin No. Pin name I/O Function Processing if not used OPEN 1~4 S1 (EP1) ~ S4 (EP4) O Output pins for switching between segment output and expansion pin output. Switched using control codes P0 and P1. When expansion pins are used, these output set data (1 or 0). 5 ~ 40 S5 ~ S40 O Segment output pins. These output waveforms correspond to serial data input from DI. OPEN 41 ~ 43 COM1 ~ COM3 O Common output pins OPEN OPEN 44, 45 KO1 (S41), KO2 (S42) O Output pins for switching between key scan output and segment output. Switching is enabled using control codes K0 and K1. 46 ~ 49 KO3 ~ KO6 O Key scan output pins OPEN 50 ~ 54 KI1 ~ KI5 I Key scan input pins OPEN 55 RST I 57 VDD1 — 58 VDD2 — 60 OSC 61 DO Reset input pin for Low Active state. Segment and common outputs are fixed at LOW level while RST is LOW, and all displays disappear. Data for LCD displays is not reset. All data in the key scan buffer is cleared. Internal reference voltage for LCD. When using in the 1 / 2 bias mode, this should be connected to VDD2. VDD — Internal reference voltage for LCD. When using in the 1 / 2 bias mode, this should be connected to VDD1. — — Oscillator pin for segment / common alternating waveforms — O Key buffer data output pin. After a key scan has been completed, if key input existed, this changes to LOW. Also, if the key data communications command is input, the contents of the key buffer are output as serial data. Since this is open drain output, it should be used with a pull-up resistor. OPEN 62 CS I Chip select input pin VSS 63 CK I Synchronous clock input pin for data transmission VSS 64 DI I Data input pin for LCD display VSS •Absolute maximum ratings (Ta = 25°C) Parameter Symbol Power supply voltage VDD VDD VIN RST, OSC, CS, CK, DI, KI1 ~ KI5 – 0.3 ~ VDD + 0.3 V VOUT OSC, DO, KO1 ~ KO6, EP1 ~ EP4 – 0.3 ~ VDD + 0.3 V Input voltage Output voltage Output current BU9768AK Pin Limits Unit – 0.3 ~ + 7.0 V IOUT (1) COM1 ~ COM3 3 mA IOUT (2) EP1 ~ EP4 5 mA IOUT (3) S1 ~ S40 IOUT (4) KO1 ~ KO6 Power dissipation BU9768AKV Pd Storage temperature Tstg — 300 µA 1 mA 800 mW∗ 750 — – 55 ~ + 125 °C ∗ This is the maximum voltage which may be applied to the VSS pin. Reduced by 8.0mW (AK) or 7.5mW (AKV) for each increase in Ta of 1°C over 25°C. 3 Standard ICs BU9768AK / BU9768AKV •Recommended operating conditions (Ta = 25°C) Parameter Symbol Pin Min. Typ. Power supply voltage VDD VDD + 4.5 — + 6.0 V Operating temperature Topr — – 40 — + 85 °C •Electrical characteristics (unless otherwise noted, V DD Max. Unit = 4.5V to 6.0V, Ta = 25°C) Parameter Symbol Pin Min. Typ. Input high level voltage VIH (1) RST, CS, CK, DI 0.8VDD VIH (2) KI1 ~ KI5 0.6VDD Input low level voltage VIL (1) RST, CS ,CK, DI VIL (2) KI1 ~ KI5 Max. Unit — VDD V — VDD V 0 — 0.2VDD V 0 — 0.2VDD V Conditions Input high level current IIH RST, CS, CK, DI — — 6.0 µA V1 = VDD Input low level current IIL RST, CS, CK, DI — — 6.0 µA V1 = VSS Input floating voltage VIF KI1 ~ KI5 — — 0.05VDD V Pull-down resistance RPD KI1 ~ KI5 50 100 200 kΩ VDD = 5.0V Output off leakage current IOFFH DO — — 6.0 µA VO = VDD KO1 ~ KO6 VDD – 2.0 VDD – 1.0 VDD – 0.5 V IO = – 1mA VOH (2) EP1 ~ EP4 VDD – 1.5 — — V IO = – 300µA VOH (3) S1 ~ S42 — VDD – 1.0 — V IO = – 20µA VOH (4) COM1 ~ COM3 — VDD – 1.0 — V IO = – 100µA VOL (1) KO1 ~ KO6 0.5 1.0 2.0 V IO = 50µA VOL (2) EP1 ~ EP4 — — 1.0 V IO = 300µA VOL (3) S1 ~ S42 — 1.0 — V IO = 20µA VOL (4) COM1 ~ COM3 — 1.0 — V IO = 100µA VOL (5) DO — 0.2 (200Ω) 0.5 (500Ω) V IO = 1mA VOH (1) Output high level voltage Output low level voltage Output intermediate level voltage Power supply current VMID (1) COM1 ~ COM3 1 / 2VDD – 1.0 — 1 / 2VDD + 1.0 V 1 / 2bias VMID (2) S1 ~ S42 2 / 3VDD – 1.0 — 2 / 3VDD + 1.0 V 1 / 3bias VMID (3) COM1 ~ COM3 2 / 3VDD – 1.0 — 2 / 3VDD + 1.0 V 1 / 3bias VMID (4) S1 ~ S42 1 / 3VDD – 1.0 — 1 / 3VDD + 1.0 V 1 / 3bias VMID (5) COM1 ~ COM3 1 / 3VDD – 1.0 — 1 / 3VDD + 1.0 V 1 / 3bias IDD1 — — 30 70 µA In sleep mode IDD2 — — 200 500 µA fOSC = 38kHz 䊊 Not designed for radiation resistance. 4 Standard ICs BU9768AK / BU9768AKV •AC timing characteristics (V Parameter DD = 4.5V to 6.0V, Ta = 25°C) Symbol Pin Min. Typ. Max. Unit Rise time tu CS, CK, DI — — 300 ns Fall time td CS, CK, DI — — 300 ns Data setup time ts (1) CK, DI 100 — — ns Data hold time th (1) CK, DI 100 — — ns tCW CS, CK 100 — — ns CS setup time ts (2) CS, CK 100 — — ns CS hold time th (2) CS, CK 100 — — ns CK HIGH level time tH CK 100 — — ns CK LOW level time tL CK 100 — — ns D0 output delay time tdl DO — — CS wait time 200 ns (Note 1) Oscillation guaranteed range OSC fOSC 38 19 kHz 76 (Note 2) (Note 1) Since DO is open drain output, the output delay time varies depending on the pull-up resistance. (Note 2) Values measured for attachments of R = 47kΩ, C = 1000pF. example •Application (1 / 2 bias mode) LCD panel C2 R2 OSC S1 (EP1) · · · · · · · · · · · · S40 VDD R1 COM1 COM2 COM3 RST C1 VDD1 µ-COM KO1 KO2 KO3 KO4 KO5 KO6 VDD2 R3 C3 GND CS CK DI DO KI1 KI2 KI3 KI4 KI5 R1, C1 : Constants should be set to match data communications. R2 : 47kΩ (fosc = 38kHz) C2 : 1000pF (fosc = 38kHz) C3 : ⭌ 0.047µF R3 : 1kΩ ~ 10kΩ Key matrix (30 maximum) Fig. 2 ∗ The pull-up resistor value should be set to a value so that the waveform is not destroyed by the wiring capacitance or other factors. 5 Standard ICs BU9768AK / BU9768AKV (1 / 3 bias mode) LCD panel C2 R2 OSC S1 (EP1) · · · · · · · · · · · · S40 VDD R1 COM1 COM2 COM3 RST C1 VDD1 µ-COM KO1 KO2 KO3 KO4 KO5 KO6 VDD2 R3 C3 C3 GND CS CK DI DO KI1 KI2 KI3 KI4 KI5 R1, C1 : Constants should be set to match data communications. R2 : 47kΩ (fosc = 38kHz) C2 : 1000pF (fosc = 38kHz) C3 : ⭌ 0.047µF R3 : 1kΩ ~ 10kΩ Key matrix (30 maximum) Fig. 3 (1 / 2 bias mode) LCD panel C2 R2 OSC S1 (EP1) · · · · · · · · · · · · S40 VDD R1 COM1 COM2 COM3 RST R3 C1 VDD1 µ-COM KO1 KO2 KO3 KO4 KO5 KO6 VDD2 R4 C3 R3 GND CS CK DI DO KI1 KI2 KI3 KI4 KI5 R1, C1 : Constants should be set to match data communications. R2 : 47kΩ (fosc = 38kHz) C2 : 1000pF (fosc = 38kHz) R3 : The constant should be set to match the panel, through testing or other means. C3 : ⭌ 0.047µF R4 : 1kΩ ~ 10kΩ Key matrix (30 maximum) Fig. 4 ∗ The pull-up resistor value should be set to a value so that the waveform is not destroyed by the wiring capacitance or other factors. 6 Standard ICs BU9768AK / BU9768AKV (1 / 3 bias mode) LCD panel C2 R2 OSC S1 (EP1) · · · · · · · · · · · · S40 VDD R1 COM1 COM2 COM3 RST R3 C1 VDD1 R3 µ-COM KO1 KO2 KO3 KO4 KO5 KO6 VDD2 R4 C3 C3 R3 GND CS CK DI DO KI1 KI2 KI3 KI4 KI5 R1, C1 : Constants should be set to match data communications. R2 : 47kΩ (fosc = 38kHz) C2 : 1000pF (fosc = 38kHz) R3 : The constant should be set to match the panel, through testing or other means. C3 : ⭌ 0.047µF R4 : 1kΩ ~ 10kΩ Key matrix (30 maximum) Fig. 5 ∗ The pull-up resistor value should be set to a value so that the waveform is not destroyed by the wiring capacitance or other factors. 7 Standard ICs BU9768AK / BU9768AKV operation •(1)Circuit Data communications The BU9768AK / BU9768AKV are able to receive LCD display data output from the controller, as well as the results of key scans. 1) LCD display data output (from controller) When LCD data is output, the command code “42” must be output at the beginning of the data. Fig. 6 shows an example of LCD display data output. CS CK LSB DI MSB 0 0 1 0 0 0 0 1 D1 D2 Command code: 42 1 byte (8 bits) D3 D4 D5 D6 D7 D8 LCD display data 1 byte (8 bits) CS CK DI D121 D122 D123 D124 D125 D126 0 0 LCD display data 1 byte (8 bits) A value of 0 LOW must always be input for the 2 bits following D126. DP S0 S1 K0 K1 P0 P1 SC Control code 1 byte (8 bits) Fig. 6 Example of LCD display data transmission q During the time that CS is LOW, the command code “42” is input synchronized to the CK clock, and CS is then set to HIGH before the rise of the next CK clock. w The LCD data is sent, and 0 (LOW level) is input for the two bits following D126. e An 8-bit control code is input, and CS is set to LOW. 8 Standard ICs BU9768AK / BU9768AKV Segment data correspondence table COM3 COM2 COM1 S1 (EP1) D1 (EP1) D2 D3 S2 (EP2) D4 (EP2) D5 D6 COM3 COM2 COM1 S22 D64 D65 D66 S23 D67 D68 D69 S3 (EP3) D7 (EP3) D8 D9 S24 D70 D71 D72 S4 (EP4) D10 (EP4) D11 D12 S25 D73 D74 D75 S5 D13 D14 D15 S26 D76 D77 D78 S6 D16 D17 D18 S27 D79 D80 D81 S7 D19 D20 D21 S28 D82 D83 D84 S8 D22 D23 D24 S29 D85 D86 D87 S9 D25 D26 D27 S30 D88 D89 D90 S10 D28 D29 D30 S31 D91 D92 D93 S11 D31 D32 D33 S32 D94 D95 D96 S12 D34 D35 D36 S33 D97 D98 D99 S13 D37 D38 D39 S34 D100 D101 D102 S14 D40 D41 D42 S35 D103 D104 D105 S15 D43 D44 D45 S36 D106 D107 D108 S16 D46 D47 D48 S37 D109 D110 D111 S17 D49 D50 D51 S38 D112 D113 D114 S18 D52 D53 D54 S39 D115 D116 D117 S19 D55 D56 D57 S40 D118 D119 D120 S20 D58 D59 D60 KO1 (S41) D121 D122 D123 S21 D61 D62 D63 KO2 (S42) D124 D125 D126 9 Standard ICs BU9768AK / BU9768AKV 1. If there is an unused segment output If there is segment output that is not used, depending on the panel, the transmission of the LCD display data can be simplified by deciding the pin or pins to be used starting from S40 (S42 if pins 44 and 45 are used as segment output, and S41 if only pin 44 is used as segment output). CS CK LSB DI MSB 0 0 1 0 0 0 0 1 D25 D26 Command code: 42 1 byte (8 bits) D27 D28 D29 D30 D31 D32 P0 P1 SC LCD display data 1 byte (8 bits) CS CK DI D121 D122 D123 D124 D125 D126 0 LCD display data 1 byte (8 bits) A value of 0 LOW must always be input for the 2 bits following D126. 0 DP S0 S1 K0 K1 Control code 1 byte (8 bits) Fig. 7 Simplified data communication This figure shows an example in which the 30 segment outputs from S11 to S40 are used, and assumes that communication is done in units of eight bits (one byte). For this reason, the data of S9 and S10 (from D25 to D30), which are not used, is input as dummy data. If the unit is not eight bits, this dummy data can be omitted, in which case the data should be input after the command code, starting from the data of D31. However, even if Pins 44 and 45 are used as key scan output and not as segment output, the data for D121 to D126 cannot be omitted. 2. Control codes The BU9768AK is designed to support various applications, depending on the combination of control codes used. • DP: Display mode control Depending on the type of display, either 1 / 2 bias drive or 1 / 3 bias drive may be selected. 1: 1 / 2 bias drive 0: 1 / 3 bias drive • S0 and S1: Sleep mode control In the sleep modes, all displays are turned off, and the oscillation of the OSC pin is stopped, enabling a lower power consumption. In sleep modes, although all of the displays are turned off, key scans are enabled. For information on key scans in the sleep modes, please refer to pages 15 to 22. Various sleep modes can be selected, depending on the application. 10 Standard ICs Control code BU9768AK / BU9768AKV Mode Segment / common output Output Key scan output OSC pin S0 S1 0 0 Normal 0 1 Sleep Fixed at LOW Stopped 1 0 Sleep Fixed at LOW Stopped 1 1 Sleep Fixed at LOW Stopped KO1 KO2 KO3 KO4 KO5 KO6 Oscillating H H H H H H L L L L L L L L H L H H H H H H H H In the Sleep modes, oscillation of the OSC pin stops, but if a button is pressed while the key scan output is on the HIGH line, oscillation begins and a key scan is carried out. When the key scan has been completed, oscillation stops again. • K0, K1: Control that switches between key scan and segment output • P0, P1: Control that switches between segment and expansion pin output The output can be switched to match a variety of applications, depending on the combination of the four bits. Key scan / segment Control code Segment / expansion pin Max. no. of display segments Max. key input K0 K1 P0 P1 44pin 45pin 1pin 2pin 3pin 4pin 0 0 0 0 KO1 KO2 S1 S2 S3 S4 120 30 0 0 0 1 KO1 KO2 EP1 EP2 S3 S4 114 30 0 0 1 0 KO1 KO2 EP1 EP2 EP3 S4 111 30 0 0 1 1 KO1 KO2 EP1 EP2 EP3 EP4 108 30 0 1 0 0 S41 KO2 S1 S2 S3 S4 123 25 0 1 0 1 S41 KO2 EP1 EP2 S3 S4 117 25 0 1 1 0 S41 KO2 EP1 EP2 EP3 S4 114 25 0 1 1 1 S41 KO2 EP1 EP2 EP3 EP4 111 25 0 0 S41 S42 S1 S2 S3 S4 126 20 0 1 S41 S42 EP1 EP2 S3 S4 120 20 1 0 S41 S42 EP1 EP2 EP3 S4 117 20 1 1 S41 S42 EP1 EP2 EP3 EP4 114 20 1 1 1 1 ∗ ∗ ∗ ∗ ∗ Don't Care • SC: Control switching the LCD display on and off Switching the LCD display on and off can be done regardless of the input data. 1: Display off 0: Display on (when displayed, displays can be obtained in accordance with the input data.) Note: When the power supply is turned on, the following settings are in effect for control codes. These initial settings for control codes should be changed to match the mode being used. When the power supply is turned on: (DP, S0, S1, K0, K1, P0, P1, SC) = (0, 0, 0, 1, 1, 0, 0, 0) 11 Standard ICs BU9768AK / BU9768AKV 2) Transmission of key data A command code of “43” should be input in order to output the results of a key scan to the BU9768AK / BU9768AKV. CS CK LSB DI MSB 1 1 0 0 0 0 1 0 Don't Care Command code: 43 1 byte (8 bits) DO D0 D1 D2 D29 D30 SA If there is data in the key buffer, DO will be LOW. 32 bits Fig. 8 Transmission of key data If CS is changed to HIGH level after the command code is input, the data in the key buffer is output synchronized to the rise of CK. Key data correspondence table KO1 (S41) KI1 KI2 KI3 KI4 KI5 D1 D2 D3 D4 D5 KO2 (S42) D6 D7 D8 D9 D10 KO3 D11 D12 D13 D14 D15 KO4 D16 D17 D18 D19 D20 KO5 D21 D22 D23 D24 D25 KO6 D26 D27 D28 D29 D30 • The data D0, which is output synchronized to the rise of CS, is unstable and should not be used. • The output SA of the 32nd bit is a state acknowledge signal and outputs the current BU9768AK / BU9768AKV mode. SA: State acknowledge signal In normal modes: SA = LOW In sleep modes : SA = HIGH 12 Standard ICs BU9768AK / BU9768AKV (2) Key scan operation With the BU9768AK / BU9768AKV, up to 30 key inputs can be received. KEY ON 15ms KO1 KO2 KO3 KO4 When the key scan is completed without problems, DO changes from HIGH to LOW. KO5 KO6 DO Fig. 9 Key scan operation One key scan requires 15ms (if fOSC = 38kHz, 582 / fOSC (sec)). Key scans which are shorter than this time cannot be received. Also, in order to prevent chattering, the key scan waveform (KO output) reaches the HIGH level twice during one key scan. After scanning has been carried out twice, the data from the two scans is compared, and if the data for all of the keys does not match, an error occurs. 1) Key scans and key data communications With the BU9768AK / BU9768AKV, if normal key input is received, DO changes from HIGH to LOW, so if DO is connected to the interrupt input pin of the controller, interrupt processing can be carried out based on the key input. Also, after DO changes to LOW following completion of a key scan, a new key scan cannot be carried out until all of the key data has been read. If multiple keys are pressed at once, multiple key data is set for the various key inputs to be distinguished. New key scan cannot be carried out until all data has been read. Key scan Key scan Key1 Key2 Key3 Key scan Key data reading DO Data corresponding to one key scan Fig. 10 Relationship between key scan and data communications 13 Standard ICs BU9768AK / BU9768AKV 2) Key scans in sleep modes In sleep modes, depending on the mode, the key scan standby state of the KO pin is restricted. Standby state in sleep mode (L) KO1 KEY1 KEY2 KEY3 KEY4 KEY5 (L)KO2 KEY6 KEY7 KEY8 KEY9 KEY10 Enlarged view of one key (L)KO3 KEY11 KEY12 KEY13 KEY14 KEY15 (L)KO4 KEY16 KEY17 KEY18 KEY19 KEY20 (L)KO5 KEY21 KEY22 KEY23 KEY24 KEY25 Key input received (H)KO6 KEY26 KEY27 KEY28 KEY29 KEY30 Kl1 Kl2 Kl3 Kl4 Kl5 Fig. 11 Example of key matrix configuration (The diodes installed on each key are to prevent erroneous recognition if multiple keys are pressed.) The figure above assumes that the control codes S0 and S1 have been set to 0 and 1, respectively. In this case, if any key between key 26 and key 30 is pressed, an HIGH level is input on the KIn line, oscillation begins, and a key scan is carried out. If any key between key 1 and key 25 is pressed, all of the KIn lines remain at LOW level, and no key scan is carried out. Oscillation resumes when the key scan has been completed. If key input in a sleep mode is to be used and interrupt processing carried out, a key on a KOn = HIGH line should be used. 14 Standard ICs BU9768AK / BU9768AKV 3) Operation flow in a key scan The flow of operations taking place during a key scan is shown below. Waiting for key input Has key been input? No Yes Key input (key scan starts) Was key scan successful? No Yes DO → LOW Waiting for input of key data read code Fig. 12 Key scan flow The “successful” judgment of the key scan shown in the illustration is based on the data from the two key scans matching for all of the keys, as described on page 13. If an error occurs, the key scan is carried out once again after the first key scan has been completed if a key has remained pressed, and continues to be carried out as long as the key is pressed, until it is successfully completed. After a key scan has been successfully completed, no new key scans can be carried out until reading of the key data has been completed. 15 Standard ICs BU9768AK / BU9768AKV (3) Output waveforms 1) 1 / 2 bias mode (frame frequency = fOSC / 384) 1 frame VDD COM1 1 / 2VDD VSS VDD COM2 1 / 2VDD VSS VDD COM3 1 / 2VDD VSS VDD When Sn (D3n-2, D3n-1, D3n) = (0, 0, 0): 1 / 2VDD Out for all COMs VSS VDD When Sn (D3n-2, D3n-1, D3n) = (0, 0, 1): 1 / 2VDD Lights between COM1 and Sn only VSS Sn VDD When Sn (D3n-2, D3n-1, D3n) = (1, 0, 1): 1 / 2VDD Out between COM2 and Sn only VSS VDD When Sn (D3n-2, D3n-1, D3n) = (1, 1, 1): 1 / 2VDD VSS 16 Lights for all COMs Standard ICs BU9768AK / BU9768AKV 2) 1 / 3 bias mode (frame frequency = fOSC / 384) 1 frame VDD 2 / 3VDD COM1 1 / 3VDD VSS VDD 2 / 3VDD COM2 1 / 3VDD VSS VDD 2 / 3VDD COM3 1 / 3VDD VSS VDD 2 / 3VDD When Sn (D3n-2, D3n-1, D3n) = (0, 0, 0): Out for all COMs 1 / 3VDD VSS VDD 2 / 3VDD 1 / 3VDD When Sn (D3n-2, D3n-1, D3n) = (0, 0, 1): Lights between COM1 and Sn only VSS Sn VDD 2 / 3VDD When Sn (D3n-2, D3n-1, D3n) = (1, 0, 1): Out between COM2 and Sn only 1 / 3VDD VSS VDD 2 / 3VDD When Sn (D3n-2, D3n-1, D3n) = (1, 1, 1): Lights for all COMs 1 / 3VDD VSS 17 Standard ICs BU9768AK / BU9768AKV (4) RST and display control After the power supply has been turned on, because the internal data of the BU9768AK / BU9768AKV (D1 to D126) is unstable, RST goes LOW at the same time that the power supply is turned on. While RST is LOW, data is transmitted using the microcomputer, and when data transmission has been completed, RST can be set to HIGH to prevent meaningless displays. (For the states of control codes when the power supply is turned on, see page 11.) VDD RST VIL t1 t2 CS Internal data Display and control data Unstable Assured Display Display t1: Communication time t2: 10µs min. Fig. 13 Communication, display and RST timing VDD R RST C GND Fig. 14 Example of RST pin processing In the circuit example shown above, the value of t1 is determined by the value of the capacitor and resistor. The value should be set in such a way that the constant determined by the capacitor and resistor is the initialized communication time + t2. 18 Standard ICs BU9768AK / BU9768AKV notes •(1)Operation Using the product with the synchronous clock stopped If the synchronous clock is to be stopped during the period that data is not being transmitted, program the product so that the rise of CK is input at least twice after the fall of CS. CS CK CK rises at least twice Fig. 15 When CK is stopped at HIGH CS CK CK rises at least twice Fig. 16 When CK is stopped at LOW (2) Precautions concerning key scans when the power supply is turned on To carry out a key scan immediately after the power supply is turned on, without transmitting data, the parameters must be set so that the following conditions are met. 1) The rise of the synchronous clock pulse is input to the CK pin at least twice. 2) Since input can only be received from keys on the KO3 to KO6 line, other keys should not be used for functions such as interrupts. (For information on the status when the power supply is turned on, please see page 11.) ∗ If data is being transferred before a key scan is carried out, after the power supply is turned on, these precautions do not apply. 19 Standard ICs BU9768AK / BU9768AKV Make sure of the following when resetting when the power is on. • When using the external reset terminal, make RST = “L” at 1ms or more with VDD at 4.5V or more. • When not using the external reset terminal, VDD has to satisfy the following conditions. Instruction receipt possible VDD ⭌ 4.5V tWAIT ⭌ 1ms VDD < 0.3V 0 < tON < 10ms •External dimensions (Units: mm) BU9768AK BU9768AKV 48 16 0.8 0.35 ± 0.1 0.15 ± 0.1 0.15 QFP-A64 20 17 64 0.5 16 0.5 12.0 ± 0.3 10.0 ± 0.2 33 32 49 1 1.4 ± 0.1 1 0.5 17 64 0.10 2.7 ± 0.1 12.0 ± 0.3 10.0 ± 0.2 32 49 0.05 16.4 ± 0.3 14.0 ± 0.2 16.4 ± 0.3 14.0 ± 0.2 48 33 0.125 ± 0.1 0.2 ± 0.1 0.1 VQFP64