DATA SHEET MOS INTEGRATED CIRCUIT µ PD16681 LCD CONTROLLER/DRIVER FOR DOT MATRIX DISPLAY OF JIS LEVEL 1 AND JIS LEVEL 2 KANJI SETS DESCRIPTION The µPD16681 is a single-chip controller driver that can display Japanese text; including JIS Level 1 kanji, JIS Level 2 kanji, hiragana, and katakana. Each chip can display up to four lines containing up to eight full width characters (11 x 12 dots), or up to four lines containing up to 16 half width characters (5 x 12 dots), as well 96 pictographs. FEATURES • LCD controller/driver for dot matrix display of JIS Level 1 and JIS Level 2 kanji sets • On-chip ROM for character generation −JIS Level 1 + Level 2 kanji (11 x 12 dots) : 6,355 characters −JIS non-kanji characters (11 x 12 dots) : 453 characters −Other characters (symbols, etc.) (11 x 12 dots): 256 characters −Half width alphanumeric characters (5 x 12 dots) : 192 characters • On-chip RAM for character generation −8 types (12 x 13 dots) • On-chip boost circuit : switchable between 3x and 4x modes • RAM for pictograph data displays : 96 bits • Outputs : 96 segments, 52 commons • Duty settings : 1/39 or 1/52 • Switchable data inputs : serial or 8-bit parallel • On-chip divider resistor • Selectable bias settings (1/8 bias, 1/7 bias, or 1/6 bias) • On-chip oscillation circuit ORDERING INFORMATION Part number Package ROM code µPD16681W-011 Wafer Standard µPD16681P-011 Chip (COG compliant) Standard The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. S13104EJ5V0DS00(5th edition) Document No. Date Published November 1999 NS CP(K) Printed in Japan The mark ★ shows major revised points. © 1999 µPD16681 1. BLOCK DIAGRAM OSCOUT OSCIN OSCBRI /RESET Oscillation Circuit Timing Generator SEGINV COMINV Index Register VDD VLCD Control Register VSS Common Driver WS Display Data RAM RAM Address Counter STB COM1 to COM51 PCOM1,PCOM2 E/SCK D0/DATA I/O Buffer 8 96 bits Shift Register D1 to D7 8 TESTOUT 96 bits Latch Circuit Segment Driver 8 RAM Data Register 8 Address Formation Circuit 8 4 3 12 7 Character Generator RAM Full-width Character Generator ROM Half-width Character Generator ROM 6 6 6 8 Pictograph Data RAM 6 Display Attribute Control Circuit DACHA D/A Converter 6 Cursor Control Circuit − C1+, C1 − C2+, C2 C3+, C3− Parallel/Serial Conversion Circuit Smooth Scroll Control Circuit DC/DC Converter VEXT OP Amp. AMPIN(+) LCD Voltage Generator AMPIN(−) AMPCHA AMPOUT Remark 2 VLCBS1 VLC2 VLC1 VLC3 /xxx indicates active low signals. Data Sheet S13104EJ5V0DS00 VLC5 VLCBS3 VLCBS2 VLC4 SEG1 to SEG96 µPD16681 2. PIN CONFIGURATION (Pad Layout) Chip size : 2.80 x 10.48 mm 2 219 241 218 1 Y X 82 108 83 107 Data Sheet S13104EJ5V0DS00 3 µPD16681 Table 2-1. Pad Layout PAD No. DUMMY1 VLCBS1 VLCBS1 VLCBS2 VLCBS2 VLCBS3 VLCBS3 AMPOUT AMPOUT AMPIN(−) AMPIN(−) AMPIN(+) AMPIN(+) VLC5 VLC5 VLC5 VLC4 VLC4 VLC4 VLC3 VLC3 VLC3 VLC2 VLC2 VLC2 VLC1 VLC1 VLC1 VLCD VLCD VLCD X (µm) Y (µm) PAD No. −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 4800 4680 4560 4440 4320 4200 4080 3960 3840 3720 3600 3480 3360 3240 3120 3000 2880 2760 2640 2520 2400 2280 2160 2040 1920 1800 1680 1560 1440 1320 1200 1080 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 X (µm) Y (µm) PAD No. DACHA AMPCHA SEGINV COMINV OSCIN OSCOUT OSCBRI D0/DATA D1 D2 D3 D4 D5 D6 D7 WS STB E/SCK /RESET TESTOUT DUMMY2 DUMMY3 DUMMY4 DUMMY5 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1120 −1030 −940 −850 −760 −670 −580 −490 −400 −310 −2400 −2520 −2640 −2760 −2880 −3000 −3120 −3240 −3360 −3480 −3600 −3720 −3840 −3960 −4080 −4200 −4320 −4440 −4560 −4680 −4800 −4920 −5113 −5113 −5113 −5113 −5113 −5113 −5113 −5113 −5113 −5113 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 Pin Name X (µm) Y (µm) PAD No. SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 −3735 −3645 −3555 −3465 −3375 −3285 −3195 −3105 −3015 −2925 −2835 −2745 −2655 −2565 −2475 −2385 −2295 −2205 −2115 −2025 −1935 −1845 −1755 −1665 −1575 −1485 −1395 −1305 −1215 −1125 −1035 −945 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 Pin Name X (µm) Y (µm) SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM26 COM25 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1665 1755 1845 1935 2025 2115 2205 2295 2385 2475 2565 2655 2745 2835 2925 3015 3105 3195 3285 3375 3465 3555 3645 3735 3825 3915 4005 4095 4185 4275 4365 4455 Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 C1 + 33 C1 + −1273 960 93 COM35 −220 −5113 153 SEG58 1273 −855 213 COM24 1273 4545 34 C1 C1− C1− C1− + −1273 840 94 COM36 −130 −5113 154 SEG57 1273 −765 214 COM23 1273 4635 −1273 −1273 −1273 −1273 720 600 480 360 95 96 97 98 COM37 COM38 COM39 COM40 −40 50 140 230 −5113 −5113 −5113 −5113 155 156 157 158 SEG56 SEG55 SEG54 SEG53 1273 1273 1273 1273 −675 −585 −495 −405 215 216 217 218 COM22 COM21 DUMMY10 DUMMY11 1273 1273 1273 1273 4725 4815 4905 4995 35 36 37 38 C2 + 39 C2 + −1273 240 99 COM41 320 −5113 159 SEG52 1273 −315 219 DUMMY12 950 5113 40 C2 C2− C2− C2− + −1273 120 100 COM42 410 −5113 160 SEG51 1273 −225 220 COM20 860 5113 −1273 −1273 −1273 −1273 0 −120 −240 −360 101 102 103 104 COM43 COM44 COM45 COM46 500 590 680 770 −5113 −5113 −5113 −5113 161 162 163 164 SEG50 SEG49 SEG48 SEG47 1273 1273 1273 1273 −135 −45 45 135 221 222 223 224 COM19 COM18 COM17 COM16 770 680 590 500 5113 5113 5113 5113 41 42 43 44 C3 + 45 C3 + −1273 −480 105 COM47 860 −5113 165 SEG46 1273 225 225 COM15 410 5113 46 C3 C3− C3− C3− VDD1 VDD1 VDD2 VDD2 VDD2 VSS VSS VSS VSS VSS VEXT + −1273 −600 106 DUMMY6 950 −5113 166 SEG45 1273 315 226 COM14 320 5113 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −1273 −720 −840 −960 −1080 −1200 −1320 −1440 −1560 −1680 −1800 −1920 −2040 −2160 −2280 107 108 109 110 111 112 113 114 115 116 117 118 119 120 DUMMY7 DUMMY8 COM48 COM49 COM50 COM51 DUMMY9 PCOM2 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 1040 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 −5113 −4905 −4815 −4725 −4635 −4545 −4455 −4365 −4275 −4185 −4095 −4005 −3915 −3825 167 168 169 170 171 172 173 174 175 176 177 178 179 180 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 1273 405 495 585 675 765 855 945 1035 1125 1215 1305 1395 1485 1575 227 228 229 230 231 232 233 234 235 236 237 238 239 240 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 PCOM1 230 140 50 −40 −130 −220 −310 −400 −490 −580 −670 −760 −850 −940 5113 5113 5113 5113 5113 5113 5113 5113 5113 5113 5113 5113 5113 5113 241 DUMMY13 −1030 5113 47 48 49 50 51 52 53 54 55 56 57 58 59 60 4 Pin Name Data Sheet S13104EJ5V0DS00 µPD16681 3. PIN FUNCTIONS 3.1 Power Supply System Pins Pin Symbol VDD Pin Name Logic power supply pin Pad No. I/O Description 50-54 − Power supply pins for logic and boost circuit 55-59 − Ground pins for logic and driver circuit 29-31 − Power supply pins for driver. Output pin for internal boost circuit. Boost circuit power supply pin VSS Logic ground Driver ground VLCD Driver power supply pins Connect a 1-µF capacitor between these pins and the VSS pins for boosting. If not using the internal boost circuit, a direct driver power supply can be input. VLC1 - VLC5 Reference power supply pins for driver VLCBS1 - VLCBS3 Bias value setting pins + - + - + - C1 , C1 C2 , C2 Capacitor connection pins 14-28 − These are reference power supply pins for the LCD driver. Leave these pins open if an internal bias has been selected. Connect a capacitor to ground. 2-7 − When selecting an internal bias, the bias value can be changed connecting these pins outside of the IC. 32-49 − These are capacitor connection pins for the boost circuit. Connect a 1-µF capacitor. C3 , C3 Data Sheet S13104EJ5V0DS00 5 µPD16681 3.2 Logic System Pins Pin Symbol Pin Name Pad No. I/O Description WS Select word length 76 I Use this pin to select the word length. An 8-bit parallel interface is used for high level and a serial interface is used for low level. This setting cannot be changed after the power has been switched on. DACHA Select D/A converter 61 I Use this pin to select whether or not to use the D/A converter for regulating the LCD driver voltage. Select high level to use the D/A converter or low level to not use it. STB Strobe 77 I This is used for the device’s select signal and strobe signal for communication. Communication is initialized at the rising edge or falling edge of STB. Command data receive standby status occurs at the falling edge of STB. Communication is enabled when STB is low. Also, enabled status or the shift clock is ignored when STB is high. E/SCK Enable/shift clock 78 I This is an input enable pin for data when the parallel interface is used. During the read-in operation, data is captured in the interface buffer at the signal’s rising edge. During a read-out operation, data is read-out from the interface buffer at the signal’s falling edge. When using a serial interface, this pin is used for the data shift clock. During the read-in operation, data is captured in the shift register at the signal’s rising edge. During a read-out operation, data is read from the shift register at the signal’s falling edge. D0/DATA Data bus/data 68 I/O This pin is used for data bus bit D0 when using the parallel interface. When using the serial interface, it is an I/O pin (tri-state) for commands and display data. D1-D7 Data bus 69-75 I/O These pins are used for data bus bits D1 to D7 when using the parallel interface. It should be fixed high or low when using the serial interface. • TESTOUT Test output 80 O This is a test output pin. Leave this pin open when using the device. /RESET Reset 79 I This pin is used for internal resets at low-level. AMPCHA Op amp switch for LCD driver’s power supply level 62 I This pin is used to control the op amp that works with the LCD driver’s power supply level. High-power mode is set when at low level and normal mode is set when at high level. VEXT Reference power supply switch 60 I This pin is used to select the reference power supply circuit’s supply mode. High level sets external mode and low level sets internal mode. SEGINV Segment direction switch 63 I This pin is used to control the segment output direction. Low level sets forward direction and high level sets reverse direction. COMINV Common scan direction switch 64 I This pin is used to switch the common scan direction. Low level sets forward direction and high level sets reverse direction. OSCIN Oscillator pins 65 I These pins are connected to a 100-kΩ resistance. When using an 66 O external oscillator, input to OSCIN and leave OSCOUT unconnected. 67 I This is an input pin for the 2-Hz external clock. Internally, it is divided by half to generate a 1-Hz signal that is used as the synchronization signal for the blink function. OSCOUT OSCBRI 6 External clock for blink function Data Sheet S13104EJ5V0DS00 µPD16681 3.3 Driver System Pins Pin Symbol Pin Name Pad No. I/O SEG1 - SEG96 Segment 115-210 O COM1 COM51 85-105 O 109-112 1/52 duty : Use COM1 to COM51. 211-216 1/39 duty : Use COM1 to COM19, COM27 to COM45, Common Description Segment output pins Common output pins 220-239 PCOM1, Pictograph common 240 PCOM2 leave COM20 to COM26, COM46 to COM51 open. O 114 AMPIN(+) Op amp inputs Common output pins for pictographs The same signal is output from PCOM1 and PCOM2. 10-13 I These are input pins for the op amp that regulates the LCD driver voltage. Leave the AMPIN(+) pin unconnected when using the on-chip D/A converter. When not using the D/A converter, a reference voltage must AMPIN(−) be input. Connect the AMPIN(−) pin to a resistor used to regulate the LCD voltage. (See diagram below.) AMPOUT Op amp outputs 8,9 O These are output pins for the op amp that regulates the LCD driver voltage. Normally, they are connected to resistors that are used to regulate the LCD voltage. (See diagram below.) Since the AMPOUT pins are used to stabilize the on-chip amp’s output, we recommend connecting them to a capacitor that is rated between 0.1 and 1.0 µF. DUMMY DUMMY pins 1,81-84, − 106-108, DUMMY pins are not connected to the internal circuit. Leave open if they are not used. 113, 217-219, 241 Figure 3-1. Voltage Control Circuit DACHA D/A converter VEXT Reference power supply circuit + AMPIN(+) − AMPIN(−) AMPOUT VLC1 VLC2 VLC3 VLCBS1 VLCBS2 VLCBS3 VLC4 VLC5 VSS R2 R1 C1 Data Sheet S13104EJ5V0DS00 7 µPD16681 4. POWER SUPPLY CIRCUIT A switchable (3x or 4x) boost circuit is included to generate a current for driving the LCD. A connection to a boostrelated capacitor is used to switch the boost circuit’s setting. The VEXT pin (H: external, L: internal) is used to switch between using an external LCD driver power supply or the on-chip boost circuit. 4.1 Boost Circuit When using the internal power supply, connect the boost-related capacitor between C1 and C1−, C2+ and C2−, and + C3+ and C3−. Also, connect the capacitor for level stabilization between VLCD and VSS, and set VEXT low to boost the potential between VDD and VSS from 3 to 4 times. Since the boost circuit uses signals from the internal oscillation circuit, the oscillation circuit must be operating. The relation between the boosted voltage and the potential is described below. The C1 , C1−, C2+, C2−, C3+, C3− and VDD pins all relate to the boost circuit, so the wire impedance should be + minimized. Figure 4-1. 3x and 4x Boost Mode VLCD = 4VDD = 12 V (During 4x boost mode) VLCD = 3VDD = 9 V (During 3x boost mode Note ) VDD = 3 V VSS = 0 V Note When set for 3x boost, connect boost-related capacitors between C2− and C3+ and C1+ and C1−. 8 Data Sheet S13104EJ5V0DS00 µPD16681 4.2 Regulation of LCD Driver Voltage 4.2.1 When not using internal power supply select or D/A converter (VEXT = L, DACHA = L) When using the internal power supply, the boosted voltage is used as the power supply for the op amp incorporated in the IC for the LCD driver’s voltage. A common mode amplifier circuit can be configured by connecting external resistors R1 and R2 and inputting the reference voltage VREF to AMPIN(+), and this configuration can be used to regulate the potential of the LCD driver voltage VLC1. If using a thermistor to regulate the LCD driver voltage to suit the liquid crystals’ temperature characteristics, we recommend connecting in parallel to R2. The LCD driver voltage VLC1 can be determined using the following formula. VLC1 = AMPOUT = 1+ R2′ = R2′ VREF R1 R2 ‚ Rth R2 + Rth Figure 4-2. When Not Using Internal Power Supply Select or D/A Converter DACHA D/A converter VREF To internal drive circuit + AMPIN(+) − AMPIN(−) AMPOUT VLC1 Rth R2 R1 C1 4.2.2 When using internal power supply select and D/A converter (VEXT = L, DACHA = H) Using the D/A converter enables commands to be entered to control the reference voltage VREF that is input to the + input of the op amp for the LCD driver voltage. The D/A converter function sets 6-bit data to the D/A converter set register to set one of the 64 modes for the reference voltage VREF between VDD and 1/2 VDD. The formula for VLC1 is the same as in 4.2.1 When not using internal power supply select or D/A converter (VEXT = L, DACHA = L) above. Data Sheet S13104EJ5V0DS00 9 µPD16681 Figure 4-3. Using Internal Power Supply Select and D/A Converter VDD VDD D/A converter DACHA VREF AMPIN(+) OPEN To internal drive circuit + − AMPIN(−) AMPOUT VLC1 Rth R2 R1 C1 4.2.3 When using an external power supply (VEXT = H) When an external power supply is used for the LCD driver voltage, the op amp incorporate in the µPD16681 (used for the LCD driver voltage) is in OFF mode. Consequently, the LCD driver’s op amp and D/A converter function cannot be used when using an external power supply. Instead, regulate the LCD driver voltage by inputting directly to the VLCD and VLC1 pins. Cautions 1. Maintain the following relation for the voltage input to the VLCD and VLC1 pins : VLCD > VLC1 2. Since the DACHA, AMPIN(+), and AMPIN(−−) pins are CMOS inputs, they should be fixed either high or low. 3. The AMPOUT pin should be left unconnected. 4.3 Reference Voltage 4.3.1 When using internal power supply (VEXT = L) When using the internal power supply, the µPD16681’s on-chip divider resistor is used to create the six-level potential (VLC1, VLC2, VLC3, VLC4, VLC5, and VSS) required for the LCD driver. 4.3.2 When using an external power supply (VEXT = H) When use of an external power supply has been selected, the op amp incorporated in the µPD16681 for the LCD driver level power supply is in OFF mode, so a reference potential must be directly input to VLC1, VLC2, VLC3, VLC4, and VLC5. Ordinarily, these levels are generated by dividing the resistance. Since large resistance values result in poorer LCD display quality, be sure to select a resistance value that suits the type of LCD panel to be used. The display quality can be improved by connecting capacitors between the level pins and ground pins. As with the resistance values described above, the capacitance values of the capacitors should be selected to suit the divided resistance values and the type of LCD panel to be used. 10 Data Sheet S13104EJ5V0DS00 µPD16681 4.4 Control of Op Amp for Level Power Supply Input to the AMPCHA pin is used to control the op amp for the LCD driver level power supply. • High power mode (AMPCHA = L) This mode maximizes the LCD drive current supply capacity in the op amp for the LCD driver level power supply. • Normal mode (AMPCHA = H) This mode uses a lower LCD drive current supply capacity in the op amp for the LCD driver level power supply, which is suitable for charging the capacitor used to stabilize the external level. Caution For either mode, be sure to connect a level stabilization capacitor (rated from about 0.1 to 1.0 µF) for the VLC1 to VLC5 pins. Poorer display quality results when these capacitors are not connected. Figure 4-4. Reference Voltage Circuit AMPOUT VLC1 + − Output to SEG and COM R VLC2 + − Output to SEG and COM R VLC3 + − Output to SEG and COM VLCBS1 Op amp for level driver R VLCBS2 R VLCBS3 2R VLC4 + − Output to SEG and COM R VLC5 + − Output to SEG and COM R VSS Output to SEG and COM Data Sheet S13104EJ5V0DS00 11 µPD16681 4.5 Bias Value Settings The bias value can be set as 1/6 bias, 1/7 bias, or 1/8 bias by selecting an internal bias for the (µPD16681 and by connecting externally from the IC among VLCBS1, VLCBS2, and VLCBS3 pins. Bias Value Connected Pin 1/8 bias VLCBS1, VLCBS2, and VLCBS3 leave open 1/7 bias Between VLCBS1 and VLCBS2 or between VLCBS2 and VLCBS3 1/6 bias Between VLCBS1 and VLCBS3 and VLCBS2 leave open 4.6 Power Supply Circuit Use Example Figure 4-5. Using Internal Power Supply and Normal Mode B) 3x boost A) 4x boost (D/A converter is not used.) To VDD VDD VDD AMP(+) VLCD R2 AMP(−) Rth (thermistor) + C2 VLCD + R1 C1+ AMPOUT VLC1 C2 + + C1 + + C1 + VLC2 C1 − C1 + C2 C1 + VLC3 open + C1 + VLC4 − C2 + C2− − C2 + C3 + C1 + VLC5 + C3+ C1 + − C3 open VDD VEXT AMPCHA VSS − VCHA VEXT VSS Remarks 1. C1 = 1.0 µF,C2 = 1.0 µF 2. Leave C2 and C3− pins open during 3x boost. + 3. Leave AMP(+) open when using the D/A converter. 12 C3 Data Sheet S13104EJ5V0DS00 µPD16681 Figure 4-6. Using External Power Supply Circuit A) Use 1/8 bias VDD AMP(+) AMP(−) To external drive supply AMPOUT open VLCD C1+ VLC1 R − C1 C2 VLC2 + R open VLC3 − C2 C3+ 4R VLC4 − R C3 VLC5 VDD VEXT R VSS Remark Fix all open input pins high or low. Data Sheet S13104EJ5V0DS00 13 µPD16681 5. LCD DISPLAY DRIVER Either a 1/52 duty driver or a 1/39 duty driver can be selected for the µPD16681. Both drivers output a drive waveform using the two-frame AC drive method. 5.1 1/52 Duty Driver When the 1/52 duty driver is selected for the µPD16681, a select signal is output once per frame from the dot block’s common outputs (COM1 to COM51) and from the pictograph block’s common outputs (same signal output from PCOM1 and PCOM2). Figure 5-1. 1/52 Duty Driver 1Frame 1 2 3 4 5 6 7 8 50 51 52 1 2 3 4 5 6 7 8 VLC1 VLC2 VLC3 SEG1 VLC4 VLC5 VSS VLC1 VLC2 VLC3 COM1 VLC4 VLC5 VSS VLC1 VLC2 VLC3 COM2 VLC4 VLC5 VSS PCOM1 PCOM2 14 VLC1 VLC2 VLC3 VLC4 VLC5 VSS Data Sheet S13104EJ5V0DS00 50 51 52 µPD16681 5.2 1/39 Duty Driver When the 1/39 duty driver is selected for the µPD16681, a select signal is output once per frame from the dot block’s common outputs (COM1 to COM19, COM27 to COM45) and from the pictograph block’s common outputs (same signal output from PCOM1 and PCOM2). Figure 5-2 1/39 Duty Driver 1Frame 1 2 3 4 5 6 7 8 37 38 39 1 2 3 4 5 6 7 8 37 38 39 VLC1 VLC2 VLC3 SEG1 VLC4 VLC5 VSS VLC1 VLC2 VLC3 COM1 VLC4 VLC5 VSS VLC1 VLC2 VLC3 COM2 VLC4 VLC5 VSS PCOM1 PCOM2 VLC1 VLC2 VLC3 VLC4 VLC5 VSS Data Sheet S13104EJ5V0DS00 15 µPD16681 6. DESCRIPTION OF BLOCKS 6.1 Display Data RAM (DDRAM) DDRAM is RAM that contains display data consisting of a 16-bit character code plus a character attribute code. The RAM capacity is 16 x 72 bits, which means that up to 72 characters can be stored in RAM. The following table shows correspondences between DDRAM addresses and LCD display positions. For further description of these correspondences, see the section 7.1 LCD display and DDRAM addresses. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1st line 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 2nd line 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 3rd line 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 4th line 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H 6.2 Full Width (11x12 dots) Character Generator ROM (FCGROM) FCGROM generates a total of 7,064 full width character patterns, of which 6,355 are JIS Level 1 + Level 2 kanji, 453 are non-kanji characters and 256 other symbols. These character patterns are displayed in 11 x12 dot font patterns based on 12-bit character codes. The section entitled 7.2.2 Full Width(11 x 12 dots) Character Code Setting Examples describes the correspondence between the character codes set to DDRAM and this full width font pattern. Also, see the section entitled 7.2 Character Codes for a description of the correspondence between the JIS code and the character code set to DDRAM. 6.3 Half Width(5 x 12 dots) Character Generator ROM (HCGROM) FCGROM generates a total of 192 half width (5 x 12 dots) character patterns, displayed in 5 x 12 dot font patterns. The section entitled 7.2 Character Codes describes the correspondence between the character code set to DDRAM and the half width font patterns. 16 Data Sheet S13104EJ5V0DS00 µPD16681 6.4 Character Generator RAM (CGRAM) CGRAM is RAM to which the user can freely set character patterns. Eight types of 12 x 13 dot character patterns can be defined. To display a character pattern that has been stored in CGRAM, the user specifies a value ranging from “000H” to “007H”. The relation between character codes and CGRAM addresses used to access CGRAM is shown below. Figure 6-1. The Relation between Character Codes and CGRAM Addresses Character code CGRAM Data CGRAM Address to C12 0 0 0 0 A0 ="0" A0 ="1" C3 C2 C1 C0 A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A 0 0 0 0 0 0 A A 0 0 0 0 0 0 0 0 0 0 1 A A 0 1 1 1 1 1 A A 1 1 1 1 0 0 0 0 1 0 A A 0 1 0 0 0 0 A A 0 0 0 1 0 0 0 0 1 1 A A 0 1 0 0 0 0 A A 0 0 0 1 0 0 0 1 0 0 A A 0 1 0 0 0 0 A A 0 0 0 1 0 0 0 1 0 1 A A 0 1 0 0 0 0 A A 0 0 0 1 0 0 0 1 1 0 A A 0 1 1 1 1 1 A A 1 1 1 1 0 0 0 1 1 1 A A 0 1 0 0 0 0 A A 0 0 0 1 0 0 1 0 0 0 A A 0 1 0 0 0 0 A A 0 0 0 1 0 0 1 0 0 1 A A 0 1 0 0 0 0 A A 0 0 0 1 0 0 1 0 1 0 A A 0 1 0 0 0 0 A A 0 0 0 1 0 0 1 0 1 1 A A 0 1 1 1 1 1 A A 1 1 1 1 0 0 1 1 0 0 A A 0 0 0 0 0 0 A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 A A 0 0 0 0 0 1 A A 0 0 0 0 0 0 0 0 0 0 1 A A 0 0 0 0 0 1 A A 0 0 0 0 0 0 0 0 1 0 A A 1 1 1 1 1 1 A A 1 1 1 1 1 0 0 0 1 1 A A 0 0 0 0 1 1 A A 1 0 0 0 0 0 0 1 0 0 A A 0 0 0 1 0 1 A A 0 1 0 0 0 0 0 1 0 1 A A 0 0 0 1 0 1 A A 0 1 0 0 0 0 0 1 1 0 A A 0 0 1 0 0 1 A A 0 0 1 0 0 0 0 1 1 1 A A 0 0 1 0 0 1 A A 0 0 1 0 0 0 1 0 0 0 A A 0 1 0 0 0 1 A A 0 0 0 1 0 0 1 0 0 1 A A 0 1 0 1 1 1 A A 1 1 0 1 0 0 1 0 1 0 A A 1 0 0 0 0 1 A A 0 0 0 0 1 0 1 0 1 1 A A 0 0 0 0 0 1 A A 0 0 0 0 0 0 1 1 0 0 A A 0 0 0 0 0 0 A A 0 0 0 0 0 0 0 0 0 0 0 · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 A A A A 0 0 0 1 A A A A 0 0 1 0 A A A A 0 0 1 1 A A A A 0 1 0 0 A A A A 0 1 0 1 A A A A 0 1 1 0 A A A A 0 1 1 1 A A A A 1 0 0 0 A A A A 1 0 0 1 A A A A 1 0 1 0 A A A A 1 0 1 1 A A A A 1 1 0 0 A A A A Data Sheet S13104EJ5V0DS00 17 µPD16681 Remarks 1. CGRAM is selected when the high-order nine bits (C11 to C3) of a character code are all zeros. At that time, the low-order three bits (C2 to C0) corresponds to CGRAM addresses 7 to 5 (A7 to A5). (Three bits: eight types.) 2. Display ON is selected when the CGRAM data value is “1”. Display OFF is selected when this data value is “0”. 3. The CGRAM address 0 (A0) corresponds to the left and right sides of the character pattern. 4. The high-order two bits of CGRAM are used to control the display attributes of the pattern corresponding to the low-order six bits. In such cases, any display attribute specification made for DDRAM is ignored. When the value of the high-order two bits is “00”, CGRAM’s pattern is displayed. 5. CGRAM addresses 4 to 1 (A4 to A1) corresponds to the line position of the character pattern. (Four bits : 13 lines) The ORed result with the cursor is taken and displayed on the 12th line. 6.5 Pictograph Display RAM (PDRAM) PDRAM is the RAM that contains pictograph display data that has been assigned to PCOM1 and PCOM2. The data display function is ON when the data value is “1” and OFF when the data value is “0”. After data is written, the address counter is automatically incremented (by one), and the value after 0FH is 00H. The correspondence between output from various segments and PDRAM addresses is shown below. PCOM1,PCOM2 Address b7 b6 b5 b4 b3 b2 b1 b0 00H X X 6 5 4 3 2 1 01H X X 12 11 10 9 8 7 02H X X 18 17 16 15 14 13 03H X X 24 23 22 21 20 19 04H X X 30 29 28 27 26 25 05H X X 36 35 34 33 32 31 06H X X 42 41 40 39 38 37 07H X X 48 47 46 45 44 43 08H X X 54 53 52 51 50 49 09H X X 60 59 58 57 56 55 0AH X X 66 65 64 63 62 61 0BH X X 72 71 70 69 68 67 0CH X X 78 77 76 75 74 73 0DH X X 84 83 82 81 80 79 0EH X X 90 89 88 87 86 85 0FH X X 96 95 94 93 92 91 Remark 18 Segment Output No. X : Don’t care Data Sheet S13104EJ5V0DS00 µPD16681 6.6 Pictograph Blink Data RAM (PBRAM) PBRAM is the RAM that contains pictograph blink data that has been assigned to PCOM1 and PCOM2. A data value of “1” is written to the address of the pictograph to be set for a blink display. After data is written, the address counter is automatically incremented (by one), and the value after 0FH is 00H. The correspondence between output from various segments and PBRAM addresses is shown below. PCOM1,PCOM2 Address Segment Output No. b7 b6 b5 b4 b3 b2 b1 b0 00H X X 6 5 4 3 2 1 01H X X 12 11 10 9 8 7 02H X X 18 17 16 15 14 13 03H X X 24 23 22 21 20 19 04H X X 30 29 28 27 26 25 05H X X 36 35 34 33 32 31 06H X X 42 41 40 39 38 37 07H X X 48 47 46 45 44 43 08H X X 54 53 52 51 50 49 09H X X 60 59 58 57 56 55 0AH X X 66 65 64 63 62 61 0BH X X 72 71 70 69 68 67 0CH X X 78 77 76 75 74 73 0DH X X 84 83 82 81 80 79 0EH X X 90 89 88 87 86 85 0FH X X 96 95 94 93 92 91 Remark X : Don’t care 6.7 Relation between Addresses and Various ROM and RAM Devices The µPD16681 assigned FCGROM addresses as shown below to HCGROM, CGRAM, and user-defined ROM. Type No. of Characters Address Range JIS kanji 6355 Same as kanji ROM IC Non-JIS kanji 453 Same as kanji ROM IC Half width alphanumeric 192 Uses addresses 0080H to 039FH in the kanji ROM IC 256 Uses addresses 1000H to 101FH in the kanji ROM IC 8 Uses addresses 0000H to 0007H in the kanji ROM IC characters User defined CGRAM Data Sheet S13104EJ5V0DS00 19 µPD16681 7. LCD DISPLAY The µPD16681’s LCD display can display four lines containing up to 8 characters (11 x 12 dots) or 16 characters (5 x 12 dots) and 96 pictographs. SEG 4 2 1 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 PCOM1 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM47 COM48 COM49 COM50 COM51 PCOM2 Remark 20 The same select signal is output from PCOM1 and PCOM2. Data Sheet S13104EJ5V0DS00 86 85 88 87 90 89 92 91 94 93 96 95 µPD16681 7.1 LCD Display and DDRAM Addresses The character code used in the µPD16681 contains 16 bits (character code + character attribute code). When data is stored to an address in DDRAM, a combination of full width (11 x 12 dots) and half width (5 x 12 dots) characters can be displayed on the LCD. The relation between the DDRAM’s character area and the actual LCD display when displaying a combination of full width and half width characters is shown below. Figure 7-1. The Relation between The DDRAM’s Character Area and The Actual LCD Display LCD display: "" : Half width(5 x 12 dots) space DDRAM: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1st line 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 2nd line 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 3rd line 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 4th line 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H Remark 42H 43H 44H 45H 46H 47H Shaded areas indicate addresses. Address characters that are not displayed are used as data for character scrolling. 7.2 Character Codes The µPD16681 is able to combine full width characters (11 x 12 dots) and half width characters (5 x 12 dots) in the same display. The character data that is stored in DDRAM is displayed starting from the top left corner of the LCD screen. A one-dot character interval is added to the left of each character font. Both full width (11 x 12 dots) and half width (5 x 12 dots) characters are handled using 16-bit code lengths and are stored in DDRAM. The 16-bit code format uses the low-order 13 bits as the character code. The remaining 3 bits are the high-order 3 bits, which specify the character width (full or half) and the display attribute. The MSB is the select bit indicating full width or half width character code: “0” specifies full width characters and “1” specifies half width characters. The character attribute code is assigned to the next two bits, and can specify attributes such as blinking for individual characters. (See the section 7.3 Display Attributes.) 7.2.1 Code format D15 D14 D13 D12 F/H A1 A0 C12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 High-order character code Low-order character code Display attribute codes Full width(11 x 12 dots) character/ Half width(5 x 12 dots) character specification Data Sheet S13104EJ5V0DS00 21 µPD16681 7.2.2 Full width (11 x 12 dots) character code setting examples The following shows the correspondence between 16-bit JIS code and the µPD16681’s 13-bit character code. This correspondence varies according to the values of the high-order 3 bits (b17, b16, and b15) in the first byte of the JIS code. Convert JIS code as shown below to generate character code for the µPD16681. (1) JIS level 1 kanji and non-kanji characters Table 7-1. When (b17, b16, b15) = (0, 1, 0) JIS C 6226 First byte b17 b16 b15 b14 Character code Remark Second byte b13 b12 b11 b27 b26 b25 b24 b23 b22 b21 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 C12 = C6 = C5 = 0 Table 7-2. When (b17, b16, b15) = (0, 1, 1) or (1, 0, 0) JIS C 6226 First byte b17 Character code Remark b16 b15 C11 Second byte b14 b13 b12 b11 b27 b26 b25 b24 b23 b22 b21 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 C12 = 0 (2) JIS level 2 kanji and non-kanji characters Table 7-3. When (b17, b16, b15) = (1, 1, 1) JIS C 6226 First byte b17 b16 b15 b14 Character code Remark Second byte b13 b12 b11 b27 b26 b25 b24 b23 b22 b21 C9 C8 C7 C11 C10 C4 C3 C2 C1 C0 C12 = 1, C6 = C5 = 0 Table 7-4. When (b17, b16, b15) = (1, 0, 1) or (1, 1, 0) JIS C 6226 First byte b17 b16 Character code Remark b15 C11 Second byte b14 b13 b12 b11 b27 b26 b25 b24 b23 b22 b21 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 C12 = 1 (3) CGRAM D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 X X 0 0 0 0 0 0 0 0 0 0 u2 u1 u0 Remark 22 CGRAM addresses for user font: u2 to u0 Data Sheet S13104EJ5V0DS00 µPD16681 7.3 Display Attributes In the µPD16681, the character code is assigned to 12 bits of the 16-bit data that is specified as full width (11 x 12 dots) characters or half width (5 x 12 dots) characters and the display attribute code is assigned to two of the remaining four bits. Normal display or blink display mode can be specified for each character unit. The blink cycle for blink display mode is 64 frames, so that display blinks on or off once every 32 frames. 7.3.1 Character code format D15 D14 D13 D12 D11 D10 F/H A1 A0 C12 C11 C10 D9 C9 D8 D7 D6 D5 D4 D3 D2 D1 D0 C8 C7 C6 C5 C4 C3 C2 C1 C0 High-order character code Low-order character code Display attribute codes Full width(11 x 12 dots) character/ Half width(5 x 12 dots) character specification 7.3.2 Display attribute specifications A1 A0 Display Mode 0 0 Normal display 0 1 Reverse display 1 0 Character blink 1 1 Reverse character blink 7.3.3 Display examples (1) Normal display (2) Reverse display Data Sheet S13104EJ5V0DS00 23 µPD16681 (3) Blink display Display alternates once every 32 frames (4) Reverse blink display Display alternates once every 32 frames 24 Data Sheet S13104EJ5V0DS00 µPD16681 8. COMMANDS 8.1 Basic format Command register (CR) Note Command register (CR) + Extended selection register (ESR) Address register (AR) + RAM Address register (RAD) Command register (CR) Note + DATA 1(DT1) +··· The command (1 or 2 bytes) immediately follows the falling edge of the STB signal, and whatever is sent after that is recognized as data. Table 8-1. Command List Command Register Contents Description b7 b6 b5 b4 b3 b2 b1 b0 Reset 0 0 1 0 0 0 1 1 Display ON/OFF 0 0 0 0 1 b2 b1 b0 Standby 0 0 0 1 0 b2 b1 b0 Duty setting 0 0 0 1 1 0 b1 b0 Cursor control 0 0 0 1 1 1 b1 b0 D/A converter setting 0 0 1 0 1 0 0 0 Scroll control 0 0 1 1 b3 b2 b1 b0 Blink setting 0 1 0 0 0 0 b1 b0 Address register 0 1 0 0 1 0 b1 b0 Data R/W mode 1 0 1 1 0 b2 b1 b0 Test mode 1 0 1 0 b3 b2 b1 b0 Data Sheet S13104EJ5V0DS00 25 µPD16681 8.1.1 Reset This command resets all of the commands in the µPD16681. LSB MSB 0 0 1 0 0 0 1 1 8.1.2 Display ON/OFF This command controls the display’s ON/OFF status. LSB MSB 0 0 0 0 1 b2 b1 b0 Selection 000 : LCD OFF (SEGn, COMn, PCOMn = VSS) 001 : LCD OFF (SEGn, COMn, PCOMn = non-select waveform) 111 : LCD ON 8.1.3 Standby This command stops the DC/DC converter, which reduces the supply current. The display is set to OFF mode (SEGn, COMn = VSS). LSB MSB 0 0 0 1 0 b2 b1 b0 Selection 000 : Normal operation 001 : Standby (stop DC/DC converter, fulll display off Note,stop OSC) Note SEGn, COMn, PCOMn = VEE 8.1.4 Duty setting This command specifies the duty setting. LSB MSB 0 0 0 1 1 0 b1 b0 Selection 00 : 1/52 duty 01 : 1/39 duty Note Note Use COM1 to COM19 and COM27 to COM45, leave COM20 to COM26 and COM46 to COM51 open when setting 1/39 duty. 26 Data Sheet S13104EJ5V0DS00 µPD16681 8.1.5 Cursor control This command controls the cursor’s ON/OFF status. LSB MSB 0 0 0 1 1 1 b1 b0 Selection 00 : Cursor OFF Note1 10 : Cursor ON (no blink) Note2 11 : Cursor ON (blink) Note3 Notes 1. 00 : Sets cursor to OFF mode. 2. 10 : Sets cursor to ON mode (cursor is displayed). The cursor is displayed at the character which occupies the display position of the currently specified DDRAM address. The “address register” + “data R/W command” combination is used to set data to DDRAM addresses. When accessing RAM, the address counter in RAM is automatically incremented (+1) or decremented (−1), and the cursor is moved accordingly. 3. 11 : This sets the cursor to ON mode and causes the cursor to blink. The blink cycle is 64 frames. The correspondence between the cursor and the RAM address is the same as when the cursor is blinking. Remark The cursor display function is valid only when the display attribute specifies “normal display” (A0 = 0, A1 = 0). 8.1.6 D/A converter set 1 The D/A converter’s output for the LCD driver is set in 64 steps from V DD to 1/2 VDD. LSB MSB 0 0 1 0 1 0 0 0 LSB MSB + 0 0 b5 b4 b3 b2 b1 b0 Extended selection D/A output selection 00H(MIN.) to 3FH(MAX.) Remark This value is set to 20H after a reset. Data Sheet S13104EJ5V0DS00 27 µPD16681 8.1.7 Scroll control This controls scrolling of displayed characters. The individual bits in the selection are allocated to their respective display lines. When the data value is “1”, scrolling is enabled for that line. The distance of the dots’ leftward (horizontal) motion is selected via the extended selection register that is input after the command. The dot move distance varies depending on the current LCD display status and the contents of DDRAM. For details, see the section 8.4 Scrolling. LSB MSB 0 0 1 1 b3 b2 b1 b0 LSB MSB + 0 b6 b5 b4 b3 b2 b1 b0 Dot move distance selection Selection b0 : Scroll selection on fourth line b1 : Scroll selection on third line b2 : Scroll selection on second line b3 : Scroll selection on first line 8.1.8 Pictograph blink setting This command performs blink control for the pictograph at addresses where the blink (PBRAM) data value is “1”. LSB MSB 0 1 0 0 0 0 b1 b0 Selection 00 : Stop blink (blink frequency = fOSC/319488) 01 : Stop blink (blink frequency = fBR1Note /2) 10 : Start blink (blink frequency = fOSC/319488) 11 : Start blink (blink frequency = fBR1Note/2) Note This refers to the frequency of the external clock that is input from the OSCBR1 pin. 28 Data Sheet S13104EJ5V0DS00 µPD16681 8.1.9 Data R/W command This command performs data read/write operations. LSB MSB 1 0 1 1 0 b2 b1 b0 LSB MSB + b7 b6 b5 b4 b3 b2 b1 b0 + · · · Selection 1 00 : Increments up from the current address Note 1 01 : Retains current address 10 : Decrements down from the current address Note 1 Selection 2 0 : Data write 1 : Data read Note 2 Notes 1. During increment mode, when the current address is the last address the next address becomes 00H. During decrement mode, when the current address is 00H, the next address becomes the last address. 2. Data read mode is cancelled at the rising edge of the STB signal (mode is switched to command/data write mode). Caution During a serial data transfer, write data in 8-bit or 16-bit segments. If the rising edge of STB occurs during the data transfer operation, the operation is not guaranteed. 8.1.10 Test mode This command sets the test mode. The test mode is only for confirming the IC’s operation. Regular or continuous use while in test mode is not guaranteed. LSB MSB 1 0 1 0 b3 b2 b1 b0 Selection 0000 : Normal operation 0001 to 1111 : Test mode Data Sheet S13104EJ5V0DS00 29 µPD16681 8.2 Address Register This command selects the address type and specifies addresses. LSB MSB 0 1 0 Caution 0 1 0 LSB MSB + b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 Selection 1 Selection 2 00 : DDRAM address DDRAM address : 00H to 47H 01 : PDRAM address PDRAM address : 00H to 0FH 10 : PBRAM address PBRAM address : 00H to 0FH 11 : CGRAM address CGRAM address : 00H to F9H Operation is not guaranteed if an invalid address is set. 8.3 Reset The contents of the various registers appear as shown below after a reset (command reset or hardware [pin] reset). Command Display ON/OFF Register Contents Description b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 1 0 0 0 LCD OFF (SEGn, COMn, PCOMn, = VSS) Standby 0 0 0 1 0 0 0 0 Normal operation Duty setting 0 0 0 1 1 0 0 0 1/52 duty Cursor control 0 0 0 1 1 1 0 0 Cursor OFF D/A converter setting 0 0 1 0 1 0 0 0 Set to 20H Scroll control 0 0 1 1 0 0 0 0 No specified scroll line Blink setting 0 1 0 0 0 0 0 0 Blink stop Address register 0 1 0 0 1 0 0 0 DDRAM is specified Data R/W mode 1 0 1 1 0 0 0 0 Data write/increment (+1) Test mode 1 0 1 0 0 0 0 0 Normal operation 30 Data Sheet S13104EJ5V0DS00 µPD16681 8.4 Scrolling Character scrolling is controlled by inputting scroll control commands (8 bits) plus scroll dot count data (8 bits). The line to be scrolled is specified by the scroll control command and the scroll dot count data sets the number of dots to be scrolled. When this command is input, the characters on the specified line are shifted leftward by the specified number of dots. The number of dots that can be scrolled differs according to the contents of the data stored in DDRAM (see 8.4.1 Scrollable number of dots and 8.4.2 Display and scroll amounts). Consequently, if scrolling is specified for an amount of data that exceeds the scrollable data, the character data, only the scrollable data is shifted and overwritten, and scrolling must be performed again. Cautions 1. For character scrolling, be sure to input a scroll control command (8 bits) plus the amount of scrolled data (8 bits). 2. If the characters on a scrolled line have various character attributes (normal/blink/reverse/ reverse/blink), the character display may become garbled after scrolling. This problem does not occur when all of the characters on the line have the same character attribute. 8.4.1 Scrollable number of dots Scroll amount = (12 dots x number of non-displayed full width characters that are stored in DDRAM) + (6 dots x number of non-displayed half width characters that are stored in DDRAM) 8.4.2 Display and scroll amounts LCD display: DDRAM status : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1st line 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 2nd line 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 3rd line 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 4th line 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H Remark 42H 43H 44H 45H 46H 47H Shaded areas indicate addresses. Address characters that are not displayed are used as data for character scrolling. Data Sheet S13104EJ5V0DS00 31 µPD16681 Character memory contents : Remarks 1. Shaded areas indicate addresses. 2. First line : (10 full width (11 x 12 dots) characters) Second line : (6 full width (11 x 12 dots) characters), "484"†(4 half width (5 x 12 dots) characters) Third line : "PB"(2 half width (5 x 12 dots) characters) Fourth line : (2 full width (5 x 12 dots) characters) Scrollable dot counts; First line : (12 dots x 10 characters) + (6 dots x 0 characters) = 120 dots Second line : (12 dots x 6 characters) + (6 dots x 4 characters) = 96 dots Third line : (12 dots x 0 characters) + (6 dots x 2 characters) = 12 dots Fourth line : (12 dots x 2 characters) + (6 dots x 0 characters) = 24 dots If scroll count data that exceeds the scrollable number of dots is entered using the scroll control command, all dots that are in the area that goes beyond the DDRAM addresses are output as OFF data. 32 Data Sheet S13104EJ5V0DS00 µPD16681 8.5 Serial Communication Format (1) Reception 1 (command write, 1 byte) STB DATA b7 SCK b6 1 b5 2 b2 3 b1 6 b0 7 8 (2) Reception 2 (command/data write, 2 bytes or more) STB b7 DATA SCK 1 b6 b5 3 2 b2 6 b1 7 b0 b7 8 1 Command 1 b6 2 b5 3 b4 4 b3 5 Command 1/Data Wait time tWAIT (3) Transmission (command/data read) STB b7 DATA SCK 1 b6 2 b5 3 b2 6 b1 7 Data read command setting b0 1 8 Wait time tWAIT Data Sheet S13104EJ5V0DS00 b7 b6 b5 b4 b3 2 3 4 5 6 Data read 33 µPD16681 8.6 Parallel Communication Format (1) 8-bit parallel interface STB D 0 - D7 E 34 Data Sheet S13104EJ5V0DS00 µPD16681 9. COMMAND EXAMPLES Table 9-1. Initial Setting (1/39 duty) + Data Input STB D7 D6 H X X D5 D4 D3 D2 D1 D0 X X X X Status Hard Reset X X L 0 0 0 1 1 0 0 1 H X X X X X X X X Duty setting (1/39 duty) L 0 1 0 0 1 0 0 0 Address register (DDRAM address selection) 0 0 0 0 0 0 0 0 DDRAM address: 00H H X X X X X X X X L 1 0 1 1 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 H X X X X X X X X L 0 1 0 0 1 0 0 1 Address register (PDRAM address selection) H 0 0 0 0 0 0 0 0 PDRAM address: 00H L X X X X X X X X L 1 0 1 1 0 0 0 0 Data write, address is incremented starting from current address X X D D D D D D PDRAM: data at 00H X X D D D D D D PDRAM: data at 01H PDRAM: data at 0FH Data write, address is incremented starting from current address Data for first character Data for second character : Data for 54th character : X X D D D D D D H X X X X X X X X L 0 1 0 0 1 0 1 0 Address register (PBRAM address selection) 0 0 0 0 0 0 0 0 PBRAM address : 00H H X X X X X X X X L 1 0 1 1 0 0 0 0 Data write, address is incremented starting from current address X X D D D D D D PBRAM: data at 00H X X D D D D D D PBRAM: data at 01H X X D D D D D D PBRAM: data at 0FH X X X X X X X X : H L 0 0 0 0 1 1 1 1 H X X X X X X X X Display ON To next processing Remark X : Don’t care Data Sheet S13104EJ5V0DS00 35 µPD16681 Table 9-2. CGRAM Data Write STB D7 D6 D5 D4 D3 D2 D1 D0 Status H X X X X X X X X L 0 1 0 0 1 0 1 1 Address register (CGRAM address selection) 0 0 0 0 0 0 H X X X X X X 0 0 CGRAM address: 00H X X L 1 0 1 1 0 0 0 0 A A D5 D4 D3 D2 D1 D0 Data for first character (at 000H) A A D5 D4 D3 D2 D1 D0 Data in first line of pattern A A D5 D4 D3 D2 D1 D0 Data for first character (at 000H) A A D5 D4 D3 D2 D1 D0 Data in second line of pattern A A D5 D4 D3 D2 D1 D0 Data for Xth character (at 00mH) A A D5 D4 D3 D2 D1 D0 Data in nth line of pattern X X X X X X X X Start Data write, address is incremented starting from current address : H To next processing Remark 36 X : Don’t care Data Sheet S13104EJ5V0DS00 µPD16681 10. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 °C, VSS = 0 V) Parameter Symbol Rating Unit Supply voltage (4x boost) VDD −0.3 to +3.75 V Supply voltage (3x boost) VDD −0.3 to +5.0 V Driver supply voltage VLCD −0.3 to +15.0, VDD ≤ VLCD V Driver reference supply input voltage VLC1-VLC5 −0.3 to VLCD+0.3 V Logic system input voltage VIN1 −0.3 to VDD+0.3 V Logic system output voltage VOUT1 −0.3 to VDD+0.3 V Logic system input/output voltage VI/O1 −0.3 to VDD+0.3 V Driver system input voltage VIN2 −0.3 to VLCD+0.3 V Driver system output voltage VOUT2 −0.3 to VLCD+0.3 V Operating ambient temperature TA −40 to +85 °C Storage temperature Tstg −55 to +150 °C Caution If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings. Recommended Operating Range Parameter Symbol MIN. TYP. MAX. Unit Supply voltage (4x boost) VDD 2.45 3.0 V Supply voltage (3x boost) VDD 2.45 4.0 V Driver supply voltage VLCD 5.0 12 V Logic system input voltage VIN 0 VDD V Driver system input voltage VLC1-VLC5 0 VLCD V 10 Remarks 1. When using an external power supply, be sure to maintain these relations: VSS < VLC5 < VLC4 < VLC3 < VLC2 < VLC1 ≤ VLCD 2. Maintain VDD ≤ VLCD when turning the power on or off. 3. Keep voltage input to the AMPIN(+) pin between 1.0 V and VDD when using an internal power supply but not using the D/A converter. Data Sheet S13104EJ5V0DS00 37 µPD16681 Electrical characteristics (unless otherwise specified, TA = −40 to +85 °C, VDD = 2.45 to 3.0 V during 4x boost mode or 2.45 to 4.0 V during 3x boost mode) Parameter Symbol High-level input voltage VIH Low-level input voltage VIL High-level input current IIH1 Low-level input current Condition MIN. TYP. MAX. 0.8VDD Unit V 0.2VDD V Except for D0/DATA and D1 to D7 1 µA IIL1 Except for D0/DATA and D1 to D7 −1 µA High-level output voltage VOH IOUT = −1.5 mA, except OSCOUT Low-level output voltage VOL IOUT = 4 mA, except OSCOUT 0.5 V High-level leakage current ILOH D0/DATA and D1 to D7, VIN/OUT = VDD 10 µA Low-level leakage current ILOL D0/DATA and D1 to D7, VIN/OUT = VSS −10 µA Common output ON resistance RCOM VLCn → COMn, VLCD ≥ 3VDD, ILOL = 50 µA 2 kΩ Segment output ON resistance RSEG VLCn → SEGn, VLCD ≥ 3VDD, ILOL = 50 µA 4 kΩ Driver voltage (boost voltage) VLCD During 3x boost 2.7VDD 3.0VDD V During 4x boost 3.6VDD 4.0VDD V 100 180 µA 135 210 µA 150 280 µA 200 340 µA 1 10 µA Current consumption IDD11 VDD−0.5 fOSC = 375 kHz, all display OFF data output, V VDD = 3.0 V during 3x boost mode (normal mode) fOSC = 375 kHz, all display OFF data output, VDD = 3.0 V during 4x boost mode Current consumption IDD12 fOSC = 375 kHz, all display OFF data output, VDD = 3.0 V during 3x boost mode (high-power mode) fOSC = 375 kHz, all display OFF data output, VDD = 3.0 V during 4x boost mode Driver system current consumption (VDD) IDD21 VDD = 3.0 V (Standby) Remark The TYP. value is a reference value when TA = 25 °C Test Circuit DACHA D/A Converter VEXT Reference supply circuit VDD + AMPIN(+) − AMPIN(−) 38 AMPOUT VLC1 VLC2 VLC3 Data Sheet S13104EJ5V0DS00 VLC4 VLC5 VSS µPD16681 Switching characteristics (unless otherwise specified, TA = −40 to +85 °C) VDD = 2.45 to 2.7 V Parameter • Oscillation frequency Symbol fOSC Conditions Self-oscillation, MIN. TYP. 180 MAX. Unit 500 kHz oscillation resistance R = 100 kΩ Transfer delay time tPHL SCK↓→DATA↓ 60 ns Transfer delay time tPLH SCK↓→DATA↑ 60 ns Remark The TYP. value is a reference value when TA = 25 °C VDD = 2.7 to 3.3 V Parameter • Symbol Conditions Self-oscillation, MIN. TYP. MAX. Unit 240 378 560 kHz Oscillation frequency fOSC Transfer delay time tPHL SCK↓→DATA↓ 60 ns Transfer delay time tPLH SCK↓→DATA↑ 60 ns oscillation resistance R = 100 kΩ Remark Use the following equation to determine the time per frame. 1 frame = 1/fOSC x 96 x number of duty fOSC = 375 kHz, Given a 1/52 duty, 1 frame = 2.67 µs ( 96 x 52 = 13.1 ms ≅ 75 Hz) Data Sheet S13104EJ5V0DS00 39 µPD16681 Required timing conditions (unless otherwise specified, TA = −40 to +85 °C) Common (1) (VDD = 2.45 to 2.7 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 500 kHz Clock frequency fOSC OSCIN external clock 180 High-level clock pulse width tWHC1 OSCIN external clock 600 ns Low-level clock pulse width tWLC1 OSCIN external clock 600 ns High-level clock pulse width tWHC2 OSCBRI external clock 400 ns Low-level clock pulse width tWLC2 OSCBRI external clock 400 ns Rise/fall time tr,tf OSCBRI external clock Reset pulse width tWRE /RESET pin 50 µs Reset cancellation time tRRE /RESET pin 50 µs Remark 100 ns The TYP. value is a reference value when TA = 25 °C. Common (2) (VDD = 2.7 to 3.3 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 375 560 kHz Clock frequency fOSC OSCIN external clock 240 High-level clock pulse width tWHC1 OSCIN external clock 500 ns Low-level clock pulse width tWLC1 OSCIN external clock 500 ns High-level clock pulse width tWHC2 OSCBRI external clock 400 ns Low-level clock pulse width tWLC2 OSCBRI external clock 400 ns Rise/fall time tr,tf OSCBRI external clock Reset pulse width tWRE /RESET pin 50 µs Reset cancellation time tRRE /RESET pin 50 µs Remark 40 The TYP. value is a reference value when TA = 25 °C. Data Sheet S13104EJ5V0DS00 100 ns µPD16681 Serial interface (1) (VDD = 2.45 to 2.7 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Shift clock cycle tCYK SCK 600 ns High-level shift clock pulse width tWHK SCK 300 ns Low-level shift clock pulse width tWLK SCK 210 ns Shift clock hold time tHSTBK STB↓→SCK↓ 260 ns Data setup time tDS1 DATA→SCK↑ 40 ns Data hold time tDH1 SCK↑→DATA 40 ns STB hold time tHKSTB SCK↑→STB↑ 260 ns STB pulse width tWSTB 210 ns Wait time tWAIT 260 ns Remark 8th CLK↑→1st CLK↓ The TYP. value is a reference value when TA = 25 °C. Serial interface (2) (VDD = 2.7 to 3.3 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Shift clock cycle tCYK SCK 500 ns High-level shift clock pulse width tWHK SCK 260 ns Low-level shift clock pulse width tWLK SCK 210 ns Shift clock hold time tHSTBK STB↓→SCK↓ 260 ns Data setup time tDS1 DATA→SCK↑ 40 ns Data hold time tDH1 SCK↑→DATA 40 ns STB hold time tHKSTB SCK↑→STB↑ 260 ns STB pulse width tWSTB 210 ns Wait time tWAIT 260 ns 8th CLK↑→1st CLK↓ Remarks 1. The TYP. value is a reference value when TA = 25 °C. 2. For details, see 8.5 Serial Communication Format (3) Transmission (command/data read). Data Sheet S13104EJ5V0DS00 41 µPD16681 Parallel interface (1) (VDD = 2.45 to 2.7 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Enable cycle time tCYCE E↑→E↑ 600 ns High-level enable pulse width tWHE E 300 ns Low-level enable pulse width tWLE E 210 ns STB pulse width tWSTB 210 ns STB hold time tWKSTB 260 ns Enable hold time tHSTBK 260 ns Data setup time tDS2 D0 to D7→E↑ 40 ns Data hold time tDH2 D0 to D7→E↓ 40 ns Remark The TYP. value is a reference value when TA = 25 °C. Parallel interface (2) (VDD = 2.7 to 3.3 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Enable cycle time tCYCE E↑→E↑ 500 ns High-level enable pulse width tWHE E 260 ns Low-level enable pulse width tWLE E 210 ns STB pulse width tWSTB 210 ns STB hold time tWKSTB 260 ns Enable hold time tHSTBK 260 ns Data setup time tDS2 D0 to D7→E↑ 40 ns Data hold time tDH2 D0 to D7→E↓ 40 ns Remark 42 The TYP. value is a reference value when TA = 25 °C. Data Sheet S13104EJ5V0DS00 µPD16681 AC timing measurement voltages VIH Input VIL VOH Output VOL AC characteristics waveforms OSC OSCIN tWHC1 tWLC1 1/fOSC tr tf OSCBRI tWHC2 tWLC2 Serial interface (input) STB tWSTB tCYK tHSTBK tWLK tHKSTB tWHK SCK tDS1 tDH1 DATA Serial interface (output) SCK tPHL tPLH DATA Data Sheet S13104EJ5V0DS00 43 µPD16681 8-bit parallel interface STB tWSTB tHSTBK tWKSTB tCYCE tWLE tWHE E tDS2 tDH2 Dn Reset tRRE /RESET tWRE Reset time 44 Reset cancellation time Data Sheet S13104EJ5V0DS00 µPD16681 11. CHARACTER CODE TABLES (standard ROM code, µPD16681W/P-011) The following tables show the correspondences between character codes and characters. Character codes ranging from 0000H to 0007H are assigned to CGRAM and those ranging from 1000H to 1380H are assigned to an area that is defined by the user when establishing custom ROM codes. • Character allocation table (1) C12 = 0 Data Sheet S13104EJ5V0DS00 45 µPD16681 Character allocation table (2) C12 = 0 46 Data Sheet S13104EJ5V0DS00 µPD16681 Character allocation table (3) C12 = 0 Data Sheet S13104EJ5V0DS00 47 µPD16681 Character allocation table (4) C12 = 0 48 Data Sheet S13104EJ5V0DS00 µPD16681 Character allocation table (5) C12 = 1 Data Sheet S13104EJ5V0DS00 49 µPD16681 Character allocation table (6) C12 = 1 50 Data Sheet S13104EJ5V0DS00 µPD16681 Character allocation table (7) C12 = 1 Data Sheet S13104EJ5V0DS00 51 µPD16681 Character allocation table (8) C12 = 1 52 Data Sheet S13104EJ5V0DS00 µPD16681 [MEMO] Data Sheet S13104EJ5V0DS00 53 µPD16681 [MEMO] 54 Data Sheet S13104EJ5V0DS00 µPD16681 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S13104EJ5V0DS00 55 µPD16681 Reference Documents NEC Semiconductor Device Reliability/Quality Control System (C10983E) Semiconductor Device Mounting Technology (C10535E) • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8