PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD17202AGF-011 4-BIT SINGLE-CHIP MICROCONTROLLER WITH LCD CONTROLLER/DRIVER AND KEY SCAN CIRCUIT FOR FPC (FRONT PANEL CONTROLLER) The µPD17202AGF-011 is a CMOS microcontroller for the FPC (Front Panel Controller) of a car stereo system. This microcontroller is housed in a 64-pin QFP and is provided with an LCD controller/driver and key scan circuit, enabling the reduction of the amount of wiring between the front panel of the car stereo system and the master microcontroller. FEATURES • LCD controller/driver : Can display up to 75 segments. 1/3 duty, 1/3 bias, frame frequency: 325.5 Hz • Key scan circuit : Can read up to 30 (5 × 6) keys. • LED output : 1 pin • 3-wire serial communication mode : CLOCK, DATA, and LOAD pins • Supply voltage : VDD = 4.5 to 5.5 V • System clock : fX = 8 MHz ORDERING INFORMATION Part Number Package µPD17202AGF-011-3BE 64-pin plastic QFP (14 × 20 mm, 1.0-mm pitch) The information in this document is subject to change without notice. Document No. U12127EJ1V0DS00 (1st edition) Date Published May 1997 N Printed in Japan © 1997 µPD17202AGF-011 PIN CONFIGURATION (Top View) 64-pin plastic QFP (14 × 20 mm, 1.0-mm pitch) IC(XTOUT) IC(VREG) IC(VDET) VLCDC 64 63 62 61 60 59 58 57 56 55 54 53 52 51 IC (XTIN) 2 50 IC (WDOUT) LCD22 3 49 RESET LCD21 4 48 XOUT LCD20 5 47 XIN LCD19 6 46 VDD LCD18 7 45 IC (REM) LCD17 8 44 IC (TMOUT/LED) LCD16 9 43 DATA (P0D3) LCD15 10 42 BLANK (P0D2) LCD14 11 41 KS4 (P0D1) LCD13 12 40 KS3 (P0D0) LCD12 13 39 KS2 (P0C3) LCD11 14 38 KS1 (P0C2) LCD10 15 37 KS0 (P0C1) LCD9 16 36 LED (P0C0) LCD8 17 35 INT (P0B3) LCD7 18 34 K5 (P0B2) LCD6 19 33 K4 (P0B1) 2. ( ): Pin names of µPD17202AGF-×××-3BE K3 (P0B0) K2 (P0A3) K1 (P0A2) K0 (P0A1) LOAD (P0A0) CLOCK (INT) GND0 LCD0 LCD1 LCD2 20 21 22 23 24 25 26 27 28 29 30 31 32 LCD3 LCD23 LCD4 1 LCD5 LCD24 Remarks 1. IC: Internally Connected 2 VLCD0 VLCD1 GND1 VLCD2 CAPL CAPH COM0 COM1 COM2 µPD17202AGF-011-3BE µPD17202AGF-011 CONTENTS 1. PIN FUNCTION ............................................................................................................................. 1.1 Pin Function List .................................................................................................................. 4 4 2. CONFIGURATION OF KEY MATRIX .......................................................................................... 2.1 Layout of Key Matrix ............................................................................................................ 2.2 Connection of Key Matrix .................................................................................................... 6 6 7 3. KEY SCAN .................................................................................................................................... 3.1 Key Scan Function ............................................................................................................... 3.2 Data Configuration ............................................................................................................... 8 8 9 4. LCD DISPLAY FUNCTION .......................................................................................................... 4.1 Configuration of LCD Data Segment and LCD Panel Display Data ................................. 4.2 LCD Display Data Configuration ........................................................................................ 10 10 12 5. SERIAL DATA COMMUNICATION .............................................................................................. 5.1 Serial Data Input ................................................................................................................... 5.2 Serial Data Output ................................................................................................................ 5.3 Timing Chart of Serial Data Communication ..................................................................... 13 14 15 16 6. APPLICATION CIRCUIT EXAMPLE ............................................................................................ 19 7. ELECTRICAL SPECIFICATIONS (preliminary) ......................................................................... 20 8. PACKAGE DRAWINGS ................................................................................................................. 25 3 µPD17202AGF-011 1. PIN FUNCTION 1.1 Pin Function List Pin No. Symbol Pin Name Description I/O Format 1 to 25 LCD24 to LCD0 LCD segment signal output These pins output segment signals to an LCD panel. They are used to control the display on the LCD panel by forming a matrix with COM0 through COM2 (pins 62 through 64). 26 58 GND0 GND1 Ground Ground pin 27 CLOCK Clock input Serial communication clock input. Data is input to or output from the DATA pin (pin 43) at the rising edge of the clock input to this pin. Input 28 LOAD Load input Serial communication load input. Commands are executed and the output status is cleared in synchronization with the rising edge of this pin. While this pin is high, clock input is invalid. This pin is connected to an internal pull-up resistor. Input 29 to 34 K0 to K5 Key return signal input These pins input key return signals from a key matrix. These pins are connected to an internal pull-down resistor. Input 35 INT Key scan end signal output This pin outputs a key scan end signal to the master microcontroller. It goes high when key scanning has ended after execution of a key data output command. This pin goes low at the rising edge of the LOAD pin (pin 28) after data has been output. While this pin is low, key data cannot be correctly output. The initial value of this pin is the low level. Be sure to connect a pull-down resistor to this pin. CMOS pushpull output 36 LED LED output This pin is connected to an LED that is used to check connection with the master microcontroller. When this pin is low, the LED lights. This pin is output depending on the LED data value of display data input (data A, refer to 4.2 LCD Display Data Configuration). This pin is floated in the initial status. N-ch opendrain output CMOS pushpull output – 5V µ PD17202AGF-011 37 to 41 4 KS0 to KS4 Key source output LED 36 These pins output key source signals to a key matrix. N-ch opendrain output µPD17202AGF-011 Pin No. Symbol 42 BLANK Pin Name Blank input Description I/O Format By connecting an external controller to this pin, the display of the LCD panel can be turned ON/OFF. Input Input level LCD display status Low Lights High Extinguishes To control this pin, connect it to an external controller via pull-up resistor; otherwise, connect it to GND via pull-down resistor. 43 DATA 44, 45 IC Serial data I/O Serial communication data I/O pin. This pin outputs data from the rising edge of the LOAD pin (pin 28) after a key data output signal has been received, to the next rising edge; otherwise, it inputs data. Internally connected Connect nothing to these pins. – 50, 51 Connect these pins to GND via pull-down resistor. 52, 53 Short-circuit pins 52 and 53. 54 N-ch opendrain output Connect this pin to VDD. 46 VDD Power supply This is a common power supply pin (VDD = 2.2 to 5.5 V). 47 XIN Crystal resonator These pins are used to connect a crystal resonator. 48 XOUT 49 RESET 55 VLCDC Input Connect an 8-MHz ceramic oscillator or crystal resonator to these pins. The accuracy of the watch is influenced only by the oscillation frequency of the oscillator. Reset input Reset input. LCD reference voltage adjustment This pin is used to adjust the reference voltage for the LCD driver. Example – Input VLCDC VLCD0 VLCD1 µ PD17202AGF-011 – VLCD2 – 55 2 MΩ 56 57 59 0.47µF 0.47µF 60 0.47µF CAPL 0.47µF CAPH 61 56 57 59 VLCD0 VLCD1 VLCD2 LCD regulator LCD regulator pin. – 60 61 CAPL CAPH LCD boosting capacitor These pins connect a capacitor used to boost the LCD driver voltage. Connect a capacitor of 0.47 µF between the CAPL and CAPH pins. – 62 to 64 COM0 to COM2 Common signal output of LCD controller/driver These pins output the common signals of the LCD controller/driver. CMOS 3state output 5 µPD17202AGF-011 2. CONFIGURATION OF KEY MATRIX 2.1 Layout of Key Matrix The µPD17202AGF-011 can be used to configure a key matrix of up to 30 keys, KEY0 through KEY29, by using the KS0 through KS4 pins (key source pins) and K0 through K5 pins (key return pins). Keys KEY0 through KEY29 are allocated as shown below. The details of each key can be set arbitrarily. Input Pin (Pin No.) K0 (29) K1 (30) K2 (31) K3 (32) K4 (33) K5 (34) KS0 (37) KEY0 KEY1 KEY2 KEY3 KEY4 KEY5 KS1 (38) KEY6 KEY7 KEY8 KEY9 KEY10 KEY11 KS2 (39) KEY12 KEY13 KEY14 KEY15 KEY16 KEY17 KS3 (40) KEY18 KEY19 KEY20 KEY21 KEY22 KEY23 KS4 (41) KEY24 KEY25 KEY26 KEY27 KEY28 KEY29 Output Pin (Pin No.) Remark Numbers in brackets ( ) are pin numbers. 6 µPD17202AGF-011 2.2 Connection of Key Matrix An example of connection of the key matrix is shown below. KSn Momentary key = Kn KS4 41 KS3 40 KS2 39 µ PD17202AGF-011 KS1 38 KS0 37 K5 34 K4 33 K0 K1 K2 K3 29 30 31 32 7 µPD17202AGF-011 3. KEY SCAN 3.1 Key Scan Function Key scanning is started when a key data output command is executed. The INT pin (pin 35) goes high when key scanning has ended. The INT pin goes low when the LOAD pin (pin 28) goes high. Figure 3-1. Timing Chart of Key Scanning 50 - 60 µ s KS0 KS1 KS2 KS3 KS4 1.6 - 1.9 ms (2.8 - 3.4 ms)Note INT Key data output command Scanning ends LOAD pin rises Note The value in brackets ( ) is when “display data input + key data output” is executed. 8 Key data output command µPD17202AGF-011 3.2 Data Configuration The data output by the key data output command consists of 30 bits. The contents of the output data are as shown below. Figure 3-2. Configuration of Output Data (Key Data Output) 30 bits MSB LSB K K K K K K E E E E E E Y Y Y Y Y Y 29 28 27 26 25 24 K K K K K K E E E E E E Y Y Y Y Y Y 17 16 15 14 13 12 ··· KS4 KS2 K E Y 5 ··· K E Y 4 K E Y 3 K E Y 2 K E Y 1 K E Y 0 KS0 The status of the output data can be identified by the data of each bit as shown below. Data Status 0 Key off 1 Key on 9 µPD17202AGF-011 4. LCD DISPLAY FUNCTION 4.1 Configuration of LCD Data Segment and LCD Panel Display Data The segments consisting of LCD0 through LCD24 pins and COM0 through COM2 pins correspond to the LCD panel display data as shown in the table below. Table 4-1 Configuration of LCD Segment and Table 4-2 Display Data Table correspond to each other. Any LCD display setting can be performed based on these tables. Table 4-1. Configuration of LCD Segment Common Pin (Pin No.) COM0 (62) COM1 (63) COM2 (64) LCD0 (25) B4 A0 B0 LCD1 (24) A3 A1 B1 LCD2 (23) A4 A2 B2 LCD3 (22) B9 A5 B5 LCD4 (21) A8 A6 B6 LCD5 (20) A9 A7 B7 LCD6 (19) B14 A10 B10 LCD7 (18) A13 A11 B11 LCD8 (17) A14 A12 B12 LCD9 (16) B19 A15 B15 LCD10 (15) A18 A16 B16 LCD11 (14) A19 A17 B17 LCD12 (13) B24 A20 B20 LCD13 (12) A23 A21 B21 LCD14 (11) A24 A22 B22 LCD15 (10) B33 B38 B28 LCD16 (9) B29 A25 B25 LCD17 (8) A28 A26 B26 LCD18 (7) A29 A27 B27 LCD19 (6) B34 A30 B30 LCD20 (5) A33 A31 B31 LCD21 (4) A34 A32 B32 LCD22 (3) B39 A35 B35 LCD23 (2) A38 A36 B36 LCD24 (1) A39 A37 B37 Segment Pin (Pin No.) 10 µPD17202AGF-011 Table 4-2. Display Data Table Segment Segment A B Data Name A B Data Name D40 A0 B0 D9 A31 B31 D39 A1 B1 D8 A32 B32 D38 A2 B2 D7 A33 B33 D37 A3 B3 Note D6 A34 B34 D36 A4 B4 D5 A35 B35 D35 A5 B5 D4 A36 B36 D34 A6 B6 D3 A37 B37 D33 A7 B7 D2 A38 B38 D1 A39 B39 Note D32 A8 B8 D31 A9 B9 D30 A10 B10 D29 A11 B11 D28 A12 B12 D27 A13 B13 Note D26 A14 B14 D25 A15 B15 D24 A16 B16 D23 A17 B17 D22 A18 B18 Note D21 A19 B19 D20 A20 B20 D19 A21 B21 D18 A22 B22 D17 A23 B23 Note D16 A24 B24 D15 A25 B25 D14 A26 B26 D13 A27 B27 D12 A28 B28 D11 A29 B29 D10 A30 B30 Note The data of segments B3, B8, B13, B18, and B23 are invalid. Do not input anything for these data. 11 µPD17202AGF-011 4.2 LCD Display Data Configuration LCD display data is divided into two parts, A and B, for transmission (refer to Table 4-2 Display Data Table). The data consists of a command (4 bits), LCD data (40 bits), and LED data (1 bit), or a total of 45 bits (only when data A is transmitted. Data B consists of 44 bits, excluding LED data (1 bit)). Figure 4-1. Configuration of Input Data for LCD Display MSB b 3 LSB b 2 b 1 b 0 D D D 40 39 38 Command (4 bits) D 3 D 2 LCD data Data A or B (40 bits) D 1 D 0 LED data (1 bit) Note Note D0 (= LED data) is necessary only when data A is transmitted. The status of the data can be identified by the data of each bit (0 or 1) as shown below. Data Status 0 Extinguishers 1 Lights The last 4 bits of the input data is read at the rising edge of the LOAD pin (pin 28) as a command, and the previous data is displayed on the LCD when display data input is identified. When a low level is input to the BLANK pin (pin 42), the LCD display is turned ON (the LED also lights when data A is transmitted). When a high level is input to the BLANK pin, the LCD display is turned OFF (refer to 5.2 Serial Data Output). Setting of the BLANK pin does not affect any operations other than the LCD display. The LCD display data is extinguished in the initial status (even if the BLANK pin is low level). The configuration of the LCD display data commands (4 bits of MSB) is shown below. Table 4-3. Serial Data I/O Commands Command Operation b3 b2 b1 b0 0 0 1 0 Inputs display data (data A) 0 0 1 1 Inputs display data (data B) 0 1 0 × Outputs key data 0 1 1 0 Inputs display data (A) + outputs key data 0 1 1 1 Inputs display data (B) + outputs key data 1 1 0 × Outputs key data 1 1 1 × Outputs key data Others ×: Undefined 12 Setting prohibited µPD17202AGF-011 5. SERIAL DATA COMMUNICATION The µPD17202AGF-011 inputs or outputs data from or to the main microcontroller through 3-wire serial communication, using the CLOCK (pin 27), DATA (pin 43), and LOAD (pin 28) pins. Figure 5-1 shows connection between the µPD17202AGF-011 and main microcontroller. Figure 5-1. Connection between µPD17202AGF-011 and Main Microcontroller DATA µ PD17202AGF-011 DATA 43 LOAD Main microcontroller CLOCK CLOCK LOAD 27 28 13 µPD17202AGF-011 5.1 Serial Data Input The serial data is input in synchronization with the rising of the CLOCK pin (pin 27) in the input status (the initial status is “input”). The last 4 bits read at the rising edge of the LOAD pin (pin 28) are identified and processed as a command. Figure 5-2 shows the timing chart of serial data input. Table 5-1 lists the serial data I/O commands. Figure 5-2. Timing Chart of Serial Data Input CLOCK LSB DATA MSB D0 D1 b0 b1 b2 b3 Input data (Last 4 bits are serial data input command) LOAD Table 5-1. Serial Data I/O Commands Command Operation b3 b2 b1 b0 0 0 1 0 Inputs display data (data A) 0 0 1 1 Inputs display data (data B) 0 1 0 × Outputs key data 0 1 1 0 Inputs display data (A) + outputs key data 0 1 1 1 Inputs display data (B) + outputs key data 1 1 0 × Outputs key data 1 1 1 × Outputs key data Others Setting prohibited ×: Undefined Remarks 1. For the data configuration of display data input, refer to 4. LCD DISPLAY FUNCTION. 2. For the data configuration of key data output, refer to 3. KEY SCAN. 3. Execute display data input before key data output. 4. If a pulse is input to the LOAD pin without display data input, the device does not operate. 5. The device does not operate when data other than an I/O command is input. 14 µPD17202AGF-011 5.2 Serial Data Output Serial data is output in synchronization with the rising of the CLOCK pin (pin 27) in the output status (the output status is established only when the key data output command is executed). Serial data is output in the following procedure. Figure 5-3 shows the timing chart of serial data output. <1> Input a key data output command. <2> Input a pulse to the LOAD pin (pin 28) (the output status is established when this pin goes high). <3> Input the clock (data is output in synchronization with the rising of the clock). <4> Input a pulse to the LOAD pin (the input status is established when this pin goes high). Figure 5-3. Timing Chart of Serial Data Output CLOCK LSB DATA MSB b0 b1 b2 Input data Input status b3 LSB K0 K1 K28 MSB K29 Output data Output status Input status LOAD 15 µPD17202AGF-011 5.3 Timing Chart of Serial Data Communication The I/O timing charts of the respective pins during serial data communication are shown below. (1) Serial data I/O 100 ns 11.7 µ s MIN. MIN. 50 ns MAX. CLOCK 11.7 µ s MIN. DATA (input) 11.5 µ s MAX. DATA (output) 100 ns MIN. 50 µ s MIN. 23.4 µ s MIN. LOAD Remark Maximum clock frequency: 43 kHz (2) On reset execution 35 ms MIN. CLOCK Clock 50 µ s MIN. RESET 16 µPD17202AGF-011 (3) On execution of display data input CLOCK 41 or 40 clocks + 4 clocks DATA Display data + command Clock Input data 2 ms MIN. 70 µ s MIN. LOAD 2 ms MIN. Less than 2 ms Valid BLANK BLANK pin Valid : Invalid Valid Invalid The device operates within 50 µs after the value of the BLANK pin has been changed. If the clock is input to the CLOCK pin, however, the higher the clock frequency, the slower the operation (example: operates within 1 ms at 43 kHz). Invalid : The device does not operate even if the value of the BLANK pin has been changed. If the value of the pin is changed during this period, the device operates after the pin value has become valid. (4) On execution of key data output CLOCK 4 clocks 30 clocks 1 clock 100 µ s MIN. DATA Command Input data Key data 2 ms MIN. 70 µ s MIN. 70 µ s MIN. LOAD 2 ms MIN. Less than 100 µ s Less than 2 ms INT BLANK BLANK pin Valid Valid : Invalid Valid Invalid Invalid The device operates within 50 µs after the value of the BLANK pin has been changed. If the clock is input to the CLOCK pin, however, the higher the clock frequency, the slower the operation (example: operates within 1 ms at 43 kHz). Invalid : The device does not operate even if the value of the BLANK pin has been changed. If the value of the pin is changed during this period, the device operates after the pin value has become valid. 17 µPD17202AGF-011 (5) On execution of display data input + key data CLOCK 41 or 40 clocks + 4 clocks 30 clocks Clock 100 µ s MIN. DATA Display data + command Input data Key data 3.5 ms MIN. 70 µ s MIN. 70 µ s MIN. LOAD Less than 100 µ s 3.5 ms MIN. Less than 3.5 ms INT BLANK 18 BLANK pin Valid Valid : Invalid Valid Invalid Invalid The device operates within 50 µs after the value of the BLANK pin has been changed. If the clock is input to the CLOCK pin, however, the higher the clock frequency, the slower the operation (example: operates within 1 ms at 43 kHz). Invalid : The device does not operate even if the value of the BLANK pin has been changed. If the value of the pin is changed during this period, the device operates after the pin value has become valid. µPD17202AGF-011 CAPL VLCD2 GND VLCD1 VLCD0 VLCDC 64 63 62 61 60 59 58 57 56 55 54 53 52 LCD24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 LCD6 19 RESET 51 50 49 XOUT 48 fx = 8 MHz XIN VDD 47 VDD 46 + 45 44 DATA 43 BLANK 42 KS4 41 40 VDD 39 38 KS0 37 LED 36 INT 35 K5 34 33 K0 K3 20 21 22 23 24 25 26 27 28 29 30 31 32 GND LCD5 LCD0 VDD µ PD17202AGF-011-3BE LCD panel COM0 COM1 COM2 CAPH 6. APPLICATION CIRCUIT EXAMPLE CLOCK LOAD Momentary key switch Connector Connector VDD BLANK CLK SIO Main microcontroller LOAD INT RES VDD GND 19 µPD17202AGF-011 7. ELECTRICAL SPECIFICATIONS (preliminary) Absolute Maximum Ratings (TA = 25 ˚C) Parameter Symbol Condition Rating Unit –0.3 to +7.0 V Supply voltage VDD Input voltage VI –0.3 to VDD + 0.3 V Output voltage VO –0.3 to VDD + 0.3 V High-level output current IOH Peak –30 mA r.m.s value –20 mA Peak –7.5 mA r.m.s value –5.0 mA Peak –22.5 mA r.m.s value –15.0 mA Peak 7.5 mA r.m.s value 5.0 mA Peak 30 mA r.m.s value 20 mA REM pin 1 pin (other than REM pin) All pins (except REM pin) Low-level output current IOL 1 pin All pins Operating temperature TA —20 to +75 ˚C Storage temperature Tstg –40 to +125 ˚C Caution If the rated value of even one of the above parameters is exceeded even momentarily, the quality of the product may be affected. The absolute maximum ratings, therefore, define the values exceeding which the product may be physically damaged. Be sure to use the product without ever exceeding these values. Capacitance (TA = 25 ˚C, VDD = 0 V) Parameter Input capacitance 20 Symbol Condition MIN. TYP. MAX. Unit CIN INT and RESET pins 10 pF CPIN Other than INT and RESET pins 10 pF µPD17202AGF-011 Recommended Operation Range (TA = –20 to +75 ˚C) Parameter Symbol Supply voltage System clock oscillation frequency Condition MIN. TYP. MAX. Unit VDD0 Where system clock is fX = 4 MHz 2.2 3.0 5.5 V VDD1 Where system clock is fX = 8 MHz 4.5 5.0 5.5 V 1.0 4.0 8.0 MHz fX fX vs VDD (MHz) 10 9 8 7 6 System clock: fX 5 4 3 Operation guaranteed range 2 1 2.2 0.5 0 2 4.5 3 4 5.5 5 6 (V) Supply voltage: VDD 21 µPD17202AGF-011 System Clock Oscillation Circuit Characteristics (TA = –20 to +75 ˚C, VDD = 2.2 to 5.5 V) Recommended Constants Oscillator Ceramic resonator Note 1 XIN XOUT Parameter Oscillation frequency (fX) Note 2 Oscillation stabilization time Note 3 Crystal resonator Note 1 XIN XOUT Condition time TYP. MAX. Unit 1.0 4.0 8.0 MHz 4 ms 8.0 MHz 10 ms 30 ms After VDD has reached MIN. value of oscillation voltage range Oscillation frequency (fX) Note 2 Oscillation stabilization MIN. 1.0 VDD = 4.5 to 6.0 V Note 3 4.0 Notes 1. Use of the ceramic resonator and crystal resonator shown on the next page is recommended. 2. The oscillation frequency only indicates the characteristics of the oscillation circuit. For the instruction execution time, refer to Recommended Operation Range. 3. The oscillation stabilization time is the time required for oscillation to stabilize after VDD application or release of the STOP mode. Caution When using the system clock oscillation circuit, wire the portion indicated by the dotted lines in the above figures to avoid adverse influence from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with any other signal lines. Do not route the wiring in the vicinity of a line through which a high alternating current flows. • Always keep the ground point of the capacitor of the oscillation circuit at the same potential as GND. Do not ground the capacitor to a ground pattern through which a high current flows. • Do not extract signals from the oscillation circuit. 22 µPD17202AGF-011 Recommended Oscillator Ceramic resonator Manufacturer Murata Mfg. Co., Ltd. Part Number External Oscillation Voltage Capacitance (pF) Range (V) C2 MIN. MAX. CSA3.58MG 30 30 2.0 6.0 CSA4.00MG 30 30 2.0 6.0 CSA4.19MG 30 30 2.0 6.0 2.0 6.0 2.0 6.0 2.0 6.0 CST3.58MGW CST4.00MGW Unnec- Unnec- essary essary CST4.19MGW Kyocera Corp. Remark C1 KBR3.58MS 33 33 2.0 6.0 KBR4.0MS 33 33 2.0 6.0 KRB4.19MS 33 33 2.0 6.0 Toko Ceramic Co. Ltd. CRHF4.00 18 18 2.0 6.0 Daishinku Corp. PRS0400BCSAN 39 33 2.0 6.0 Capacitorcontained type Crystal resonator Manufacturer Kinseki Corp. Frequency (MHz) 4.0 External Capacitance (pF) Retainer HC-49U-S Oscillation Voltage Range (V) C1 C2 MIN. MAX. 22 22 2.0 6.0 Remark External Circuit Example XIN C1 XOUT C2 23 µPD17202AGF-011 DC Characteristics (VDD = 3 V, TA = –20 to +75 ˚C, fX = 4 MHz) Parameter Symbol Low-voltage detection voltage VDET R = 2.2 MΩ High-level input voltage VIH1 RESET, INT pins VIH2 Other than RESET, INT pins VIL1 Low-level input voltage High-level input current Low-level input current Condition MIN. TYP. MAX. Unit 1.3 2.0 2.9 V 0.8 VDD VDD V 0.7 VDD VDD V RESET, INT pins 0 0.2 VDD V VIL2 Other than RESET, INT pins 0 0.3 VDD V IIH1 INT pin VIH = VDD 0.2 µA IIH2 RESET pin VIH = VDD 0.2 µA IIH3 P0A through P0D pins VIH = VDD 0.2 µA IIL1 INT pin VIL = 0 V –0.2 µA IIL2 RESET pin VIL = 0 V w/o pull-up resistor –0.2 µA –120 µA –0.2 µA –30 µA –0.2 µA VIL = 0 V w/pull-up resistor IIL3 IIL4 P0A, P0B pins –30 –60 VIL = 0 V w/o pull-up resistor IIL5 VIL = 0 V w/pull-up resistor –8 –15 IIL6 P0C, P0D pins VIL = 0 V IOH1 P0A, P0B pins VOH = VDD – 0.3 V –0.6 –2.0 –4.0 mA IOH2 REM pin VOH = VDD – 2.0 V –7.0 –15.0 –25.0 mA IOH3 LED pin VOH = VDD – 0.3 V –0.3 –1.0 –2.0 mA IOL1 P0A, P0B pins VOL = 0.3 V 0.5 1.5 2.5 mA IOL2 P0C, P0D pins VOL = 0.3 V 0.5 1.5 2.5 mA IOL3 REM pin VOL = 0.3 V 0.5 1.5 2.5 mA IOL4 LED, WDOUT pins VOL = 0.3 V 0.5 1.5 2.5 mA IDD1 Operating mode 0.6 1.5 mA IDD2 HALT mode 0.5 1.5 mA VLCDC voltage VLCDC VDD = 3 V, TA = 25 ˚C, R1 = R2 = 1 MΩ 0.5 0.6 0.7 V LCD output voltage variable range VLCD0 External variable resistor (0 to 2.2 MΩ) 0.8 1.8 V Doubler output voltage VLCD1 C1 to C4 = 0.47 µF 1.9 VLCD0 2 VLCD0 V Tripler output voltage VLCD2 C1 to C4 = 0.47 µF 2.85 VLCD0 3 VLCD0 V Common output current ICOM VDS = 0.2 V 30 µA Segment output current ILCD VDS = 0.2 V 5 µA High-level output current Low-level output current Supply current AC Characteristics (TA = –20 to +75 ˚C, VDD = 3 V) Parameter INT high-, low-level widths RESET low-level width 24 Symbol Condition MIN. TYP. MAX. Unit tIOH 50 µs tIOL 50 µs tRSL 50 µs µPD17202AGF-011 8. PACKAGE DRAWINGS 64 PIN PLASTIC QFP (14 20) A B 51 52 33 32 detail of lead end C D S R Q 64 1 20 19 F J G H I P M K M N L NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 23.2±0.2 0.913 +0.009 –0.008 B 20.0±0.2 0.787 +0.009 –0.008 C 14.0±0.2 0.551 +0.009 –0.008 D 17.2±0.2 0.677±0.008 F 1.0 0.039 G 1.0 0.039 H 0.40±0.10 0.016 +0.004 –0.005 I 0.20 0.008 J 1.0 (T.P.) 0.039 (T.P.) K 1.6±0.2 0.063±0.008 L 0.8±0.2 0.031 +0.009 –0.008 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N 0.10 0.004 P 2.7 0.106 Q 0.125±0.075 0.005±0.003 R 5°±5° 5°±5° S 3.0 MAX. 0.119 MAX. S64GF-100-3B8, 3BE-3 25 µPD17202AGF-011 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 26 µPD17202AGF-011 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 27 µPD17202AGF-011 The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5