EDI88512VA-RP HI-RELIABILITY PRODUCT 512Kx8 Plastic Monolithic 3.3V SRAM CMOS FEATURES ■ 512Kx8 bit CMOS Static WEDC's ruggedized plastic 512Kx8 SRAM that allows the user to capitalize on the cost advantage of using a plastic component while not sacrificing all of the reliability available in a full military device. ■ Random Access Memory • Access Times of 15, 17, 20, 25ns • Extended Temperature Testing Extended temperature testing is performed with the test patterns developed for use on WEDC’s fully compliant 512Kx8 SRAMs. WEDC fully characterizes devices to determine the proper test patterns for testing at temperature extremes. This is critical because the operating characteristics of a device change when it is operated beyond the commercial temperature range. Using commercial methods will not guarantee a devicee that operates reliabily in the field at temperature extremes. Users of WEDC’s ruggedized plastic benefit from WEDC’s extensive experience in characterizing SRAMs for use in military systems. ■ 36 lead JEDEC Approved Revolutionary Pinout • Plastic SOJ (Package 319) ■ Single +3.3V (±10%) Supply Operation WEDC’s ruggedized plastic SOJ is footprint compatible with WEDC’s full military ceramic 36 pin SOJ. FIG. 1 PIN CONFIGURATION PIN DESCRIPTION TOP VIEW A0 A1 A2 A3 A4 CS I/O0 I/O1 Vcc Vss I/O2 I/O3 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 pin Revolutionary 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC I/O0-7 Data Inputs/Outputs A0-18 Address Inputs WE Write Enable CS Chip Select OE Output Enable VCC Power (+3.3V ) VSS Ground NC Not Connected BLOCK DIAGRAM Memory Array AØ-18 Address Buffer Address Decoder I/O Circuits I/OØ-7 WE CS OE June 1999 Rev. 1 1 White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 EDI88512VA-RP TRUTH TABLE ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Unit OE CS WE Mode Output Power V X H L X H L L L X H H L Standby Output Deselect Read Write High Z High Z Data Out Data In Icc 2 , Icc3 Icc 1 Icc 1 Icc 1 -0.5 to 7.0 Operating Temperature TA (Ambient) 0 to +70 °C -40 to +85 °C Military -55 to +125 °C Storage Temperature, Plastic -65 to +125 °C 0.55 W Output Current 20 mA Junction Temperature, TJ 175 °C Commercial Industrial Power Dissipation RECOMMENDED OPERATING CONDITIONS NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameter Supply Voltage Symbol VCC Min 3.0 Typ 3.3 Max 3.6 Unit V Supply Voltage VSS 0 0 0 V Input High Voltage VIH 2.2 — Vcc +0.3 V Input Low Voltage VIL -0.3 — +0.8 V CAPACITANCE (TA = +25°C) Parameter Symbol Condition Address Lines CI VIN = Vcc or Vss, f = 1.0MHz Max Unit 7 pF Data Lines CO VIN = Vcc or Vss, f = 1.0MHz 8 pF These parameters are sampled, not 100% tested. DC CHARACTERISTICS (VCC = 5V, TA = -55°C to +125°C) Parameter Symbol Conditions Units Input Leakage Current ILI VIN = 0V to VCC Min -2 Output Leakage Current ILO VI/O = 0V to VCC -2 2 µA Operating Power Supply Current ICC1 WE, CS = VIL, II/O = 0mA, Min Cycle — 170 mA — 160 mA Standby (TTL) Power Supply Current ICC2 CS ≥ VIH, VIN ≤ VIL, VIN ≥ VIH — 50 mA Full Standby Power Supply Current ICC3 CS ≥ VCC -0.2V VIN ≥ Vcc -0.2V or VIN ≤ 0.2V — 10 mA Output Low Voltage VOL IOL = 8.0mA — 0.4 V Output High Voltage VOH IOH = -4.0mA 2.4 — V (15ns) (20-55ns) Max 2 µA NOTE: DC test conditions: VIL = 0.3V, VIH = Vcc -0.3V AC TEST CONDITIONS Figure 1 Figure 2 Vcc 480Ω Q Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load Vcc 480Ω NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2) Q 255Ω 30pF VSS to 3.0V 5ns 1.5V Figure 1 255Ω White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 5pF 2 EDI88512VA-RP AC CHARACTERISTICS – READ CYCLE (VCC = 5.0V, VSS = 0V, TA = 0°C to +70°C) Parameter Symbol JEDEC Alt. Min 15ns Read Cycle Time tAVAV tRC 15 Address Access Time tAVQV tAA 15 17 20 25 Chip Enable Access Time tELQV tACS 15 17 20 25 Chip Enable to Output in Low Z (1) tELQX tCLZ 3 Chip Disable to Output in High Z (1) tEHQZ tCHZ 0 Output Hold from Address Change tAVQX tOH 0 Output Enable to Output Valid tGLQV tOE Output Enable to Output in Low Z (1) tGLQX tOLZ 0 Output Disable to Output in High Z(1) tGHQZ tOHZ 0 17ns Max Min 20ns Max 17 0 7 0 8 0 7 0 10 12 8 0 Max Min ns ns ns 0 0 ns ns 10 0 Units ns 0 8 0 Max 3 0 7 Min 25 3 0 7 25ns Max 20 3 7 Min ns ns 10 ns Max Units 1. This parameter is guaranteed by design but not tested. AC CHARACTERISTICS – WRITE CYCLE (VCC = 5.0V, VSS = 0V, TA = 0°C to +70°C) Parameter Symbol JEDEC Alt. Min 15ns 17ns Write Cycle Time tAVAV tWC 15 17 20 25 ns Chip Enable to End of Write tELWH tELEH tCW tCW 13 13 14 14 15 15 17 17 ns ns Address Setup Time tAVWL tAVEL tAS tAS 0 0 0 0 0 0 0 0 ns ns Address Valid to End of Write tAVWH tAVEH tAW tAW 12 12 14 14 15 15 17 17 ns ns Write Pulse Width tWLWH tWLEH tWP tWP 12 12 14 14 15 15 17 17 ns ns Write Recovery Time tWHAX tEHAX tWR tWR 0 0 0 0 0 0 0 0 ns ns Data Hold Time tWHDX tEHDX tDH tDH 0 0 0 0 0 0 0 0 ns ns Write to Output in High Z (1) tWLQZ tWHZ 0 Data to Write Time tDVWH tDVEH tDW tDW 8 8 8 8 10 10 12 12 ns ns Output Active from End of Write (1) tWHQX tWLZ 0 0 0 0 ns Max 7 Min 0 20ns Max 8 Min 0 25ns 8 0 10 ns 1. This parameter is guaranteed by design but not tested. 3 White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 EDI88512VA-RP FIG. 2 TIMING WAVEFORM - READ CYCLE tAVAV ADDRESS tAVQV CS tAVAV ADDRESS ADDRESS 1 ADDRESS 2 tAVQV tAVQX tELQV tELQX tEHQZ tGLQV tGLQX tGHQZ OE DATA I/O DATA 1 DATA I/O DATA 2 READ CYCLE 2 (WE HIGH) READ CYCLE 1 (WE HIGH; OE, CS LOW) FIG. 3 WRITE CYCLE - WE CONTROLLED tAVAV ADDRESS tAVWH tELWH tWHAX CS tAVWL tWLWH WE tDVWH DATA IN tWHDX DATA VALID tWLQZ tWHQX HIGH Z DATA OUT WRITE CYCLE 1, WE CONTROLLED FIG. 4 WRITE CYCLE - CS CONTROLLED tAVAV WS32K32-XHX ADDRESS tAVEH tELEH tEHAX CS tAVEL tWLEH WE tDVEH DATA IN DATA VALID HIGH Z DATA OUT WRITE CYCLE 2, CS CONTROLLED White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 tEHDX 4 EDI88512VA-RP FIG. 5 NORMALIZED OPERATING GRAPHS Write Pulse Width vs. Temp. ICC1 (20ns) vs Temp 14 Write Pulse Width (ns) 13 220 ICC1 (ma) 210 200 190 180 11 10 9 8 7 170 160 12 6 -55 25 -55 125 25 125 Temp. (C) Temp. (C) TAVQV vs. Temp ICC3 vs. Temp 10 22 TAVQV (ns) 18 190 16 0.1 14 12 0.01 -55 25 -55 125 25 125 Temp. (C) Temp. (C) ICCDR vs. Temp 10 1 ICCDR (ma) ICC3 (ma) 20 1 0.1 0.01 0.001 -55 25 125 Temp. (C) IDR, 2V 5 Normalized curves are offered as a service to our customers. They are not to be construed as a guarantee of operating characterics. Characteristics of actual devices will vary. IDR, 3V White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 EDI88512VA-RP PACKAGE 319: 36 LEAD, PLASTIC SMALL OUTLINE J-LEAD (SOJ) 0.920 0.930 0.395 0.405 0.360 0.435 0.380 0.445 0.026 0.032 Pin 1 Indicator 0.148 max. 0.375 TYP. 0.050 TYP. 0.027 min. 0.015 0.021 ALL DIMENSIONS ARE IN INCHES ORDERING INFORMATION EDI 8 8 512 VA X X X WHITE ELECTRONIC DESIGNS SRAM ORGANIZATION, 512Kx8 TECHNOLOGY: VA = 3.3V CMOS Standard Power ACCESS TIME (ns) PACKAGE TYPE: M = 36 lead Plastic SOJ DEVICE GRADE: B = MIL-STD-883 Compliant M = Military Screened -55°C to +125°C I = Industrial -40°C to +85°C C = Commercial 0°C to +70°C White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 6