SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER www.ti.com FEATURES • • • • • • • • • • • • OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels GTLP-to-LVTTL 1-to-6 Fanout Driver LVTTL-to-GTLP 1-to-2 Fanout Driver LVTTL Interfaces Are 5-V Tolerant Medium-Drive GTLP Outputs (50 mA) Reduced-Drive LVTTL Outputs (–12 mA/12 mA) Variable Edge-Rate Control (ERC) Input Selects GTLP Rise and Fall Times for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads Ioff and Power-Up 3-State Support Hot Insertion Distributed VCC and GND Pins Minimize High-Speed Switching Noise Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) SCES285E – OCTOBER 1999 – REVISED APRIL 2005 DGV, DW, OR PW PACKAGE (TOP VIEW) AI AO1 GNDT AO2 VCC AO3 GNDT AO4 VCC AO5 GNDT AO6 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 GNDT OEAB BO1 GNDG VREF GNDG ERC BO2 GNDG BI OEBA GNDT DESCRIPTION/ORDERING INFORMATION The SN74GTLP817 is a medium-drive fanout driver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP reduced output swing (<1 V), reduced input threshold levels, improved differential input, and OEC™ circuitry. The improved GTLP OEC circuitry minimizes bus settling time and has been designed and tested using several backplane models. The medium drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 19 Ω. BO1 and BO2 can be tied together to drive an equivalent load impedance down to 11 Ω. GTLP is the Texas Instruments (TI™) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLP817 is given only at the preferred higher noise-margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels. Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input reference voltage. GNDT is the TTL output ground, while GNDG is the GTLP output ground, and both may be separated from each other for a quieter device. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. OEC, TI are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2005, Texas Instruments Incorporated SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER www.ti.com SCES285E – OCTOBER 1999 – REVISED APRIL 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. This device features adjustable edge-rate control (ERC). Changing the ERC input voltage between GND and VCC adjusts the B-port output rise and fall times. This allows the designer to optimize system data-transfer rate and signal integrity to the backplane load. ERC automatically is selected to the same speed as alternate source 1-to-6 fanout drivers that use pin 18 for 3.3-V or 5-V VCC. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION PACKAGE (1) TA (1) TOP-SIDE MARKING SN74GTLP817DW Tape and reel SN74GTLP817DWR TSSOP – PW Tape and reel SN74GTLP817PWR GT817 TVSOP – DGV Tape and reel SN74GTLP817DGVR GT817 SOIC – DW –40°C to 85°C ORDERABLE PART NUMBER Tube GTLP817 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. <BR/> FUNCTIONAL DESCRIPTION The SN74GTLP817 is a fanout driver providing LVTTL-to-GTLP translation and GTLP-to-LVTTL translation in the same package. The LVTTL-to-GTLP direction is a 1-to-2 fanout driver with a single output enable (OEAB). The GTLP-to-LVTTL direction is a 1-to-6 fanout driver with a single output enable (OEBA). Data polarity is inverting for both directions. 2 SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER www.ti.com SCES285E – OCTOBER 1999 – REVISED APRIL 2005 FUNCTION TABLES OUTPUT CONTROL (A TO B) INPUTS AI OEAB OUTPUT BOn MODE Isolation X H Z H L L L L H Inverted transparent OUTPUT CONTROL (B TO A) INPUTS BI OEBA OUTPUT AOn MODE Isolation X H Z H L L L L H Inverted transparent B-PORT EDGE-RATE CONTROL (ERC) INPUT ERC NOMINAL VOLTAGE OUTPUT B-PORT EDGE RATE H VCC Slow L GND Fast LOGIC LEVEL LOGIC DIAGRAM (POSITIVE LOGIC) 23 18 22 OEAB ERC BO1 GTLP Outputs (LVTTL Input) AI OEBA AO1 AO2 AO3 LVTTL Outputs AO4 AO5 AO6 1 17 BO2 14 2 4 6 8 15 20 BI (GTLP Input) VREF 10 12 3 SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER www.ti.com SCES285E – OCTOBER 1999 – REVISED APRIL 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage range |VGNDG – VGNDT| Ground dc voltage difference VI Input voltage range (2) VO Voltage range applied to any output in the high-impedance or power-off state (2) IO Current into any output in the low state IO Current into any A output in the high state (3) MIN MAX –0.5 4.6 V 0.3 V AI port and control inputs –0.5 7 BI port and VREF –0.5 4.6 AO port –0.5 7 BO port –0.5 4.6 AO port 24 BO port 100 Continuous current through each VCC or GND UNIT V V mA 24 mA ±100 mA IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA θJA Package thermal impedance (4) Tstg (1) (2) (3) (4) 4 Storage temperature range DGV package 86 DW package 46 PW package 88 –65 150 °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This current flows only when the output is in the high state and VO > VCC. The package thermal impedance is calculated in accordance with JESD 51-7. SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER www.ti.com SCES285E – OCTOBER 1999 – REVISED APRIL 2005 Recommended Operating Conditions VCC (1) (2) (3) (4) Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage MIN NOM MAX UNIT V 3.15 3.3 3.45 GTL 1.14 1.2 1.26 GTLP 1.35 1.5 1.65 GTL 0.74 0.8 0.87 GTLP 0.87 1 1.1 BI ERC AI, OE VCC 5.5 VCC 5.5 Low-level input voltage VCC – 0.6 Input clamp current IOH High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate ∆t/∆VCC Power-up ramp rate TA Operating free-air temperature (1) (2) (3) (4) V 2 VREF – 0.05 ERC GND AI, OE IIK V VREF + 0.05 BI VIL V VTT AI, OE BI V 0.6 V 0.8 –18 mA AO port –12 mA AO port 12 BO port 50 Outputs enabled mA 10 –40 ns/V µs/V 20 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Normal connection sequence is GND first and VCC = 3.3 V, I/O, control inputs, VTT, VREF (any order) last. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. 5 SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER www.ti.com SCES285E – OCTOBER 1999 – REVISED APRIL 2005 Electrical Characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH AO port VCC = 3.15 V, II = –18 mA VCC = 3.15 V to 3.45 V, IOH = –100 µA VCC – 0.2 IOH = –100 µA VCC – 0.2 VCC = 3.15 V VCC = 3.15 V to 3.45 V, AO port VCC = 3.15 V VOL BO port II BI, AI, OE, ERC AO port IOZH BO port AO port IOZL BO port ICC AO or BO port ∆ICC (2) Ci Co (1) (2) MIN TYP (1) TEST CONDITIONS VCC = 3.15 V VCC = 3.45 V, VCC = 3.45 V VCC = 3.45 V VCC = 3.45 V, IO = 0, VI (AI or control input) = VCC or GND, VI (BI input) = VTT or GND IOH = –6 mA 2.4 IOH = –12 mA 2.2 MAX UNIT –1.2 V V IOL = 100 µA 0.2 IOL = 100 µA 0.2 IOL = 6 mA 0.4 IOL = 12 mA 0.5 IOL = 100 µA 0.2 IOL = 40 mA 0.5 IOL = 50 mA 0.55 VI = 0 or 5.5 V ±5 VO = VCC 10 VO = 1.5 V 5 VO = GND –10 VO = 5.5 V –5 Outputs high 10 Outputs low 10 Outputs disabled 10 AI, OE VCC = 3.45 V, One A-port or control input at VCC – 0.6 V, Other A-port or control inputs at VCC or GND AI, OE, ERC VI = VCC or 0 4 4.4 BI VI = VTT or 0 3.5 3.9 AO port VO = VCC or 0 4 4.5 BO port VO = VTT or 0 5 5.4 1 V µA µA µA mA mA pF pF All typical values are at VCC = 3.3 V, TA = 25°C. This is the increase in supply current for each input that is at the specified LVTTL voltage level, rather than VCC or GND. Hot-Insertion Specifications for A Port over recommended operating free-air temperature range PARAMETER Ioff TEST CONDITIONS VCC = 0, VI or VO = 0 to 5.5 V IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, MIN MAX UNIT 10 µA OE = 0 ±30 µA OE = 0 ±30 µA MAX UNIT Hot-Insertion Specifications for B Port over recommended operating free-air temperature range PARAMETER Ioff 6 TEST CONDITIONS VCC = 0, VI or VO = 0 to 1.5 V IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 1.5 V, IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 1.5 V, MIN 10 µA OE = 0 ±30 µA OE = 0 ±30 µA SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER www.ti.com SCES285E – OCTOBER 1999 – REVISED APRIL 2005 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1) PARAMETER tPLH tPHL tPLH tPHL ten tdis ten tdis TO (OUTPUT) EDGE RATE (1) AI BO Slow AI BO Fast OEAB BO Slow OEAB BO Fast tr Rise time, B outputs (20% to 80%) tf Fall time, B outputs (80% to 20%) tPLH tPHL ten tdis (1) (2) FROM (INPUT) BI AO OEBA AO MIN TYP (2) MAX 3 6 1.8 4.7 2 5 1.5 4.2 3 6.1 2 4.7 2.1 6 1.5 4.7 Slow 2.5 Fast 1.4 Slow 1.7 Fast 1 UNIT ns ns ns ns ns ns 2.3 6 1.9 4.7 1.1 6.3 1.2 5 ns ns Slow (ERC = VCC) and Fast (ERC = GND) All typical values are at VCC = 3.3 V, TA = 25°C. 7 SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER www.ti.com SCES285E – OCTOBER 1999 – REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION 1.5 V 6V 500 Ω From Output Under Test S1 Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND CL = 50 pF (see Note A) 500 Ω S1 Open 6V GND LOAD CIRCUIT FOR AO PORTS 25 Ω From Output Under Test Test Point CL = 30 pF (see Note A) LOAD CIRCUIT FOR BO PORTS 3V 1.5 V Input 1.5 V 0V tPLH tPHL VOH 1V Output 1V 3V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (AI to BO port) 1V 1V 0V tPLH 1.5 V tPLZ 3V 1.5 V VOL + 0.3 V VOL tPZH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (BI to AO port) 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) tPHL VOH Output 1.5 V tPZL 1.5 V Input Output Control Output Waveform 2 S1 at GND (see Note B) tPHZ VOH 1.5 V VOH − 0.3 V ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (AO ports) NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 8 SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER www.ti.com SCES285E – OCTOBER 1999 – REVISED APRIL 2005 Distributed-Load Backplane Switching Characteristics The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer's backplane application probably is a distributed load. The physical representation is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a resistor inductance capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum performance in this RLC circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC load, to help the designer better understand the performance of the GTLP device in this typical backplane. See www.ti.com/sc/gtlp for more information. 38 Ω 0.25” ZO = 70 Ω 2” Conn. 1” Conn. 2” Conn. Conn. 1” 1” 0.25” 38 Ω 1.5 V 1.5 V 1” Rcvr Rcvr Rcvr Slot 2 Slot 9 Slot 10 Drvr Slot 1 Figure 2. Medium-Drive Test Backplane 1.5 V 19 Ω From Output Under Test LL = 19 nH Test Point CL = 9 pF Figure 3. Medium-Drive RLC Network 9 SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER www.ti.com SCES285E – OCTOBER 1999 – REVISED APRIL 2005 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 3) PARAMETER tPLH tPHL tPLH tPHL ten tdis ten tdis (1) (2) 10 FROM (INPUT) TO (OUTPUT) EDGE RATE (1) AI BO Slow AI BO Fast OEAB BO Slow OEAB BO Fast tr Rise time, B outputs (20% to 80%) tf Fall time, B outputs (80% to 20%) Slow (ERC = VCC) and Fast (ERC = GND) All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models. TYP (2) 4.4 4.4 3.2 3.2 4 4.4 2.9 3.1 Slow 1.8 Fast 1 Slow 2 Fast 1.6 UNIT ns ns ns ns ns ns PACKAGE OPTION ADDENDUM www.ti.com 6-Jun-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74GTLP817DGVR ACTIVE TVSOP DGV 24 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SN74GTLP817DGVRE4 ACTIVE TVSOP DGV 24 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SN74GTLP817DW ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLP817DWE4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLP817DWR ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLP817DWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLP817PW ACTIVE TSSOP PW 24 60 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SN74GTLP817PWE4 ACTIVE TSSOP PW 24 60 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SN74GTLP817PWR ACTIVE TSSOP PW 24 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SN74GTLP817PWRE4 ACTIVE TSSOP PW 24 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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