TI PGA112

PG
A1
16
PGA112, PGA113
PGA116, PGA117
PG
A1
17
PG
A1
12
PG
A1
13
www.ti.com
SBOS424 – MARCH 2008
Single-Supply, Single-Ended, Precision
Programmable Gain Amplifier with MUX
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
23
•
•
•
•
•
•
•
•
•
•
•
•
Rail-to-Rail Input/Output
Offset: 25µV (typ), 100µV (max)
Zerø Drift: 0.35µV/°C (typ), 1.2µV/°C (max)
Low Noise: 12nV/√Hz
Input Offset Current: ±5nA max (+25°C)
Gain Error: 0.1% max (G ≤ 32),
0.3% max (G > 32)
Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128
(PGA112, PGA116)
Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200
(PGA113, PGA117)
Gain Switching Time: 200ns
Two Channel MUX: PGA112, PGA113
10 Channel MUX: PGA116, PGA117
Four Internal Calibration Channels
Amplifier Optimized for Driving CDAC ADCs
Output Swing: 50mV to Supply Rails
AVDD and DVDD for Mixed Voltage Systems
IQ = 1.1mA (typ)
Software/Hardware Shutdown: IQ ≤ 4µA (typ)
Temperature Range: –40°C to +125°C
SPI™ Interface (10MHz) with Daisy-Chain
Capability
Remote e-Meter Reading
Automatic Gain Control
Portable Data Acquisition
PC-Based Signal Acquisition Systems
Test and Measurement
Programmable Logic Controllers
Battery-Powered Instruments
Handheld Test Equipment
DESCRIPTION
The PGA112 and PGA113 (binary/scope gains) offer
two analog inputs, a three-pin SPI interface, and
software shutdown in an MSOP-10 package. The
PGA116 and PGA117 (binary/scope gains) offer 10
analog inputs, a four-pin SPI interface with
daisy-chain capability, and hardware and software
shutdown in a TSSOP-20 package.
All versions provide internal calibration channels for
system-level calibration. The channels are tied to
GND, 0.9VCAL, 0.1VCAL, and VREF, respectively. VCAL,
an external voltage connected to Channel 0, is used
as the system calibration reference. Binary gains are:
1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2,
5, 10, 20, 50, 100, and 200.
+3V
+5V
CBYPASS
0.1mF
CBYPASS
0.1mF
CBYPASS
0.1mF
DVDD
AVDD
10
1
MSP430
Microcontroller
PGA112
PGA113
VCAL/CH0
CH1
3
MUX
2
Output
Stage
5
VOUT
ADC
CAL1
10kW
0.9VCAL
0.1VCAL
80kW
G=1
RF
CAL2
CAL3
CAL4
10kW
VREF
RI
SPI
Interface
CAL2/3
6
4
GND
VREF
7
SCLK
8
DIO
9
CS
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI is a trademark of Motorola.
All other trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
PGA112,, PGA113
PGA116, PGA117
www.ti.com
SBOS424 – MARCH 2008
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE AND MODEL COMPARISON
SHUTDOWN
DEVICE
# OF MUX
INPUTS
GAINS
(Eight Each)
SPI
DAISY-CHAIN
HARDWARE
SOFTWARE
PACKAGE
PGA112
Two
Binary
No
No
ü
MSOP-10
PGA113
Two
Scope
No
No
ü
MSOP-10
PGA116
10
Binary
ü
ü
ü
TSSOP-20
PGA117
10
Scope
ü
ü
ü
TSSOP-20
ORDERING INFORMATION (1)
PRODUCT
DESCRIPTION
(Gains/Channels)
PACKAGE-LEAD
PACKAGE
DESIGNATOR
PACKAGE
MARKING
PGA112
Binary (2)/2 Channels
MSOP-10
DGS
P112
PGA113 (3)
Scope (4)/2 Channels
MSOP-10
DGS
P113
(3)
Binary /10 Channels
TSSOP-20
PW
PGA116
PGA117 (3)
Scope (4)/10 Channels
TSSOP-20
PW
PGA117
PGA116
(1)
(2)
(3)
(4)
(2)
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Binary gains: 1, 2, 4, 8, 16, 32, 64, and 128.
Available Q2 2008.
Scope gains: 1, 2, 5, 10, 20, 50, 100, and 200.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
PGA112, PGA113, PGA116, PGA117
UNIT
+7
V
Supply Voltage
Signal Input Terminals, Voltage
(2)
GND – 0.5 to (AVDD) + 0.5
V
±10
mA
Signal Input Terminals, Current (2)
Output Short-Circuit
Continuous
Operating Temperature
–40 to +125
°C
Storage Temperature
–65 to +150
°C
Junction Temperature
+150
°C
Human Body Model (HBM)
3000
V
Charged Device Model (CDM)
1000
V
Machine Model (MM)
300
V
ESD Ratings:
(1)
(2)
2
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should
be current limited to 10mA or less.
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): PGA112 PGA113
PGA112,, PGA113
PGA116, PGA117
www.ti.com
SBOS424 – MARCH 2008
ELECTRICAL CHARACTERISTICS: VS = AVDD = DVDD = +5V
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.
At TA = +25°C, RL = 10kΩ//CL = 100pF connected to DVDD/2, and VREF = GND, unless otherwise noted.
PGA112, PGA113
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
AVDD = DVDD = +5V, VREF = VIN = AVDD/2, VCM = 2.5V
±25
±100
µV
AVDD = DVDD = +5V, VREF = VIN = AVDD/2, VCM = 4.5V
±75
±325
µV
AVDD = DVDD = +5V, VCM = 2.5V
0.35
1.2
µV/°C
vs Temperature, –40°C to +85°C
AVDD = DVDD = +5V, VCM = 2.5V
0.15
0.9
µV/°C
vs Temperature, –40°C to +125°C
AVDD = DVDD = +5V, VCM = 4.5V
0.6
1.8
µV/°C
vs Temperature, –40°C to +85°C
AVDD = DVDD = +5V, VCM = 4.5V
0.3
1.3
µV/°C
AVDD = DVDD = +2.2V to +5.5V, VCM = 0.5V,
VREF = VIN = AVDD/2
5
20
µV/V
AVDD = DVDD = +2.2V to +5.5V, VCM = 0.5V,
VREF = VIN = AVDD/2
5
40
µV/V
VREF = VIN = AVDD/2
±1.5
±5
VREF = VIN = AVDD/2
See Typical Characteristics
OFFSET VOLTAGE
Input Offset Voltage
VOS
vs Temperature, –40°C to +125°C
vs Power Supply
dVOS/dT
PSRR
Over Temperature, –40°C to +125°C
INPUT ON-CHANNEL CURRENT
Input On-Channel Current (Ch0, Ch1)
IIN
Over Temperature, –40°C to +125°C
nA
nA
INPUT VOLTAGE RANGE
Input Voltage Range (1)
IVR
No Output Phase Reversal (2)
Overvoltage Input Range
GND – 0.1
AVDD + 0.1
V
GND – 0.3
AVDD + 0.3
V
INPUT IMPEDANCE (Channel On) (3)
Channel Input Capacitance
CCH
2
Channel Switch Resistance
RSW
150
Ω
Amplifier Input Capacitance
CAMP
3
pF
Amplifier Input Resistance
RAMP
Input Resistance to GND
10
GΩ
RIN
CAL1 or CAL2 Selected
100
kΩ
VCAL/CH0
pF
GAIN SELECTIONS
Nominal Gains
DC Gain Error
Binary gains: 1, 2, 4, 8, 16, 32, 64, 128
1
Scope gains: 1, 2, 5, 10, 20, 50, 100, 200
1
128
200
G=1
VOUT = GND + 85mV to DVDD – 85mV
0.1
%
1 < G ≤ 32
VOUT = GND + 85mV to DVDD – 85mV
0.1
%
G ≥ 50
VOUT = GND + 85mV to DVDD – 85mV
0.3
G=1
VOUT = GND + 85mV to DVDD – 85mV
0.5
ppm/°C
1 < G ≤ 32
VOUT = GND + 85mV to DVDD – 85mV
2
ppm/°C
G ≥ 50
VOUT = GND + 85mV to DVDD – 85mV
6
ppm/°C
Op Amp + Input = 0.9VCAL,
VREF = VCAL = AVDD/2, G = 1
0.02
%
CAL2 DC Gain Drift (4)
Op Amp + Input = 0.9VCAL,
VREF = VCAL = AVDD/2, G = 1
2
ppm/°C
CAL3 DC Gain Error (4)
Op Amp + Input = 0.1VCAL,
VREF = VCAL = AVDD/2, G = 1
0.02
%
CAL3 DC Gain Drift (4)
Op Amp + Input = 0.1VCAL,
VREF = VCAL = AVDD/2, G = 1
2
ppm/°C
CCH
See Figure 1
2
pF
ILKG
VREF = GND, VOFF-CHANNEL = AVDD/2,
VON-CHANNEL = AVDD/2 – 0.1V
±0.05
VREF = GND, VOFF-CHANNEL = AVDD/2,
VON-CHANNEL = AVDD/2 – 0.1V
See Typical Characteristics
DC Gain Drift
CAL2 DC Gain Error
(4)
0.006
%
INPUT IMPEDANCE (Channel Off) (3)
Input Impedance
INPUT OFF-CHANNEL CURRENT
Input Off-Channel Current (Ch0, Ch1) (5)
Over Temperature, –40°C to +125°C
Channel-to-Channel Crosstalk
(1)
(2)
(3)
(4)
(5)
±1
130
nA
dB
Gain error is a function of the input voltage. Gain error outside of the range (GND + 85mV ≤ VOUT ≤ DVDD – 85mV) increases to 0.5%
(typical).
Input voltages beyond this range must be current limited to < |10mA| through the input protection diodes on each channel to prevent
permanent destruction of the device.
See Figure 1.
Total VOUT error must be computed using input offset voltage error multiplied by gain. Includes op amp G = 1 error.
Maximum specification limitation limited by final test time and capability.
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): PGA112 PGA113
3
PGA112,, PGA113
PGA116, PGA117
www.ti.com
SBOS424 – MARCH 2008
ELECTRICAL CHARACTERISTICS: VS = AVDD = DVDD = +5V (continued)
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.
At TA = +25°C, RL = 10kΩ//CL = 100pF connected to DVDD/2, and VREF = GND, unless otherwise noted.
PGA112, PGA113
PARAMETER
CONDITIONS
MIN
IOUT = ±0.25mA, AVDD ≥ DVDD (6)
IOUT = ±5mA, AVDD ≥ DVDD (6)
TYP
MAX
UNIT
GND + 0.05
DVDD – 0.05
V
GND + 0.25
DVDD – 0.25
OUTPUT
Voltage Output Swing from Rail
VOUT = GND + 85mV to DVDD – 85mV (7)
DC Output Nonlinearity
Short-Circuit Current
Capacitive Load Drive
ISC
CLOAD
V
0.0015
%FSR
–30/+60
mA
See Typical Characteristics
NOISE
Input Voltage Noise Density
en
f > 10kHz, CL = 100pF, VS = 5V
12
nV/√Hz
f > 10kHz, CL = 100pF, VS = 2.2V
22
nV/√Hz
f = 0.1Hz to 10Hz, CL = 100pF, VS = 5V
0.362
µVPP
f = 0.1Hz to 10Hz, CL = 100pF, VS = 2.2V
0.736
µVPP
f = 10kHz, CL = 100pF
400
fA/√Hz
SR
See Table 1
V/µs
tS
See Table 1
µs
See Table 1
MHz
Input Voltage Noise
en
Input Current Density
In
SLEW RATE
Slew Rate
SETTLING TIME
Settling Time
FREQUENCY RESPONSE
Frequency Response
THD + NOISE
G = 1, f = 1kHz, VOUT = 4VPP at 2.5VDC, CL = 100pF
0.003
%
G = 10, f = 1kHz, VOUT = 4VPP at 2.5VDC, CL = 100pF
0.005
%
G = 50, f = 1kHz, VOUT = 4VPP at 2.5VDC, CL = 100pF
0.03
%
G = 128, f = 1kHz, VOUT = 4VPP at 2.5VDC, CL = 100pF
0.08
%
G = 200, f = 1kHz, VOUT = 4VPP at 2.5VDC, CL = 100pF
0.1
%
G = 1, f = 20kHz, VOUT = 4VPP at 2.5VDC, CL = 100pF
0.02
%
G = 10, f = 20kHz, VOUT = 4VPP at 2.5VDC, CL = 100pF
0.01
%
G = 50, f = 20kHz, VOUT = 4VPP at 2.5VDC, CL = 100pF
0.03
%
G = 128, f = 20kHz, VOUT = 4VPP at 2.5VDC, CL = 100pF
0.08
%
G = 200, f = 20kHz, VOUT = 4VPP at 2.5VDC, CL = 100pF
0.11
%
POWER SUPPLY
Operating Voltage Range (6)
Quiescent Current Analog
AVDD
2.2
5.5
DVDD
2.2
5.5
V
0.45
mA
0.45
mA
1.2
mA
1.2
mA
IQA
IO = 0, G = 1, VOUT = VREF
0.33
IQD
IO = 0, G = 1, VOUT = VREF, SCLK at 10MHz,
CS = Logic 0, DIO = Logic 0
0.75
Over Temperature, –40°C to +125°C
Quiescent Current Digital (8) (9) (10)
IO = 0, G = 1, VOUT = VREF, SCLK at 10MHz,
CS = Logic 0, DIO = Logic 0
Over Temperature, –40°C to +125°C (8) (9)(10)
Shutdown Current Analog + Digital (8) (9)
ISDA + ISDD
V
IO = 0, VOUT = VREF, G = 1, SCLK Idle
4
µA
IO = 0, VOUT = 0, G = 1, SCLK at 10MHz,
CS = Logic 0, DIO = Logic 0
245
µA
Digital interface disabled and Command Register set to POR
values for DVDD < POR Trip Voltage
1.6
V
POWER-ON RESET (POR)
POR Trip Voltage
(6)
(7)
(8)
(9)
(10)
4
When AVDD is less than DVDD, the output is clamped to AVDD + 300mV.
Measurement limited by noise in test equipment and test time.
Does not include current into or out of the VREF pin. Internal RF and RI are always connected between VOUT and VREF.
Digital logic levels: DIO = logic 0. 10µA internal current source.
Includes current from op amp output structure.
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): PGA112 PGA113
PGA112,, PGA113
PGA116, PGA117
www.ti.com
SBOS424 – MARCH 2008
ELECTRICAL CHARACTERISTICS: VS = AVDD = DVDD = +5V (continued)
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.
At TA = +25°C, RL = 10kΩ//CL = 100pF connected to DVDD/2, and VREF = GND, unless otherwise noted.
PGA112, PGA113
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
TEMPERATURE RANGE
Specified Range
–40
+125
°C
Operating Range
–40
+125
°C
θJA
Thermal Resistance
MSOP-10
°C/W
164
DIGITAL INPUTS (SCLK, CS, DIO)
Logic Low
0
0.3DVDD
V
Input Leakage Current (SCLK and CS only)
–1
+1
µA
Weak Pull-Down Current (DIO only)
µA
10
Logic High
0.7DVDD
Hysteresis
DVDD
700
V
mV
DIGITAL OUTPUT (DIO)
Logic High
IOH = –3mA (sourcing)
DVDD – 0.4
DVDD
V
Logic Low
IOL = +3mA (sinking)
GND
GND + 0.4
V
CHANNEL AND GAIN TIMING
Channel Select Time
0.2
µs
Gain Select Time
0.2
µs
SHUTDOWN MODE TIMING
4.0
µs
VOUT goes high-impedance, RF and RI remain connected
between VOUT and VREF
2.0
µs
DVDD ≥ 2V
40
µs
DVDD ≤ 1.5V
5
µs
Enable Time
Disable Time
POWER-ON-RESET (POR) TIMING
POR Power-Up Time
POR Power-Down Time
Table 1. Frequency Response versus Gain (CL = 100pF, RL= 10kΩ)
TYPICAL
–3dB
BINARY
FREQUENCY
GAIN (V/V)
(MHz)
SLEW
RATEFALL
(V/µs)
SLEW
RATERISE
(V/µs)
0.1%
0.01%
SETTLING SETTLING
TIME:
TIME:
4VPP
4VPP
(µs)
(µs)
SCOPE
GAIN
(V/V)
TYPICAL
–3dB
FREQUENCY
(MHz)
SLEW
RATEFALL
(V/µs)
SLEW
RATERISE
(V/µs)
0.1%
0.01%
SETTLING SETTLING
TIME:
TIME:
4VPP
4VPP
(µs)
(µs)
1
10
8
3
2
2.55
1
10
8
3
2
2.55
2
3.8
9
6.4
2
2.6
2
3.8
9
6.4
2
2.6
4
2
12.8
10.6
2
2.6
5
1.8
12.8
10.6
2
2.6
8
1.8
12.8
10.6
2
2.6
10
1.8
12.8
10.6
2.2
2.6
16
1.6
12.8
12.8
2.3
2.6
20
1.3
12.8
9.1
2.3
2.8
32
1.8
12.8
13.3
2.3
3
50
0.9
9.1
7.1
2.4
3.8
64
0.6
4
3.5
3
6
100
0.38
4
3.5
4.4
7
128
0.35
2.5
2.5
4.8
8
200
0.23
2.3
2
6.9
10
Mux
Switch
CHx
(Input)
RSW
CAMP
CCH
VOUT
RAMP
Break-Before-Make
RF
RI
VREF
Figure 1. Equivalent Input Circuit
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): PGA112 PGA113
5
PGA112,, PGA113
PGA116, PGA117
www.ti.com
SBOS424 – MARCH 2008
SPI TIMING: VS = AVDD = DVDD = +2.2V to +5V
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.
At TA = +25°C, RL = 10kΩ//CL = 100pF connected to DVDD/2, and VREF = GND, unless otherwise noted.
PGA112, PGA113,
PGA116, PGA117
PARAMETER
TEST CONDITIONS
MIN
Input Capacitance (SCLK, CS, and DIO pins)
TYP
MAX
1
pF
(1)
Input Rise/Fall Time
(CS, SCLK, and DIO pins)
Output Rise/Fall Time (DIO pin)
CS High Time (CS pin)
tRFI
(1)
tRFO
(1)
CLOAD = 60pF
UNIT
2
µs
10
ns
tCSH
40
ns
tCSO
10
ns
CS Fall to First SCLK Edge Setup Time
tCSSC
10
SCLK Frequency (2)
fSCLK
SCLK Edge to CS Fall Setup Time (1)
ns
10
MHz
SCLK High Time (3)
tHI
40
ns
SCLK Low Time (3)
tLO
40
ns
tSCCS
10
ns
SCLK Last Edge to CS Rise Setup Time (1)
CS Rise to SCLK Edge Setup Time
(1)
tCS1
10
ns
DIN Setup Time
tSU
10
ns
DIN Hold Time
tHD
10
ns
SCLK to DOUT Valid Propagation Delay
(1)
CS Rise to DOUT Forced to Hi-Z (1)
(1)
(2)
(3)
6
tDO
25
ns
tSOZ
20
ns
Ensured by design; not production tested.
When using devices in daisy-chain mode, the maximum clock frequency for SCLK is determined by a combination of propagation delay
time (tDO ≤ 25ns), data input setup time (tSU ≥ 10ns), SCLK high time (tHI ≥ 40ns), and DOUT rise and fall times (tRFO ≤ 10ns). In
addition, maximum clock frequency depends directly on the number of devices in the daisy-chain.
tHI and tLO must not be less than 1/SCLK (max).
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): PGA112 PGA113
PGA112,, PGA113
PGA116, PGA117
www.ti.com
SBOS424 – MARCH 2008
SPI TIMING DIAGRAMS
tCSH
CS
tCSSC
tSCCS
tLO
tCS1
tCS0
tHI
SCLK
tSU
1/fSCLK
tHD
DIN
tSOZ
tDO
Hi-Z
Hi-Z
DOUT
Figure 2. SPI Mode 0, 0
tCSH
CS
tCSSC
tSCCS
tHI
tCS1
tCS0
tLO
SCLK
1/fSCLK
tSU
tHD
DIN
tDO
Hi-Z
tSOZ
Hi-Z
DOUT
Figure 3. SPI Mode 1, 1
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): PGA112 PGA113
7
PGA112,, PGA113
PGA116, PGA117
www.ti.com
SBOS424 – MARCH 2008
PIN CONFIGURATIONS
MSOP-10
DGS PACKAGE
(TOP VIEW)
AVDD
1
CH1
2
PGA112
PGA113
10
DVDD
9
CS
8
DIO
VCAL/CH0
3
VREF
4
7
SCLK
VOUT
5
6
GND
PGA112, PGA113 TERMINAL FUNCTIONS
MSOP
PACKAGE
PIN #
NAME
DESCRIPTION
1
AVDD
Analog supply voltage (+2.2V to +5.5V)
2
CH1
Input MUX channel 1
3
VCAL/CH0
Input MUX channel 0 and VCAL input. For system calibration purposes, connect this pin to a
low-impedance external reference voltage to use internal calibration channels. The four internal
calibration channels are connected to GND, 0.9VCAL, 0.1VCAL, and VREF, respectively. VCAL is loaded
with 100kΩ (typical) when internal calibration channels CAL2 or CAL3 are selected. Otherwise,
VCAL/CH0 appears as high impedance.
4
VREF
Reference input pin. Connect external reference for VOUT offset shift or to midsupply for midsupply
referenced systems. VREF must be connected to a low-impedance reference capable of sourcing and
sinking at least 2mA or VREF must be connected to GND.
5
VOUT
Analog voltage output. When AVDD < DVDD, VOUT is clamped to AVDD + 300mV.
6
GND
Ground pin
7
SCLK
Clock input for SPI serial interface
8
DIO
Data input/output for SPI serial interface. DIO contains a weak, 10µA internal pull-down current source.
9
CS
Chip select line for SPI serial interface
10
8
DVDD
Digital and op amp output stage supply voltage (+2.2V to +5.5V). Useful in multi-supply systems to
prevent overvoltage/lockup condition on an analog-to-digital (ADC) input (for example, a microcontroller
with an ADC running on +3V and the PGA powered from +5V). Digital I/O levels to be relative to DVDD.
DVDD should be bypassed with a 0.1µF ceramic capacitor, and DVDD must supply the current for the
digital portion of the PGA as well as the load current for the op amp output stage.
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TSSOP-20
PW PACKAGE
(TOP VIEW)
AVDD
1
20
CH6
CH5
2
19
DVDD
CH4
3
18
CS
CH3
4
17
DOUT
16
DIN
PGA116
PGA117
CH2
5
CH1
6
15
SCLK
VCAL/CH0
7
14
GND
VREF
8
13
ENABLE
VOUT
9
12
CH9
CH7
10
11
CH8
PGA116, PGA117 TERMINAL FUNCTIONS
TSSOP
PACKAGE
PIN #
NAME
DESCRIPTION
1
AVDD
Analog supply voltage (+2.2V to +5.5V)
2
CH5
Input MUX channel 5
3
CH4
Input MUX channel 4
4
CH3
Input MUX channel 3
5
CH2
Input MUX channel 2
6
CH1
Input MUX channel 1
7
VCAL/CH0
Input MUX channel 0 and VCAL input. For system calibration purposes, connect this pin to a
low-impedance external reference voltage to use internal calibration channels. The four internal
calibration channels are connected to GND, 0.9VCAL, 0.1VCAL, and VREF, respectively. VCAL is loaded
with 100kΩ (typical) when internal calibration channels CAL2 or CAL3 are selected. Otherwise,
VCAL/CH0 appears as high impedance.
8
VREF
Reference input pin. Connect external reference for VOUT offset shift or to midsupply for midsupply
referenced systems. VREF must be connected to a low-impedance reference capable of sourcing and
sinking at least 2mA or to GND.
9
VOUT
Analog voltage output. When AVDD < DVDD, VOUT is clamped to AVDD + 300mV.
10
CH7
Input MUX channel 7
11
CH8
Input MUX channel 8
12
CH9
Input MUX channel 9
13
ENABLE
Hardware enable pin. Logic low puts the part into Shutdown mode (IQ < 1µA).
14
GND
Ground pin
15
SCLK
Clock input for SPI serial interface
16
DIN
17
DOUT
18
CS
Data input for SPI serial interface. DIN contains a weak, 10µA internal pull-down current source to
allow for ease of daisy-chain configurations.
Data output for SPI serial interface. DOUT goes to high-Z state when CS goes high for standard SPI
interface.
Chip select line for SPI serial interface
19
DVDD
Digital and op amp output stage supply voltage (+2.2V to +5.5V). Useful in multi-supply systems to
prevent overvoltage/lockup condition on an ADC input (for example, a microcontroller with an ADC
running on +3V and the PGA powered from +5V). Digital I/O levels to be relative to DVDD. DVDD should
be bypassed with a 0.1µF ceramic capacitor, and DVDD must supply the current for the digital portion of
the PGA as well as the load current for the op amp output stage.
20
CH6
Input MUX channel 6
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TYPICAL APPLICATION CIRCUITS
+3V
+5V
CBYPASS
0.1mF
CBYPASS
0.1mF
AVDD
CBYPASS
0.1mF
DVDD
1
10
MSP430
Microcontroller
PGA112
PGA113
3
VCAL/CH0
MUX
2
CH1
Output
Stage
5
VOUT
7
SCLK
ADC
CAL1
10kW
0.9VCAL
0.1VCAL
80kW
RF
G=1
CAL2
CAL3
VREF
CAL4
RI
SPI
Interface
CAL2/3
10kW
6
4
GND
VREF
8
DIO
9
CS
Figure 4. PGA112, PGA113 (MSOP-10)
+5V
CBYPASS
0.1mF
AVDD
VCAL/CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
1
7
+3V
6
19
5
DVDD
CBYPASS
0.1mF
PGA116
PGA117
4
CBYPASS
0.1mF
3
2
MSP430
Microcontroller
20
10
MUX
11
12
Output
Stage
9
VOUT
15
SCLK
16
DIN
18
CS
17
DOUT
ADC
CAL1
10kW
0.9VCAL
0.1VCAL
80kW
G=1
RF
CAL2
CAL3
CAL4
10kW
VREF
RI
SPI
Interface
CAL2/3
14
8
GND
VREF
13
ENABLE
Figure 5. PGA116, PGA117 (TSSOP-20)
10
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SBOS424 – MARCH 2008
TYPICAL CHARACTERISTICS
At TA = +25°C, AVDD = DVDD = 5V, RL = 10kΩ connected to DVDD/2, VREF = GND, and CL = 100pF, unless otherwise noted.
OFFSET VOLTAGE PRODUCTION DISTRIBUTION
VCM = 2.5V
VCM = 4.5V
-250
-225
-200
-175
-150
-125
-100
-75
-50
-25
0
25
50
75
100
125
150
175
200
225
250
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Population
Population
OFFSET VOLTAGE PRODUCTION DISTRIBUTION
Offset Voltage (mV)
Offset Voltage (mV)
Figure 6.
Figure 7.
OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION
(–40°C to +85°C)
OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION
(–40°C TO +85°C)
VCM = 4.5V
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Population
Population
VCM = 2.5V
Offset Voltage Drift (mV/°C)
Offset Voltage Drift (mV/°C)
Figure 8.
Figure 9.
OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION
(–40°C to +125°C)
OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION
(–40°C TO +125°C)
VCM = 4.5V
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Population
Population
VCM = 2.5V
Offset Voltage Drift (mV/°C)
Offset Voltage Drift (mV/°C)
Figure 10.
Figure 11.
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SBOS424 – MARCH 2008
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = DVDD = 5V, RL = 10kΩ connected to DVDD/2, VREF = GND, and CL = 100pF, unless otherwise noted.
INPUT OFFSET VOLTAGE vs INPUT VOLTAGE
PGA112/PGA116 NONLINEARITY
0.0010
DC Output Nonlinearity Error (%FSR)
100
Input Offset Voltage (mV)
80
60
40
20
0
-20
-40
-60
-80
AVDD = DVDD = +5V
0.0008
G=1
0.0006
0.0004
0.0002
0
-0.0002
G = 16
-0.0004
-0.0006
G = 128
-0.0008
-0.0010
-100
0
1
2
3
4
0
5
0.5
Input Voltage (V)
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VOUT (V)
Figure 12.
Figure 13.
GAIN ERROR PRODUCTION DISTRIBUTION
GAIN ERROR PRODUCTION DISTRIBUTION
-0.10
-0.09
-0.08
-0.07
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
-0.10
-0.09
-0.08
-0.07
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
Population
G=2
Population
G=1
Gain Error (%)
Gain Error (%)
Figure 14.
Figure 15.
GAIN ERROR PRODUCTION DISTRIBUTION
GAIN ERROR PRODUCTION DISTRIBUTION
G = 128
-0.20
-0.18
-0.16
-0.14
-0.12
-0.10
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
Population
-0.10
-0.09
-0.08
-0.07
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
Population
G = 32
Gain Error (%)
Gain Error (%)
Figure 16.
12
G=2
Figure 17.
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SBOS424 – MARCH 2008
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = DVDD = 5V, RL = 10kΩ connected to DVDD/2, VREF = GND, and CL = 100pF, unless otherwise noted.
GAIN ERROR DRIFT PRODUCTION DISTRIBUTION
(–40°C to +125°C)
GAIN ERROR DRIFT PRODUCTION DISTRIBUTION
(–40°C to +125°C)
G=1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
Population
Population
G=2
Gain Error Drift (ppm/°C)
Gain Error Drift (ppm/°C)
Figure 18.
Figure 19.
GAIN ERROR DRIFT PRODUCTION DISTRIBUTION
(–40°C to +125°C)
GAIN ERROR DRIFT PRODUCTION DISTRIBUTION
(–40°C to +125°C)
G = 128
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
0
0.15
0.30
0.45
0.60
0.75
0.90
1.05
1.20
1.35
1.50
1.65
1.80
1.95
2.10
2.25
2.40
2.55
2.70
2.85
3.00
Population
Population
G = 32
Gain Error Drift (ppm/°C)
Gain Error Drift (ppm/°C)
CAL2 GAIN ERROR PRODUCTION DISTRIBUTION
CAL3 GAIN ERROR PRODUCTION DISTRIBUTION
-0.10
-0.09
-0.08
-0.07
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
-0.10
-0.09
-0.08
-0.07
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
Population
Figure 21.
Population
Figure 20.
Gain Error (%)
Gain Error (%)
Figure 22.
Figure 23.
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SBOS424 – MARCH 2008
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = DVDD = 5V, RL = 10kΩ connected to DVDD/2, VREF = GND, and CL = 100pF, unless otherwise noted.
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
> 2.0
Population
CAL3 GAIN ERROR DRIFT PRODUCTION DISTRIBUTION
(–40°C to +125°C)
Population
CAL2 GAIN ERROR DRIFT PRODUCTION DISTRIBUTION
(–40°C to +125°C)
Gain Error Drift (ppm/°C)
Gain Error Drift (ppm/°C)
Figure 24.
Figure 25.
0.1Hz TO 10Hz NOISE
0.1Hz TO 10Hz NOISE
100nV/div
VS = 5V
250nV/div
VS = 2.2V
2.5s/div
2.5s/div
Figure 26.
Figure 27.
SPECTRAL NOISE DENSITY
PGA112 THD + NOISE vs FREQUENCY
(VOUT = 2VPP)
100
1
1k
G = 128
G = 32
50
Voltage Noise, VS = 2.2V
20
200
G = 16
0.1
THD+N (%)
500
Current Noise, VS = 5V
Current Noise (fA/ÖHz)
Voltage Noise (nV/ÖHz)
G = 64
0.01
0.001
Voltage Noise, VS = 5V
G=1
10
1
10
100
1k
10k
100
100k
G=8
G=4
0.0001
10
Frequency (Hz)
100
1k
10k
100k
Frequency (Hz)
Figure 28.
14
G=2
Figure 29.
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SBOS424 – MARCH 2008
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = DVDD = 5V, RL = 10kΩ connected to DVDD/2, VREF = GND, and CL = 100pF, unless otherwise noted.
PGA112 THD + NOISE vs FREQUENCY
(VOUT = 4VPP)
PGA113 THD + NOISE vs FREQUENCY
(VOUT = 2VPP)
1
1
G = 200 G = 100
G = 128
G = 32
G = 64
G = 20
G = 16
0.1
THD+N (%)
0.1
THD+N (%)
G = 50
0.01
0.01
G=8
0.001
0.001
G=2
G=4
G=2
G=1
G=1
0.0001
G=5
G = 10
0.0001
10
100
1k
10k
100k
10
100
1k
10k
Frequency (Hz)
Frequency (Hz)
Figure 30.
Figure 31.
PGA113 THD + NOISE vs FREQUENCY
(VOUT = 4VPP)
QUIESCENT CURRENT
vs TEMPERATURE
1
100k
0.8
G = 200
G = 100
G = 50
0.7
G = 20
0.1
0.6
Digital
IQ (mA)
THD+N (%)
0.5
0.01
0.4
0.3
Analog
G=1
0.001
0.2
G=2
G=5
VS = 5.5V
0.1
G = 10
0.0001
VS = 2.2V
fSCLK = 10MHz
0
10
100
1k
10k
100k
-50
-25
0
Frequency (Hz)
25
50
75
100
125
Temperature (°C)
Figure 32.
Figure 33.
TOTAL QUIESCENT CURRENT
vs SUPPLY VOLTAGE
SHUTDOWN QUIESCENT CURRENT
vs TEMPERATURE
4.0
1.2
SCLK = 5MHz
SCLK = 10MHz
3.5
1.0
Digital
Shutdown IQ (mA)
IQA + IQD (mA)
3.0
0.8
SCLK = 2MHz
SCLK = 500kHz
0.6
0.4
2.5
2.0
1.5
Analog
1.0
0.2
0.5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
-50
-25
0
25
50
Supply Voltage (V)
Temperature (°C)
Figure 34.
Figure 35.
75
100
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SBOS424 – MARCH 2008
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = DVDD = 5V, RL = 10kΩ connected to DVDD/2, VREF = GND, and CL = 100pF, unless otherwise noted.
OUTPUT VOLTAGE
vs OUTPUT CURRENT
OUTPUT VOLTAGE
vs OUTPUT CURRENT
5.5
2.2
VS = 2.2V
G=1
1.8
4.5
1.6
4.0
1.4
1.2
+125°C
1.0
+25°C
-40°C
0.8
0.6
VS = 5.5V
G=1
5.0
Output Voltage (V)
Output Voltage (V)
2.0
3.5
+125°C
3.0
+25°C
2.5
2.0
-40°C
1.5
0.4
1.0
0.2
0.5
0
0
0
2
4
6
8
10
12
14
16
18
20
0
22 24
10
30
40
50
60
70
Output Current (mA)
Figure 36.
Figure 37.
OUTPUT VOLTAGE SWING vs FREQUENCY
80
90
100
OUTPUT VOLTAGE SWING vs FREQUENCY
2.5
2.5
AVDD = DVDD = 2.2V
AVDD = DVDD = 2.2V
G=4
2.0
G=8
1.5
G=2
1.0
Output Voltage (V)
2.0
Output Voltage (V)
20
Output Current (mA)
0.5
1.5
G = 16
G = 64
1.0
G = 32
0.5
G=1
G = 128
0
0
1k
10k
100k
1M
10M
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
Figure 38.
Figure 39.
OUTPUT VOLTAGE SWING vs FREQUENCY
OUTPUT VOLTAGE SWING vs FREQUENCY
6
6
G=8
G = 16
5
G=4
4
3
G=1
2
G=2
1
Output Voltage (V)
Output Voltage (V)
5
G = 32
4
3
G = 64
2
1
AVDD = DVDD = 5.5V
0
100
16
10M
1k
10k
100k
1M
10M
AVDD = DVDD = 5.5V
0
100
1k
10k
G = 128
100k
Frequency (Hz)
Frequency (Hz)
Figure 40.
Figure 41.
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10M
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SBOS424 – MARCH 2008
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = DVDD = 5V, RL = 10kΩ connected to DVDD/2, VREF = GND, and CL = 100pF, unless otherwise noted.
SMALL-SIGNAL OVERSHOOT
vs LOAD CAPACITANCE
GAIN vs SETTLING TIME
50
12
40
Settling Time (ms)
Overshoot (%)
G=1
30
G>2
20
10
0.01%
8
6
0.1%
4
2
0
0
100
200
300
400
500
600
700
800
50
150
200
Figure 42.
Figure 43.
INPUT ON-CHANNEL CURRENT
vs TEMPERATURE
INPUT OFF-CHANNEL LEAKAGE CURRENT
vs TEMPERATURE
40
CH0
30
20
10
CH1
0
-25
25
50
75
100
125
12
10
8
CH0
6
4
2
CH1
0
-50
0
-25
25
50
75
Temperature (°C)
Temperature (°C)
Figure 44.
Figure 45.
POWER-SUPPLY REJECTION RATIO
vs FREQUENCY
110
100
125
CROSSTALK vs FREQUENCY
140
G=1
100
130
90
G=2
70
120
Crosstalk (dB)
G = 200
80
PSRR (dB)
100
Gain
50
0
-50
0
Load Capacitance (pF)
| Input Off-Channel Leakage Current (nA) |
0
| Input On-Channel Current (nA) |
CL = 100pF//RL = 10kW
VOUT = 4VPP
10
G = 50
60
50
G = 10
40
30
110
100
90
80
20
70
10
60
0
0.1
1
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 46.
Figure 47.
1M
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SBOS424 – MARCH 2008
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = DVDD = 5V, RL = 10kΩ connected to DVDD/2, VREF = GND, and CL = 100pF, unless otherwise noted.
SMALL-SIGNAL PULSE RESPONSE
G = 20
G = 10
G=1
100mV
SMALL-SIGNAL PULSE RESPONSE
100mV
G = 50
Output
Output
0V
VIN/G
VIN/G
Input
Input
0V
0V
2.5ms/div
2.5ms/div
Figure 48.
Figure 49.
LARGE-SIGNAL PULSE RESPONSE
LARGE-SIGNAL PULSE RESPONSE
G = 10
G=2
G=1
G = 50
Output
2V/div
2V/div
G = 100, 200
0V
Input
Output
G = 100, 200
Input
2.5ms/div
2.5ms/div
Figure 50.
Figure 51.
POWER-UP/POWER-DOWN TIMING
OUTPUT OVERDRIVE PERFORMANCE
VIN
5V
1V/div
Output (1V/div)
0V
VOUT
Supply (5V/div)
0V
18
0V
VS = 5V
RL = 10kW
CL = 100pF
25ms/div
1ms/div
Figure 52.
Figure 53.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = DVDD = 5V, RL = 10kΩ connected to DVDD/2, VREF = GND, and CL = 100pF, unless otherwise noted.
OUTPUT VOLTAGE vs SHUTDOWN MODE
Active
Active
In
Shutdown
In
Shutdown
2V/div
Output
Output
CS
CS
10ms/div
Figure 54.
SERIAL INTERFACE INFORMATION
edge), the device takes no action. This condition
provides reliable serial communication. Furthermore,
this condition also provides a way to quickly reset the
SPI interface to a known starting condition for data
synchronization. Transmitted data are latched
internally on the rising edge of CS.
SERIAL DIGITAL INTERFACE: SPI MODES
The PGA uses a standard serial peripheral interface
(SPI). Both SPI Mode 0,0 and Mode 1,1 are
supported, as shown in Figure 55 and described in
Table 2.
If there are not even-numbered increments of 16
clocks (that is, 16, 32, 64, and so forth) between CS
going low (falling edge) and CS going high (rising
SPI Mode 0, 0 (CPOL = 0, CPHA = 0)
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
DIN
DOUT
SPI Mode 1, 1 (CPOL = 1, CPHA = 1)
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
DIN
DOUT
Figure 55. SPI Mode 0,0 and Mode 1,1
Table 2. SPI Mode Setting Description
MODE
CPOL
CPHA
CPOL DESCRIPTION
CPHA DESCRIPTION
0, 0
0
0 (1)
Clock idles low
Data are read on the rising edge of clock. Data change on the falling edge of clock.
1, 1
1
1 (2)
Clock idles high
Data are read on the rising edge of clock. Data change on the falling edge of clock.
(1)
(2)
CPHA = 0 means sample on first clock edge (rising or falling) after a valid CS.
CPHA = 1 means sample on second clock edge (rising or falling) after a valid CS.
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On the PGA116/PGA117, CS, DIN, and SCLK are
Schmitt-triggered CMOS logic inputs. DIN has a weak
internal
pull-down
to
support
daisy-chain
communications on the PGA116/PGA117. DOUT is a
CMOS logic output. When CS is high, the state of
DOUT is high-impedance. When CS is low, DOUT is
driven as illustrated in Figure 56.
On the PGA112/PGA113, there are digital output and
digital input gates both internally connected to the
DIO pin. DIN is an input-only gate and DOUT is a
digital output that can give a 3-state output. The DIO
pin has a weak 10µA pull-down current source to
prevent the pin from floating in systems with a
high-impedance SPI DOUT line. When CS is high,
the state of the internal DOUT gate is
high-impedance. When CS is low, the state of DIO
depends on the previous valid SPI communication;
either DIO becomes an output to clock out data or it
remains an input to receive data. This structure is
shown in Figure 57.
DOUT
DIN
10mA
PGA116
PGA117
Figure 56. Digital I/O Structure—PGA116/PGA117
DOUT
DIO
DIN
10mA
PGA112
PGA113
Figure 57. Digital I/O Structure—PGA112/PGA113
20
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DIO
Pin
DIO
Pin
DIO
Pin
DIO
Pin
DOUT
DIN
SCLK
CS
DOUT
DIN
SCLK
CS
DOUT
DIN
SCLK
CS
DOUT
DIN
SCLK
CS
0
D15
1
D15
0
1
D15
1
D15
1
1
D14
2
D14
1
2
D14
2
D14
2
D13
1
3
D13
1
3
D13
3
D13
3
D12
0
4
D12
0
4
D12
4
D12
4
D11
1
5
D11
1
5
D11
5
D11
5
Hi-Z
D10
0
6
Hi-Z
D10
0
6
Hi-Z
D10
6
Hi-Z
D10
6
D8
8
D7
9
D6
10
D8
8
D7
9
D6
10
D8
0
8
D7
0
9
D6
0
10
D9
1
7
D8
0
8
0
D7
9
0
D6
10
SPI Read, Mode = 1, 1
D9
1
7
SPI Read, Mode = 0, 0
D9
7
SPI Write, Mode = 1, 1
D9
7
SPI Write, Mode = 0, 0
0
D5
11
D5
0
11
D5
11
D5
11
0
D4
12
D4
0
12
D4
12
D4
12
0
D3
13
D3
0
13
D3
13
D3
13
0
D2
14
D2
0
14
D2
14
D2
14
0
D1
15
D1
0
15
D1
15
D1
15
0
D0
16
D0
0
16
D0
16
D0
16
17
0
D14
0
18
D15
0
D14
0
18
D15
17
0
19
D13
D13
0
19
20
0
0
21
0
0
22
0
22
D10
D10
21
D11
D11
D12
D12
0
20
0
D9
23
D9
0
23
0
D8
24
D8
0
24
25
G3
D7
26
G2
D6
G2
D6
D7
26
G3
25
D5
G1
27
G1
D5
27
29
30
31
32
32
CH0
D0
D0
CH0
31
CH1
D1
D1
CH1
30
CH2
D2
D2
CH2
29
CH3
D3
D3
CH3
28
G0
D4
D4
G0
28
Hi-Z
Hi-Z
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PGA116, PGA117
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SPI SERIAL INTERFACE: PGA112/PGA113 ONLY
Figure 58. SPI Serial Interface Timing Diagrams
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SPI COMMANDS: PGA112/PGA113 ONLY
Table 3. SPI Commands (PGA112/PGA113) (1) (2)
D14
D13
D12
D11
D10
D9
D8
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
READ
0
0
1
0
1
0
1
0
G3
G2
G1
G0
CH3
CH2
CH1
CH0
WRITE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NOP WRITE
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
SDN_DIS
WRITE
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
1
SDN_EN WRITE
(1)
(2)
D7
D6
D5
D4
D3
D2
D1
THREE-WIRE
SPI COMMAND
D15
D0
SDN = Shutdown mode. Enter Shutdown mode by issuing an SDN_EN command. Shutdown mode is cleared (returned to the last valid
write configuration) by a SDN_DIS command or by any valid Write command.
POR (power-on-reset) value of internal Gain/Channel Select Register is all 0s. This value sets Gain = 1, and Channel = VCAL/CH0.
Table 4. Gain Selection Bits (PGA112/PGA113)
G3
G2
G1
G0
BINARY GAIN
SCOPE GAIN
0
0
0
0
1
1
0
0
0
1
2
2
0
0
1
0
4
5
0
0
1
1
8
10
0
1
0
0
16
20
0
1
0
1
32
50
0
1
1
0
64
100
0
1
1
1
128
200
Table 5. MUX Channel Selection Bits (PGA112/PGA113)
(1)
(2)
(3)
(4)
(5)
22
CH3
CH2
CH1
CH0
PGA112
PGA113
0
0
0
0
VCAL/CH0
0
0
0
1
CH1
0
0
1
0
X(1)
0
0
1
1
X
0
1
0
0
X
0
1
0
1
X
0
1
1
0
X
0
1
1
1
X
1
0
0
0
X
1
0
0
1
X
1
0
1
0
Factory Reserved
1
0
1
1
X
1
1
0
0
CAL1(2)
1
1
0
1
CAL2(3)
1
1
1
0
CAL3(4)
1
1
1
1
CAL4(5)
X = channel is not used.
CAL1: connects to GND.
CAL2: connects to 0.9VCAL.
CAL3: connects to 0.1VCAL.
CAL4: connects to VREF.
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APPLICATION INFORMATION
The PGA112/PGA113 and PGA116/PGA117 are
single-ended input, single-supply, programmable gain
amplifiers with an input multiplexer. Multiplexer
channel selection and gain selection are done
through
a
standard
SPI
interface.
The
PGA112/PGA113 have a two-channel input MUX and
the PGA116/PGA117 have a 10-channel input MUX.
The PGA112 and PGA116 provide binary gain
selections (1, 2, 4, 8, 16, 32, 64, 128) and the
PGA113 and PGA117 provide scope gain selections
(1, 2, 5, 10, 20, 50, 100, 200). All models use a
split-supply architecture with an analog supply, AVDD,
and a digital supply, DVDD. This split-supply
architecture allows for ease of interface to
analog-to-digital
converters
(ADCs)
and
microcontrollers in mixed-supply voltage systems,
such as where the analog supply is +5V and the
digital supply is +3V. Four internal calibration
channels are provided for system-level calibration.
The channels are tied to GND, 0.9VCAL, 0.1VCAL, and
VREF, respectively. VCAL, an external voltage
connected to VCAL/CH0, acts as the system
calibration reference. If VCAL is the system ADC
reference, then gain and offset calibration on the
ADC are easily accomplished through the PGA using
only one MUX input. If calibration is not used, then
VCAL/CH0 can be used as a standard MUX input. All
four versions provide a VREF pin that can be tied to
ground or, for ease of scaling, to midsupply in
single-supply systems where midsupply is used as a
virtual ground. The PGA112/PGA113 offer a
software-controlled shutdown feature for low standby
power. The PGA116/PGA117 offer both hardwareand software-controlled shutdown for low standby
power. The PGA112/PGA113 have a three-wire SPI
digital interface; the PGA116/PGA117 have a
four-wire SPI digital interface. The PGA116/117 also
have daisy-chain capability.
OP AMP: INPUT STAGE
The PGA op amp is a rail-to-rail input and output
(RRIO) single-supply op amp. The input topology
uses two separate input stages in parallel to achieve
rail-to-rail input. As Figure 59 shows, there is a
PMOS transistor on each input for operation down to
ground; there is also an NMOS transistor on each
input in parallel for operation to the positive supply
rail. When the common-mode input voltage (that is,
the single-ended input, because this PGA is
configured internally for noninverting gain) crosses a
level that is typically about 1.5V below the positive
supply, there is a transition between the NMOS and
PMOS transistors. The result of this transition
appears as a small input offset voltage transition that
is reflected to the output by the selected PGA gain.
This transition may be either increasing or
decreasing, and differs from part to part as described
in Figure 60 and Figure 61. These figures illustrate
possible differences in input offset voltage between
two different devices when used with AVDD = +5V.
Because the exact transition region varies from
device to device, the Electrical Characteristics table
specifies an input offset voltage above and below this
input transition region.
AVDD
Reference
Current
VIN+
VIN-
GND
Figure 59. PGA Rail-to-Rail Input Stage
80
70
Input Offset Voltage (mV)
FUNCTIONAL DESCRIPTION
60
50
40
30
20
10
AVDD = 5V
0
0
1
2
3
4
5
6
Input Voltage (V)
Figure 60. VOS versus Input Voltage—Case 1
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50
CH0
AVDD = 5V
Input Offset Voltage (mV)
40
CH1
PGA112
PGA113
MUX
VOUT
RI
30
VIN0
VIN1
VREF
20
10
VS/2
RF
+
G=1
-
0
-10
Figure 63. PGA112/PGA113 Configuration for
Positive and Negative Excursions Around
Midsupply Virtual Ground
-20
-30
0
1
2
3
4
5
6
VOUT0 = G ´ VIN0 - AVDD/2 ´ (G - 1)
Input Voltage (V)
When: G = 1
Figure 61. VOS versus Input Voltage—Case 2
Then: VOUT0 = G × VIN0
OP AMP: GENERAL GAIN EQUATIONS
Figure 62 shows the basic configuration for using the
PGA112/113 as a gain block. VOUT/VIN is the selected
noninverting gain, depending on the model selected,
for either binary or scope gains.
PGA112
PGA113
CH1
VOUT
RI
VOUT1 = G ´ (VIN1 + AVDD/2) - AVDD/2 ´ (G - 1)
VOUT1 = G ´ VIN1 + AVDD/2, where: -AVDD/2 < G ´ VIN1 < +AVDD/2
(3)
Where:
G = 1, 2, 4, 8, 16, 32, 64, and 128 (binary gains)
G = 1, 2, 5, 10, 20, 50, 100, and 200 (scope
gains)
Table 6 details the internal typical values for the op
amp internal feedback resistor (RF) and op amp
internal input resistor (RI) for both binary and scope
gains.
VIN
VREF
(2)
RF
G=1
Table 6. Typical RF and RI versus Gain
Figure 62. PGA112/PGA113 Used as a Gain Block
VOUT = G ´ VIN
(1)
Where:
G = 1, 2, 4, 8, 16, 32, 64, and 128 (binary gains)
G = 1, 2, 5, 10, 20, 50, 100, and 200 (scope
gains)
Figure 63 shows the PGA configuration and gain
equations for VREF = AVDD/2. VOUT0 is VOUT when
CH0 is selected and VOUT1 is VOUT when CH1 is
selected. Notice the VREF pin has no effect for G = 1
because the internal feedback resistor, RF, is shorted
out. This configuration allows for positive and
negative voltage excursions around a midsupply
virtual ground.
24
Binary
Gain
(V/V)
RI (Ω)
Scope
Gain
(V/V)
RF (Ω)
1
0
RF (Ω)
RI (Ω)
3.25k
1
0
2
3.25k
3.25k
3.25k
2
3.25k
3.25k
4
9.75k
3.25k
5
13k
3.25k
8
22.75k
3.25k
10
29.25k
3.25k
16
48.75k
3.25k
20
61.75k
3.25k
32
100.75k
3.25k
50
159.25k
3.25k
64
204.75k
3.25k
100
321.75k
3.25k
128
412.75k
3.25k
200
646.75k
3.25k
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OP AMP: FREQUENCY RESPONSE VERSUS
GAIN
Table 7 documents how small-signal bandwidth and
slew rate change correspond to changes in PGA
gain.
Full power bandwidth (that is, the highest frequency
that a sine wave can pass through the PGA for a
given gain) is related to slew rate by Equation 4:
SR (V/ms) = 2pf ´ VOP (1 ´ 10-6)
(4)
Where:
SR = Slew rate in V/µs
f = Frequency in Hz
VOP = Output peak voltage in volts
Example:
For G = 8, then SR = 10.6V/µs (slew rate rise is
minimum slew rate).
For a 5V system, choose 0.1V < VOUT < 4.9V or
VOUTPP = 4.8V or VOUTP = 2.4V.
SR (V/µs) = 2πf × VOP (1 × 10–6).
10.6 = 2πf (2.4) (1 × 10–6) → f = 702.9kHz
This example shows that a G = 8 configuration
can produce a 4.8VPP sine wave with frequency
up to 702.9kHz. This computation only shows the
theoretical upper limit of frequency for this
example, but does not indicate the distortion of
the sine wave. The acceptable distortion depends
on the specific application. As a general
guideline, maintain two to three times the
calculated slew rate to minimize distortion on the
sine wave. For this example, the application
should only use G = 8, 4.8VPP, up to a frequency
range of 234kHz to 351kHz, depending upon the
acceptable distortion. For a given gain and slew
rate requirement, check for adequate small-signal
bandwidth (typical –3dB frequency) in order to
assure that the frequency of the signal can be
passed without attenuation.
ANALOG MUX
The analog input MUX provides two input channels
for the PGA112/PGA113 and 10 input channels for
the PGA116/PGA117. The MUX switches are
designed to be break-before-make and thereby
eliminate any concerns about shorting the two input
signal sources together.
Four internal MUX CAL channels are included in the
analog MUX for ease of system calibration. These
CAL channels allow ADC gain and offset errors to be
calibrated out. This calibration does not remove the
offset and gain errors of the PGA for gains greater
than 1, but most systems should see a significant
increase in the ADC accuracy. In addition, these CAL
channels can be used by the ADC to read the
minimum and maximum possible voltages from the
PGA. With these minimum and maximum levels
known, the system architecture can be designed to
indicate an out-of-range condition on the measured
analog input signals if these levels are ever
measured.
To use the CAL channels, VCAL/CH0 must be
permanently connected to the system ADC reference.
There is a typical 100kΩ load from VCAL/CH0 to
ground. Table 8 illustrates how to use the CAL
channels with VREF = ground. Table 9 describes how
to use the CAL channels with VREF = AVDD/2. The
VREF pin must be connected to a source that is
low-impedance for both dc and ac in order to
maintain gain and nonlinearity accuracy. Worst-case
current demand on the VREF pin occurs when G = 1
because there is a 3.25kΩ resistor between VOUT and
VREF. For a 5V system with AVDD/2 = 2.5V, the VREF
pin buffer must source and sink 2.5V/3.25kΩ = 0.7mA
minimum for a VOUT that can swing from ground to
+5V.
Table 7. Frequency Response versus Gain (CL = 100pF, RL= 10kΩ)
TYPICAL
–3dB
BINARY
FREQUENCY
GAIN (V/V)
(MHz)
SLEW
RATEFALL
(V/µs)
SLEW
RATERISE
(V/µs)
0.1%
0.01%
SETTLING SETTLING
TIME:
TIME:
4VPP
4VPP
(µs)
(µs)
SCOPE
GAIN
(V/V)
TYPICAL
–3dB
FREQUENCY
(MHz)
SLEW
RATEFALL
(V/µs)
SLEW
RATERISE
(V/µs)
0.1%
0.01%
SETTLING SETTLING
TIME:
TIME:
4VPP
4VPP
(µs)
(µs)
1
10
8
3
2
2.55
1
10
8
3
2
2.55
2
3.8
9
6.4
2
2.6
2
3.8
9
6.4
2
2.6
4
2
12.8
10.6
2
2.6
5
1.8
12.8
10.6
2
2.6
8
1.8
12.8
10.6
2
2.6
10
1.8
12.8
10.6
2.2
2.6
16
1.6
12.8
12.8
2.3
2.6
20
1.3
12.8
9.1
2.3
2.8
32
1.8
12.8
13.3
2.3
3
50
0.9
9.1
7.1
2.4
3.8
64
0.6
4
3.5
3
6
100
0.38
4
3.5
4.4
7
128
0.35
2.5
2.5
4.8
8
200
0.23
2.3
2
6.9
10
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+3V
+3V
CBYPASS
0.1mF
CBYPASS
0.1mF
CBYPASS
0.1mF
AVDD
DVDD
REF3225
PGA112
PGA113
VCAL/CH0
MUX
VOUT
Output
Stage
CH1
2.5V
ADC Ref
ADC
CAL1
10kW
RF
G=1
0.9VCAL
0.1VCAL
80kW
MSP430
Microcontroller
CAL2
CAL3
10kW
RI
VREF
CAL4
SCLK
DIO
SPI
Interface
CAL2/3
CS
VREF
GND
Figure 64. Using CAL Channels with VREF = Ground
Table 8. Using the MUX CAL Channels with VREF = GND
(AVDD = 3V, DVDD = 3V, ADC Ref = 2.5V, and VREF = GND)
26
FUNCTION
MUX
SELECT
GAIN
SELECT
MUX INPUT
OP AMP
(+In)
OP AMP
(VOUT)
DESCRIPTION
Minimum Signal
CAL1
1
GND
GND
50mV
Minimum signal level that the
MUX, op amp, and ADC can
read. Op amp VOUT is limited
by negative saturation.
Gain Calibration
CAL2
1
0.9 ×
(VCAL/CH0)
2.25V
2.25V
90% ADC Ref for system
full-scale or gain calibration
of the ADC.
Maximum Signal
CAL2
2
0.9 ×
(VCAL/CH0)
2.25V
2.95V
Maximum signal level that
the MUX, op amp, and ADC
can read. Op amp VOUT is
limited by positive saturation.
System is limited by ADC
max input of 2.5V (ADC Ref
= 2.5V).
Offset Calibration
CAL3
1
0.1 ×
(VCAL/CH0)
0.25V
0.25V
10% ADC Ref for system
offset calibration of the ADC.
Minimum Signal
CAL4
1
VREF
GND
50mV
Minimum signal level that the
MUX, op amp, and ADC can
read. Op amp VOUT is limited
by negative saturation.
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+3V
+3V
CBYPASS
0.1mF
AVDD
CBYPASS
0.1mF
CBYPASS
0.1mF
DVDD
PGA112
PGA113
VCAL/CH0
ADC Ref
MUX
CAL1
10kW
MSP430
Microcontroller
CAL2
0.1VCAL
CAL3
80kW
ADC
RF
G=1
0.9VCAL
VOUT
Output
Stage
CH1
RI
VREF
CAL4
SCLK
SPI
Interface
CAL2/3
10kW
DIO
CS
VREF
GND
RF
10kW
CF
2.7nF
+3V
CBYPASS
0.1mF
+3V
RX
100kW
RY
100kW
(1.5V)
OPA364
CL2
0.1mF
0.1mF
Figure 65. Using CAL Channels with VREF = AVDD/2
Table 9. Using the MUX CAL Channels with VREF = AVDD/2
(AVDD = 3V, DVDD = 3V, ADC Ref = 3V, and VREF = 1.5V)
FUNCTION
MUX
SELECT
GAIN
SELECT
MUX INPUT
OP AMP
(+In)
OP AMP
(VOUT)
DESCRIPTION
Minimum Signal
CAL1
1
GND
GND
50mV
Minimum signal level that the MUX,
op amp, and ADC can read. Op amp
VOUT is limited by negative saturation.
Gain Calibration
CAL2
1
0.9 ×
(VCAL/CH0)
2.7V
2.7V
90% ADC Ref for system full-scale or
gain calibration of the ADC.
Maximum Signal
CAL2
4 or 5
0.9 ×
(VCAL/CH0)
2.25V
2.95V
Maximum signal level that the MUX,
op amp, and ADC can read. Op amp
VOUT is limited by positive saturation.
Offset Calibration
CAL3
1
0.1 ×
(VCAL/CH0)
0.3V
0.3V
10% ADC Ref for system offset
calibration of the ADC.
VREF Check
CAL4
1
VREF
1.5V
1.5V
Midsupply voltage used as VREF.
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SYSTEM CALIBRATION USING THE
PGA112/PGA113
Analog-to-digital converters (ADCs) contain two major
errors that can be easily removed by calibration at a
system level. These errors are gain error and offset
error, as shown in Figure 66. Figure 66 shows a
typical transfer function for a 12-bit ADC. The analog
input is on the x-axis with a range from 0V to
(VREF_ADC – 1LSB), where VREF_ADC is the ADC
reference voltage. The y-axis is the hexadecimal
equivalent of the digital codes that result from ADC
conversions. The dotted red line represents an ideal
transfer function with 0000h representing 0V analog
input and 0FFFh representing an analog input of
(VREF_ADC – 1LSB). The solid blue line illustrates the
offset error. Although the solid blue line includes both
offset error and gain error, at an analog input of 0V
the offset error voltage, VZ_ACTUAL, can be measured.
The dashed black line represents the transfer function
with gain error. The dashed black line is equivalent to
the solid blue line without the offset error, and can be
measured and computed using VZ_ACTUAL and
VZ_IDEAL. The difference between the dashed black
line and the dotted red line is the gain error. Gain and
offset error can be computed by taking zero input and
full-scale input readings. Using these error
calculations, compute a calibrated ADC reading to
remove the ADC gain and offset error.
VFS_ACTUAL
Gain Error
0FFFh
In practice, the zero input (0V) or full-scale input
(VREF_ADC – 1LSB) of ADCs cannot always be
measured because of internal offset error and gain
error. However, if measurements are made very close
to the full-scale input and the zero input, both zero
and full-scale can be calibrated very accurately with
the assumption of linearity from the calibration points
to the desired end points of the ADC ideal transfer
function. For the zero calibration, choose
10%VREF_ADC; this value should be above the internal
offset error and sufficiently out of the noise floor
range of the ADC. For the gain calibration, choose
90%VREF_ADC; this value should be less than the
internal gain error and sufficiently below the tolerance
of VREF. These key points can be summarized in this
way:
For zero calibration:
• The ADC cannot read the ideal zero because of
offset error
• Must be far enough above ground to be above
noise floor and ADC offset error
• Therefore, choose 10%VREF_ADC for zero
calibration
For gain calibration:
• The ADC cannot read the ideal full-scale because
of gain error
• Must be far enough below full-scale to be below
the VREF tolerance and ADC gain error
• Therefore, choose 90%VREF_ADC for gain
calibration
VFS_IDEAL
Transfer Function
with Offset Error + Gain Error
Id
ea
lT
ra
ns
fe
rF
un
ct
io
n
Digital Output
Transfer Function
with Gain Error Only
VZ_ACTUAL
0000h
VZ_IDEAL
Offset Error
0V
Analog Input
VREF_ADC - 1LSB
Figure 66. ADC Offset and Gain Error
28
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The 12-bit ADC example in Figure 67 illustrates the
technique for calibrating an ADC using a
10%VREF_ADC and 90%VREF_ADC reading where
VREF_ADC is the ADC reference voltage. Note that the
10%VREF reading also contains a gain error because
it is not a VIN = 0 calibration point. First, use the
90%VREF and 10%VREF points to compute the
measured gain error. The measured gain error is then
used to remove the gain error from the 10%VREF
reading, giving a measured 10%VREF number. The
measured 10%VREF number is used to compute the
measured offset error.
VREF = +5V
Offset Error = +4LSB
Gain Error = +6LSB
Digital Output (VAD_MEAS)
0FFFh (4.99878V)
(4.5114751443V)
(5)
VREF10 = 0.1(VREF_ADC)
(6)
VMEAS90 = ADCMEASUREMENT at VREF90
(7)
VMEAS10 = ADCMEASUREMENT at VREF10
(8)
2. Compute the ADC measured gain. The slope of
the curve connecting the measured 10%VREF and
measured 90%VREF point is computed and
compared to the slope between the ideal
10%VREF and ideal 90%VREF. This result is the
measured gain.
VMEAS90 - VMEAS10
GMEAS =
VREF90 - VREF10
(9)
3. Compute the ADC measured offset.
measured offset is computed by taking
difference between the measured 10%VREF
the (ideal 10%VREF) × (measured gain).
OMEAS = VMEAS10 - (VREF10 ´ GMEAS)
rF
un
ct
io
n
Transfer Function
with Offset Error + Gain Error
VREF90 = 0.9(VREF_ADC)
Id
ea
lT
ra
ns
fe
4. Compute the calibrated ADC readings.
VAD_MEAS = Any VIN ADCMEASUREMENT
VADC_CAL =
(0.5056191443V)
0000h (0V)
0V
0.5V
(0.1 ´ VREF_ADC)
VIN
4.5V
(0.9 ´ VREF_ADC)
4.99878V
(VREF_ADC - 1LSB)
Figure 67. 12-Bit Example of ADC Calibration for
Gain and Offset Error
The gain error and offset error in ADC readings can
be calibrated
by
using
10%VREF_ADC and
90%VREF_ADC calibration points. Because the
calibration is ratiometric to VREF_ADC, the exact value
of VREF_ADC does not need to be known in the end
application.
Follow these steps to compute a calibrated ADC
reading:
1. Take the ADC reading at VIN = 90% × VREF and
VIN = 10% × VREF. The ADC readings for
10%VREF and 90%VREF are taken.
The
the
and
(10)
(11)
VAD_MEAS - OMEAS
GMEAS
(12)
Any ADC reading can therefore be calibrated by
removing the gain error and offset error. The
measured offset is subtracted from the ADC reading
and then divided by the measured gain to give a
corrected reading. If this calibration is performed on a
timed basis, relative to the specific application, gain
and offset error over temperature are also removed
from the ADC reading by calibration.
For example; given:
• 12-Bit ADC
• ADC Gain Error = +6LSB
• ADC Offset Error = +4LSB
• ADC Reference (VREF_ADC) = +5V
• Temperature = +25°C
Table 10 shows the resulting system accuracy.
Table 10. Bits of System Accuracy (1) (to 0.5LSB)
(1)
VIN
ADC ACCURACY WITHOUT
CALIBRATION
ADC ACCURACY WITH PGA112
CALIBRATION
10%VREF_ADC
8.80 Bits
12.80 Bits
90%VREF_ADC
7.77 Bits
11.06 Bits
Difference in maximum input offset voltage for VIN = 10%VREF_ADC and VIN = 90%VREF_ADC is the reason for different accuracies.
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APPLICATIONS: GENERAL-PURPOSE INPUT
SCALING
Figure 68 is an example application that
demonstrates the flexibility of the PGA for
general-purpose input scaling. VIN0 is a ±100mV input
that is ac-coupled into CH0. The PGA112/PGA113 is
powered from a +5V supply voltage, VS, and
configured with the VREF pin connected to VS/2
(+2.5V). VCH0 is the ±100mV input, level-shifted and
centered on VS/2 (+2.5V). A gain of 20 is applied to
CH0, and because of the PGA113 configuration, the
output voltage at VOUT is ±2V centered on VS/2
(+2.5V).
Table 11 summarizes the scaling resistor values for
RA, RX, and RB for different ADC Ref voltages.
VREF_ADC is the reference voltage used for the ADC
connected to the PGA112/PGA113 output. It is
assumed the ADC input range is 0V to VREF_ADC. The
Bipolar Input to Single-Supply Scaling section gives
the algorithm to compute resistor values for
references not listed in Table 11. As a general
guideline, RB should be chosen such that the input
on-channel current multiplied by RB is less than or
equal to the input offset voltage. This value ensures
that the scaling network contributes no more error
than the input offset voltage. Individual applications
may require other design trade-offs.
CH1 is set to G = 1; through a resistive divider and
scalar network, we can read ±5V or 0V. This setting
provides bipolar to single-ended input scaling.
VCH0
VIN0
+2.6V
+100mV
+2.5V
0
+2.4V
CA
-100mV
VIN0
200mVPP
PGA112
PGA113
CH0
RA
+4.5V
+2.5V
AVDD
MUX
CH1
VOUT0
VS
(+5V)
DVDD
RI
+0.5V
VOUT
G = 20
VREF
VOUT1
RF
VREF_ADC
RX
VS/2
(+2.5V)
+4.9625V
+
+37.5mV
G=1
RA
VIN1
RB
Figure 68. General-Purpose Input Scaling
30
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Table 11. Bipolar to Single-Ended Input Scaling (1) (2)
VREF_ADC (V)
VIN1 (V)
CH1 INPUT
RA (kΩ)
RX (Ω)
RB (kΩ)
2.5
–5
0.047613
9.2
4.81k
10
0
1.247613
3.16
2.4k
10
13.5
5.76k
10
4.02
2.87k
10
37
7.87k
10
6.49
3.92k
10
24
965
10
9.2
4.81k
10
2.5
3
3
4.096
4.096
5
5
(1)
(2)
5
2.447613
–10
0.050317
0
1.250317
10
2.450317
–5
0.058003
0
1.498003
5
2.938003
–10
0.059303
0
1.499303
10
2.939303
–5
0.082224
0
2.048304
5
4.014384
–10
0.086018
0
2.052098
10
4.018178
–5
0.093506
0
2.493506
5
4.893506
–10
0.095227
0
2.495227
10
4.895227
Scaling is based on 0.02(VREF_ADC) to 0.98(VREF_ADC), using standard 0.1% resistor values.
Assumes symmetrical VIN and symmetrical scaling for CH1 input minimum and maximum.
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Bipolar Input to Single-Supply Scaling
Note that this process assumes a symmetrical VIN1
and that symmetrical scaling is used for CH1 input
minimum and maximum values. The following steps
give the algorithm to compute resistor values for
references not listed in Table 11.
Step 1: Choose the following:
a. VREF_ADC = 2.5V (ADC reference voltage)
b. | VIN1 | = 5
(magnitude of VIN, assuming scaling is for ±VIN1)
c. Choose RB as a standard resistor value. The
input on-channel current multiplied by RB should
be less than the input offset voltage, such that RB
is not a major source of inaccuracy.
RB = 10kΩ (select as a starting value for
resistors)
d. For the most negative VIN1, choose the
percentage (in decimal format) of VREF_ADC
desired at the ADC input.
RA =
kVO+ = 1 – kVO–
kVO+ = 1 – 0.02 = 0.98
(CH1 input = kVO+ × VREF_ADC when VIN1 = +VIN1)
Step 2: Compute the following:
a. To simplify analysis, create one constant called
kVO.
kVO = kVO+ - kVO0.96 = 0.98 - 0.02
b. A constant, g, is created to simplify resistor value
computations.
kVO ´ VREF_ADC
g=
2 ´ |VIN1| - kVO ´ VREF_ADC
1-g
2 ´ 10kW ´ 0.315789474
1 - 0.315789474
d. RX can now be computed from the starting value
of RB and the computed value for RA.
RB ´ RA
RX =
R B + RA
9.23077kW =
4.81kW =
10kW ´ 9.23077kW
10kW + 9.23077kW
VREF_ADC
(2.5V)
+
RB
10kW
VIN1
(+5V, -5V)
kVO– = 0.02
(CH1 input = kVO– × VREF_ADC when VIN1 = –VIN1)
e. For the most positive VIN1, choose the percentage
(in decimal format) of VREF_ADC desired at the
ADC input. Since this scaling is based on
symmetry, kVO+ must be the same percentage
away from VREF_ADC at the upper limit as at the
lower limit where kVO– is computed.
2 ´ RB ´ g
RX
4.81kW
CH1 Input
(2.447817V,
0.0474093V)
RA
9.2kW
Figure 69. Bipolar to Single-Ended Input
Algorithm
APPLICATIONS: HIGH GAIN/WIDE
BANDWIDTH CONSIDERATIONS
As a result of the combination of wide bandwidth and
high gain capability of the PGA112/PGA113 and
PGA116/PGA117, there are several printed circuit
board (PCB) design and system recommendations to
consider for optimum application performance.
1. Power-supply
bypass.
Bypass
each
power-supply pin separately. Use a ceramic
capacitor
connected
directly
from
the
power-supply pin to the ground pin of the IC on
the same PCB plane. Vias can then be used to
connect to ground and voltage planes. This
configuration keeps parasitic inductive paths out
of the local bypass for the PGA. Good analog
design practice dictates the use of a large value
tantalum bypass capacitor on the PCB for each
respective voltage.
0.96 ´ 2.5
2 ´ 5 - 0.96 ´ 2.5
c. RA is now selected from the starting value of RB
and the g constant.
0.315789474 =
32
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2. Signal trace routing. Keep VOUT and other low
impedance traces away from MUX channel inputs
that are high impedance. Poor signal routing can
cause positive feedback, unwanted oscillations,
or excessive overshoot and ringing on
step-changing signals. If the input signals are
particularly noisy, separate MUX input channels
with guard traces on either side of the signal
traces. Connect the guard traces to ground near
the PGA and at the signal entry point into the
PCB. On multilayer PCBs, ensure that there are
no parallel traces near MUX input traces on
adjacent layers; capacitive coupling from other
layers can be a problem. Use ground planes to
isolate MUX input signal traces from signal traces
on other layers.
Bypass capacitors greater than 100pF are
recommended. Lower impedances and a bypass
capacitor placed directly at the input MUX
channels keep crosstalk between channels to a
minimum as a result of parasitic capacitive
coupling from adjacent PCB traces and pin-to-pin
capacitance.
APPLICATIONS: DRIVING/INTERFACING TO
ADCS
CDAC SAR ADCs contain an input sampling
capacitor, CSH, to sample the input signal during a
sample period as shown in Figure 70. After the
sample period, CSH is removed from the input signal.
Subsequent comparisons of the charge stored on CSH
are performed during the ADC conversion process.
To achieve optimal op amp stability, input signal
settling, and the demands for charge from the input
signal conditioning circuitry, most ADC applications
are optimized by the use of a resistor (RFILT) and
capacitor (CFILT) filter placed between the op amp
output and ADC input. For the PGA112/PGA113,
setting CFILT = 1nF and RFILT = 100Ω yields optimum
system performance for sampling converters
operating at speeds up to 500kHz, depending upon
the application settling time and accuracy
requirements.
Additionally, group and route the digital signals
into the PGA as far away as possible from the
analog MUX input signals. Most digital signals
are fast rise/fall time signals with low-impedance
drive capability that can easily couple into the
high-impedance inputs of the input MUX
channels. This coupling can create unwanted
noise that gains up to VOUT.
3. Input MUX channels and source impedance.
Input MUX channels are high-impedance; when
combined with high gain, the channels can pick
up unwanted noise. Keep the input signal
sources low-impedance (< 10kΩ). Also, consider
bypassing input MUX channels with a ceramic
bypass capacitor directly at the MUX input pin.
+3V
+5V
CBYPASS
0.1mF
CBYPASS
0.1mF
AVDD
DVDD
1
VCAL/CH0
CH1
3
CBYPASS
0.1mF
10
PGA112
PGA113
(MSOP-10)
MUX
2
Output
Stage
5
VOUT
RFILT
100W
CFILT
(1nF)
CAL1
10kW
0.9VCAL
0.1VCAL
80kW
CDAC SAR
ADC
CAL3
CAL4
10kW
RF
G=1
CAL2
CSH
40pF
VREF
RI
SPI
Interface
CAL2/3
6
4
GND
VREF
7
SCLK
8
DIO
9
CS
12-Bit Settling ® 500kHz
16-Bit Settling ® 300kHz
Figure 70. Driving/Interfacing to ADCs
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POWER SUPPLIES
At initial power-on, the state of the PGA is G = 1 and
Channel 0 active. CAUTION: For most applications,
set AVDD ≥ DVDD to prevent VOUT from driving
current into AVDD and raising the voltage level of
AVDD.
Figure 71 shows a typical mixed-supply voltage
system where the analog supply, AVDD, is +5V and
the digital supply voltage, DVDD, is +3V. The analog
output stage of the PGA and the SPI interface digital
circuitry are both powered from DVDD. When
considering the power required for DVDD, use the
Electrical Characteristics table and add any load
current anticipated on VOUT; this load current must be
provided by DVDD. This split-supply architecture
ensures
compatible
logic
levels
with
the
microcontroller. It also ensures that the PGA output
cannot run the input for the onboard ADC into an
overvoltage condition; this condition could cause
device latch-up and system lock-up, and require
power-supply sequencing. Each supply pin should be
individually bypassed with a 0.1µF ceramic capacitor
directly at the device to ground. If there is only one
power supply in the system, AVDD and DVDD can both
be connected to the same supply; however, it is
recommended to use individual bypass capacitors
directly at each respective supply pin to a single point
ground. VOUT is diode-clamped to AVDD (as shown in
Figure 71); therefore, set DVDD less than or equal to
AVDD + 0.3V. DVDD and AVDD must be within the
operating voltage range of +2.2V to +5.5V.
SHUTDOWN AND POWER-ON-RESET (POR)
The PGA112/PGA113 have a software shutdown
mode, and the PGA116/PGA117 offer both a
hardware and software shutdown mode. When the
PGA is shut down, it goes into a low-power standby
mode. The Electrical Characteristics table details the
current draw in shutdown mode with and without the
SPI interface being clocked. In shutdown mode, RF
and RI remain connected between VOUT and VREF.
When DVDD is less than 1.6V, the digital interface is
disabled and the channel and gain selections are
held to the respective POR states of Gain = 1 and
Channel = VCAL/CH0. When DVDD is above 1.8V, the
digital interface is enabled and the POR gain and
channel states remain unchanged until a valid SPI
communication is received.
+3V
+5V
VCAL/CH0
CH1
3
AVDD
DVDD
1
10
PGA112
PGA113
(MSOP-10)
MSP430
Microcontroller
MUX
2
Output
Stage
5
VOUT
ADC
CAL1
10kW
0.9VCAL
0.1VCAL
80kW
RF
G=1
CAL2
CAL3
CAL4
10kW
VREF
RI
SPI
Interface
CAL2/3
6
4
GND
VREF
7
SCLK
8
DIO
9
CS
Figure 71. Split Power-Supply Architecture: AVDD ≠ DVDD
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PACKAGE OPTION ADDENDUM
www.ti.com
31-Mar-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
PGA112AIDGSR
ACTIVE
MSOP
DGS
10
2500
TBD
Call TI
Call TI
PGA112AIDGST
ACTIVE
MSOP
DGS
10
250
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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