ETC LXT9785BC

LXT9785
Advanced 10/100 8-Port PHY
Datasheet
The LXT9785 is an 8-port Fast Ethernet PHY Transceiver that supports IEEE 802.3 physical
layer applications at both 10Mbps and 100Mbps. This device provides both Serial/Source
Synchronous (SMII/SS-SMII) and Reduced Media Independent (RMII) Interfaces for switching
and other independent port applications.
All network ports provide a combination twisted-pair (TP) or pseudo-ECL (PECL) interface for
both 10Mbps or 100Mbps (10BASE-T and 100BASE-TX) Ethernet over twisted-pair, or
100Mbps (100BASE-FX) Ethernet over fiber-optic media .
The LXT9785 provides three discrete LED driver outputs for each port. The device supports
both half-duplex and full-duplex operation at 10Mbps and 100Mbps and requires only a single
2.5V power supply.
Applications
■
10BASE-T, 10/100BASE-TX, or
100BASE-FX Switches and multi-port
NICs.
Product Features
■
■
■
■
■
■
■
Eight IEEE 802.3-compliant 10BASE-T or
100BASE-TX ports with integrated filters.
2.5V operation.
Optimized for dual-high stacked RJ-45
applications.
Proprietary Optimal Signal Processing™
architecture improves SNR by 3 dB over
ideal analog filters.
Robust baseline wander correction.
100BASE-FX fiber-optic capability on all
ports.
Supports both auto-negotiation systems and
legacy systems without auto-negotiation
capability.
■
■
■
■
■
■
■
JTAG boundary scan.
Multiple RMII or SMII/SS-SMII ports for
independent PHY port operation.
Configurable via MDIO port or external
control pins.
Low power consumption; 250 mW per port
typical.
Auto MDIX crossover capabilities.
208-pin PQFP and 241-pin BGA packages.
MDIO sectionalization into 2x4 or 1x8
configurations.
As of January 15, 2001, this document replaces the Level One document
known as LXT9785 Advanced 10/100 8-Port PHY Datasheet.
Order Number: 249241-002
January 2001
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXT9785 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Contents
1.0
Pin Assignments and Signal Descriptions ....................................................12
1.1
2.0
Functional Description...........................................................................................51
2.1
2.2
2.3
2.4
2.5
2.6
Datasheet
Signal Name Conventions...................................................................................39
Introduction..........................................................................................................51
2.1.1 OSP™ Architecture ................................................................................51
2.1.2 Comprehensive Functionality .................................................................51
2.1.2.1 Sectionalization .........................................................................52
Interface Descriptions..........................................................................................52
2.2.1 10/100 Network Interface .......................................................................52
2.2.1.1 Twisted-Pair Interface ...............................................................53
2.2.1.2 MDI Crossover (MDIX) ..............................................................53
2.2.1.3 Fiber Interface ...........................................................................53
Media Independent Interface (MII) Interfaces .....................................................53
2.3.1 Global MII Mode Select ..........................................................................54
2.3.2 Internal Loopback...................................................................................54
2.3.3 RMII Data Interface ................................................................................54
2.3.4 Serial Media Independent Interface (SMII) and Source Synchronous Data
Interfaces54
2.3.4.1 SMII Interface ............................................................................54
2.3.4.2 Source Synchronous Interface ..................................................55
2.3.5 Configuration Management Interface .....................................................55
2.3.6 MII Isolate...............................................................................................55
2.3.6.1 MDIO Management Interface ....................................................55
2.3.6.2 MII Sectionalization ...................................................................57
2.3.6.3 MII Interrupts .............................................................................57
2.3.6.4 Hardware Control Interface .......................................................57
Operating Requirements .....................................................................................58
2.4.1 Power Requirements..............................................................................58
2.4.2 Clock/SYNC Requirements ....................................................................58
2.4.2.1 Reference Clock ........................................................................58
2.4.2.2 TxClk Signal (SS-SMII only) ......................................................58
2.4.2.3 TxSYNC Signal (SMII/SS-SMII) ................................................58
2.4.2.4 RxSYNC Signal (SS-SMII only).................................................58
2.4.2.5 RxCLK Signal (SS-SMII only)....................................................58
Initialization..........................................................................................................59
2.5.1 MDIO Control Mode ...............................................................................59
2.5.2 Hardware Control Mode .........................................................................59
2.5.3 Power-Down Mode.................................................................................60
2.5.3.1 Global (Hardware) Power Down................................................60
2.5.3.2 Port (Software) Power Down .....................................................61
2.5.4 Reset ......................................................................................................61
2.5.5 Hardware Configuration Settings ...........................................................62
Link Establishment ..............................................................................................62
2.6.1 Auto-Negotiation.....................................................................................62
2.6.1.1 Base Page Exchange................................................................62
2.6.1.2 Next Page Exchange.................................................................62
3
LXT9785 — Advanced 10/100 8-Port PHY
2.7
2.8
2.9
2.10
2.11
3.0
Application Information ......................................................................................... 88
3.1
3.2
4
2.6.1.3 Controlling Auto-Negotiation ..................................................... 63
2.6.1.4 Link Criteria ............................................................................... 63
2.6.1.5 Parallel Detection ...................................................................... 63
Serial MII Operation ............................................................................................ 64
2.7.1 SMII Reference Clock ............................................................................ 67
2.7.2 TxSYNC Pulse (SMII/SS-SMII) .............................................................. 67
2.7.3 Transmit Data Stream ............................................................................ 67
2.7.3.1 Transmit Enable ........................................................................ 67
2.7.3.2 Transmit Error ........................................................................... 67
2.7.4 Receive Data Stream ............................................................................. 68
2.7.4.1 Carrier Sense ............................................................................ 68
2.7.4.2 Receive Data Valid.................................................................... 68
2.7.4.3 Receive Error ............................................................................ 68
2.7.4.4 Receive Status Encoding .......................................................... 68
2.7.5 Collision.................................................................................................. 68
2.7.5.1 Source Synchronous SMII......................................................... 70
RMII Operation.................................................................................................... 74
2.8.1 RMII Reference Clock ............................................................................ 74
2.8.2 Transmit Enable ..................................................................................... 74
2.8.3 Carrier Sense & Data Valid .................................................................... 74
2.8.4 Receive Error ......................................................................................... 74
2.8.5 Out-of-Band Signalling ........................................................................... 74
2.8.6 4B/5B Coding Operations ...................................................................... 74
100Mbps Operation............................................................................................. 78
2.9.1 100BASE-X Network Operations ........................................................... 78
2.9.2 100BASE-X Protocol Sublayer Operations ............................................ 78
2.9.2.1 PCS Sublayer............................................................................ 78
2.9.3 PMA Sublayer ........................................................................................ 80
2.9.3.1 Twisted-Pair PMD Sublayer ...................................................... 82
2.9.3.2 Fiber PMD Sublayer .................................................................. 82
10Mbps Operation............................................................................................... 83
2.10.1 Preamble Handling................................................................................. 83
2.10.2 Dribble Bits............................................................................................. 83
2.10.3 Link Test................................................................................................. 83
2.10.3.1Link Failure................................................................................ 84
2.10.4 Jabber .................................................................................................... 84
Monitoring Operations......................................................................................... 84
2.11.1 Monitoring Auto-Negotiation................................................................... 84
2.11.2 Per-Port LED Driver Functions............................................................... 84
2.11.3 Out-of-Band Signalling ........................................................................... 85
2.11.4 Boundary Scan Interface........................................................................ 86
2.11.5 State Machine ........................................................................................ 86
2.11.6 Instruction Register ................................................................................ 86
2.11.7 Boundary Scan Register ........................................................................ 87
Design Recommendations .................................................................................. 88
General Design Guidelines ................................................................................. 88
3.2.1 Power Supply Filtering ........................................................................... 88
3.2.2 Power and Ground Plane Layout Considerations .................................. 89
3.2.2.1 Chassis Ground......................................................................... 89
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
3.2.3
3.2.4
3.3
MII Terminations.....................................................................................89
Twisted-Pair Interface ............................................................................90
3.2.4.1 Magnetics Information ...............................................................90
3.2.5 The Fiber Interface .................................................................................90
3.2.6 LED Circuit .............................................................................................90
Typical Application Circuits .................................................................................92
4.0
Test Specifications ..................................................................................................94
5.0
Register Definitions...............................................................................................119
6.0
Package Specifications .......................................................................................136
Datasheet
5
LXT9785 — Advanced 10/100 8-Port PHY
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
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32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
6
LXT9785 Block Diagram ..................................................................................... 11
LXT9785 RMII 208-Pin PQFP Assignments ....................................................... 12
LXT9785 SMII 208-Pin PQFP Assignments ....................................................... 13
LXT9785 SS-SMII 208-Pin PQFP Assignments ................................................. 14
LXT9785 RMII 241-Ball PBGA Assignments ...................................................... 15
LXT9785 SMII 241-Ball PBGA Assignments ...................................................... 16
LXT9785 SS-SMII 241-Ball PBGA Assignments ................................................ 17
LXT9785 Interfaces............................................................................................. 52
Internal Loopback................................................................................................ 54
Management Interface Read Frame Structure.................................................... 56
Management Interface Write Frame Structure.................................................... 56
Port Address Scheme ......................................................................................... 56
Interrupt Logic ..................................................................................................... 57
Initialization Sequence ........................................................................................ 60
Auto-Negotiation Operation................................................................................. 63
Typical SMII Interface Diagram........................................................................... 65
Typical SMII Quad Sectionalization Diagram...................................................... 66
100Mbps Serial MII Data Flow ............................................................................ 67
Serial MII Transmit Synchronization ................................................................... 68
Serial MII Receive Synchronization .................................................................... 69
Typical SS-SMII Interface Diagram..................................................................... 71
Typical SS-SMII Quad Sectionalization Diagram................................................ 72
Source Synchronous Transmit Timing ................................................................ 73
Source Synchronous Receive Timing ................................................................. 73
RMII Data Flow ................................................................................................... 75
Typical RMII Interface Diagram........................................................................... 76
Typical RMII Quad Sectionalization Diagram...................................................... 77
100BASE-X Frame Format ................................................................................. 78
Protocol Sublayers .............................................................................................. 79
LED Pulse Stretching .......................................................................................... 85
RMII Programmable Out-of-Bank Signaling........................................................ 86
LED Circuit .......................................................................................................... 91
Power and Ground Supply Connections ............................................................. 92
Typical Twisted-Pair Interface............................................................................. 93
Typical Fiber Interface......................................................................................... 93
SMII - 100BASE-TX Receive Timing .................................................................. 98
SMII - 100BASE-TX Transmit Timing ................................................................. 99
SMII - 100BASE-FX Receive Timing ................................................................ 100
SMII - 100BASE-FX Transmit Timing ............................................................... 101
SMII - 10BASE-T Receive Timing..................................................................... 102
SMII - 10BASE-T Transmit Timing.................................................................... 103
Source Synchronous SMII 100BASE-TX Receive Timing ................................ 104
Source Synchronous SMII 100BASE-TX Transmit Timing ............................... 105
Source Synchronous SMII - 100BASE-FX Receive Timing .............................. 106
Source Synchronous SMII - 100BASE-FX Transmit Timing ............................. 107
Source Synchronous SMII - 10BASE-T Receive Timing .................................. 108
Source Synchronous SMII - 10BASE-T Transmit Timing ................................. 109
RMII - 100BASE-TX Receive Timing ................................................................ 110
RMII - 100BASE-TX Transmit Timing ............................................................... 111
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
50
51
52
53
54
55
56
57
58
59
60
61
62
RMII - 100BASE-FX Receive Timing ................................................................112
RMII - 100BASE-FX Transmit Timing ...............................................................113
RMII - 10BASE-T Receive Timing.....................................................................114
RMII - 10BASE-T Transmit Timing....................................................................115
Auto-Negotiation and Fast Link Pulse Timing ...................................................116
Fast Link Pulse Timing ......................................................................................116
MDIO Write Timing (MDIO Sourced by MAC)...................................................117
MDIO Read Timing (MDIO Sourced by PHY) ...................................................117
Power-Up Timing...............................................................................................118
Reset Recovery Timing .....................................................................................118
PHY Identifier Bit Mapping ................................................................................122
LXT9785 208-Pin PQFP Plastic Package Specification....................................136
LXT9785 241-Ball PBGA Package Specification (LXT9785BC) .......................137
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
RMII PQFP Pin List .............................................................................................18
SMII PQFP Pin List .............................................................................................25
SS-SMII PQFP Pin List .......................................................................................32
LXT9785 RMII Signal Descriptions .....................................................................39
LXT9785 SMII / SS-SMII Common Signal Descriptions......................................41
LXT9785 SMII Specific Signal Descriptions ........................................................41
LXT9785 SS-SMII Specific Signal Descriptions ..................................................42
MDIO Control Interface Signals...........................................................................43
LXT9785 Signal Detect .......................................................................................44
LXT9785 Network Interface Signal Descriptions.................................................44
LXT9785 JTAG Test Signal Descriptions............................................................45
LXT9785 Miscellaneous Signal Descriptions ......................................................46
LXT9785 LED Signal Descriptions ......................................................................48
LXT9785 Power Supply Signal Descriptions.......................................................49
Unused / Reserved Pins......................................................................................50
MDIX Selection....................................................................................................53
MII Mode Select ..................................................................................................54
Global Hardware Configuration Settings .............................................................62
SMII Signal Summary..........................................................................................64
RX Status Encoding Bit Definitions .....................................................................69
Source Synchronous SMII..................................................................................70
4B/5B Coding ......................................................................................................80
BSR Mode of Operation ......................................................................................87
Supported JTAG Instructions ..............................................................................87
Magnetics Requirements.....................................................................................91
Absolute Maximum Ratings.................................................................................94
Operating Conditions...........................................................................................94
Digital I/O Characteristics (VCCIO = 2.5V +/- 5%) ..............................................95
Digital I/O Characteristics (VCCIO = 3.3V +/- 5%) ..............................................96
Required Clock Characteristics ...........................................................................96
100BASE-TX Transceiver Characteristics ..........................................................96
100BASE-FX Transceiver Characteristics ..........................................................97
10BASE-T Transceiver Characteristics...............................................................97
SMII - 100BASE-TX Receive Timing Parameters ...............................................98
Tables
Datasheet
7
LXT9785 — Advanced 10/100 8-Port PHY
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
8
SMII - 100BASE-TX Transmit Timing Parameters .............................................. 99
SMII - 100BASE-FX Receive Timing Parameters ............................................. 100
SMII - 100BASE-FX Transmit Timing Parameters ............................................ 101
SMII - 10BASE-T Receive Timing Parameters ................................................. 102
SMII-10BASE-T Transmit Timing Parameters .................................................. 103
Source Synchronous SMII 100BASE-TX Receive Timing Parameters............. 104
Source Synchronous SMII 100BASE-TX Transmit Timing ............................... 105
Source Synchronous SMII - 100BASE-FX Receive Timing Parameters .......... 106
Source Synchronous SMII - 100BASE-FX Transmit Timing Parameters ......... 107
Source Synchronous SMII - 10BASE-T Receive Timing Parameters ............... 108
Source Synchronous SMII - 10BASE-T Transmit Timing Parameters.............. 109
RMII - 100BASE-TX Receive Timing Parameters............................................. 110
RMII - 100BASE-TX Transmit Timing Parameters............................................ 111
RMII - 100BASE-FX Receive Timing Parameters............................................. 112
RMII - 100BASE-FX Transmit Timing Parameters............................................ 113
RMII - 10BASE-T Receive Timing Parameters ................................................. 114
RMII - 10BASE-T Transmit Timing Parameters ................................................ 115
Auto-Negotiation and Fast Link Pulse Timing Parameters ............................... 116
MDIO Timing Parameters ................................................................................. 117
Power-Up Timing Parameters.......................................................................... 118
Reset Recovery Timing Parameters ................................................................. 118
Register Set ...................................................................................................... 119
Control Register (Address 0)............................................................................. 120
Status Register (Address 1) .............................................................................. 121
PHY Identification Register 1 (Address 2)......................................................... 122
PHY Identification Register 2 (Address 3)......................................................... 122
Auto-Negotiation Advertisement Register (Address 4)4 ................................... 123
Auto-Negotiation Link Partner Base Page Ability Register (Address 5) ............ 124
Auto-Negotiation Expansion (Address 6) .......................................................... 125
Auto-Negotiation Next Page Transmit Register (Address 7)............................. 125
Auto-Negotiation Link Partner Next Page Receive Register (Address 8) ......... 126
Port Configuration Register (Address 16, Hex 10) ............................................ 127
Quick Status Register (Address 17, Hex 11) .................................................... 128
Interrupt Enable Register (Address 18, Hex 12) ............................................... 128
Interrupt Status Register (Address 19, Hex 13) ................................................ 130
LED Configuration Register (Address 20, Hex 14) ........................................... 131
Receive Error Count Register (Address 21)...................................................... 132
RMII Out-of-Band Signalling Register (Address 25) ......................................... 133
Trim Enable Register (Address 27)................................................................... 133
Register Bit Map................................................................................................ 134
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Revision History
Date
Revision
January 2001
002
Description
Global: Add bar to all LEDm_n for active low status.
Tables 1, 2 and 3: Add RMII, SMII, and SS-SMII numeric pin lists.
Introduction: Deleted “(up to 100 meters)” and “(up to 185 meters)”.
Sectionalization: Change second sentence.
SMII/SS-SMII Interfaces: Delete text from “SMII Interface: “The SMII interface only operates with
VCCIO at 3.3V (refer to Table 26 on page 73).”
Reference Clock: Changed language.
Simplified SMII Application Diagram: Delete old Figure 17 -- redundant.
Under Purpose, switch descriptions for TXD and RXD.
Per-Port LED Driver Functions: Add text to third paragraph after first line:
LED Circuits: Add LED Circuit text and diagram.
Power and Ground Connections: Add 0.1 µF capacitor value to figure.
Typical Twisted-Pair Interface: Change capacitor value from 0.1 µF to .01 µF.
Delete old Figure 35 and old Table 33, SMII Sync Timing (Parameters)
Delete Old Figure 37 Typical RMII Interface -- redundant.
Absolute Maximum Ratings: Change Operating temperature for Case under Max from “120” to
“+120”.
Operating Conditions: Two lines for Recommended Supply Voltage for VCCPECL are:
I/O (SD_2P5V = 0); Sym=VCCPECL; Min=3.14; Typ (2.5)=2.5; Typ (3.3)=3.3; Max=3.46
I/O (SD_2P5V = 1): Sym= VCCPECL; Min=2.38; TypTyp=2.5 ; Max=2.53. For Supply Voltage, I/O
(SD_205V = 1) under Max, change value from “2.53” to “2.63”.
Delete Table note 3
Digital I/O Characteristics (2.5V): Change Output Low Voltage/Max = 0.2 (was 0.1); Output High
voltage/Min = 2.07 (was 2.27). Add to Input Low voltage SD pins: Sym=VIL-SD, Max=0.755V.
Add to Input High voltage SD pins: Sym=VIH-SD, Min=1.58V. Add new line: Output Low voltage
(LEDn_m pins)
Digital I/O Characteristics (3.3V): Add new table.
Required Clock Characteristics: Delete “Input Low voltage” and “Input High voltage” lines.
100BASE-FX Transceiver Characteristics: Remove TBDs.
Modify all timing diagrams and related tables due to completion of Intel’s design verification testing.
Control Register (Address 0): Restructure table notes.
Status Register (Address 1): Change as follows: 1 = Extended register capabilities
0 = Basic register capabilities.
Auto-Negotiation Advertisement Register (Address 4): Add table note 4: “Restart Auto-Negotiation
process whenever Register 4 is written/modified.” Table note 2: Change pin “79” to pin “50”. Table
note 3: Change “LED/CFG” to “CFG”.
Port Configuration Register (Address 16, Hex 10): For Register bit 16.7 under description, change
to: “Write as one. Ignore on read”. (changed from zero)
Receive Error Count Register: Add text to paragraph under Description.
Datasheet
9
Advanced 10/100 8-Port PHY — LXT9785
Figure 1. LXT9785 Block Diagram
8 Port Global
Functions
RMII/SMII Contr
ADD_<4:0>
MDIO
Management /
Mode Select
Logic & LED
Drivers
2
MDC
2
MDINT
RESET
PWRDN
Clock
Generator
REFCLK
SYNC (SMII only)
2
Register Set
Manchester
Encoder
TX PCS
TXDn
Parallel/Serial
Converter
Scrambler
& Encoder
Auto
Negotiation
Mgmt
Counters
10
100
Pulse
Shaper
TP
Driver
ECL
Driver
CIM
+
TP /
Fiber
Out
+
Fiber
select n
Media
Select
Clock Generator
+
Adaptive EQ with BL
Wander Cancellation
100TX
+
RX PCS
RXDn
Port LED
Drivers
3
Serial to
Parallel
Converter
Carrier Sense
Data Valid
Error Detect
TPFONn
-
Register Set
LEDn_<2:0>
TPFOPn
10
100
Manchester
Decoder
100FX
Slicer
TP /
Fiber In
TPFIPn
TPFINn
-
Decoder &
Descrambler
+
10BT
Per-Port Functions
PORT 0
-
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
Datasheet
11
LXT9785 — Advanced 10/100 8-Port PHY
1.0
Pin Assignments and Signal Descriptions
208 ....... VCCIO
207 ....... GNDIO
206 ....... RXD6_0
205 ....... RXD6_1
204 ....... TXD7_1
203 ....... TXD7_0
202 ....... TXEN7
201 ....... RXER7
200 ....... CRS_DV7
199 ....... GNDIO
198 ....... RXD7_0
197 ....... RXD71
196 ....... VCCD
195 ....... GNDD
194 ....... LED7_3
193 ....... LED7_2
192 ....... LED7_1
191 ....... LED6_3
190 ....... LED6_2
189 ....... LED6_1
188 ....... GNDIO
187 ....... LED5_3
186 ....... LED5_2
185 ....... LED5_1
184 ....... VCCD
183 ....... GNDD
182 ....... LED4_3
181 ....... LED4_2
180 ....... LED4_1
179 ....... SGND
178 ....... ModeSel1
177 ....... ModeSel0
176 ....... Section
175 ....... RESET
174 ....... PWRDWN
173 ....... G_FX/TP
172 ....... N/C
171....... TRST
170 ....... TCK
169 ....... TMS
168 ....... TDO
167 ....... TDI
166 ....... SD7
165 ....... SD6
164 ....... VCCPECL
163 ....... GNDPECL
162 ....... SD5
161 ....... SD4
160 ....... N/C
159 ....... N/C
158 ....... VCCR7
157 ....... TPFIP7
Figure 2. LXT9785 RMII 208-Pin PQFP Assignments
Part #
LOT #
FPO #
LXT9785 XX
XXXXXX
XXXXXXXX
Rev #
156 .......TPFIN7
155 .......GNDR7
154 .......TPFOP7
153 .......TPFON7
152 .......VCCT6/7
151 .......TPFON6
150 .......TPFOP6
149 .......GNDR6
148 .......GNDT6/7
147 .......TPFIN6
146 .......TPFIP6
145 .......VCCR6
144 .......VCCR5
143 .......TPFIP5
142 .......TPFIN5
141 .......GNDR5
140 .......TPFOP5
139 .......TPFON5
138 .......VCCT4/5
137 .......TPFON4
136 .......TPFOP4
135 .......GNDR4
134 .......GNDT4/5
133 .......TPFIN4
132 .......TPFIP4
131 .......VCCR4
130 .......VCCR3
129 .......TPFIP3
128 .......TPFIN3
127 .......GNDT2/3
126 .......GNDR3
125 .......TPFOP3
124 .......TPFON3
123 .......VCCT2/3
122 .......TPFON2
121 .......TPFOP2
120 .......GNDR2
119 .......TPFIN2
118 .......TPFIP2
117 .......VCCR2
116 .......VCCR1
115 .......TPFIP1
114 .......TPFIN1
113 .......GNDT0/1
112 .......GNDR1
111 .......TPFOP1
110 .......TPFON1
109 .......VCCT0/1
108 .......TPFON0
107 .......TPFOP0
106 .......GNDR0
105 .......TPFIN0
TXD1_1 ..... 53
RXD0_1 ..... 54
RXD0_0 ..... 55
VCCIO ..... 56
GNDIO ..... 57
CRS_DV0 ..... 58
RXER0/MDIX ..... 59
TXEN0 ..... 60
TXD0_0 ..... 61
TXD0_1 ..... 62
MDC0 ..... 63
MDIO0 ..... 64
VCCD ..... 65
GNDD ..... 66
MDINT0 ..... 67
LED3_3 ..... 68
LED3_2 ..... 69
LED3_1 ..... 70
LED2_3 ..... 71
LED2_2 ..... 72
LED2_1 ..... 73
GNDIO ..... 74
LED1_3 ..... 75
LED1_2 ..... 76
LED1_1 ..... 77
VCCD ..... 78
GNDD ..... 79
LED0_3 ..... 80
LED0_2 ..... 81
LED0_1 ..... 82
AMDIX_EN ..... 83
MDDIS ..... 84
CFG_3 ..... 85
CFG_2 ..... 86
CFG_1 ..... 87
ADD_4 ..... 88
ADD_3 ..... 89
ADD_2 ..... 90
ADD_1 ..... 91
ADD_0 ..... 92
TxSlew_1 ..... 93
TxSlew_0 ..... 94
SD_2P5V ..... 95
SD0 ..... 96
SD1 ..... 97
VCCPECL ..... 98
GNDPECL ..... 99
SD2 ..... 100
SD3 ..... 101
N/C ..... 102
VCCR0 ..... 103
TPFIP0 ..... 104
CRS_DV6 ..... 1
RXER6 ..... 2
TXEN6 ..... 3
TXD6_0 ..... 4
TXD6_1 ..... 5
REFCLK1 ..... 6
RXD5_1 ..... 7
RXD5_0 ..... 8
GNDIO ..... 9
CRS_DV5 ..... 10
RXER5 ..... 11
TXEN5 ..... 12
TXD5_0 ..... 13
TXD5_1 ..... 14
RXD4_1 ..... 15
RXD4_0 ..... 16
CRS_DV4 ..... 17
VCCIO ..... 18
GNDIO ..... 19
RXER4 ..... 20
TXEN4 ..... 21
TXD4_0 ..... 22
TXD4_1 ..... 23
MDC1 ..... 24
MDIO1 ..... 25
MDINT1 ..... 26
RXD3_1 ..... 27
RXD3_0 ..... 28
VCCIO ..... 29
GNDIO ..... 30
CRS_DV3 ..... 31
RXER3 ..... 32
TXEN3 ..... 33
TXD3_0 ..... 34
TXD3_1 ..... 35
RXD2_1 ..... 36
RXD2_0 ..... 37
GNDIO ..... 38
CRS_DV2 ..... 39
RXER2 ..... 40
TXEN2 ..... 41
TXD2_0 ..... 42
TXD2_1 ..... 43
REFCLK0 ..... 44
RXD1_1 ..... 45
RXD1_0 ..... 46
VCCIO ..... 47
GNDIO ..... 48
CRS_DV1 ..... 49
ER1/PAUSE ..... 50
TXEN1 ..... 51
TXD1_0 ..... 52
12
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
208 .......
207 .......
206 .......
205 .......
204 .......
203 .......
202 .......
201 .......
200 .......
199 .......
198 .......
197 .......
196 .......
195 .......
194 .......
193 .......
192 .......
191 .......
190 .......
189 .......
188 .......
187 .......
186 .......
185 .......
184 .......
183 .......
182 .......
181 .......
180 .......
179 .......
178 .......
177 .......
176 .......
175 .......
174 .......
173 .......
172 .......
171.......
170 .......
169 .......
168 .......
167 .......
166 .......
165 .......
164 .......
163 .......
162 .......
161 .......
160 .......
159 .......
158 .......
157 .......
VCCIO
GNDIO
RXD6
N/C
SYNC1
TXD7
N/C
N/C
N/C
GNDIO
RXD7
N/C
VCCD
GNDD
LED7_3
LED7_2
LED7_1
LED6_3
LED6_2
LED6_1
GNDIO
LED5_3
LED5_2
LED5_1
VCCD
GNDD
LED4_3
LED4_2
LED4_1
SGND
ModeSel_1
ModeSel_0
Section
RESET
PWRDWN
G_FX/TP
N/C
TRST
TCK
TMS
TDO
TDI
SD7
SD6
VCCPECL
GNDPECL
SD5
SD4
N/C
N/C
VCCR7
TPFIP7
Figure 3. LXT9785 SMII 208-Pin PQFP Assignments
Part #
LOT #
FPO #
LXT9785 XX
XXXXXX
XXXXXXXX
Rev #
156 .......TPFIN7
155 .......GNDR7
154 .......TPFOP7
153 .......TPFON7
152 .......VCCT6/7
151 .......TPFON6
150 .......TPFOP6
149 .......GNDR6
148 .......GNDT6/7
147 .......TPFIN6
146 .......TPFIP6
145 .......VCCR6
144 .......VCCR5
143 .......TPFIP5
142 .......TPFIN5
141 .......GNDR5
140 .......TPFOP5
139 .......TPFON5
138 .......VCCT4/5
137 .......TPFON4
136 .......TPFOP4
135 .......GNDR4
134 .......GNDT4/5
133 .......TPFIN4
132 .......TPFIP4
131 .......VCCR4
130 .......VCCR3
129 .......TPFIP3
128 .......TPFIN3
127 .......GNDT2/3
126 .......GNDR3
125 .......TPFOP3
124 .......TPFON3
123 .......VCCT2/3
122 .......TPFON2
121 .......TPFOP2
120 .......GNDR2
119 .......TPFIN2
118 .......TPFIP2
117 .......VCCR2
116 .......VCCR1
115 .......TPFIP1
114 .......TPFIN1
113 .......GNDT0/1
112 .......GNDR1
111 .......TPFOP1
110 .......TPFON1
109 .......VCCT0/1
108 .......TPFON0
107 .......TPFOP0
106 .......GNDR0
105 .......TPFIN0
N/C ..... 53
N/C ..... 54
RXD0 ..... 55
VCCIO ..... 56
GNDIO ..... 57
N/C ..... 58
MDIX ..... 59
N/C ..... 60
TXD0 ..... 61
N/C ..... 62
MDC0 ..... 63
MDIO0 ..... 64
VCCD ..... 65
GNDD ..... 66
MDINT0 ..... 67
LED3_3 ..... 68
LED3_2 ..... 69
LED3_1 ..... 70
LED2_3 ..... 71
LED2_2 ..... 72
LED2_1 ..... 73
GNDIO ..... 74
LED1_3 ..... 75
LED1_2 ..... 76
LED1_1 ..... 77
VCCD ..... 78
GNDD ..... 79
LED0_3 ..... 80
LED0_2 ..... 81
LED0_1 ..... 82
AMDIX_EN ..... 83
MDDIS ..... 84
CFG_3 ..... 85
CFG_2 ..... 86
CFG_1 ..... 87
ADD_4 ..... 88
ADD_3 ..... 89
ADD_2 ..... 90
ADD_1 ..... 91
ADD_0 ..... 92
TxSlew_1 ..... 93
TxSlew_0 ..... 94
SD_2P5V ..... 95
SD0 ..... 96
SD1 ..... 97
VCCPECL ..... 98
GNDPECL ..... 99
SD2 ..... 100
SD3 ..... 101
N/C ..... 102
VCCR0 ..... 103
TPFIP0 ..... 104
N/C ..... 1
N/C ..... 2
N/C ..... 3
TXD6 ..... 4
N/C ..... 5
REFCLK1 ..... 6
N/C ..... 7
RXD5 ..... 8
GNDIO ..... 9
N/C ..... 10
N/C ..... 11
N/C ..... 12
TXD5 ..... 13
N/C ..... 14
N/C ..... 15
RXD4 ..... 16
N/C ..... 17
VCCIO ..... 18
GNDIO ..... 19
N/C ..... 20
N/C ..... 21
TXD4 ..... 22
N/C ..... 23
MDC1 ..... 24
MDIO1 ..... 25
MDINT1 ..... 26
N/C ..... 27
RXD3 ..... 28
VCCIO ..... 29
GNDIO ..... 30
N/C ..... 31
N/C ..... 32
N/C ..... 33
TXD3 ..... 34
SYNC0 ..... 35
N/C ..... 36
RXD2 ..... 37
GNDIO ..... 38
N/C ..... 39
N/C ..... 40
N/C ..... 41
TXD2 ..... 42
N/C ..... 43
REFCLK0 ..... 44
N/C ..... 45
RXD1 ..... 46
VCCIO ..... 47
GNDIO ..... 48
N/C ..... 49
PAUSE ..... 50
N/C ..... 51
TXD1 ..... 52
Datasheet
13
LXT9785 — Advanced 10/100 8-Port PHY
208 ....... VCCIO
207 ....... GNDIO
206 ....... N/C
205 ....... RXD6
204 ....... TX_SYNC1
203 ....... TXD7
202 ....... N/C
201 ....... TX_CLK1
200 ....... N/C
199 ....... GNDIO
198 ....... N/C
197 ....... RXD7
196 ....... VCCD
195 ....... GNDD
194 ....... LED7_3
193 ....... LED7_2
192 ....... LED7_1
191 ....... LED6_3
190 ....... LED6_2
189 ....... LED6_1
188 ....... GNDIO
187 ....... LED5_3
186 ....... LED5_2
185 ....... LED5_1
184 ....... VCCD
183 ....... GNDD
182 ....... LED4_3
181 ....... LED4_2
180 ....... LED4_1
179 ....... SGND
178 ....... ModeSel_1
177 ....... ModeSel_0
176 ....... Section
175 ....... RESET
174 ....... PWRDWN
173 ....... G_FX/TP
172 ....... N/C
171....... TRST
170 ....... TCK
169 ....... TMS
168 ....... TDO
167 ....... TDI
166 ....... SD7
165 ....... SD6
164 ....... VCCPECL
163 ....... GNDPECL
162 ....... SD5
161 ....... SD4
160 ....... N/C
159 ....... N/C
158 ....... VCCR7
157 ....... TPFIP7
Figure 4. LXT9785 SS-SMII 208-Pin PQFP Assignments
Part #
LOT #
FPO #
LXT9785 XX
XXXXXX
XXXXXXXX
Rev #
156 .......TPFIN7
155 .......GNDR7
154 .......TPFOP7
153 .......TPFON7
152 .......VCCT6/7
151 .......TPFON6
150 .......TPFOP6
149 .......GNDR6
148 .......GNDT6/7
147 .......TPFIN6
146 .......TPFIP6
145 .......VCCR6
144 .......VCCR5
143 .......TPFIP5
142 .......TPFIN5
141 .......GNDR5
140 .......TPFOP5
139 .......TPFON5
138 .......VCCT4/5
137 .......TPFON4
136 .......TPFOP4
135 .......GNDR4
134 .......GNDT4/5
133 .......TPFIN4
132 .......TPFIP4
131 .......VCCR4
130 .......VCCR3
129 .......TPFIP3
128 .......TPFIN3
127 .......GNDT2/3
126 .......GNDR3
125 .......TPFOP3
124 .......TPFON3
123 .......VCCT2/3
122 .......TPFON2
121 .......TPFOP2
120 .......GNDR2
119 .......TPFIN2
118 .......TPFIP2
117 .......VCCR2
116 .......VCCR1
115 .......TPFIP1
114 .......TPFIN1
113 .......GNDT0/1
112 .......GNDR1
111 .......TPFOP1
110 .......TPFON1
109 .......VCCT0/1
108 .......TPFON0
107 .......TPFOP0
106 .......GNDR0
105 .......TPFIN0
N/C ..... 53
RXD0 ..... 54
N/C ..... 55
VCCIO ..... 56
GNDIO ..... 57
RX_SYNC0 ..... 58
MDIX ..... 59
RX_CLK0 ..... 60
TXD0 ..... 61
N/C ..... 62
MDC0 ..... 63
MDIO0 ..... 64
VCCD ..... 65
GNDD ..... 66
MDINT0 ..... 67
LED3_3 ..... 68
LED3_2 ..... 69
LED3_1 ..... 70
LED2_3 ..... 71
LED2_2 ..... 72
LED2_1 ..... 73
GNDIO ..... 74
LED1_3 ..... 75
LED1_2 ..... 76
LED1_1 ..... 77
VCCD ..... 78
GNDD ..... 79
LED0_3 ..... 80
LED0_2 ..... 81
LED0_1 ..... 82
AMDIX_EN ..... 83
MDDIS ..... 84
CFG_3 ..... 85
CFG_2 ..... 86
CFG_1 ..... 87
ADD_4 ..... 88
ADD_3 ..... 89
ADD_2 ..... 90
ADD_1 ..... 91
ADD_0 ..... 92
TxSlew_1 ..... 93
TxSlew_0 ..... 94
SD_2P5V ..... 95
SD0 ..... 96
SD1 ..... 97
VCCPECL ..... 98
GNDPECL ..... 99
SD2 ..... 100
SD3 ..... 101
N/C ..... 102
VCCR0 ..... 103
TPFIP0 ..... 104
N/C ..... 1
N/C ..... 2
N/C ..... 3
TXD6 ..... 4
N/C ..... 5
REFCLK1 ..... 6
RXD5 ..... 7
N/C ..... 8
GNDIO ..... 9
N/C ..... 10
N/C ..... 11
N/C ..... 12
TXD5 ..... 13
N/C ..... 14
RXD4 ..... 15
N/C ..... 16
RX_SYNC1 ..... 17
VCCIO ..... 18
GNDIO ..... 19
N/C ..... 20
RX_CLK1 ..... 21
TXD4 ..... 22
N/C ..... 23
MDC1 ..... 24
MDIO1 ..... 25
MDINT1 ..... 26
RXD3 ..... 27
N/C ..... 28
VCCIO ..... 29
GNDIO ..... 30
N/C ..... 31
TX_CLK0 ..... 32
N/C ..... 33
TXD3 ..... 34
TX_SYNC0 ..... 35
RXD2 ..... 36
N/C ..... 37
GNDIO ..... 38
N/C ..... 39
N/C ..... 40
N/C ..... 41
TXD2 ..... 42
N/C ..... 43
REFCLK0 ..... 44
RXD1 ..... 45
N/C ..... 46
VCCIO ..... 47
GNDIO ..... 48
N/C ..... 49
PAUSE ..... 50
N/C ..... 51
TXD1 ..... 52
14
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Figure 5. LXT9785 RMII 241-Ball PBGA Assignments
RMI
I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
A
GNDD
VCCIO
RXD1_0
TXD2_1
CRS_D
V2
TXD3_1
TXEN3
VCCIO
GNDD
MDIO1
TXD4_0
RXER4
RXD4_0
TXEN5
RXER5
TXD6_1
RXER6
B
RXD0_1
TXEN1
GNDD
RXD1_1
TXD2_0
RXD2_0
GNDD
CRS_D
V3
RXD3_1
MDC1
TXEN4
CRS_D
V4
TXD5_0
RXD5_0
RXD5_1
CRS_
DV6
RXD6_1
B
C
VCCIO
RXD0_0
TXD1_0
CRS_D
V1
GNDD
TXEN2
RXD2_1
RXER3
MDINT1
TXD4_1
VCCIO
RXD4_1
GNDD
TXEN6
RXD6_0
TXD7_1
GNDD
C
D
GNDD
RXER0/
MDIX
GNDD
TXD1_1
RXER1/
PAUSE
GNDD
RXER2
TXD3_0
RXD3_0
GNDD
TXD5_1
CRS_D
V5
TXD6_0
VCCIO
GNDD
TXEN7
RXER7
D
E
MDC0
TXD0_0
TXEN0
CRS_D
V0
GNDD
REF
CLK0
GNDD
GNDD
REF
CLK1
GNDD
TXD7_0
CRS_D
V7
RXD7_0
GNDD
E
F
MDINT0
LED3_1
MDIO0
TXD0_1
VCCD
GNDD
RXD7_1
N/C
LED7_3
LED7_2
F
G
LED2_3
N/C
LED3_2
LED3_3
N/C
VCCD
N/C
LED7_1
N/C
LED6_3
G
H
LED1_3
LED2_1
LED2_2
N/C
N/C
LED6_1
LED6_2
LED5_3
H
J
LED0_3
N/C
LED1_2
LED1_1
VCCD
LED5_1
LED5_2
LED4_3
J
K
AMDIX_
EN
LED0_2
LED0_1
N/C
SGND
N/C
LED4_1
LED4_2
K
L
MDDIS
CFG_3
CFG_2
ADD_4
VCC
PECL
VCC
PECL
PWR
DWN
SEC
TION
MODE
SEL_0
MODE
SEL_1
L
M
CFG_1
ADD_3
ADD_2
TxSLE
W_1
GND
PECL
GND
PECL
G_FX/
TP
RESET
TCK
TRST
M
N
ADD_1
ADD_0
TxSLE
W_0
SD1
SD3
VCCT
VCCT
P
SD_2P5
V
SD0
SD2
VCCR
GNDR
GNDR
VCCR
VCCR
VCCR
R
GNDT
TPFIP
(0)
GNDT
TPFON(
1)
GNDT
TPFIP
(2)
GNDR
TPFIN
(3)
T
TPFIN
(0)
TPFOP
(0)
TPFOP
(1)
TPFIN
(1)
TPFIN
(2)
TPFOP
(2)
TPFON
(3)
U
TPFON
(0)
GNDT
TPFIP
(1)
GNDT
TPFON
(2)
GNDT
1
2
3
4
5
6
Datasheet
VCCD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
VCCT
N/C
A
VCCT
VCCT
VCCR
TDI
TDO
TMS
SD7
N
VCCR
VCCR
VCCR
GNDR
GNDT
SD4
SD5
SD6
P
GNDR
TPFON
(4)
GNDR
TPFIP
(6)
GNDR
TPFOP
(7)
GNDT
TPFIP
(7)
GNDT
R
TPFIP
(3)
TPFIP
(4)
TPFOP
(4)
TPFOP
(5)
TPFIN
(5)
TPFIN
(6)
TPFOP
(6)
TPFON
(7)
TPFIN
(7)
GNDT
T
TPFOP
(3)
GNDR
TPFIN
(4)
GNDT
TPFON
(5)
GNDT
TPFIP
(5)
GNDT
TPFON
(6)
GNDT
GNDT
U
7
8
9
10
11
12
13
14
15
16
17
15
LXT9785 — Advanced 10/100 8-Port PHY
Figure 6. LXT9785 SMII 241-Ball PBGA Assignments
16
SMI
I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
A
GNDD
VCCIO
RXD1
N/C
N/C
SYNC0
N/C
VCCIO
GNDD
MDIO1
TXD4
N/C
RXD4
N/C
N/C
N/C
N/C
B
N/C
N/C
GNDD
N/C
TXD2
RXD2
GNDD
N/C
N/C
MDC1
N/C
N/C
TXD5
RXD5
N/C
N/C
N/C
B
C
VCCIO
RXD0
TXD1
N/C
GNDD
N/C
N/C
N/C
MDINT1
N/C
VCCIO
N/C
GNDD
N/C
RXD6
SYNC1
GNDD
C
D
GNDD
MDIX
GNDD
N/C
PAUSE
GNDD
N/C
TXD3
RXD3
GNDD
N/C
N/C
TXD6
VCCIO
GNDD
N/C
N/C
D
E
MDC0
TXD0
N/C
N/C
GNDD
REF
CLK0
GNDD
GNDD
REF
CLK1
GNDD
TXD7
N/C
RXD7
GNDD
E
F
MDINT0
LED3_1
MDIO0
N/C
VCCD
GNDD
N/C
N/C
LED7_3
LED7_2
F
G
LED2_3
N/C
LED3_2
LED3_3
N/C
VCCD
N/C
LED7_1
N/C
LED6_3
G
H
LED1_3
LED2_1
LED2_2
N/C
N/C
LED6_1
LED6_2
LED5_3
H
J
LED0_3
N/C
LED1_2
LED1_1
VCCD
LED5_1
LED5_2
LED4_3
J
K
AMDIX_
EN
LED0_2
LED0_1
N/C
N/C
LED4_1
LED4_2
K
L
MDDIS
CFG_3
CFG_2
ADD_4
VCC
PECL
VCC
PECL
PWR
DWN
SECTIO
N
MODE
SEL_0
MODE
SEL_1
L
M
CFG_1
ADD_3
ADD_2
TxSLE
W_1
GND
PECL
GND
PECL
G_FX/
TP
RESET
TCK
TRST
M
N
ADD_1
ADD_0
TxSLE
W_0
SD1
SD3
VCCT
VCCT
P
SD_2P5
V
SD0
SD2
VCCR
GNDR
GNDR
VCCR
VCCR
VCCR
R
GNDT
TPFIP
(0)
GNDT
TPFON(
1)
GNDT
TPFIP
(2)
GNDR
TPFIN
(3)
T
TPFIN(
0)
TPFOP(
0)
TPFOP(
1)
TPFIN(
1)
TPFIN(
2)
TPFOP(
2)
TPFON(
3)
U
TPFON(
0)
GNDT
TPFIP
(1)
GNDT
TPFON(
2)
GNDT
1
2
3
4
5
6
VCCD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
VCCT
N/C
SGND
A
VCCT
VCCT
VCCR
TDI
TDO
TMS
SD7
N
VCCR
VCCR
VCCR
GNDR
GNDT
SD4
SD5
SD6
P
GNDR
TPFON(
4)
GNDR
TPFIP
(6)
GNDR
TPFOP(
7)
GNDT
TPFIP
(7)
GNDT
R
TPFIP
(3)
TPFIP
(4)
TPFOP(
4)
TPFOP(
5)
TPFIN
(5)
TPFIN
(6)
TPFOP(
6)
TPFON(
7)
TPFIN(
7)
GNDT
T
TPFOP(
3)
GNDR
TPFIN
(4)
GNDT
TPFON(
5)
GNDT
TPFIP
(5)
GNDT
TPFON(
6)
GNDT
GNDT
U
7
8
9
10
11
12
13
14
15
16
17
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Figure 7. LXT9785 SS-SMII 241-Ball PBGA Assignments
SSSMI
I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
A
GNDD
VCCIO
N/C
N/C
N/C
TX_SY
NC0
N/C
VCCIO
GNDD
MDIO1
TXD4
N/C
N/C
N/C
N/C
N/C
N/C
B
RXD0
N/C
GNDD
RXD1
TXD2
N/C
GNDD
N/C
RXD3
MDC1
RX_
CLK1
RX_SY
NC1
TXD5
N/C
RXD5
N/C
RXD6
B
C
VCCIO
RXD0
TXD1
N/C
GNDD
N/C
RXD2
TX_CL
K0
MDINT1
N/C
VCCIO
RXD4
GNDD
N/C
N/C
TX_SY
NC1
GNDD
C
D
GNDD
MDIX
GNDD
N/C
PAUSE
GNDD
N/C
TXD3
N/C
GNDD
N/C
N/C
TXD6
VCCIO
GNDD
N/C
TX_CL
K1
D
E
MDC0
TXD0
RX_
CLK0
Rx_SY
NC0
GNDD
REF
CLK0
GNDD
GNDD
REF
CLK1
GNDD
TXD7
N/C
N/C
GNDD
E
F
MDINT0
LED3_1
MDIO0
N/C
VCCD
GNDD
RXD7
N/C
LED7_3
LED7_2
F
G
LED2_3
N/C
LED3_2
LED3_3
N/C
VCCD
N/C
LED7_1
N/C
LED6_3
G
H
LED1_3
LED2_1
LED2_2
N/C
N/C
LED6_1
LED6_2
LED5_3
H
J
LED0_3
N/C
LED1_2
LED1_1
VCCD
LED5_1
LED5_2
LED4_3
J
K
AMDIX_
EN
LED0_2
LED0_1
N/C
SGND
N/C
LED4_1
LED4_2
K
L
MDDIS
CFG_3
CFG_2
ADD_4
VCC
PECL
VCC
PECL
PWR
DWN
SEC
TION
MODE
SEL_0
MODE
SEL_1
L
M
CFG_1
ADD_3
ADD_2
TxSLE
W_1
GND
PECL
GND
PECL
G_FX/
TP
RESET
TCK
TRST
M
N
ADD_1
ADD_0
TxSLE
W_0
SD1
SD3
VCCT
VCCT
P
SD_2P
5V
SD0
SD2
VCCR
GNDR
GNDR
VCCR
VCCR
VCCR
R
GNDT
TPFIP
(0)
GNDT
TPFON
(1)
GNDT
TPFIP
(2)
GNDR
TPFIN
(3)
T
TPFIN
(0)
TPFOP
(0)
TPFOP
(1)
TPFIN
(1)
TPFIN
(2)
TPFOP
(2)
TPFON
(3)
U
TPFON
(0)
GNDT
TPFIP
(1)
GNDT
TPFON
(2)
GNDT
1
2
3
4
5
6
Datasheet
VCCD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
VCCT
N/C
A
VCCT
VCCT
VCCR
TDI
TDO
TMS
SD7
N
VCCR
VCCR
VCCR
GNDR
GNDT
SD4
SD5
SD6
P
GNDR
TPFON
(4)
GNDR
TPFIP
(6)
GNDR
TPFOP
(7)
GNDT
TPFIP
(7)
GNDT
R
TPFIP
(3)
TPFIP
(4)
TPFOP
(4)
TPFOP
(5)
TPFIN
(5)
TPFIN
(6)
TPFOP
(6)
TPFON
(7)
TPFIN
(7)
GNDT
T
TPFOP
(3)
GNDR
TPFIN
(4)
GNDT
TPFON
(5)
GNDT
TPFIP
(5)
GNDT
TPFON
(6)
GNDT
GNDT
U
7
8
9
10
11
12
13
14
15
16
17
17
LXT9785 — Advanced 10/100 8-Port PHY
Table 1.
RMII PQFP Pin List
Pin
Type1
Symbol
1
CRS_DV6
2
3
Reference for Full
Description
O, TS, SL
Table 4 on page 39
RXER6
O, TS, SL, ID
Table 4 on page 39
TXEN6
I, ID
Table 4 on page 39
4
TXD6_0
I, ID
Table 4 on page 39
5
TXD6_1
I, ID
Table 4 on page 39
6
REFCLK1
I
Table 4 on page 39
7
RXD5_1
O, TS, ID
Table 4 on page 39
8
RXD5_0
O, TS
Table 4 on page 39
9
GNDIO
–
Table 14 on page 49
10
CRS_DV5
O, TS, SL
Table 4 on page 39
11
RXER5
O, TS, SL, ID
Table 4 on page 39
12
TXEN5
I, ID
Table 4 on page 39
13
TXD5_0
I, ID
Table 4 on page 39
14
TXD5_1
I, ID
Table 4 on page 39
15
RXD4_1
O, TS,ID
Table 4 on page 39
16
RXD4_0
O, TS
Table 4 on page 39
17
CRS_DV4
O, TS, SL
Table 4 on page 39
18
VCCIO
–
Table 14 on page 49
19
GNDIO
–
Table 14 on page 49
20
RXER4
O, TS, SL, ID
Table 4 on page 39
21
TXEN4
I, ID
Table 4 on page 39
22
TXD4_0
I, ID
Table 4 on page 39
23
TXD4_1
I, ID
Table 4 on page 39
24
MDC1
I, ST, ID
Table 8 on page 43
25
MDIO1
I/O, TS, SL, IP
Table 8 on page 43
26
MDINT1
OD, TS, SL, IP
Table 8 on page 43
27
RXD3_1
O, TS, ID
Table 4 on page 39
28
RXD3_0
O, TS
Table 4 on page 39
29
VCCIO
–
Table 14 on page 49
30
GNDIO
–
Table 14 on page 49
31
CRS_DV3
O, TS, SL
Table 4 on page 39
32
RXER3
O, TS, SL, ID
Table 4 on page 39
33
TXEN3
I, ID
Table 4 on page 39
1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,
OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal
Pull-up, ID=Weak Internal Pull-down
18
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Table 1.
RMII PQFP Pin List (Continued)
Pin
Type1
Symbol
Reference for Full
Description
34
TXD3_0
I, ID
Table 4 on page 39
35
TXD3_1
I, ID
Table 4 on page 39
36
RXD2_1
O, TS, ID
Table 4 on page 39
37
RXD2_0
O, TS
Table 4 on page 39
38
GNDIO
–
Table 14 on page 49
39
CRS_DV2
O, TS, SL
Table 4 on page 39
40
RXER2
O, TS, SL, ID
Table 4 on page 39
41
TXEN2
I, ID
Table 4 on page 39
42
TXD2_0
I, ID
Table 4 on page 39
43
TXD2_1
I, ID
Table 4 on page 39
44
REFCLK0
I
Table 4 on page 39
45
RXD1_1
O, TS, ID
Table 4 on page 39
46
RXD1_0
O, TS
Table 4 on page 39
47
VCCIO
–
Table 14 on page 49
48
GNDIO
–
Table 14 on page 49
49
CRS_DV1
O, TS, SL
Table 4 on page 39
50
RXER1/PAUSE
O, TS, SL, ID
Table 12 on page 46
51
TXEN1
I, ID
Table 4 on page 39
52
TXD1_0
I, ID
Table 4 on page 39
53
TXD1_1
I, ID
Table 4 on page 39
54
RXD0_1
O, TS, ID
Table 4 on page 39
55
RXD0_0
O, TS
Table 4 on page 39
56
VCCIO
–
Table 14 on page 49
57
GNDIO
–
Table 14 on page 49
58
CRS_DV0
O, TS, SL
Table 4 on page 39
59
RXER0/MDIX
O, TS, SL, ID
Table 12 on page 46
60
TXEN0
I, ID
Table 4 on page 39
61
TXD0_0
I, ID
Table 4 on page 39
62
TXD0_1
I, ID
Table 4 on page 39
63
MDC0
I, ST, ID
Table 8 on page 43
64
MDIO0
I/O, TS, SL, IP
Table 8 on page 43
65
VCCD
–
Table 14 on page 49
66
GNDD
–
Table 14 on page 49
67
MDINT0
OD, TS, SL, IP
Table 8 on page 43
1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,
OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal
Pull-up, ID=Weak Internal Pull-down
Datasheet
19
LXT9785 — Advanced 10/100 8-Port PHY
Table 1.
RMII PQFP Pin List (Continued)
Pin
Symbol
Type1
Reference for Full
Description
68
LED3_3
OD, TS, SO, IP
Table 13 on page 48
69
LED3_2
OD, TS, SL, IP
Table 13 on page 48
70
LED3_1
OD, TS, SL, IP
Table 13 on page 48
71
LED2_3
OD, TS, SL, IP
Table 13 on page 48
72
LED2_2
OD, TS, SL, IP
Table 13 on page 48
73
LED2_1
OD, TS, SL, IP
Table 13 on page 48
74
GNDIO
–
Table 14 on page 49
75
LED1_3
OD, TS, SL, IP
Table 13 on page 48
76
LED1_2
OD, TS, SL, IP
Table 13 on page 48
77
LED1_1
OD, TS, SL, IP
Table 13 on page 48
78
VCCD
–
Table 14 on page 49
79
GNDD
–
Table 14 on page 49
80
LED0_3
OD, TS, SL, IP
Table 13 on page 48
81
LED0_2
OD, TS, SL, IP
Table 13 on page 48
82
LED0_1
OD, TS, SL, IP
Table 13 on page 48
83
AMDIX_EN
I, ST, IP
Table 12 on page 46
84
MDDIS
I, ST, ID
Table 8 on page 43
85
CFG_3
I, ST, ID
Table 12 on page 46
86
CFG_2
I, ST, ID
Table 12 on page 46
87
CFG_1
I, ST, ID
Table 12 on page 46
88
ADD_4
I, ST, ID
Table 12 on page 46
89
ADD_3
I, ST, ID
Table 12 on page 46
90
ADD_2
I, ST, ID
Table 12 on page 46
91
ADD_1
I, ST, ID
Table 12 on page 46
92
ADD_0
I, ST, ID
Table 12 on page 46
93
TxSLEW_1
I, ST, ID
Table 12 on page 46
94
TxSLEW_0
I, ST, ID
Table 12 on page 46
95
SD_2P5V
I, ST, ID
Table 9 on page 44
96
SD0
I
Table 9 on page 44
97
SD1
I
Table 9 on page 44
98
VCCPECL
–
Table 14 on page 49
99
GNDPECL
–
Table 14 on page 49
100
SD2
I
Table 9 on page 44
101
SD3
I
Table 9 on page 44
1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,
OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal
Pull-up, ID=Weak Internal Pull-down
20
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Table 1.
RMII PQFP Pin List (Continued)
Pin
102
Type1
Symbol
N/C
Reference for Full
Description
–
Table 15 on page 50
103
VCCR0
–
Table 14 on page 49
104
TPFIP0
AO/AI
Table 10 on page 44
105
TPFIN0
AO/AI
Table 10 on page 44
106
GNDR0
–
Table 14 on page 49
107
TPFOP0
AO/AI
Table 10 on page 44
108
TPFON0
AO/AI
Table 10 on page 44
109
VCCT0/1
–
Table 14 on page 49
110
TPFON1
AO/AI
Table 10 on page 44
111
TPFOP1
AO/AI
Table 10 on page 44
112
GNDR1
–
Table 14 on page 49
113
GNDT0/1
–
Table 14 on page 49
114
TPFIN1
AO/AI
Table 10 on page 44
115
TPFIP1
AO/AI
Table 10 on page 44
116
VCCR1
–
Table 14 on page 49
117
VCCR2
–
Table 14 on page 49
118
TPFIP2
AO/AI
Table 10 on page 44
119
TPFIN2
AO/AI
Table 10 on page 44
120
GNDR2
–
Table 14 on page 49
121
TPFOP2
AO/AI
Table 10 on page 44
122
TPFON2
AO/AI
Table 10 on page 44
123
VCCT2/3
–
Table 14 on page 49
124
TPFON3
AO/AI
Table 10 on page 44
125
TPFOP3
AO/AI
Table 10 on page 44
126
GNDR3
–
Table 14 on page 49
127
GNDT2/3
–
Table 14 on page 49
128
TPFIN3
AO/AI
Table 10 on page 44
129
TPFIP3
AO/AI
Table 10 on page 44
130
VCCR3
–
Table 14 on page 49
131
VCCR4
–
Table 14 on page 49
132
TPFIP4
AO/AI
Table 10 on page 44
133
TPFIN4
AO/AI
Table 10 on page 44
134
GNDT4/5
–
Table 14 on page 49
135
GNDR4
–
Table 14 on page 49
1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,
OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal
Pull-up, ID=Weak Internal Pull-down
Datasheet
21
LXT9785 — Advanced 10/100 8-Port PHY
Table 1.
RMII PQFP Pin List (Continued)
Pin
136
Type1
Symbol
TPFOP4
Reference for Full
Description
AO/AI
Table 10 on page 44
137
TPFON4
AO/AI
Table 10 on page 44
138
VCCT4/5
–
Table 14 on page 49
139
TPFON5
AO/AI
Table 10 on page 44
140
TPFOP5
AO/AI
Table 10 on page 44
141
GNDR5
–
Table 14 on page 49
142
TPFIN5
AO/AI
Table 10 on page 44
143
TPFIP5
AO/AI
Table 10 on page 44
144
VCCR5
–
Table 14 on page 49
145
VCCR6
–
Table 14 on page 49
146
TPFIP6
AO/AI
Table 10 on page 44
147
TPFIN6
AO/AI
Table 10 on page 44
148
GNDT6/7
–
Table 14 on page 49
149
GNDR6
–
Table 14 on page 49
150
TPFOP6
AO/AI
Table 10 on page 44
151
TPFON6
AO/AI
Table 10 on page 44
152
VCCT6/7
–
Table 14 on page 49
153
TPFON7
AO/AI
Table 10 on page 44
154
TPFOP7
AO/AI
Table 10 on page 44
155
GNDR7
–
Table 14 on page 49
156
TPFIN7
AO/AI
Table 10 on page 44
157
TPFIP7
AO/AI
Table 10 on page 44
158
VCCR7
–
Table 14 on page 49
159
N/C
–
Table 15 on page 50
160
N/C
–
Table 15 on page 50
161
SD4
I
Table 9 on page 44
162
SD5
I
Table 9 on page 44
163
GNDPECL
–
Table 14 on page 49
164
VCCPECL
–
Table 14 on page 49
165
SD6
I
Table 9 on page 44
166
SD7
I
Table 9 on page 44
167
TDI
I, ST, IP
Table 11 on page 45
168
TDO
O, TS
Table 11 on page 45
169
TMS
I, ST, IP
Table 11 on page 45
1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,
OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal
Pull-up, ID=Weak Internal Pull-down
22
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Table 1.
RMII PQFP Pin List (Continued)
Pin
Type1
Symbol
Reference for Full
Description
170
TCK
I, ST, ID
Table 11 on page 45
171
TRST
I, ST, IP
Table 11 on page 45
172
N/C
–
Table 15 on page 50
173
G_FX/TP
I, ST, ID
Table 12 on page 46
174
PWRDWN
I, ST, ID
Table 12 on page 46
175
RESET
I, ST, IP
Table 12 on page 46
176
Section
I, ST, ID
Table 12 on page 46
177
ModeSel0
I, ST, ID
Table 12 on page 46
178
ModeSel1
I, ST, ID
Table 12 on page 46
179
SGND
–
Table 14 on page 49
180
LED4_1
OD, TS, SL, IP
Table 13 on page 48
181
LED4_2
OD, TS, SL, IP
Table 13 on page 48
182
LED4_3
OD, TS, SL, IP
Table 13 on page 48
183
GNDD
–
Table 14 on page 49
184
VCCD
–
Table 14 on page 49
185
LED5_1
OD, TS, SL, IP
Table 13 on page 48
186
LED5_2
OD, TS, SL, IP
Table 13 on page 48
187
LED5_3
OD, TS, SL, IP
Table 13 on page 48
188
GNDIO
–
Table 14 on page 49
189
LED6_1
OD, TS, SL, IP
Table 13 on page 48
190
LED6_2
OD, TS, SL, IP
Table 13 on page 48
191
LED6_3
OD, TS, SL, IP
Table 13 on page 48
192
LED7_1
OD, TS, SL, IP
Table 13 on page 48
193
LED7_2
OD, TS, SL, IP
Table 13 on page 48
194
LED7_3
OD, TS, SL, IP
Table 13 on page 48
195
GNDD
–
Table 14 on page 49
196
VCCD
–
Table 14 on page 49
197
RXD7_1
O, TS, ID
Table 4 on page 39
198
RXD7_0
O, TS
Table 4 on page 39
199
GNDIO
–
Table 14 on page 49
200
CRS_DV7
O, TS, SL
Table 4 on page 39
201
RXER7
O, TS, SL, ID
Table 4 on page 39
202
TXEN7
I, ID
Table 4 on page 39
203
TXD7_0
I, ID
Table 4 on page 39
1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,
OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal
Pull-up, ID=Weak Internal Pull-down
Datasheet
23
LXT9785 — Advanced 10/100 8-Port PHY
Table 1.
RMII PQFP Pin List (Continued)
Pin
204
Type1
Symbol
TXD7_1
Reference for Full
Description
I, ID
Table 4 on page 39
205
RXD6_1
O, TS, ID
Table 4 on page 39
206
RXD6_0
O, TS
Table 4 on page 39
207
GNDIO
–
Table 14 on page 49
208
VCCIO
–
Table 14 on page 49
1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,
OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal
Pull-up, ID=Weak Internal Pull-down
24
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Table 2.
SMII PQFP Pin List
Pin
Symbol
Type1
Reference for Full
Description
1
N/C
–
Table 15 on page 50
2
N/C
–
Table 15 on page 50
3
N/C
–
Table 15 on page 50
4
TXD6
I, ID
Table 15 on page 50
5
N/C
I, ID
Table 15 on page 50
6
REFCLK1
I
Table 5 on page 41
7
N/C
–
Table 15 on page 50
8
RXD5
O, TS
Table 6 on page 41
9
GNDIO
–
Table 14 on page 49
10
N/C
–
Table 15 on page 50
11
N/C
–
Table 15 on page 50
12
N/C
–
Table 15 on page 50
13
TXD5
I, ID
Table 5 on page 41
14
N/C
–
Table 15 on page 50
15
N/C
O, TS,ID
Table 15 on page 50
16
RXD4
O, TS
Table 6 on page 41
17
N/C
–
Table 15 on page 50
18
VCCIO
–
Table 14 on page 49
19
GNDIO
–
Table 14 on page 49
20
N/C
O, TS, SL, ID
Table 15 on page 50
21
N/C
I, ID
Table 15 on page 50
22
TXD4
I, ID
Table 5 on page 41
23
N/C
–
Table 15 on page 50
24
MDC1
I, ST, ID
Table 8 on page 43
25
MDIO1
I/O, TS, SL, IP
Table 8 on page 43
26
MDINT1
OD, TS, SL, IP
Table 8 on page 43
27
N/C
–
Table 15 on page 50
28
RXD3
O, TS
Table 6 on page 41
29
VCCIO
–
Table 14 on page 49
30
GNDIO
–
Table 14 on page 49
31
N/C
–
Table 15 on page 50
32
N/C
–
Table 15 on page 50
33
N/C
–
Table 15 on page 50
1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,
OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak
Internal Pull-up, ID=Weak Internal Pull-down
Datasheet
25
LXT9785 — Advanced 10/100 8-Port PHY
Table 2.
SMII PQFP Pin List (Continued)
Pin
Symbol
Type1
Reference for Full
Description
34
TXD3
I, ID
Table 5 on page 41
35
SYNC0
I, ID
Table 6 on page 41
36
N/C
–
Table 15 on page 50
37
RXD2
O, TS
Table 6 on page 41
38
GNDIO
–
Table 14 on page 49
39
N/C
–
Table 15 on page 50
40
N/C
–
Table 15 on page 50
41
N/C
–
Table 15 on page 50
42
TXD2
I, ID
Table 5 on page 41
43
N/C
–
Table 15 on page 50
44
REFCLK0
I
Table 5 on page 41
45
N/C
–
Table 15 on page 50
46
RXD1
O, TS
Table 6 on page 41
47
VCCIO
–
Table 14 on page 49
48
GNDIO
–
Table 14 on page 49
49
N/C
–
Table 15 on page 50
50
PAUSE
I, ID
Table 12 on page 46
51
N/C
52
TXD1
–
Table 15 on page 50
I, ID
Table 5 on page 41
53
N/C
–
Table 15 on page 50
54
N/C
–
Table 15 on page 50
55
RXD0
O, TS
Table 6 on page 41
56
VCCIO
–
Table 14 on page 49
57
GNDIO
–
Table 14 on page 49
58
N/C
–
Table 15 on page 50
59
MDIX
I, ID
Table 12 on page 46
60
N/C
–
Table 15 on page 50
61
TXD0
I, ID
Table 5 on page 41
62
N/C
–
Table 15 on page 50
63
MDC0
I, ST, ID
Table 8 on page 43
64
MDIO0
I/O, TS, SL, IP
Table 8 on page 43
65
VCCD
–
Table 14 on page 49
66
GNDD
–
Table 14 on page 49
67
MDINT0
OD, TS, SL, IP
Table 8 on page 43
1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,
OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak
Internal Pull-up, ID=Weak Internal Pull-down
26
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Table 2.
SMII PQFP Pin List (Continued)
Pin
Symbol
Type1
Reference for Full
Description
68
LED3_3
OD, TS, SO, IP
Table 13 on page 48
69
LED3_2
OD, TS, SL, IP
Table 13 on page 48
70
LED3_1
OD, TS, SL, IP
Table 13 on page 48
71
LED2_3
OD, TS, SL, IP
Table 13 on page 48
72
LED2_2
OD, TS, SL, IP
Table 13 on page 48
73
LED2_1
OD, TS, SL, IP
Table 13 on page 48
74
GNDIO
–
Table 14 on page 49
75
LED1_3
OD, TS, SL, IP
Table 13 on page 48
76
LED1_2
OD, TS, SL, IP
Table 13 on page 48
77
LED1_1
OD, TS, SL, IP
Table 13 on page 48
78
VCCD
–
Table 14 on page 49
79
GNDD
–
Table 14 on page 49
80
LED0_3
OD, TS, SL, IP
Table 13 on page 48
81
LED0_2
OD, TS, SL, IP
Table 13 on page 48
82
LED0_1
OD, TS, SL, IP
Table 13 on page 48
83
AMDIX_EN
I, ST, IP
Table 12 on page 46
84
MDDIS
I, ST, ID
Table 8 on page 43
85
CFG_3
I, ST, ID
Table 12 on page 46
86
CFG_2
I, ST, ID
Table 12 on page 46
87
CFG_1
I, ST, ID
Table 12 on page 46
88
ADD_4
I, ST, ID
Table 12 on page 46
89
ADD_3
I, ST, ID
Table 12 on page 46
90
ADD_2
I, ST, ID
Table 12 on page 46
91
ADD_1
I, ST, ID
Table 12 on page 46
92
ADD_0
I, ST, ID
Table 12 on page 46
93
TxSLEW_1
I, ST, ID
Table 12 on page 46
94
TxSLEW_0
I, ST, ID
Table 12 on page 46
95
SD_2P5V
I, ST, ID
Table 9 on page 44
96
SD0
I
Table 9 on page 44
97
SD1
I
Table 9 on page 44
98
VCCPECL
–
Table 14 on page 49
99
GNDPECL
–
Table 14 on page 49
100
SD2
I
Table 9 on page 44
101
SD3
I
Table 9 on page 44
1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,
OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak
Internal Pull-up, ID=Weak Internal Pull-down
Datasheet
27
LXT9785 — Advanced 10/100 8-Port PHY
Table 2.
SMII PQFP Pin List (Continued)
Pin
Symbol
102
N/C
103
104
Type1
Reference for Full
Description
–
Table 15 on page 50
VCCR0
–
Table 14 on page 49
TPFIP0
AI/AO
Table 10 on page 44
105
TPFIN0
AI/AO
Table 10 on page 44
106
GNDR0
–
Table 14 on page 49
107
TPFOP0
AO/AI
Table 10 on page 44
108
TPFON0
AO/AI
Table 10 on page 44
109
VCCT0/1
–
Table 14 on page 49
110
TPFON1
AO/AI
Table 10 on page 44
111
TPFOP1
AO/AI
Table 10 on page 44
112
GNDR1
–
Table 14 on page 49
113
GNDT0/1
–
Table 14 on page 49
114
TPFIN1
AI/AO
Table 10 on page 44
115
TPFIP1
AI/AO
Table 10 on page 44
116
VCCR1
–
Table 14 on page 49
117
VCCR2
–
Table 14 on page 49
118
TPFIP2
AI/AO
Table 10 on page 44
119
TPFIN2
AI/AO
Table 10 on page 44
120
GNDR2
–
Table 14 on page 49
121
TPFOP2
AO/AI
Table 10 on page 44
122
TPFON2
AO/AI
Table 10 on page 44
123
VCCT2/3
–
Table 14 on page 49
124
TPFON3
AO/AI
Table 10 on page 44
125
TPFOP3
AO/AI
Table 10 on page 44
126
GNDR3
–
Table 14 on page 49
127
GNDT2/3
–
Table 14 on page 49
128
TPFIN3
AI/AO
Table 10 on page 44
129
TPFIP3
AI/AO
Table 10 on page 44
130
VCCR3
–
Table 14 on page 49
131
VCCR4
–
Table 14 on page 49
132
TPFIP4
AI/AO
Table 10 on page 44
133
TPFIN4
AI/AO
Table 10 on page 44
134
GNDT4/5
–
Table 14 on page 49
135
GNDR4
–
Table 14 on page 49
1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,
OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak
Internal Pull-up, ID=Weak Internal Pull-down
28
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Table 2.
SMII PQFP Pin List (Continued)
Pin
Symbol
Type1
Reference for Full
Description
136
TPFOP4
AO/AI
Table 10 on page 44
137
TPFON4
AO/AI
Table 10 on page 44
138
VCCT4/5
–
Table 14 on page 49
139
TPFON5
AO/AI
Table 10 on page 44
140
TPFOP5
AO/AI
Table 10 on page 44
141
GNDR5
–
Table 14 on page 49
142
TPFIN5
AI/AO
Table 10 on page 44
143
TPFIP5
AI/AO
Table 10 on page 44
144
VCCR5
–
Table 14 on page 49
145
VCCR6
–
Table 14 on page 49
146
TPFIP6
AI/AO
Table 10 on page 44
147
TPFIN6
AI/AO
Table 10 on page 44
148
GNDT6/7
–
Table 14 on page 49
149
GNDR6
–
Table 14 on page 49
150
TPFOP6
AO/AI
Table 10 on page 44
151
TPFON6
AO/AI
Table 10 on page 44
152
VCCT6/7
–
Table 14 on page 49
153
TPFON7
AO/AI
Table 10 on page 44
154
TPFOP7
AO/AI
Table 10 on page 44
155
GNDR7
–
Table 14 on page 49
156
TPFIN7
AI/AO
Table 10 on page 44
157
TPFIP7
AI/AO
Table 10 on page 44
158
VCCR7
–
Table 14 on page 49
159
N/C
–
Table 15 on page 50
160
N/C
–
Table 15 on page 50
161
SD4
I
Table 9 on page 44
162
SD5
I
Table 9 on page 44
163
GNDPECL
–
Table 14 on page 49
164
VCCPECL
–
Table 14 on page 49
165
SD6
I
Table 9 on page 44
166
SD7
I
Table 9 on page 44
167
TDI
I, ST, IP
Table 11 on page 45
168
TDO
O, TS
Table 11 on page 45
169
TMS
I, ST, IP
Table 11 on page 45
1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,
OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak
Internal Pull-up, ID=Weak Internal Pull-down
Datasheet
29
LXT9785 — Advanced 10/100 8-Port PHY
Table 2.
SMII PQFP Pin List (Continued)
Pin
Symbol
Type1
Reference for Full
Description
170
TCK
I, ST, ID
Table 11 on page 45
171
TRST
I, ST, IP
Table 11 on page 45
172
N/C
–
Table 15 on page 50
173
G_FX/TP
I, ST, ID
Table 12 on page 46
174
PWRDWN
I, ST, ID
Table 12 on page 46
175
RESET
I, ST, IP
Table 12 on page 46
176
Section
I, ST, ID
Table 12 on page 46
177
ModeSel0
I, ST, ID
Table 12 on page 46
178
ModeSel1
I, ST, ID
Table 12 on page 46
179
SGND
–
Table 14 on page 49
180
LED4_1
OD, TS, SL, IP
Table 13 on page 48
181
LED4_2
OD, TS, SL, IP
Table 13 on page 48
182
LED4_3
OD, TS, SL, IP
Table 13 on page 48
183
GNDD
–
Table 14 on page 49
184
VCCD
–
Table 14 on page 49
185
LED5_1
OD, TS, SL, IP
Table 13 on page 48
186
LED5_2
OD, TS, SL, IP
Table 13 on page 48
187
LED5_3
OD, TS, SL, IP
Table 13 on page 48
188
GNDIO
–
Table 14 on page 49
189
LED6_1
OD, TS, SL, IP
Table 13 on page 48
190
LED6_2
OD, TS, SL, IP
Table 13 on page 48
191
LED6_3
OD, TS, SL, IP
Table 13 on page 48
192
LED7_1
OD, TS, SL, IP
Table 13 on page 48
193
LED7_2
OD, TS, SL, IP
Table 13 on page 48
194
LED7_3
OD, TS, SL, IP
Table 13 on page 48
195
GNDD
–
Table 14 on page 49
196
VCCD
–
Table 14 on page 49
197
N/C
O, TS, ID
Table 4 on page 39
198
RXD7
O, TS
Table 6 on page 41
199
GNDIO
–
Table 14 on page 49
200
N/C
–
Table 15 on page 50
201
N/C
–
Table 15 on page 50
202
N/C
–
Table 15 on page 50
203
TXD7
I, ID
Table 5 on page 41
1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,
OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak
Internal Pull-up, ID=Weak Internal Pull-down
30
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Table 2.
SMII PQFP Pin List (Continued)
Pin
Symbol
204
SYNC1
205
N/C
206
RXD6
207
208
Type1
Reference for Full
Description
I, ID
Table 6 on page 41
–
Table 15 on page 50
O, TS
Table 6 on page 41
GNDIO
–
Table 14 on page 49
VCCIO
–
Table 14 on page 49
1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,
OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak
Internal Pull-up, ID=Weak Internal Pull-down
Datasheet
31
LXT9785 — Advanced 10/100 8-Port PHY
Table 3.
SS-SMII PQFP Pin List
Pin
Symbol
Type1
Reference for Full
Description
1
N/C
–
Table 15 on page 50
2
N/C
–
Table 15 on page 50
3
N/C
–
Table 15 on page 50
4
TXD6
I, ID
Table 5 on page 41
5
N/C
I, ID
Table 15 on page 50
6
REFCLK1
7
RXD5
8
9
I
Table 5 on page 41
O, TS, ID
Table 7 on page 42
N/C
–
Table 15 on page 50
GNDIO
–
Table 14 on page 49
10
N/C
–
Table 15 on page 50
11
N/C
–
Table 15 on page 50
12
N/C
–
Table 15 on page 50
13
TXD5
I, ID
Table 5 on page 41
14
N/C
15
RXD4
16
N/C
17
RX_SYNC1
–
Table 15 on page 50
O, TS, ID
Table 7 on page 42
–
Table 15 on page 50
O, TS, ID
Table 7 on page 42
18
VCCIO
–
Table 14 on page 49
19
GNDIO
–
Table 14 on page 49
20
N/C
–
Table 15 on page 50
21
RX_CLK1
O, TS, ID
Table 7 on page 42
22
TXD4
I, ID
Table 5 on page 41
23
N/C
–
Table 15 on page 50
24
MDC1
I, ST, ID
Table 8 on page 43
25
MDIO1
I/O, TS, SL, IP
Table 8 on page 43
26
MDINT1
OD, TS, SL, IP
Table 8 on page 43
27
RXD3
O, TS, ID
Table 7 on page 42
28
N/C
–
Table 15 on page 50
29
VCCIO
–
Table 14 on page 49
30
GNDIO
–
Table 14 on page 49
31
N/C
–
Table 15 on page 50
32
TX_CLK0
I, ID
Table 7 on page 42
33
N/C
–
Table 15 on page 50
1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,
OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak
Internal Pull-up, ID=Weak Internal Pull-down
32
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Table 3.
SS-SMII PQFP Pin List (Continued)
Pin
Symbol
34
TXD3
35
TX_SYNC0
36
RXD2
37
Type1
Reference for Full
Description
I, ID
Table 5 on page 41
I, ID
Table 7 on page 42
O, TS, ID
Table 7 on page 42
N/C
–
Table 15 on page 50
38
GNDIO
–
Table 14 on page 49
39
N/C
–
Table 15 on page 50
40
N/C
–
Table 15 on page 50
41
N/C
–
Table 15 on page 50
42
TXD2
I, ID
Table 5 on page 41
43
N/C
–
Table 15 on page 50
44
REFCLK0
I
Table 5 on page 41
45
RXD1
O, TS, ID
Table 7 on page 42
46
N/C
–
Table 15 on page 50
47
VCCIO
–
Table 14 on page 49
48
GNDIO
–
Table 14 on page 49
49
N/C
–
Table 15 on page 50
50
PAUSE
I, ID
Table 12 on page 46
51
N/C
52
TXD1
–
Table 15 on page 50
I, ID
Table 5 on page 41
53
N/C
–
Table 15 on page 50
54
RXD0
O, TS, ID
Table 7 on page 42
55
56
N/C
–
Table 15 on page 50
VCCIO
–
Table 14 on page 49
57
GNDIO
–
Table 14 on page 49
58
RX_SYNC0
O, TS, ID
Table 7 on page 42
59
MDIX
I, ID
Table 12 on page 46
60
RX_CLK0
–
Table 7 on page 42
61
TXD0
I, ID
Table 5 on page 41
62
N/C
–
Table 15 on page 50
63
MDC0
I, ST, ID
Table 8 on page 43
64
MDIO0
I/O, TS, SL, IP
Table 8 on page 43
65
VCCD
–
Table 14 on page 49
66
GNDD
–
Table 14 on page 49
67
MDINT0
OD, TS, SL, IP
Table 8 on page 43
1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,
OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak
Internal Pull-up, ID=Weak Internal Pull-down
Datasheet
33
LXT9785 — Advanced 10/100 8-Port PHY
Table 3.
SS-SMII PQFP Pin List (Continued)
Pin
Symbol
Type1
Reference for Full
Description
68
LED3_3
OD, TS, SO, IP
Table 13 on page 48
69
LED3_2
OD, TS, SL, IP
Table 13 on page 48
70
LED3_1
OD, TS, SL, IP
Table 13 on page 48
71
LED2_3
OD, TS, SL, IP
Table 13 on page 48
72
LED2_2
OD, TS, SL, IP
Table 13 on page 48
73
LED2_1
OD, TS, SL, IP
Table 13 on page 48
74
GNDIO
–
Table 14 on page 49
75
LED1_3
OD, TS, SL, IP
Table 13 on page 48
76
LED1_2
OD, TS, SL, IP
Table 13 on page 48
77
LED1_1
OD, TS, SL, IP
Table 13 on page 48
78
VCCD
–
Table 14 on page 49
79
GNDD
–
Table 14 on page 49
80
LED0_3
OD, TS, SL, IP
Table 13 on page 48
81
LED0_2
OD, TS, SL, IP
Table 13 on page 48
82
LED0_1
OD, TS, SL, IP
Table 13 on page 48
83
AMDIX_EN
I, ST, IP
Table 12 on page 46
84
MDDIS
I, ST, ID
Table 8 on page 43
85
CFG_3
I, ST, ID
Table 12 on page 46
86
CFG_2
I, ST, ID
Table 12 on page 46
87
CFG_1
I, ST, ID
Table 12 on page 46
88
ADD_4
I, ST, ID
Table 12 on page 46
89
ADD_3
I, ST, ID
Table 12 on page 46
90
ADD_2
I, ST, ID
Table 12 on page 46
91
ADD_1
I, ST, ID
Table 12 on page 46
92
ADD_0
I, ST, ID
Table 12 on page 46
93
TxSLEW_1
I, ST, ID
Table 12 on page 46
94
TxSLEW_0
I, ST, ID
Table 12 on page 46
95
SD_2P5V
I, ST, ID
Table 9 on page 44
96
SD0
I
Table 9 on page 44
97
SD1
I
Table 9 on page 44
98
VCCPECL
–
Table 14 on page 49
99
GNDPECL
–
Table 14 on page 49
100
SD2
I
Table 9 on page 44
101
SD3
I
Table 9 on page 44
1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,
OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak
Internal Pull-up, ID=Weak Internal Pull-down
34
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Table 3.
SS-SMII PQFP Pin List (Continued)
Pin
102
Symbol
N/C
Type1
Reference for Full
Description
–
Table 15 on page 50
103
VCCR0
–
Table 14 on page 49
104
TPFIP0
AI/AO
Table 10 on page 44
105
TPFIN0
AI/AO
Table 10 on page 44
106
GNDR0
–
Table 14 on page 49
107
TPFOP0
AO/AI
Table 10 on page 44
108
TPFON0
AO/AI
Table 10 on page 44
109
VCCT0/1
–
Table 14 on page 49
110
TPFON1
AO/AI
Table 10 on page 44
111
TPFOP1
AO/AI
Table 10 on page 44
112
GNDR1
–
Table 14 on page 49
113
GNDT0/1
–
Table 14 on page 49
114
TPFIN1
AI/AO
Table 10 on page 44
115
TPFIP1
AI/AO
Table 10 on page 44
116
VCCR1
–
Table 14 on page 49
117
VCCR2
–
Table 14 on page 49
118
TPFIP2
AI/AO
Table 10 on page 44
119
TPFIN2
AI/AO
Table 10 on page 44
120
GNDR2
–
Table 14 on page 49
121
TPFOP2
AO/AI
Table 10 on page 44
122
TPFON2
AO/AI
Table 10 on page 44
123
VCCT2/3
–
Table 14 on page 49
124
TPFON3
AO/AI
Table 10 on page 44
125
TPFOP3
AO/AI
Table 10 on page 44
126
GNDR3
–
Table 14 on page 49
127
GNDT2/3
–
Table 14 on page 49
128
TPFIN3
AI/AO
Table 10 on page 44
129
TPFIP3
AI/AO
Table 10 on page 44
130
VCCR3
–
Table 14 on page 49
131
VCCR4
–
Table 14 on page 49
132
TPFIP4
AI/AO
Table 10 on page 44
133
TPFIN4
AI/AO
Table 10 on page 44
134
GNDT4/5
–
Table 14 on page 49
135
GNDR4
–
Table 14 on page 49
1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,
OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak
Internal Pull-up, ID=Weak Internal Pull-down
Datasheet
35
LXT9785 — Advanced 10/100 8-Port PHY
Table 3.
SS-SMII PQFP Pin List (Continued)
Type1
Reference for Full
Description
TPFOP4
AO/AI
Table 10 on page 44
137
TPFON4
AO/AI
Table 10 on page 44
138
VCCT4/5
–
Table 14 on page 49
139
TPFON5
AO/AI
Table 10 on page 44
140
TPFOP5
AO/AI
Table 10 on page 44
Pin
136
Symbol
141
GNDR5
–
Table 14 on page 49
142
TPFIN5
AI/AO
Table 10 on page 44
143
TPFIP5
AI/AO
Table 10 on page 44
144
VCCR5
–
Table 14 on page 49
145
VCCR6
–
Table 14 on page 49
146
TPFIP6
AI/AO
Table 10 on page 44
147
TPFIN6
AI/AO
Table 10 on page 44
148
GNDT6/7
–
Table 14 on page 49
149
GNDR6
–
Table 14 on page 49
150
TPFOP6
AO/AI
Table 10 on page 44
151
TPFON6
AO/AI
Table 10 on page 44
152
VCCT6/7
–
Table 14 on page 49
153
TPFON7
AO/AI
Table 10 on page 44
154
TPFOP7
AO/AI
Table 10 on page 44
155
GNDR7
–
Table 14 on page 49
156
TPFIN7
AI/AO
Table 10 on page 44
157
TPFIP7
AI/AO
Table 10 on page 44
158
VCCR7
–
Table 14 on page 49
159
N/C
–
Table 15 on page 50
160
N/C
–
Table 15 on page 50
161
SD4
I
Table 9 on page 44
162
SD5
I
Table 9 on page 44
163
GNDPECL
–
Table 14 on page 49
164
VCCPECL
–
Table 14 on page 49
165
SD6
I
Table 9 on page 44
166
SD7
I
Table 9 on page 44
167
TDI
I, ST, IP
Table 11 on page 45
168
TDO
O, TS
Table 11 on page 45
169
TMS
I, ST, IP
Table 11 on page 45
1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,
OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak
Internal Pull-up, ID=Weak Internal Pull-down
36
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Table 3.
SS-SMII PQFP Pin List (Continued)
Pin
Symbol
Type1
Reference for Full
Description
170
TCK
I, ST, ID
Table 11 on page 45
171
TRST
I, ST, IP
Table 11 on page 45
172
N/C
–
Table 15 on page 50
173
G_FX/TP
I, ST, ID
Table 12 on page 46
174
PWRDWN
I, ST, ID
Table 12 on page 46
175
RESET
I, ST, IP
Table 12 on page 46
176
Section
I, ST, ID
Table 12 on page 46
177
ModeSel0
I, ST, ID
Table 12 on page 46
178
ModeSel1
I, ST, ID
Table 12 on page 46
179
SGND
–
Table 14 on page 49
180
LED4_1
OD, TS, SL, IP
Table 13 on page 48
181
LED4_2
OD, TS, SL, IP
Table 13 on page 48
182
LED4_3
OD, TS, SL, IP
Table 13 on page 48
183
GNDD
–
Table 14 on page 49
184
VCCD
–
Table 14 on page 49
185
LED5_1
OD, TS, SL, IP
Table 13 on page 48
186
LED5_2
OD, TS, SL, IP
Table 13 on page 48
187
LED5_3
OD, TS, SL, IP
Table 13 on page 48
188
GNDIO
–
Table 14 on page 49
189
LED6_1
OD, TS, SL, IP
Table 13 on page 48
190
LED6_2
OD, TS, SL, IP
Table 13 on page 48
191
LED6_3
OD, TS, SL, IP
Table 13 on page 48
192
LED7_1
OD, TS, SL, IP
Table 13 on page 48
193
LED7_2
OD, TS, SL, IP
Table 13 on page 48
194
LED7_3
OD, TS, SL, IP
Table 13 on page 48
195
GNDD
–
Table 14 on page 49
196
VCCD
–
Table 14 on page 49
197
RXD7
O, TS, ID
Table 7 on page 42
198
N/C
–
Table 15 on page 50
199
GNDIO
–
Table 14 on page 49
200
N/C
–
Table 15 on page 50
201
TX_CLK1
I, ID
Table 7 on page 42
202
N/C
–
Table 15 on page 50
203
TXD7
I, ID
Table 5 on page 41
1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,
OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak
Internal Pull-up, ID=Weak Internal Pull-down
Datasheet
37
LXT9785 — Advanced 10/100 8-Port PHY
Table 3.
SS-SMII PQFP Pin List (Continued)
Pin
204
Symbol
TX_SYNC1
Type1
Reference for Full
Description
I, ID
Table 7 on page 42
205
RXD6
O, TS, ID
Table 7 on page 42
206
N/C
–
Table 15 on page 50
207
GNDIO
–
Table 14 on page 49
208
VCCIO
–
Table 14 on page 49
1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,
OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak
Internal Pull-up, ID=Weak Internal Pull-down
38
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
1.1
Signal Name Conventions
Signal names may contain either a port designation or a serial designation, or a combination of the
two designations. Signal naming conventions are as follows:
• Port Number Only. Individual signals that apply to a particular port are designated by the
Signal Mnemonic, immediately followed by the Port Designation. For example, Transmit
Enable signals would be identified as TXEN0, TXEN1, and TXEN2.
• Serial Number Only. A set of signals which are not tied to any specific port are designated by
the Signal Mnemonic, followed by an underscore and a serial designation. For example, a set
of three Global Configuration signals would be identified as CFG_1, CFG_2, and CFG_3.
• Port and Serial Number. In cases where each port is assigned a set of multiple signals, each
signal is designated in the following order: Signal Mnemonic, Port Designation, an
underscore, and the serial designation. For example, a set of three Port Configuration signals
would be identified as RXD0_0 and RXD0_1, RXD1_0 and RXD1_1, and RXD2_0 and
RXD2_1.
Table 4.
LXT9785 RMII Signal Descriptions
Pin-Ball
Designation
PQFP
Type1
Symbol
Signal Description2,3
PBGA
44
6
E6,
E12
REFCLK0
REFCLK1
I
Reference Clock. 50 MHz RMII reference clock is always required. RMII
inputs are sampled on the rising edge of REFCLK, RMII outputs are
sourced on the falling edge. See “Clock/SYNC Requirements” on page 58
for detailed CLK requirements.
61
62
E2,
F4
TXD0_0
TXD0_1
I, ID
Transmit Data - Port 0. Inputs containing 2-bit parallel di-bits to be
transmitted from port 0 are clocked in synchronously to REFCLK.
52
53
C3,
D4
TXD1_0
TXD1_1
I, ID
Transmit Data - Port 1. Inputs containing 2-bit parallel di-bits to be
transmitted from Port 1 are clocked in synchronously to REFCLK
42
43
B5
A4
TXD2_0
TXD2_1
I, ID
Transmit Data - Port 2. Inputs containing 2-bit parallel di-bits to be
transmitted from port 2 are clocked in synchronously to REFCLK.
34
35
D8,
A6
TXD3_0
TXD3_1
I, ID
Transmit Data - Port 3. Inputs containing 2-bit parallel di-bits to be
transmitted from Port 3 are clocked in synchronously to REFCLK.
22
23
A11,
C10
TXD4_0
TXD4_1
I, ID
Transmit Data - Port 4. Inputs containing 2-bit parallel di-bits to be
transmitted from Port 4 are clocked in synchronously to REFCLK.
13
14
B13,
D11
TXD5_0
TXD5_1
I, ID
Transmit Data - Port 5. Inputs containing 2-bit parallel di-bits to be
transmitted from Port 5 are clocked in synchronously to REFCLK.
4
5
D13,
A16
TXD6_0
TXD6_1
I, ID
Transmit Data - Port 6. Inputs containing 2-bit parallel di-bits to be
transmitted from Port 6 are clocked in synchronously to REFCLK.
203
204
E14,
C16
TXD7_0
TXD7_1
I, ID
Transmit Data - Port 7. Inputs containing 2-bit parallel di-bits to be
transmitted from Port 7 are clocked in synchronously to REFCLK.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able
output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID resistors are also
disabled when the output is enabled.
3. RXD[0:7]_0, RXD[0:7]_1, CRS_DV[0:7] and RXER[0:7] outputs are tri-stated in Isolation and H/W Power-Down modes and
during H/W reset.
Datasheet
39
LXT9785 — Advanced 10/100 8-Port PHY
Table 4.
LXT9785 RMII Signal Descriptions (Continued)
Pin-Ball
Designation
PQFP
Symbol
Type1
Signal Description2,3
PBGA
60
51
41
33
21
12
3
202
E3,
B2,
C6,
A7,
B11,
A14,
C14,
D16
TXEN0
TXEN1
TXEN2
TXEN3
TXEN4
TXEN5
TXEN6
TXEN7
I, ID
Transmit Enable - Ports 0-7. Active High input enables respective port
transmitter. This signal must be synchronous to the REFCLK.
55
54
C2,
B1
RXD0_0
RXD0_1
O, TS
O, TS, ID
Receive Data - Port 0. Receive data signals (2-bit parallel di-bits) are
driven synchronously to REFCLK.
46
45
A3,
B4
RXD1_0
RXD1_1
O, TS
O, TS, ID
Receive Data - Port 1. Receive data signals (2-bit parallel di-bits) are
driven synchronously to REFCLK.
37
36
B6,
C7
RXD2_0
RXD2_1
O, TS
O, TS, ID
Receive Data - Port 2. Receive data signals (2-bit parallel di-bits) are
driven synchronously to REFCLK.
28
27
D9,
B9
RXD3_0
RXD3_1
O, TS
O, TS, ID
Receive Data - Port 3. Receive data signals (2-bit parallel di-bits) are
driven synchronously to REFCLK.
16
15
A13,
C12
RXD4_0
RXD4_1
O, TS
O, TS, ID
Receive Data - Port 4. Receive data signals (2-bit parallel di-bits) are
driven synchronously to REFCLK.
8
7
B14,
B15
RXD5_0
RXD5_1
O, TS
O, TS, ID
Receive Data - Port 5. Receive data signals (2-bit parallel di-bits) are
driven synchronously to REFCLK.
206
205
C15,
B17
RXD6_0
RXD6_1
O, TS
O, TS, ID
Receive Data - Port 6. Receive data signals (2-bit parallel di-bits) are
driven synchronously to REFCLK.
198
197
E16,
F14
RXD7_0
RXD7_1
O, TS
O, TS, ID
Receive Data - Port 7. Receive data signals (2-bit parallel di-bits) are
driven synchronously to REFCLK.
58
49
39
31
17
10
1
200
E4,
C4,
A5,
B8,
B12,
D12,
B16,
E15
CRS_DV0
CRS_DV1
CRS_DV2
CRS_DV3
CRS_DV4
CRS_DV5
CRS_DV6
CRS_DV7
O, TS, SL,
ID
Carrier Sense/Receive Data Valid - Ports 0-7. On detection of valid
carrier, these signals are asserted asynchronously with respect to
REFCLK. CRS_DVn is deasserted on loss of carrier, synchronous to
REFCLK.
59
50
40
32
20
11
2
201
D2,
D5,
D7,
C8,
A12,
A15,
A17,
D17
RXER0
RXER1
RXER2
RXER3
RXER4
RXER5
RXER6
RXER7
O, TS, SL,
ID
Receive Error - Ports 0-7. These signals are synchronous to the
respective REFCLK. Active High indicates that received code group is
invalid, or that PLL is not locked.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able
output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID resistors are also
disabled when the output is enabled.
3. RXD[0:7]_0, RXD[0:7]_1, CRS_DV[0:7] and RXER[0:7] outputs are tri-stated in Isolation and H/W Power-Down modes and
during H/W reset.
40
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Table 5.
LXT9785 SMII / SS-SMII Common Signal Descriptions
Pin/Ball
Designation
PQFP
Type1
Symbol
Signal Description2
PBGA
61
52
42
34
22
13
4
203
E2,
C3,
B5,
D8,
A11,
B13,
D13,
E14
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
I, ID
Transmit Data - Ports 0-7. These serial input streams provide data to be
transmitted to the network. The LXT9785 clocks the data in synchronously to
REFCLK.
44
6
E6,
REFCLK0
REFCLK1
I
Reference Clock. The LXT9785 always requires a 125 MHz reference clock
input. Refer to Functional Description for detailed clock requirements. REFCLK0
and REFCLK1 are always connected regardless of sectionalization mode.
E12
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able
output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.
2. The IP/ID resistors are disabled during H/W Power-Down mode.
Table 6.
LXT9785 SMII Specific Signal Descriptions
Pin/Ball
Designation
PQFP
Symbol
Type1
Signal Description2,3
PBGA
35
204
A6,
C16
SYNC0
SYNC1
55
46
37
28
16
8
206
198
C2,
A3,
B6,
D9,
A13,
B14,
C15,
E16
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
I, ID
SMII Synchronization. The MAC must generate a SYNC pulse every 10
REFCLK cycles to synchronize the SMII. SYNC0 is used when 1x8 port
sectionalization is selected. SYNC0 and SYNC1 are to be used when 2x4
port sectionalization is chosen.
O, TS
Receive Data - Ports 0-7. These serial output streams provide data
received from the network. The LXT9785 drives the data out synchronously
to REFCLK.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able
output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.
2. The IP/ID resistors are disabled during H/W Power-Down mode.
3. RXD[0:7] outputs are tri-stated in Isolation and H/W Power-Down modes and during H/W reset.
Datasheet
41
LXT9785 — Advanced 10/100 8-Port PHY
Table 7.
LXT9785 SS-SMII Specific Signal Descriptions
Pin/Ball
Designation
PQFP
Symbol
Type1
Signal Description2,3
PBGA
35
204
A6,
C16
TX_SYNC0
TX_SYNC1
58
17
E4,
B12
RX_SYNC0
32
201
C8,
D17
TX_CLK0
TX_CLK1
RX_SYNC1
I, ID
SS-SMII Transmit Synchronization. The MAC must generate a TX_SYNC
pulse every 10 TX_CLK cycles to mark the start of TXD segments.
TX_SYNC0 is used when 1x8 port sectionalization is selected.
O, TS,
ID
SS-SMII Receive Synchronization. The LXT9785 generates these pulses
every 10 RX_CLK cycles to mark the start of RXD segments for the MAC.
RX_SYNC1 is used and RX_SYNC0 is tri-stated when 1x8 port
sectionalization is selected. These outputs are only enabled when SS-SMII
mode is enabled.
I, ID
SS-SMII Transmit Clock. The MAC sources this 125 MHz clock as the
timing reference for TXD and TX_SYNC. Only TX_CLK0 is used when 1x8
port sectionalization is selected. See “Clock/SYNC Requirements” on page 58 for
detailed clock requirements.
60
21
E3,
B11
RX_CLK0
RX_CLK1
O, TS,
ID
SS-SMII Receive Clock. The LXT9785 generates these clocks, based on
REFCLK, to provide a timing reference for RXD and RX_SYNC to the MAC.
RX_CLK1 used and RX_CLK0 is tri-stated when 1x8 port sectionalization is
selected. See “Clock/SYNC Requirements” on page 58 for detailed clock
requirements. These outputs are only enabled when SS-SMII mode is
enabled.
54
45
36
27
15
7
205
197
B1,
B4,
C7,
B9,
C12,
B15,
B17,
F14
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
O, TS,
ID
Receive Data - Ports 0-7. These serial output streams provide data received
from the network. The LXT9785 drives the data out synchronously to
REFCLK.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able
output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID resistors are also
disabled when the output is enabled.
3. RXD[0:7], RXSYNC[0:1], and RXCLK[0:1] outputs are tri-stated in Isolation and H/W Power-Down modes and during H/W
reset.
42
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Table 8.
MDIO Control Interface Signals
Pin/Ball
Designation
PQFP
64
25
67
26
63
24
Symbol
Type1
Signal Description2,3,4
PBGA
F3,
A10
F1,
C9
E1,
B10
MDIO0
MDIO1
MDINT0
MDINT1
MDC0
MDC1
I/O, TS, SL,
IP
OD,TS, SL,
IP
I, ST, ID
Management Data Input/Output. Bidirectional serial data channel for
communication between the PHY and MAC or switch ASIC. Only MDIO0
is used when 1x8 port sectionalization is selected. In 2x4 port
sectionalization mode, MDIO0 accesses ports 0-3 and MDIO1 accesses
Ports 4-7. For an example, refer to Figure 22 on page 72.
Management Data Interrupt. When bit 18.1 = 1, an active Low output on
this Pin indicates status change. Only MDINT0 is used when 1x8 port
sectionalization is selected. In 2x4 port sectionalization mode, MDINT0
is associated with Ports 0-3 and MDINT1 is associated with Ports 4-7. For
an example, refer to Figure 22 on page 72.
Management Data Clock. Clock for the MDIO serial data channel.
Maximum frequency is 20 MHz. Only MDC0 is used when 1x8 port
sectionalization is selected. In 2x4 port sectionalization mode, MDC0
clocks Ports 0-3 register accesses and MDC1 clocks Ports 4-7 register
accesses. For an example, refer to Figure 22 on page 72.
Management Disable. When MDDIS is tied High, the MDIO port is
completely disabled and the Hardware Control Interface pins set their
respective bits at power up and reset.
84
L1
MDDIS
I, ST, ID
When MDDIS is pulled Low at power up or reset, via the internal pull-down
resistor or by tieing it to ground, the Hardware Control Interface Pins
control only the initial or “default” values of their respective register bits.
After the power-up/reset cycle is complete, bit control reverts to the MDIO
serial channel.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able
output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID resistors are also
disabled when the output is enabled.
3. MDIO[0:1] and MDINT[0:1] outputs are tri-stated in H/W Power-Down mode and during H/W reset.
4. Supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation, where X is the
register number (0-32) and Y is the bit number (0-15).
Datasheet
43
LXT9785 — Advanced 10/100 8-Port PHY
Table 9.
LXT9785 Signal Detect
Pin/Ball
Designation
PQFP
Type1
Symbol
Signal Description2,3
PBGA
95
P1
SD_2P5V
96
97
100
101
161
162
165
166
P2,
N4,
P3,
N5,
P15,
P16,
P17,
N17
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
I, ST, ID
Signal Detect 2.5 Volt Interface. When the SD interface is at 2.5 V, tie this
input to VCCPECL. Floating this input or tieing it to GNDPECL indicates that
a 3.3 V SD interface is being used.
Signal Detect - Ports 0-7. The SD inputs are only applicable for ports set in
Fiber mode.
I
When SD is high, the process of searching for receive idles for the purpose of
bring link up is initiated.
If SD is low, link is declared lost.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able
output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.
2. The IP/ID resistors are disabled during H/W Power-Down mode.
3. Tie SD[0:7] inputs to GNDPECL if unused.
Table 10. LXT9785 Network Interface Signal Descriptions
Pin/Ball Designation
Symbol
PQFP
Type1
Signal Description
PBGA
107, 108
111, 110
121, 122
125, 124
136, 137
140, 139
150, 151
154, 153
T2, U1,
T3, R4,
T6, U5,
U7, T7,
T10, R10,
T11, U11,
T14,U15,
R14, T15
TPFOP0, TPFON0
TPFOP1, TPFON1
TPFOP2, TPFON2
TPFOP3, TPFON3
TPFOP4, TPFON4
TPFOP5, TPFON5
TPFOP6, TPFON6
TPFOP7, TPFON7
104, 105
115, 114
118, 119
129, 128
132, 133
143, 142
146, 147
157, 156
R2, T1,
U3, T4,
R6, T5,
T8, R8,
T9, U9,
U13, T12,
R12, T13,
R16, T16
TPFIP0, TPFIN0
TPFIP1, TPFIN1
TPFIP2, TPFIN2
TPFIP3, TPFIN3
TPFIP4, TPFIN4
TPFIP5, TPFIN5
TPFIP6, TPFIN6
TPFIP7, TPFIN7
Twisted-Pair/Fiber Outputs2, Positive & Negative,
Ports 0-7.
AO/AI
During 100BASE-TX or 10BASE-T operation, TPFO pins drive
802.3 compliant pulses onto the line.
During 100BASE-FX operation, TPFO pins produce differential
PECL outputs for fiber transceivers.
Twisted-Pair/Fiber Inputs3, Positive & Negative,
Ports 0-7.
AI/AO
During 100BASE-TX or 10BASE-T operation, TPFI pins receive
differential 100BASE-TX or 10BASE-T signals from the line.
During 100BASE-FX operation, TPFI pins receive differential
PECL inputs from fiber transceivers.
1. Type Column Coding: AI = Analog Input, AO = Analog Output.
2. Switched to Inputs (see TPFIP/N desc.) when not in Fiber mode and MDIX is not active [i.e., Twisted-Pair, non-crossover MDI
mode].
3. Switched to Outputs (see TPFOP/N desc.) when not in Fiber mode and MDIX is not active [i.e., Twisted-Pair, non-crossover
MDI mode].
44
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Table 11. LXT9785 JTAG Test Signal Descriptions
Pin/Ball
Designation
PQFP
Symbol
Type1
Signal Description2,3
PBGA
167
N14
TDI
I, ST, IP
Test Data Input. Test data sampled with respect to the rising edge of TCK.
168
N15
TDO
O, TS
Test Data Output. Test data driven with respect to the falling edge of TCK.
169
N16
TMS
I, ST, IP
Test Mode Select.
170
M16
TCK
I, ST, ID
Test Clock. Clock input for JTAG test.
171
M17
TRST
I, ST, IP
Test Reset. Reset input for JTAG test.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain, TS = Tri-State-able output, SMT = Schmitt Triggered input, SL
= Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID resistors are also
disabled when the output is enabled.
3. TDO output is tri-stated in H/W Power-Down mode and during H/W reset.
Datasheet
45
LXT9785 — Advanced 10/100 8-Port PHY
Table 12. LXT9785 Miscellaneous Signal Descriptions
Pin/Ball
Designation
PQFP
Symbol
Type1
Signal Description2
PBGA
Tx Output Slew Controls 0 and 1 Defaults.
These pins are read at startup or reset. Their value at that time is used to
set the default state of register bits 27.11:10 for all ports. These register
bits can be read and overwritten after startup / reset.
94
93
N3,
M4
TxSLEW_0
TxSLEW_1
These pins select the TX output slew rate for all ports (rise and fall time)
as follows:
I, ST, ID
TxSLEW_1
TxSLEW_0
Slew Rate (Rise and Fall Time)
0
0
3.3 ns
0
1
3.6 ns
1
0
3.9 ns
1
1
4.2 ns
Pause Default. This pin is read at startup or reset. Its value at that time is
used to set the default state of register bit 4.10 for all ports. This register
bit can be read and overwritten after startup / reset.
50
D5
PAUSE
I, ID
When High, the LXT9785 advertises Pause capabilities on all ports during
auto-negotiation.
This pin is shared with RMII-RXER1. An external pull-up resistor (see
applications section for value) can be used to set Pause active while
RXER1 is tri-stated during H/W reset. If no pull-up is used, the default
Pause state is set inactive via the internal pull-down resistor.
174
L14
PWRDWN
I, ST, ID
Power-Down. When High, forces the LXT9785 into global power-down
mode.
Pin is not on JTAG chain.
175
M15
RESET
I, ST, IP
Reset. This active low input is OR’ed with the control register Reset bit
(0.15). When held Low, all outputs are forced to inactive state.
Pin is not on JTAG chain
Address <4:0>. Sets base address. Each port adds its port number
(starting with 0) to this address to determine its PHY address.
88
89
90
91
92
L4,
M2,
M3,
N1,
N2
ADD_4
ADD_3
ADD_2
ADD_1
ADD_0
I, ST, ID
Port 0 Address = Base
Port 1 Address = Base + 1
Port 2 Address = Base + 2
Port 3 Address = Base + 3
Port 4 Address = Base + 4
Port 5 Address = Base + 5
Port 6 Address = Base + 6
Port 7 Address = Base + 7
Mode Select[1:0]
178
177
L17,
L16
MODESEL_1
MODESEL_0
I, ST, ID
00 = RMII
01 = SMII
10 = SS-SMII
11= Reserved
All ports are configured the same. Interfaces cannot be mixed and must
be all RMII, SMII, or SS-SMII.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able
output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.
2. The IP/ID resistors are disabled during H/W Power-Down mode.
46
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Table 12. LXT9785 Miscellaneous Signal Descriptions (Continued)
Pin/Ball
Designation
PQFP
Symbol
Type1
Signal Description2
PBGA
Sectionalization Select. This pin selects sectionalization into separate
ports.
176
L15
SECTION
I, ST, ID
0 = 1x8 ports,
1 = 2x4 ports
83
K1
AMDIX_EN
I, ST, IP
Auto-MDIX Enable Default. This pin is read at startup or reset. Its value
at that time is used to set the default state of register bit 27.9 for all ports.
These register bits can be read and overwritten after startup / reset. Refer
to Table 16 on page 53.
When active (high), automatic MDI crossover (MDIX) (regardless of
segmentation) is selected for all ports. When inactive (low) MDIX is
selected according to the MDIX pin.
MDIX Select Default. This pin is read at startup or reset. Its value at that
time is used to set the default state of register bit 27.8 for all ports. These
register bits can be read and overwritten after startup / reset. Refer to
Table 16 on page 53.
When AMDIX_EN is active this pin is ignored.
59
D2
MDIX
I, ID
When AMDIX_EN is inactive, all ports are forced to the MDI or the MDIX
function regardless of segmentation. If this pin is active (high), MDI
crossover (MDIX) is selected. If this pin is inactive, non-crossover MDI
mode is set.
This pin is shared with RMII-RXER0. An external pull-up resistor (see
applications section for value) can be used to set MDIX active while
RXER0 is tri-stated during H/W reset. If no pull-up is used, the default
MDIX state is set inactive via the internal pull-down resistor. Do not tie this
pin directly to VCCIO (vs. using a pull-up) in non-RMII modes.
85
86
87
173
L2,
L3,
M1
M14
CFG_3
CFG_2
CFG_1
G_FX/TP
I, ST, ID
Global Port Configuration Defaults 1-3. These pins are read at startup
or reset. Their value at that time is used to set the default state of register
bits shown in Table 18 on page 62 for all ports. These register bits can be
read and overwritten after startup / reset.
When operating in Hardware Control Mode, these pins provide
configuration control options for all the ports (refer to page 62 for details).
I, ST, ID
Global FX/TP Enable Default. This pin is read at startup or reset. Its
value at that time is used to set the default state of register bit 16.0 for all
ports. These register bits can be read and overwritten after startup /
reset. Refer to “Port Configuration Register (Address 16, Hex 10)” on
page 127.
This input selects whether all the ports are defaulted to TP vs. FX mode.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able
output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.
2. The IP/ID resistors are disabled during H/W Power-Down mode.
Datasheet
47
LXT9785 — Advanced 10/100 8-Port PHY
Table 13. LXT9785 LED Signal Descriptions
Pin/Ball
Designation
PQFP
Symbol
Type1
Signal Description2,3
PBGA
82
81
80
K3,
K2,
J1
LED0_1
LED0_2
LED0_3
OD, TS, SL,
IP
Port 0 LED Drivers 1-3. These pins drive LED indicators for Port 0.
Each LED can display one of several available status conditions as
selected by the LED Configuration Register (refer to Table 70 on
page 131 for details).
77
76
75
J4,
J3,
H1
LED1_1
LED1_2
LED1_3
OD, TS, SL,
IP
Port 1 LED Drivers 1-3. These pins drive LED indicators for Port 1.
Each LED can display one of several available status conditions as
selected by the LED Configuration Register (refer to Table 70 on
page 131 for details).
73
72
71
H2,
H3,
G1
LED2_1
LED2_2
LED2_3
OD, TS, SL,
IP
Port 2 LED Drivers 1-3. These pins drive LED indicators for Port 2.
Each LED can display one of several available status conditions as
selected by the LED Configuration Register (refer to Table 70 on
page 131 for details).
70
69
68
F2,
G3,
G4
LED3_1
LED3_2
LED3_3
OD, TS, SL,
IP
Port 3 LED Drivers 1-3. These pins drive LED indicators for Port 3.
Each LED can display one of several available status conditions as
selected by the LED Configuration Register (refer to Table 70 on
page 131 for details).
180
181
182
K16,
K17,
J17
LED4_1
LED4_2
LED4_3
OD, TS, SL,
IP
Port 4 LED Drivers 1-3. These pins drive LED indicators for Port 4.
Each LED can display one of several available status conditions as
selected by the LED Configuration Register (refer to Table 70 on
page 131 for details).
185
186
187
J15,
J16,
H17
LED5_1
LED5_2
LED5_3
OD, TS, SL,
IP
Port 5 LED Drivers 1-3. These pins drive LED indicators for Port 5.
Each LED can display one of several available status conditions as
selected by the LED Configuration Register (refer to Table 70 on
page 131 for details).
189
190
191
H15,
H16,
G17
LED6_1
LED6_2
LED6_3
OD, TS, SL,
IP
Port 6 LED Drivers 1-3. These pins drive LED indicators for Port 6.
Each LED can display one of several available status conditions as
selected by the LED Configuration Register (refer to Table 70 on
page 131 for details).
192
193
194
G15,
F17,
F16
LED7_1
LED7_2
LED7_3
OD, TS, SL,
IP
Port 7 LED Drivers 1-3. These pins drive LED indicators for Port 7.
Each LED can display one of several available status conditions as
selected by the LED Configuration Register (refer to Table 70 on
page 131 for details).
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able
output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID resistors are also
disabled when the output is enabled.
3. The LED outputs are tri-stated in H/W Power-Down mode and during H/W reset.
48
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Table 14. LXT9785 Power Supply Signal Descriptions
Pin/Ball Designation
Symbol
PQFP
Type
Signal Description
PBGA
65, 78, 184,
196
G13, J14,
F5, J5
18, 29, 47,
56, 208
A2, A8,
C1, C11,
D14
98, 164
-
Digital Power Supply - Core. +2.5V supply for core digital circuits.
VCCIO
-
Digital Power Supply - I/O Ring. +2.5/3.3V supply for digital I/O
circuits. The digital input circuits running off of this rail, having a TTL-level
threshold and over-voltage protection, may be interfaced with 3.3/5.0 V,
when the IO supply is 3.3V, and 2.5/3.3/5.0 V when 2.5V.
L13, L5
VCCPECL
-
Digital Power Supply - PECL Signal Detect Inputs. +2.5/3.3V supply
for PECL Signal Detect input circuits. If Fiber Mode is not used, tie these
pins to GNDPECL to save power.
103, 116,
117, 130,
131, 144,
145, 158
N13, P4,
P7, P8,
P9, P10,
P11, P12
VCCR
-
Analog Power Supply - Receive. +2.5V supply for all analog receive
circuits.
109, 123,
138, 152
N6, N7,
N9, N11,
N12
VCCT
-
Analog Power Supply - Transmit. +2.5V supply for all analog transmit
circuits.
66, 79,
183, 195
A1, A9,
B3, B7,
C5, C13,
C17, D1,
D3, D6,
D10, D15,
E5, E7,
E9, E11,
E13, E17,
F13, H8,
H9, H10,
J8, J9,
J10, K8,
K9, K10
GNDD
-
Digital Ground. Ground return for core digital supplies (VCCD). All
ground pins can be tied together using a single ground plane.
GNDIO
-
Digital GND - I/O Ring. Ground return for digital I/O circuits (VCCIO).
9, 19, 30,
38, 48, 57,
74, 188,
199, 207
VCCD
99, 163
M5, M13
GNDPECL
-
Digital GND - PECL Signal Detect Inputs. Ground return for PECL
Signal Detect input circuits.
106, 112,
120, 126,
135, 141,
149, 155
P5, P6,
P13, R7,
R9, R11,
R13, U8
GNDR
-
Analog Ground - Receive. Ground return for receive analog supply. All
ground pins can be tied together using a single ground plane.
113, 127,
134, 148
P14, R1,
R3, R5,
R15, R17,
T17, U2,
U4, U6,
U10, U12,
U14, U16,
U17
GNDT
-
Analog Ground - Transmit. Ground return for transmit analog supply.
All ground pins can be tied together using a single ground plane.
179
K14
SGND
-
Substrate Ground. Ground for chip substrate. All ground pins can be
tied together using a single ground plane.
Datasheet
49
LXT9785 — Advanced 10/100 8-Port PHY
Table 15. Unused / Reserved Pins
Pin/Ball Designation
Symbol
PQFP
N/C
Type1
Signal Description
PBGA
F15, G2,
G5, G14,
G16, H4,
H14, J2,
J13, K4,
K15
N/C
No Connection.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able
output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.
50
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
2.0
Functional Description
2.1
Introduction
The LXT9785 is an 8-port Fast Ethernet 10/100 PHY transceiver that supports 10Mbps and
100Mbps networks, complying with all applicable requirements of IEEE 802.3 standards. The
device incorporates a Serial MII (SMII), Source Synchronous SMII (SS-SMII), and a Reduced MII
(RMII) to enable each individual network port to interface with multiple 10/100 MACs. Each port
directly drives either a 100BASE-TX line or a 10BASE-T line. The LXT9785 also supports
100BASE-FX operation via a Pseudo-ECL (PECL) interface. The device has a 241-pin BGA or a
208- pin QFP package.
2.1.1
OSP™ Architecture
The Intel LXT9785 incorporates high-efficiency Optimal Signal Processing™ design techniques,
combining the best properties of digital and analog signal processing to produce a truly optimal
device.
The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by
as much as 3 dB over an ideal all-analog equalizer. Using OSP mixed-signal processing techniques
in the receive equalizer avoids the quantization noise and calculation truncation errors found in
traditional DSP-based receivers (typically complex DSP engines with A/D converters). The result
is improved receiver noise and cross-talk performance.
The OSP architecture also requires substantially less computational logic than traditional DSPbased designs. The result is lower power consumption and reduced logic switching noise generated
by DSP engines clocked at speeds up to 125 MHz. The logic switching noise can be a considerable
source of EMI when generated from the device’s power supplies.
The OSP-based LXT9785 provides improved data recovery, EMI performance and power
consumption.
2.1.2
Comprehensive Functionality
The LXT9785 performs all functions of the Physical Coding Sublayer (PCS) and Physical Media
Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X specification. This device
also performs all functions of the Physical Media Dependent (PMD) sublayer for 100BASE-TX
connections.
On power-up, the LXT9785 reads its configuration inputs to check for forced operation settings. If
not configured for forced operation, each port uses auto-negotiation/parallel detection to
automatically determine line operating conditions. If the PHY device on the other side of the link
supports auto-negotiation, the LXT9785 auto-negotiates with it using Fast Link Pulse (FLP)
Bursts. If the PHY partner does not support auto-negotiation, the LXT9785 automatically detects
the presence of either link pulses (10Mbps PHY) or Idle symbols (100Mbps PHY) and set its
operating conditions accordingly.
The LXT9785 provides half-duplex and full-duplex operation at 100Mbps and10Mbps.
Datasheet
51
LXT9785 — Advanced 10/100 8-Port PHY
2.1.2.1
Sectionalization
The LXT9785’s sectional design allows flexibility with large multiport MACs and ASICs. With the
use of the Section pin, the LXT9785 can be configured into a single 8-port or two separate 4-port
sections, each with its own MDIO (with separate MDC clock) and MII data (with separate
REFCLK/TX_CLK/RX_CLK clocks) interfaces. See Figure 17 on page 66, Figure 22 on page 72,
and Figure 27 on page 77.
2.2
Interface Descriptions
2.2.1
10/100 Network Interface
The LXT9785 supports both 10BASE-T and 100BASE-TX Ethernet over twisted-pair, or
100Mbps Ethernet over fiber media (100BASE-FX). Each network interface port consists of four
external pins (two differential signal pairs). The pins are shared between twisted-pair (TP) and
fiber. The LXT9785 pinout is designed to interface seamlessly with dual-high stacked RJ-45
connectors. Refer to Table 10 on page 44 for specific pin assignments.
The LXT9785 output drivers generate either 100BASE-TX, 10BASE-T, or 100BASE-FX output.
When not transmitting data, the device generates IEEE 802.3-compliant link pulses or idle code.
Input signals are decoded either as a 100BASE-TX, 100BASE-FX, or 10BASE-T input, depending
on the mode selected. Auto-negotiation/parallel detection or manual control is used to determine
the speed of this interface.
Figure 8. LXT9785 Interfaces
TXENn
TXDn_0
TPFOPn
TXDn_1
DATA
I/F
TXCLK
TPFONn
RXCLK
RXDn_1
TPFIPn
RXDn_0
TPFINn
Network
I/F
RXERn
CRS_DVn
MDIOn
MDIO
Mgmt
I/F
MDCn
MDINTn
MDDIS
Direct Drive
Port LEDs/
Controls
Addr &
MDIX/
Contr
LEDn_2
LEDn_2
LEDn_3
MDIX_Enb
VCCIO
+3.3V
OR
+2.5V
VCCD
+2.5V
Mode Select
ADD<4:0>
GNDD
.01uF
52
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
2.2.1.1
Twisted-Pair Interface
The LXT9785 supports either 100BASE-TX or 10BASE-T connections over 100Ω, Category 5,
Unshielded Twisted-Pair (UTP). Only a transformer, load resistors, RJ-45, and bypass capacitors
are required to complete this interface. Using Intel’s patented waveshaping technology, the
transmitter shapes the outgoing signal to help reduce the need for external EMI filters. Four slew
rate settings (refer to Table 12 on page 46) allow the designer to match the output waveform to the
magnetic characteristics. Both transmit and receive terminations are built into the LXT9785 so no
external components are required between the LXT9785 and the external transformer. The
transmitter uses a transformer with a center tap to help reduce power consumption.
When operating at 100Mbps, MLT3 symbols are continuously transmitted and received. When not
transmitting data, the LXT9785 generates “IDLE” symbols.
During 10Mbps operation, LXT9785 encoded data is exchanged. When no data are being
exchanged, the line is left in an idle state.
2.2.1.2
MDI Crossover (MDIX)
The LXT9785 crossover function, which is compliant to the IEEE 802.3, clause 23 standard,
connects the transmit output of the device to the far-end receiver in a link segment. This function
can be disabled via register bit 27.9:8 or by using the hardware configuration pins.
Table 16. MDIX Selection
AMDIX_EN
2.2.1.3
MDIX
MDIX Mode
0
0
MDIX Disabled
0
1
MDIX forced
1
X
AUTO-MDIX
Fiber Interface
The LXT9785 provides a PECL interface that complies with the ANSI X3.166 specification. This
interface is suitable for driving a fiber-optic coupler (see Figure 35 on page 93).
Fiber ports cannot be enabled via auto-negotiation and must be enabled via the Global Hardware
Control Interface pins or MDIO registers. All ports are selected for fiber or twisted-pair when
configured via hardware, and can only be intermixed via software. Using external circuitry, the
LXT9785 can interface the fiber transceiver with 2.5V, 3.3V, or 5V supply voltages. Fiber mode
per port may be selected using register 16.0. Please refer to Table 10 on page 44 for correct pin
assignments.
2.3
Media Independent Interface (MII) Interfaces
The LXT9785 supports Reduced MII or Serial MII, but not concurrently. The interface mode
selection pins configures the device for either RMII or SMII/SS-SMII on all eight ports. Refer to
Table 17 for the mode select settings.
Datasheet
53
LXT9785 — Advanced 10/100 8-Port PHY
2.3.1
Global MII Mode Select
The mode select pins are used for MII interface configuration settings upon power-up sequencing.
All ports are configured the same and cannot be intermixed.
Table 17. MII Mode Select
2.3.2
ModeSel1
ModeSel0
RMII
0
0
SMII
0
1
SS-SMII
1
0
Reserved
1
1
Internal Loopback
A test loopback function is available for 10Mbps and 100Mbps mode testing. Bits 0.8, 0.13, and
0.14 must be set to 1 for correct operation. When data is looped back, whatever the MAC transmits
is looped back in its entirety, including the preamble.
Figure 9. Internal Loopback
LXT9785
RMII/
SMII/
SSSMII
inter
face
2.3.3
Fx
Driver
Digital
Block
Loopback
Analog
Block
Tx
Driver
RMII Data Interface
The LXT9785 provides a separate RMII for each network port, each complying with the RMII
standard. The RMII includes both a data interface and an MDIO management interface. The RMII
Data Interface exchanges data between the LXT9785 and up to eight Media Access Controllers
(MACs).
2.3.4
Serial Media Independent Interface (SMII) and Source Synchronous
Data Interfaces
2.3.4.1
SMII Interface
The LXT9785 provides an independent serial interface for each network port. All SMII ports use a
common reference clock and SYNC signal. The SMII Data Interface exchanges data between the
LXT9785 and multiple Media Access Controllers (MACs). All signals are synchronous to the
54
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
reference clock. One SYNC control stream is sourced by the MAC to the PHY. Both the transmit
and receive data streams are segmented into boundaries delimited by the SYNC pulses. This
interface is expected to operate up to 6 inches of trace lengths.
2.3.4.2
Source Synchronous Interface
The new revision to the SMII interface, SS-SMII, allows for a longer trace length and helps to
relieve timing constraints, requiring the addition of four new signals, TxCLK, TxSYNC, RxCLK,
and RxSYNC. The transmit TxClk and TxSync are sourced from the MAC to the PHY and
referenced to the RefCLK input. The receive RxCLK and RxSync are sourced by the PHY to the
MAC and in reference to the RefCLK.
2.3.5
Configuration Management Interface
The LXT9785 provides an MDIO Management Interface and a Hardware Control Interface (via the
CFG pins) for device configuration and management. Mode control selection is provided via the
MDDIS pin as shown in Table 8 on page 43. When sectionalization (2x4) is selected, separate
MDIO interfaces are enabled (see Figure 14 on page 60).
2.3.6
MII Isolate
In applications where the MII needs to be isolated from the bus, the RMII and the SMII/SS-SMII
configurations can be tri-stated using Register 0.10. Ports 0 and 1 control RxClk0, RxClk1,
RxSync0, and RxSync1. When 2x4 sectionalization is selected, ports 1-3 and 5-7 can be
individually port isolated. For global shut down, Ports 0 and 1 must be isolated to control the
RxClkn and RxSyncn synchronization pins. If ports 0 and 1 are individually set to isolate, the
remaining associated quad sectionalization ports must also be set to isolate.
2.3.6.1
MDIO Management Interface
The LXT9785 supports the IEEE 802.3 MII Management Interface, also known as the
Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to
monitor and control the state of the LXT9785. The MDIO interface consists of a physical
connection, a specific protocol that runs across the connection, and an internal set of addressable
registers. Some registers are required and their functions are defined by the IEEE 802.3
specification. Additional registers allow for expanded functionality. Specific bits in the registers
are referenced using an “X.Y” notation, where X is the register number (0-32) and Y is the bit
number (0-15).
The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of this
interface is controlled by the MDDIS input pin. When MDDIS is High, all the MDIOs are
completely disabled. The Hardware Control Interface provides primary configuration control.
When MDDIS is Low, the MDIO port is enabled for both read and write operations and the
Hardware Control Interface is not used. The timing for the MDIO Interface is shown in Table 53
on page 117. MDIO read and (write) cycles are shown in Figure 10 (read) and Figure 11 (write)
on page 56.
Datasheet
55
LXT9785 — Advanced 10/100 8-Port PHY
Figure 10. Management Interface Read Frame Structure
MDC
MDIO
(Read)
0
32 "1"s
1
Preamble
High Z
1
ST
A4
0
Op Code
A3
A0
R4
PHY Address
R3
R0
Z
D15 D15D14 D14 D1
0
Turn
Around
Register Address
D1 D0
Data
Write
Idle
Read
Figure 11. Management Interface Write Frame Structure
MDC
MDIO
(Write)
32 "1"s
Idle
Preamble
0
1
0
ST
1
A4
Op Code
A3
A0
R4
PHY Address
R3
R0
Register Address
1
0
Turn
Around
D15
D14
D1
Data
D0
Idle
Write
The protocol allows one controller to communicate with multiple LXT9785 chips. Pins
ADD_<4:0> determine the base address. Each port adds its port number to the base address to
obtain its port address as shown in Figure 12.
Figure 12. Port Address Scheme
BASE ADD_<4:0>
(example ADD_<4:0> = 4)
LXT9785
56
Port 0
PHY ADD_<4:0> (BASE+0)
Port 1
PHY ADD_<4:0> (BASE+1)
Port 2
PHY ADD_<4:0> (BASE+2)
Port 3
PHY ADD_<4:0> (BASE+3)
Port 4
PHY ADD_<4:0> (BASE+4)
Port 5
PHY ADD_<4:0> (BASE+5)
Port 7
PHY ADD_<4:0> (BASE+7)
ex. 4
ex. 5
ex. 6
ex. 7
ex. 8
ex. 9
ex. 11
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
2.3.6.2
MII Sectionalization
When sectionalized into two quad sections, the MDIO bus splits into two separate PHY access
ports. Ports 0-3 of the MDIO section operate independently of ports 4-7. The MII isolate function
is unaffected and operates normally. Sectionalization is selected by pulling pin 176 High on the
initial power-up sequence (refer to Figure 14 on page 60). In applications that need
sectionalization, such as 1x8 and 2x4 and have a single MDIO bus structure, it is necessary that the
addressing scheme be contiguous. For example, the first eight ports are addressed 0-7, so the next
four ports must be addressed 8-11.
2.3.6.3
MII Interrupts
The LXT9785 provides a single per-section interrupt pin that is available to all ports. Interrupt
logic is shown in Figure 13. The LXT9785 also provides two dedicated interrupt registers for each
port. Register 18 provides interrupt enable and mask functions and Register 19 provides interrupt
status. Setting bit 18.1 to 1 enables a port to request interrupt via the MDINT pin. An active Low
on this pin indicates a status change on the device. Because it is a shared interrupt, there is no
indication which port is requesting interrupt service (see Figure 13).
There are five conditions that may cause an interrupt:
•
•
•
•
•
Auto-negotiation complete.
Speed status change.
Duplex status change.
Link status change.
Isolate status change.
Figure 13. Interrupt Logic
Event X Enable Reg
AND
Event X Status Reg
OR
..
.
AND
Per Event
Force Interrupt
Interrupt Enable
...
Port
Combine
Logic
Interrupt Pin
Per port
Interrupt (Event) Status Register is cleared on read.
X = Any Interrupt capability
2.3.6.4
Hardware Control Interface
The LXT9785 provides a Hardware Control Interface for applications where the MDIO is not
desired. Refer to “Initialization” on page 59 for additional details.
Datasheet
57
LXT9785 — Advanced 10/100 8-Port PHY
2.4
Operating Requirements
2.4.1
Power Requirements
The LXT9785 requires four power supply inputs: VCCD, VCCA, VCCPECL and VCCIO. The
digital and analog circuits require 2.5V supplies (VCCD, VCCR, and VCCT). These inputs may be
supplied from a single source although decoupling is required to each respective ground. The fiber
VCCPECL supply can be connected to either 2.5V or 3.3V.
A separate power supply may be used for the MII, JTAG and MDIO (VCCIO) interfaces. The
power supply may be either +2.5V or +3.3V. VCCIO should be supplied from the same power
source used to supply the controller on the other side of the interface. Refer to Table 27 on page 94
for I/O characteristics.
As a matter of good practice, these supplies should be as clean as possible. Typical filtering and
decoupling are shown in Figure 33 on page 92.
2.4.2
Clock/SYNC Requirements
2.4.2.1
Reference Clock
The LXT9785 requires a constant enabled reference clock (REFCLK). REFCLK’s frequency must
be 50 MHz for RMII or 125 MHz for SMII/SS-SMII. The reference clock is used to generate
transmit signals and recover receive signals. A crystal-based clock is recommended over a derived
clock (i.e., PLL-based) to minimize transmit jitter. Refer to Table 30 on page 96 for clock timing
requirements.
For applications that use a single 8-port sectionalization, RefClk0 and RefClk1 must always be tied
together and to the source.
2.4.2.2
TxClk Signal (SS-SMII only)
The LXT9785 requires a 125 MHz input transmit clock synchronous with TxDatan. See Figure 23
on page 73.
2.4.2.3
TxSYNC Signal (SMII/SS-SMII)
The LXT9785 requires a 12.5 MHz input pulse for SMII synchronization. See Figure 23 on page
73.
2.4.2.4
RxSYNC Signal (SS-SMII only)
The LXT9785 provides a 12.5 MHz output pulse synchronous with the RxDATAn outputs. See
Figure 24 on page 73.
2.4.2.5
RxCLK Signal (SS-SMII only)
In SMII mode, the LXT9785 provides a 125 MHz clock output in reference to the output
RxDATAn. Rx Clk is referenced and synchronized to the RefCLK. See Figure 24 on page 73.
58
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
2.5
Initialization
When the LXT9785 is first powered on, reset, or encounters a link failure state, it checks the MDIO
register configuration bits to determine the line speed and operating conditions to use for the
network link. The configuration bits may be set by the Hardware Control or MDIO interface as
shown in Figure 14 on page 60.
2.5.1
MDIO Control Mode
In the MDIO Control mode, the LXT9785 reads the Hardware Control Interface pins to set the
initial (default) values of the MDIO registers. Once the initial values are set, bit control reverts to
the MDIO interface.
2.5.2
Hardware Control Mode
In the Hardware Control Mode, the LXT9785 disables direct write operations to the MDIO
registers via the MDIO Interface. On power-up or hardware reset, the LXT9785 reads the
Hardware Control Interface pins and sets the MDIO registers accordingly.
The following modes are available using either Hardware Control or MDIO Control:
• Force network link to 100BASE-FX (Fiber).
• Force network link operation to:
— 100BASE-TX, Full-Duplex
— 100BASE-TX, Half-Duplex
— 10BASE-T, Full-Duplex
— 10BASE-T, Half-Duplex
•
•
•
•
Allow auto-negotiation/parallel-detection.
Auto/Manual MDIX enable/disable.
Pause for full duplex links operation.
Global Output Slew Rate Control.
When the network link is forced to a specific configuration, the LXT9785 immediately begins
operating the network interface as commanded. When auto-negotiation is enabled, the LXT9785
begins the auto-negotiation/ parallel-detection operation.
Datasheet
59
LXT9785 — Advanced 10/100 8-Port PHY
Figure 14. Initialization Sequence
Power-up or Reset
Read H/W Control
Interface
Initialize MDIO Registers
MDIO Control
Mode
Low
MDDIS Voltage
Level?
Hardware Control
Mode
High
Pass Control to MDIO
Interface
Disable MDIO Writes
Software
Reset?
Hardware
Reset?
Yes
Yes
Reset MDIO Registers to
values read at H/W
Control Interface at last
Hardware Reset
2.5.3
Power-Down Mode
The LXT9785 incorporates numerous features to maintain the lowest power possible. The device
can be put into a low-power state via register 0 as well as a near-zero power state with the power
down pin. When in power-down mode, the device is not capable of receiving or transmitting
packets.
The lowest power operation is achieved using the Global power-down pin. This pin powers down
every circuit in the device, including all clocks. This power-down pin is active High. All registers
are unaltered and maintained when the Global PWRDWN pin is released.
Individual ports (software power down) can be powered down using Control Register 0, bit 1. This
bit powers down a significant portion of the port, but clocks to the register section remain active.
This allows the management interface to remain active during register power-down. The powerdown bit is active High.
2.5.3.1
Global (Hardware) Power Down
The global power-down mode is controlled by the PWRDWN pin. When PWRDWN is High, the
following conditions are true:
• All LXT9785 ports and the clock are shut down.
60
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
•
•
•
•
2.5.3.2
All outputs are tri-stated.
All weak pad pull-up and pull-down resistors are disabled.
The MDIO registers are not accessible.
Configuration pins are not read upon release of the PWRDWN pin, and registers are reloaded
with the value of the last Hardware reset.
Port (Software) Power Down
Individual port power-down control is provided by bit 0.11 in the respective port Control Registers
(refer to Table 57 on page 120). During individual port power-down, the following conditions are
true:
•
•
•
•
2.5.4
The individual port is shut down.
The MDIO registers remain accessible.
Pull-up and pull-down resisters are not affected and the outputs are not tri-stated.
The register remains unchanged.
Reset
The LXT9785 provides both hardware and software resets. Configuration control of AutoNegotiation, speed, and duplex mode selection is handled differently for each. During a hardware
reset, settings for bits 0.13, 0.12, and 0.8 are read in from the pins (refer to Table 18 for pin settings
and Table 57 on page 120 for register bit definitions).
During a software reset (0.15 = 1), the bit settings are not re-read from the pins, and revert back to
the values that were read in during the last hardware reset. Any changes to pin values from the last
hardware reset is not detected during a software reset.
During a hardware reset, register information is unavailable for 1 ms after deassertion of the reset.
All MII interface pins are disabled during a hardware reset and released to the bus on deassertion
of reset.
During a software reset (0.15 = 1) the registers are available for reading. The reset bit should be
polled to see when the part has completed reset (0.15 = 0). Pull up and pull down resisters are not
affected.
Datasheet
61
LXT9785 — Advanced 10/100 8-Port PHY
2.5.5
Hardware Configuration Settings
The LXT9785 provides a hardware option to set the initial device configuration. The hardware
option uses three Global CFG pins that provide control for all ports (see Table 18).
Table 18. Global Hardware Configuration Settings
CFG
Pin Settings1
Desired Mode
AutoNeg
Speed
Resulting Register Bit Values
Duplex
1
2
3
Half
Low
Low
Low
0.12
0.13
0.8
4.8
4.7
4.6
4.5
0
10
0
Full
Low
Low
High
Disabled
1
N/A
0
Auto-Negotiation Advertisement
0
Half
Low
High
Low
Full
Low
High
High
Half
High
Low
Low
1
0
0
1
Full
High
Low
High
1
1
1
1
Half
High
High
Low
1
0
0
Full
High
High
High
1
1
1
100
1
1
100
Enabled
N/A
0
1
0
1
1
1
1
1
10/100
1. Refer to for CFG pin assignments.
2.6
Link Establishment
2.6.1
Auto-Negotiation
The LXT9785 attempts to auto-negotiate with its link partner by sending Fast Link Pulse (FLP)
bursts. Each burst consists of 33 link pulses spaced 62.5 µs apart. Odd link pulses (clock pulses)
are always present. Link pulses (data pulses) may also be present or absent to indicate a “1” or a
“0”. Each FLP burst exchanges 16 bits of data, referred to as a “page”. All devices that support
auto-negotiation must implement the “Base Page”, defined by IEEE 802.3 (registers 4 and 5). The
LXT9785 also supports the optional “Next Page” function (registers 7 and 8).
2.6.1.1
Base Page Exchange
By exchanging Base Pages, the LXT9785 and its link partner communicate their capabilities to
each other. Both sides must receive at least three identical base pages for negotiation to proceed.
Each side finds their highest common capabilities, exchange more pages, and agree on the
operating state of the line.
2.6.1.2
Next Page Exchange
Additional information, exceeding that required by base page exchange, is also sent via “Next
Pages”. The LXT9785 fully supports the IEEE 802.3 method of negotiation via Next Page
exchange. The Next Page exchange uses register 7 to send information and register 8 to receive it.
Next Page exchange occurs only if both ends of the link advertise their ability to exchange Next
Pages. A special mode has been added to make next page exchange easier for software. When
register 6 “page” is received, it stays set until read. This bit should be cleared whenever a new
negotiation occurs, preventing the user from reading an old value in register 6 and assuming there
is valid information in registers 5 and 8. Additionally, register 6 contains a new bit that indicates
62
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
when the current received page is the base page. This information is useful for recognizing when
next pages must be re-sent due to the start of a new negotiation process. Bit 16.1 and the page
received bit are also cleared upon reading register 6.
2.6.1.3
Controlling Auto-Negotiation
When auto-negotiation is controlled by software, the following steps are recommended:
• After power-up, power-down, or reset, the power-down recovery time, as specified in Table 54
on page 118, must be exhausted before proceeding.
• Set the auto-negotiation advertisement register bits.
• Enable auto-negotiation (set MDIO bit 0.12 = 1).
2.6.1.4
Link Criteria
In 100Mbps mode, link is established when the scrambler becomes locked and remains locked for
approximately 50ms. Link remains up unless the descrambler receives less than 12 consecutive idle
symbols in any 2 ms period. This provides a very robust operation, filtering out any small noise hits
that may disrupt the link.
In 10Mbps mode, link is established based on the link state machine found in IEEE 802.3, 14.X.
Receiving 100Mbps idle patterns does not bring up a 10Mbps link.
2.6.1.5
Parallel Detection
In parallel with auto-negotiation, the LXT9785 also monitors for 10Mbps Normal Link Pulses
(NLP) or 100Mbps Idle symbols. If either symbol is detected, the device automatically reverts to
the corresponding operating mode. Parallel detection allows the LXT9785 to communicate with
devices that do not support auto-negotiation.
Figure 15. Auto-Negotiation Operation
Power-Up, Reset,
Link Failure
Start
Disable
Auto-Negotiation
Go To Forced
Settings
Done
Datasheet
0.12 = 0
0.12 = 1
Check Value
0.12
Attempt AutoNegotiation
YES
Enable
Auto-Neg/Parallel Detection
Listen for 100TX
Idle Symbols
Link Set?
Listen for 10T
Link Pulses
NO
63
LXT9785 — Advanced 10/100 8-Port PHY
2.7
Serial MII Operation
The LXT9785 exchanges transmit and receive data with the controller via the Serial MII (SMII).
The SMII performs the following functions:
•
•
•
•
Conveys complete MII information between a 10/100 PHY and MAC with two pins per port.
Allows a multi-port MAC/PHY communication with one system clock.
Operates in both half and full duplex.
Supports per-packet switching between 10Mbps and 100Mbps data rates.
The Serial MII operates at 125 MHz using a global reference clock and frame synchronization
signal (REFCLK and SYNC). Each port has an individual two-line data interface (TXDn and
RXDn). All signals are synchronous to REFCLK. Table 19 summarizes the SMII signals.
Data is exchanged in 10-bit serial words. Each word contains one data byte (two nibbles of 4B
coded data) and two status bits. When the port is operating at 100Mbps, each word contains a new
data byte. When the port is operating at 10Mbps, each data byte is repeated 10 times.
Table 19. SMII Signal Summary
Signal
To
From
Purpose
TXD
PHY
MAC
Transmit data & control
SYNC
PHY
MAC
Synchronization
RXD
MAC
PHY
Receive data & control
REFCLK
MAC &
PHY
System
Synchronization
1. Refer to Table 5 on page 41 for detailed signal descriptions.
64
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Figure 16. Typical SMII Interface Diagram
Typical SMII Interface
in a 16-Port System
SECTION
RxDatan
MDIO0
MDC0
Magnetics/Fiber Transceiver
8
TxDatan
SYNC0
LXT9785 8-Port Phy
8-Port Media
Access Controller
( MAC)
8
MDINT0
RefCLK0
125 MHz Sourced
Externally or from
Switch ASIC
RefCLK1
SYSTEM CLK
RefCLK0 RefCLK1
RxDatan
MDIO0
MDC0
Magnetics/Fiber Transceiver
8
TxDatan
SYNC0
LXT9785 8-Port Phy
8-Port Media
Access Controller
(MAC)
8
MDINT0
SECTION
Datasheet
65
LXT9785 — Advanced 10/100 8-Port PHY
Figure 17. Typical SMII Quad Sectionalization Diagram
Typical SMII Interface in a
24-Port System
RefClk0
8
RefClk1
TxDatan
8
12-Port Media
Access Controller
( MAC)
RxDatan
MDIO0
MDC0
MDINT0
4
SECTION
TxDatan
RxDatan
LXT9785
4-Port (sec)
MDIO0
MDC0
MDINT0
RefClk0
125 MHz Sourced
Externally or from
Switch ASIC
RefClk1
TxDatan
4
SYNC1
4
RxDatan
VCC
SECTION
8
TxDatan
SYNC0
8
RxData n
Magnetics/Fiber Transceiver
MDINT0
MDIO0
MDC0
LXT 9785 8-Port Phy
12-Port Media
Access Controller
( MAC)
MDINT1
MDIO1
MDC1
Magnetics/Fiber Transceiver
4-Port (sec)
SYNC0
4
Magnetics/Fiber Transceiver
LXT9785 8-Port Phy
SYNC0
SECTION
RefClk0 RefClk1
66
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Figure 18. 100Mbps Serial MII Data Flow
Serial Data Stream
To/From
MAC
S0
S1 D0 D1 D2
Strip
TX_EN &
TX_ER
Status
Bits
2 Nibbles Tx/Rx Data
2 Symbols Tx/Rx Data
D0 D1 D2 D3
S0
S1
S2
S3
S4
S0
S1
S2
S3
S4
4B/5B
D3 D4 D5 D6 D7
2.7.1
Insert
CRS &
RX_DV
Status
Bits
D0 D1 D2 D3
To/From
PMD
Sublayer
SMII Reference Clock
The REFCLK operates at 125 MHz. The transmit and receive data and control streams must always
be synchronized to the REFCLK by the MAC and PHY. The LXT9785 samples these signals on
the rising edge of the REFCLK.
2.7.2
TxSYNC Pulse (SMII/SS-SMII)
The TxSYNC pulse delimits segment boundaries and synchronizes with REFCLK. The MAC must
continuously generate a TxSYNC pulse once every 10 REFCLK cycles. The TxSYNC pulse
signals the start of each new segment (see Figure 22 on page 72).
2.7.3
Transmit Data Stream
Transmit data and control information are signaled in ten- bit segments. In 100Mbps mode, each
segment contains a new byte of data. In 10Mbps mode, the MAC must repeat a 10M serial word
ten times on TXD. The LXT9785 may sample that serial word at any point.
The TxSYNC pulse signals the start of a new segment as shown in Figure 19 on page 68.
2.7.3.1
Transmit Enable
The MAC must assert the TX_EN bit in each segment of TXData, and de-assert TX_ENn after the
last segment of the packet.
2.7.3.2
Transmit Error
When the MAC asserts the TX_ER bit in 100BASE-X mode, the LXT9785 drives “H” symbols
onto the network interface. TX_ER does not have any function in 10M operation.
Datasheet
67
LXT9785 — Advanced 10/100 8-Port PHY
Figure 19. Serial MII Transmit Synchronization
CLOCK
TxSYNC
TX
2.7.4
TX_ER TX_EN TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7 TX_ER
Receive Data Stream
Receive data and control information are signalled in ten- bit segments. In 100Mbps mode, each
segment contains a new byte of data. In 10Mbps mode, each segment is repeated ten times (except
for the CRS bit), and the MAC can sample any of the ten segments.
2.7.4.1
Carrier Sense
The CRS bit (slot 0) is generated when a packet is received from the network interface. The CRS
bit is set in real time, even in 10Mbps mode (all other bits are repeated in 10 sequential segments).
2.7.4.2
Receive Data Valid
The LXT9785 asserts the RX_DV bit (slot 1) when it receives a valid packet. The assertion timing
changes depending on line operating speed:
• For 100 TX and 100 FX links, the RX_DV bit is asserted from the first nibble of preamble to
the last nibble of the data packet.
• For 10 BT links, the entire preamble is truncated. The RX_DV bit is asserted with the first
nibble of the Start-of-Frame Delimiter (SFD) “5D” and remains asserted until the end of the
packet.
2.7.4.3
Receive Error
When the LXT9785 receives an invalid symbol from the network in 100BASE-TX mode, it drives
“1110” on the associated RXD pin.
2.7.4.4
Receive Status Encoding
The LXT9785 encodes status information onto the RXD line during IPG as seen in Table 20 on
page 69. Status bit RXD<5> indicates the validity of the upper nibble (RXD<7:4> of the last byte
of the previous frame). RXD and RX_DV are passed through the internal elasticity FIFO to smooth
any clock rate differences between the recovered clock and the 125 MHz reference clock.
2.7.5
Collision
The SMII interface does not provide a collision output and relies on the MAC to interpret COL
conditions using CRS and TX_EN. CRS is unaffected by the transmit path.
68
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Figure 20. Serial MII Receive Synchronization
CLOCK
RxSYNC
RX
CRS
RXD0
RX_DV RXER
RXD1
Speed
RXD2
Duplex
RXD3
Link
RXD4
J abber
RXD5
Valid
RXD6
FCE
RXD7
RXD7
CRS
Table 20. RX Status Encoding Bit Definitions
Signal
Definition
CRS
Carrier Sense - identical to MII, except that it is not an asynchronous signal.
RX_DV
Receive Data Valid - identical to MII. When RX_DV = 0, status information is
transmitted to the MAC. When RX_DV = 1, received data is transmitted to the
MAC.
0 = Status Byte
1 = Valid Data Byte
RX_ER
(RXD0)
Inter-frame status bit RXD0 indicates whether or not the PHY detected an error
somewhere in the previous frame.
0 = No Error
1 = Error
SPEED
(RXD1)
Inter-frame status bit RXD1 indicates port operating speed.
0 = 10Mbps
1 = 100Mbps
DUPLEX
(RXD2)
Inter-frame status bit RXD2 indicates port duplex condition.
0 = Half
1 = Full
LINK
(RXD3)
Inter-frame status bit RXD3 indicates port link status.
0 = Down
1 = Up
JABBER
(RXD4)
Inter-frame status bit RXD4 indicates port jabber status.
0 = OK
1 = Error
VALID
(RXD5)
Inter-frame status bit RXD5 conveys the validity of the upper nibble of the last byte
of the previous frame.
0 = Invalid
1 = Valid
False Carrier
(RXD6)
Inter-frame status bit RXD6 indicates whether or not the PHY has detected a false
carrier event.
0 = No FC detected
1 = FC detected
RXD7
This bit is set to 1.
Always = 1
1. Both RXD0 and RXD5 bits are valid in the segment immediately following a frame, and remain valid until the first data
segment of the next frame begins.
Datasheet
69
LXT9785 — Advanced 10/100 8-Port PHY
2.7.5.1
Source Synchronous SMII
Some system designs require the PHY to be placed between 3 to 12 inches away from the MAC. A
new source synchronous SMII definition has been added because of this requirement. To provide a
source synchronous interface between the PHY and MAC, the PHY must drive the RxClk and the
RxSYNC signals to the MAC. Also, the MAC must drive the TxClk and the TxSYNC signal to the
PHY. The RefClk is also needed to synchronize the data to the PHY’s core clock domain. TxData is
clocked in using TxClk and then synchronized to RefClk and transmitted to the twisted-pair. The
RxData is synchronized to the RxClk. See Figure 24 on page 73.
Table 21. Source Synchronous SMII
Signal
70
To
From
Purpose
TxData
PHY
MAC
Transmit data & control
TxCLK
PHY
MAC
Transmit clock
TxSYNC
PHY
MAC
Synchronization pulses
RxData
MAC
PHY
Receive data & control
RxCLK
MAC
PHY
Receive clock
RxSYNC
MAC
PHY
Receive Synchronization
RefClk
MAC
System
Synchronization
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Figure 21. Typical SS-SMII Interface Diagram
Typical SS-SMII Interface in
a 16-Port System
SECTION
TxDatan
8
RxDatan
RxSYNC1
RxCLK1
MDIO0
MDC0
Magnetics/Fiber Transceiver
TxSYNC0
TxCLK0
LXT9785 8-Port Phy
8-Port Media
Access Controller
( MAC)
8
MDINT0
RefCLK0,1
125 MHz Sourced
Externally or from
Switch ASIC
SYS_CLK
RxDatan
RxSYNC1
RxCLK1
MDIO0
MDC0
MDINT0
Magnetics/Fiber Transceiver
8
RefCLK0,1
TxDatan
TxSYNC0
TxCLK0
LXT9785 8-Port Phy
8-Port Media
Access Controller
(MAC)
8
SECTION
Note:
Datasheet
For SMII operation TxCLK1, RxSYNCn and RxCLKn pins are ignored
71
LXT9785 — Advanced 10/100 8-Port PHY
Figure 22. Typical SS-SMII Quad Sectionalization Diagram
Typical SS-SMII Interface
in a 24-Port System
RefClk0
8
RefClk1
RxSYNC1
12-Port Media
Access Controller
( MAC)
RxCLK1
MDIO0
MDC0
MDINT0
SECTION
4
MDINT0
RefClk0
125 MHz Sourced
Externally or from
Switch ASIC
RefClk1
TxData n
TxSYNC1
TxCLK1
RxData n
RxSYNC1
RxCLK1
4
4
LXT9785
4-port (sec)
MDIO0
MDC0
Magnetics/Fiber Transceiver
TxDatan
TxSYNC0
TxCLK0
RxData n
RxSYNC0
RxCLK0
4-port (sec)
4
VCC
MDINT1
MDIO1
SECTION
MDC1
MDINT0
MDIO0
TxData n
TxSYNC0
TxCLK0
8
RxData n
RxSYNC1
RxCLK1
Magnetics/Fiber Transceiver
MDC0
8
LXT9785 8-Port Phy
12-Port Media
Access Controller
( MAC)
Magnetics/Fiber Transceiver
TxCLK0
RxDatan
8
LXT9785 8-Port Phy
TxDatan
TxSYNC0
SECTION
RefClk0 RefClk1
72
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Figure 23. Source Synchronous Transmit Timing
SS-SMII Transmit Timing
TxCLK
TxSYNC
TXER TXEN TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 TXER
TxData
TxCLK
TxSYNC
TXER TXEN Frcerr Speed Dplx LINK Jabr
TxData
TXER
All signals are
synchronous to the clock
Figure 24. Source Synchronous Receive Timing
SS-SMII Receive Timing
RxCLK
RxSYNC
RxData
CRS RXDV RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 CRS
RxCLK
RxSYNC
RxData
CRS RXDV RXER Speed Dplx LINK Jabr UPnib FlsCar
CRS
All signals are
synchronous to the clock
Datasheet
73
LXT9785 — Advanced 10/100 8-Port PHY
2.8
RMII Operation
The LXT9785 provides an independent Reduced MII port for each network port. Each RMII uses
four signals to pass received data to the MAC: RXDn<1:0>, RXERn, and CRS_DVn (where n
reflects the port number). Three signals are used to transmit data from the MAC: TXDn_<1:0> and
TXENn. Both receive and transmit signals are clocked by REFCLK. Data transmission across the
RMII is implemented in di-bit pairs which equal a 4-bit wide nibble.
2.8.1
RMII Reference Clock
The LXT9785 requires a 50 MHz reference clock (REFCLK). The device samples the RMII input
signals on the rising edge of REFCLK and drives RMII output signals on the falling edge.
2.8.2
Transmit Enable
TXENn must be asserted and de-asserted synchronously with REFCLK. The MAC must assert
TXENn at the same time as the first nibble of preamble. TXENn must be de-asserted after the last
bit of the packet.
2.8.3
Carrier Sense & Data Valid
The LXT9785 asserts CRS_DVn when it detects activity on the line. However, RXDn outputs
zeros until the received data is decoded and available for transfer to the controller.
2.8.4
Receive Error
Whenever the LXT9785 receives an errored symbol from the network, it asserts RXERn. When it
detects a bad Start-of-Stream Delimiter (SSD) it drives a “10” jam pattern on the RXD pins to
indicate a false carrier event.
2.8.5
Out-of-Band Signalling
The LXT9785 has the capability of encoding status information in the RXData stream during IPG.
See “Monitoring Operations” on page 84 for details.
2.8.6
4B/5B Coding Operations
The 100BASE-X protocol specifies the use of a 5-bit symbol code on the network media. However,
data is normally transmitted across the RMII interface in 2-bit nibblets or “di-bits”. The LXT9785
incorporates a parallel/serial converter that translates between di-bit pairs and 4-bit nibbles, and a
4B/5B encoder/decoder circuit that translates between 4-bit nibbles and 5-bit symbols for the
100BASE-X connection. Figure 25 on page 75 shows the data conversion flow from nibbles to
symbols. Table 22 on page 80 shows 4B/5B symbol coding (not all symbols are valid).
74
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Figure 25. RMII Data Flow
Reduced MII Mode Data Flow
D0
D2
+1
Parallel
to
Serial
D0 D1 D2 D3
D1
D3
di-bit
pairs
Datasheet
Serial
to
Parallel
0
Scramble
4-bit
nibbles
4B/5B
S0
S1
S2
5-bit
symbols
S3
S4
DeScramble
MLT3
0
0
-1
Transition = 1.
No Transition = 0.
All transitions must follow
pattern: 0, +1, 0, -1, 0, +1...
75
LXT9785 — Advanced 10/100 8-Port PHY
Figure 26. Typical RMII Interface Diagram
Typical RMII Interface
in a 16-Port System
SECTION
8
TxD0n
8
8
8
8
TxENn
RxD0n
RxD1n
CRS_DVn
RxERn
MDIO0
Magnetics/Fiber Transceiver
8
TxD1n
LXT9785 8-Port Phy
8-Port Media
Access Controller
( MAC)
8
MDC0
MDINT0
50 Mhz Sourced
Externally or from
Switch ASIC
RefClk0
RefClk1
RefClk0
RefClk1
MDINT0
MDIO0
TxD0 n
8
TxD1 n
8
8
TxEN n
RxD0 n
Magnetics/Fiber Transceiver
8
LXT9785 8-Port Phy
8-Port Media
Access Controller
( MAC)
MDC0
8
RxD1n
8
8
CRS_DV n
RxER n
SECTION
76
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Figure 27. Typical RMII Quad Sectionalization Diagram
Typical RMII Interface
in a 24-Port System
RefClk0 RefClk1
8
TxENn
8
RxD0n
8
RxD1n
12-Port Media
Access Controller
( MAC)
8
CRS_DVn
8
RxERn
MDIO0
MDC0
MDINT0
4
4
TxD0n
TxD1n
TxENn
RxD0n
RxD1n
CRS_DV n
RxERn
50 MHz Sourced
Externally or from
Switch ASIC
RefClk1
4
4
4
4
4
MDINT1
MDIO1
MDC1
4-Port (sec)
TxD0n
TxD1n
TxEN n
RxD0 n
RxD1n
CRS_DVn
RxER n
4
4
VCC
SECTION
MDINT0
8
8
8
8
8
8
8
TxD0 n
TxD1n
TxEN n
RxD0 n
RxD1n
CRS_DV n
RxER n
Magnetics/Fiber Transceiver
MDIO0
MDC0
LXT9785 8-Port Phy
12-Port Media
Access Controller
( MAC)
LXT9785
MDIO0
MDC0
MDINT0
RefClk0
Magnetics/Fiber Transceiver
4
4
4
SECTION
4-Port (sec)
4
4
Magnetics/Fiber Transceiver
8
LXT9785 8-Port Phy
TxD0n
TxD1n
8
SECTION
RefClk0 RefClk1
Datasheet
77
LXT9785 — Advanced 10/100 8-Port PHY
2.9
100Mbps Operation
2.9.1
100BASE-X Network Operations
During 100BASE-X operation, the LXT9785 transmits and receives 5-bit symbols across the
network link. Figure 28 shows the structure of a standard frame packet. When the MAC is not
actively transmitting data, the LXT9785 sends out Idle symbols on the line.
In 100BASE-TX mode, the device scrambles the data and transmits it to the network using MLT-3
line code. The MLT-3 signals received from the network are descrambled and decoded, and sent
across the RMII to the MAC.
In 100BASE-FX mode, the LXT9785 transmits and receives NRZI signals across the PECL
interface. An external 100FX transceiver module is required to complete the fiber connection.
As shown in Figure 28, the MAC starts each transmission with a preamble pattern. As soon as the
LXT9785 detects the start of preamble, it transmits a J/K Start-of-Stream Delimiter (SSD) symbol
to the network. It then encodes and transmits the rest of the packet, including the balance of the
preamble, the Start-of-Frame Delimiter (SFD), packet data, and CRC. Once the packet ends, the
LXT9785 transmits the T/R End-of-Stream Delimiter (ESD) symbol and then returns to
transmitting Idle symbols.
Figure 28. 100BASE-X Frame Format
64-Bit Preamble
(8 Octets)
P0
P1
Replaced by
/J/K/ code-groups
Start-of-Stream
Delimiter (SSD)
2.9.2
P6
Destination and Source
Address (6 Octets each)
SFD
DA
DA
SA
Packet Length
(2 Octets)
SA
L1
L2
Data Field
Frame Check Field InterFrame Gap / Idle Code
(Pad to minimum packet size)
(4 Octets)
(> 12 Octets)
D0
Start-of-Frame
Delimiter (SFD)
D1
Dn
CRC
I0
IFG
Replaced by
/T/R/ code-groups
End-of-Stream Delimiter (ESD)
100BASE-X Protocol Sublayer Operations
In a 7-layer communications model, the LXT9785 is a Physical Layer 1 (PHY) device. The
LXT9785 implements the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA),
and Physical Medium Dependent (PMD) sublayers of the reference model defined by the IEEE
802.3u specification. The following paragraphs discuss the LXT9785 operation from the reference
model point of view.
2.9.2.1
PCS Sublayer
The Physical Coding Sublayer (PCS) provides the RMII interface, as well as the 4B/5B encoding/
decoding function. For 100TX and 100FX operation, the PCS layer provides IDLE symbols to the
PMD-layer line driver as long as TXEN is de-asserted. For 10T operation, the PCS layer merely
provides a bus interface and serialization/de-serialization function. 10T operation does not use the
4B/5B encoder.
78
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Preamble Handling
When the MAC asserts TXEN, the PCS substitutes a /J/K/ symbol pair, also known as the Start-ofStream Delimiter (SSD), for the first two nibbles received across the RMII. The PCS layer
continues to encode the remaining RMII data until TXEN is de-asserted (see Table 22 on page 80).
It then returns to supplying IDLE symbols to the line driver.
The PCS layer performs the opposite function in the receive direction by substituting two preamble
nibbles for the SSD.
Dribble Bits
The LXT9785 handles dribbles bits in all modes. If one through four dribble bits are received, the
nibble is passed across the RMII, padded with ones if necessary. If five through seven dribble bits
are received, the second nibble is not sent to the RMII bus.
Figure 29. Protocol Sublayers
MII Interface
PCS
Sublayer
PMA
Sublayer
LXT9785
Encoder/Decoder
Serializer/De-serializer
Link/Carrier Detect
PECL Interface
PMD
Sublayer
Scrambler/
De-scrambler
100BASE-TX
Datasheet
Fiber Transceiver
100BASE-FX
79
LXT9785 — Advanced 10/100 8-Port PHY
2.9.3
PMA Sublayer
Table 22. 4B/5B Coding
Code Type
DATA
IDLE
CONTROL
INVALID
1.
2.
3.
4.
80
4B Code
3210
Name
5B Code
43210
0000
0
11110
Data 0
0001
1
01001
Data 1
0010
2
10100
Data 2
0011
3
10101
Data 3
0100
4
01010
Data 4
0101
5
01011
Data 5
Interpretation
0110
6
01110
Data 6
0111
7
01111
Data 7
1000
8
10010
Data 8
1001
9
10011
Data 9
1010
A
10110
Data A
1011
B
10111
Data B
1100
C
11010
Data C
1101
D
11011
Data D
1110
E
11100
Data E
1111
F
11101
Data F
undefined
I1
1 1 1 11
Idle. Used as inter stream fill code.
0101
J2
11000
Start-of-Stream Delimiter (SSD), part 1 of 2.
0101
2
10001
Start-of-Stream Delimiter (SSD), part 2 of 2.
undefined
T3
01101
End-of-Stream Delimiter (ESD), part 1 of 2.
undefined
R3
00111
End-of-Stream Delimiter (ESD), part 2 of 2.
undefined
H4
00100
Transmit Error. Used to force signalling errors.
undefined
Invalid
00000
Invalid
undefined
Invalid
00001
Invalid
undefined
Invalid
00010
Invalid
undefined
Invalid
00011
Invalid
undefined
Invalid
00101
Invalid
undefined
Invalid
00110
Invalid
undefined
Invalid
01000
Invalid
undefined
Invalid
01100
Invalid
undefined
Invalid
10000
Invalid
undefined
Invalid
11001
Invalid
K
The /I/ (Idle) code group is sent continuously between frames.
The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/.
The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/.
An /H/ (Error) code group is used to signal an error condition.
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Link
In 100Mbps mode, the LXT9785 establishes a link whenever the scrambler becomes locked and
remains locked for approximately 50 ms. Whenever the scrambler loses lock (<12 consecutive idle
symbols during a 2 ms window), the link is taken down. This provides a robust link, filtering out
any small noise hits that may otherwise disrupt the link. Furthermore, 100Mbps idle patterns will
not bring up a 10Mbps link.
The LXT9785 reports link failure via the RMII status bits (1.2, 17.10, and 19.4) and interrupt
functions. If auto-negotiate is enabled, link failure causes the device to re-negotiate.
Link Failure Override
The LXT9785 normally transmits 100Mbps data packets or Idle symbols only if it detects the link
is up, and transmits only FLP bursts if the link is not up. Setting bit 16.14 = 1 overrides this
function, allowing the LXT9785 to transmit data packets even when the link is down. This feature
is provided as a diagnostic tool.
Note:
Auto-negotiation must be disabled to transmit data packets in the absence of link. If autonegotiation is enabled, the LXT9785 automatically begins transmitting FLP bursts if the link goes
down.
Carrier Sense/Data Valid (RMII)
The LXT9785 asserts CRS_DV whenever the respective port receiver is in a non-idle state (as
defined by the RMII Specification Revision 1.2), including false carrier events. Assertion of
CRS_DV is asynchronous with respect to REFCLK. In the event that signal decoding is not
complete when CRS_DV is asserted, the LXT9785 outputs 00 on the RXD1:0 lines until the
decoded data are available.
When the line returns to an idle state, CRS_DV is de-asserted asynchronously with respect to
REFCLK. If the FIFO still contains data to be passed to the MAC via the RMII when CRS is deasserted, CRS_DV toggles on nibble boundaries until the FIFO is empty. For 100BASE-X signals,
CRS_DV toggles at 25 MHz. For 10BASE-T signals, CRS_DV toggles at 2.5 MHz.
Carrier Sense (SMII)
For 100TX and 100FX links, a Start-of-Stream Delimiter (SSD) or /J/K/ symbol pair causes
assertion of carrier sense (CRS). An End-of-Stream Delimiter (ESD), or /T/R/ symbol pair causes
de-assertion of CRS. The PMA layer also de-asserts CRS if IDLE symbols are received without /T/
R/. In this event, the RX_ER bit in the RX Status Frame is asserted for one clock cycle when CRS
is de-asserted.
For 10T links, CRS assertion is based on receipt of valid preamble, and de-assertion on receipt of
an End-of-Frame (EOF) marker.
Receive Data Valid (SMII)
The LXT9785 asserts the RX_DV bit when it receives a valid packet. However, RXD outputs zeros
until the received data are decoded and available for transfer to the controller.
Datasheet
81
LXT9785 — Advanced 10/100 8-Port PHY
2.9.3.1
Twisted-Pair PMD Sublayer
The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and
descrambling, line coding and decoding (MLT-3 for 100TX, Manchester for 10T), as well as
receiving, polarity correction, and baseline wander correction functions.
Scrambler/Descrambler (100TX Only)
The purpose of the scrambler is to spread the signal power spectrum and further reduce EMI using
an 11-bit, non-data-dependent polynomial. The receiver automatically decodes the polynomial
whenever IDLE symbols are received.
The scrambler/descrambler can be bypassed by setting bit 16.12 = 1. The scrambler is
automatically bypassed when the fiber port is enabled. Scrambler bypass is provided for diagnostic
and test support.
Baseline Wander Correction
The LXT9785 provides a baseline wander correction function which makes the device robust
under all network operating conditions. The MLT3 coding scheme used in 100BASE-TX is, by
definition, “unbalanced”. This means that the DC average value of the signal voltage can “wander”
significantly over short time intervals (tenths of seconds). This wander may cause receiver errors,
particularly in less robust designs, at long line lengths (100 meters). The exact characteristics of the
wander are completely data dependent.
The LXT9785 baseline wander correction characteristics allow the device to recover error-free data
while receiving worst-case “killer” packets over all cable lengths.
Polarity Correction
The LXT9785 automatically detects and corrects for the condition where the receive signal
(TPFIP/N) is inverted. Reversed polarity is detected if eight inverted link pulses or four inverted
End-of-Frame (EOF) markers are received consecutively. If link pulses or data are not received by
the maximum receive time-out period, the polarity state is reset to a non-inverted state.
2.9.3.2
Fiber PMD Sublayer
The LXT9785 provides a PECL interface for connection to an external fiber-optic transceiver. (The
external transceiver provides the PMD function for fiber media.) The device uses an NRZI format
for the fiber interface. The fiber interface operates at 100Mbps and does not support 10FL
applications.
Far End Fault Indications
The LXT9785 Signal Detect pins independently detect signal faults from the local fiber
transceivers via the SD pins. The device also uses bit 1.4 to report Remote Fault indications
received from its link partner. The device “ORs” both fault conditions to set bit 1.4. Bit 1.4 is set
once and clears when read.
Either fault condition causes the LXT9785 to drop the link unless Forced Link Pass is selected
(16.14 = 1). Link down condition is then reported via interrupts and status bits.
82
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
In response to locally detected signal faults (SD activated by the local fiber transceiver), the
affected port can transmit the far end fault code if fault code transmission is enabled by bit 16.2.
• When bit 16.2 = 1, transmission of the far end fault code is enabled. The LXT9785 transmits
far end fault code if fault conditions are detected by the Signal Detect pins.
• When bit 16.2 = 0, the LXT9785 does not transmit far end fault code. It continues to transmit
idle code and may or may not drop link depending on the setting for bit 16.14.
The occurrence of a Far End Fault causes all transmission of data from the Reconciliation Sublayer
to stop and the Far End fault code to begin. The Far End Fault code consists of 84 ones’s followed
by a single “0” and is repeated until the Far End Fault condition is removed.
2.10
10Mbps Operation
The LXT9785 operates as a standard 10BASE-T transceiver and supports all the standard 10Mbps
functions. During 10BASE-T (10T) operation, the LXT9785 transmits and receives Manchesterencoded data across the network link. When the MAC is not actively transmitting data, the device
sends out link pulses on the line.
In 10T mode, the polynomial scrambler/descrambler is inactive. Manchester-encoded signals
received from the network are decoded by the LXT9785 and sent across the RMII to the MAC.
Note:
2.10.1
The LXT9785 does not support fiber connections at 10Mbps.
Preamble Handling
The LXT9785 offers two options for preamble handling, selected by bit 16.5. In 10T Mode when
bit 16.5 = 0, the device strips the entire preamble off the received packets. CRS_DV is asserted
simultaneously with SFD. CRS_DV is held Low for the duration of the preamble. When CRS_DV
is asserted, the very first two nibbles driven by the LXT9785 are the SFD “5D” hex followed by the
body of the packet.
When bit 16.5 = 1 in 10T mode, the LXT9785 passes the preamble through the RMII and asserts
CRS_DV simultaneously.
2.10.2
Dribble Bits
The LXT9785 device handles dribble bits in all modes. If one through four dribble bits are
received, the nibble is passed across the RMII. If five through seven dribble bits are received, the
second nibble is not sent onto the RMII bus.
2.10.3
Link Test
The LXT9785 always transmits link pulses in 10T mode. When enabled, the link test function
monitors the connection for link pulses. Once link pulses are detected, data transmission is enabled
and remains enabled as long as either the link pulses or data transmission continue. If link pulses
stop, the data transmission is disabled.
If the link test function is disabled, the LXT9785 transmits to the connection regardless of detected
link pulses. The link test function is disabled by setting bit 16.14 = 1.
Datasheet
83
LXT9785 — Advanced 10/100 8-Port PHY
2.10.3.1
Link Failure
Link failure occurs if Link Test is enabled and link pulses or packets stop being received. If this
condition occurs, the LXT9785 returns to the auto-negotiation phase if auto-negotiation is enabled.
2.10.4
Jabber
If a transmission exceeds the jabber timer, the LXT9785 disables the transmit and loopback
functions. The RMII does not include a Jabber pin, but the MAC may read Register 1 or 25 to
determine Jabber status. The LXT9785 automatically exits jabber mode after the unjab time has
expired. This function is disabled by setting bit 16.10 = 1.
2.11
Monitoring Operations
2.11.1
Monitoring Auto-Negotiation
Auto-negotiation may be monitored as follows:
• Bits 1.2 and 17.10 = 1 once the link is established.
• Additional bits in Register 1 (refer to Table 58 on page 121) and Register 17 (refer to Table 67
on page 128) can be used to determine the link operating conditions and status.
2.11.2
Per-Port LED Driver Functions
The LXT9785 incorporates three direct drive LEDs per port (LEDn_1, LEDn_2, and LEDn_3). On
power up, all the LEDs lights up for approximately one second after reset de-asserts. Each LED
may be programmed to one of several different display modes using the LED Configuration
Register. Each per-port LED may be programmed (refer to Table 70 on page 131) to indicate one of
the following conditions:
•
•
•
•
•
•
•
Operating Speed
Transmit Activity
Receive Activity
Collision Condition
Link Status
Duplex Mode
Isolate Condition
The LEDs can also be programmed to display various combined status conditions. For example,
setting bits 20.15:12 = 1101 produces the following combination of Link and Activity indications:
• If Link is down, LED is off.
• If Link is up, LED is on.
• If Link is up AND activity is detected, the LED blinks at the stretch interval selected by bits
20.3:2 and continues to blink as long as activity is present.
84
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
The LED driver pins are open drain circuits (10mA max current rating). Refer to “LED Circuit” on
page 90 under the Application Information Section for LED circuit design details. The LED
Configuration Register also provides optional LED pulse stretching to 30, 60, or 100 ms. If during
this pulse stretch period, the event occurs again, the pulse stretch time is further extended (see
Table 70 on page 131).
When an event such as receiving a packet occurs, it is edge detected and starts the stretch timer.
The LED driver remains asserted until the stretch timer expires. If another event occurs before the
stretch timer expires, the stretch timer is reset and the stretch time extended.
When a long event (such as duplex status) occurs, it is edge detected and starts the stretch timer.
When the stretch timer expires, the edge detector is reset so that a long event causes another pulse
to be generated from the edge detector. The edge detector resets the stretch timer, causing the LED
driver to remain asserted. Figure 30 shows how the stretch operation functions.
Figure 30. LED Pulse Stretching
Event
LED
stretch
stretch
stretch
Note: The direct drive LED outputs in this diagram are shown as active Low.
2.11.3
Out-of-Band Signalling
The LXT9785 provides an out-of-band signalling option to transfer status information across the
RMII receive interface. This feature is enabled when register 25.0 = 1 and uses the RXD(1:0) data
bus during the Inter-Packet Gap (IPG) time as shown in Figure 31.
The two status bits transferred across the RXD bus are software selectable via Register 25 (see
Table 72 on page 133).
In normal operation, the LXT9785 stuffs the RXD bus with zeros during the IPG. A softwareselectable bit enables the RMII out-of-band signalling feature. Once this bit is set, the LXT9785
replaces the zeros with selected status bits during the IPG.
Datasheet
85
LXT9785 — Advanced 10/100 8-Port PHY
Figure 31. RMII Programmable Out-of-Bank Signaling
REFCLK
CRS_DV
RXD(1)
sta tus 1
status 1
0s
data
data
data
data
status 1
status 1
status 1
status 1
status 1
RXD(0)
sta tus 0
status 0
0s
data
data
data
data
status 0
status 0
status 0
status 0
status 0
1. When network activity is detected, the LXT9785 asserts CRS_DV asynchronously with respect to REFCLK.
2. After CRS_DV is asserted, the LXT9785 will zero-stuff the RXData bits until the received data has been processed through
the FIFO.
3. When network activity ceases, the LXT9785 de-asserts CRS_DV synchronously with respect to REFCLK. CRS_DV will
toggle until all data in the FIFO has been processed through the RMII. Once the FIFO is empty, LXT9785 will drive the status
bits selected by the Out-of-Band Signalling Register (refer to Table 72 on page 133) on the RXD outputs.
The LXT9785 includes an IEEE 1149.1 boundary scan test port for board level testing. All digital
input, output, and input/output pins are accessible.
2.11.4
Boundary Scan Interface
This interface consists of five pins (TMS, TDI, TDO, TCK and TRST). It includes a state machine,
data register array, and instruction register. The TMS and TDI pins are internally pulled up and the
TCK pin is internally pulled down. TDO does not have an internal pull-up or pull-down.
2.11.5
State Machine
The TAP controller is a 16-state machine driven by the TCK and TMS pins. Upon reset, the
TEST_LOGIC_RESET state is entered. The state machine is also reset when TMS and TDI are
High for five TCK periods.
2.11.6
Instruction Register
The IDCODE instruction is always invoked after the state machine resets. The decode logic
ensures the correct data flow to the Data registers according to the current instruction. Valid
instructions are listed in Table 24 on page 87.
86
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
2.11.7
Boundary Scan Register
Each Boundary Scan Register (BSR) cell has two stages. A flip-flop and a latch are used for the
serial shift stage and the parallel output stage. There are four modes of operation as listed in Table
23.
Table 23. BSR Mode of Operation
Mode
Description
1
Capture
2
Shift
3
Update
4
System Function
Table 24. Supported JTAG Instructions
Name
Datasheet
Code
Description
Data
Register
EXTEST
0000000000000000
External Test
BSR
IDCODE
1111111111111110
ID Code Inspection
ID REG
SAMPLE
1111111111111000
Sample Boundary
BSR
High Z
1111111111001111
Force Float
Bypass
Clamp
1111111111101111
Clamp
BSR
BYPASS
1111111111111111
Bypass Scan
Bypass
87
LXT9785 — Advanced 10/100 8-Port PHY
3.0
Application Information
3.1
Design Recommendations
The LXT9785 is designed to comply with IEEE 802.3 requirements to provide outstanding receive
Bit Error Rate (BER), and long-line-length performance. To achieve maximum performance from
the LXT9785, attention to detail and good design practices are required. Refer to the LXT9785
Design and Layout Guide application note for detailed design and layout information.
3.2
General Design Guidelines
Adherence to generally accepted design practices is essential to minimize noise levels on power
and ground planes. Up to 50 mV maximum of noise is considered acceptable. High-frequency
switching noise can be reduced, and its effects eliminated, by following these simple guidelines
throughout the design:
• Fill in unused areas of the signal planes with solid copper and attach them with vias to a VCC
or ground plane that is not located adjacent to the signal layer.
• Use ample bulk and decoupling capacitors throughout the design (a value of 0.01 µF is
recommended for decoupling caps).
•
•
•
•
•
•
Provide ample power and ground planes.
Provide termination on all high-speed switching signals and clock lines.
Provide impedance matching on long traces to prevent reflections.
Route high-speed signals next to a continuous, unbroken ground plane.
Filter and shield DC-DC converters, oscillators, etc.
Do not route any digital signals between the LXT9785 and the RJ-45 connectors at the edge of
the board.
• Do not extend any circuit power and ground plane past the center of the magnetics or to the
edge of the board. Use this area for chassis ground, or leave it void.
3.2.1
Power Supply Filtering
Power supply ripple and digital switching noise on the VCC plane may cause EMI problems and
degrade line performance. The best approach to this problem is to minimize ground noise as much
as possible using good general techniques and by filtering the VCC plane. It is generally difficult
to predict in advance the performance of any design, although certain factors greatly increase the
risk of having problems:
• Poorly-regulated or over-burdened power supplies.
• Wide data busses (32-bits+) running at a high clock rate.
• DC-to-DC converters.
88
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Intel recommends filtering the power supply to the analog VCC pins of the LXT9785. This has two
benefits. First, it keeps digital switching noise out of the analog circuitry inside the LXT9785,
helping with line performance. Second, if the VCC planes are laid out correctly, digital switching
noise is kept away from external connectors, reducing EMI problems.
The recommended implementation is to break the VCC plane into two sections. The digital section
supplies power to the VCCD and VCCIO pins of the LXT9785. The analog section supplies power
to the VCCA pins. The break between the two planes should run underneath the device. In designs
with more than one the LXT9785, a single continuous analog VCC plane can be used to supply
them all.
The digital and analog VCC planes should be joined at one or more points by ferrite beads. The
beads should produce at least a 100Ω impedance at 100 MHz. Beads should be placed so that
current flow is evenly distributed. The maximum current rating of the beads should be at least
150% of the current that is actually expected to flow through them. A bulk cap (2.2 -10 uF) should
be placed on each side of each bead.
In addition, a high-frequency bypass cap (0.01uF) should be placed near each analog VCC pin.
3.2.2
Power and Ground Plane Layout Considerations
Great care needs to be taken when laying out the power and ground planes.
• Follow the guidelines in the LXT9785 Design and Layout Guide (Application Note 151) for
locating the split between the digital and analog VCC planes.
• Keep the digital VCC plane away from the TPFOP/N and TPFIP/N signals, the magnetics, and
the RJ-45 connectors.
• Place the layers so that the TPFOP/N and TFPIP/N signals can be routed near or next to the
ground plane. For EMI reasons, it is more important to shield TPFOP/N than TPFIP/N.
3.2.2.1
Chassis Ground
For ESD reasons, it is a good design practice to create a separate chassis ground that encircles the
board and is isolated via moats and keep-out areas from all circuit-ground planes and active
signals. Chassis ground should extend from the RJ-45 connectors to the magnetics, and can be used
to terminate unused signal pairs (Bob Smith termination). In single-point grounding applications,
provide a single connection between chassis and circuit grounds with a 2 kV isolation capacitor. In
multi-point grounding schemes (chassis and circuit grounds joined at multiple points), provide
2 kV isolation to the Bob Smith termination.
3.2.3
MII Terminations
Series termination resistors are required on all the SS-SMII output signals driven by the LXT9785.
Special trace layout consideration should be used when using the SMII interface. Keep all traces
orthogonal and as short as possible. Whenever possible, route the clock and sync traces evenly
between the longest and shortest data routes. This minimizes round-trip, clock-to-data delays and
allows a larger margin to the setup and hold requirements.
Datasheet
89
LXT9785 — Advanced 10/100 8-Port PHY
3.2.4
Twisted-Pair Interface
Use the following standard guidelines for a twisted-pair interface:
•
•
•
•
•
Place the magnetics as close as possible to the LXT9785.
Keep transmit pair traces as short as possible; both traces should have the same length.
Avoid vias and layer changes as much as possible.
Keep the transmit and receive pairs apart to avoid cross-talk.
Route the transmit pair adjacent to a ground plane. The optimum arrangement is to place the
transmit traces two to three layers from the ground plane, with no intervening signals.
• Improve EMI performance by filtering the TPO center tap. A single ferrite bead rated at 400
mA may be used to supply center tap current to all ports.
3.2.4.1
Magnetics Information
The LXT9785 requires a 1:1 ratio for the receive transformers and a 1:1 ratio for the transmit
transformers. The transformer isolation voltage should be rated at 2 kV to protect the circuitry from
static voltages across the connectors and cables. Refer to Table 25 on page 91 for transformer
requirements. Before committing to a specific component, designers should contact the
manufacturer for current product specifications, and validate the magnetics for the specific
application.
3.2.5
The Fiber Interface
The fiber interface consists of a PECL transmit and receive pair to an external fiber-optic
transceiver. The transmit and receive pair should be DC-coupled to the transceiver, and biased
appropriately. Refer to the fiber transceiver manufacturer’s recommendations for termination
circuitry. Figure 35 on page 93 shows a typical example.
3.2.6
LED Circuit
Each Direct Drive LED has a corresponding open-drain pin. The LEDs are connected via a currentlimiting resistor to a positive-voltage rail. The LEDs are turned on when the output pin drives Low.
The open-drain LED pins are 5V tolerant, allowing use of either a 3.3V or 5V rail. A 5V rail eases
LED component selection by allowing more common, high-forward voltage LEDs to be used.
Refer to Figure 32 for a circuit illustration.
90
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Figure 32. LED Circuit
VLED
R
LEDn_m
Inside
IC
Outside
IC
VLED = 3.3 to 5 Volts +/- 5%
Table 25. Magnetics Requirements
Parameter
Min
Nom
Max
Units
Rx turns ratio
–
1:1
–
–
Tx turns ratio
–
1:1
–
–
Insertion loss
0.0
0.6
1.1
dB
Primary inductance
Test Condition
350
–
–
µH
Transformer isolation
–
2
–
kV
Differential to common mode
rejection
40
–
–
dB
.1 to 60 MHz
35
–
–
dB
60 to 100 MHz
-16
–
–
dB
30 MHz
-10
–
–
dB
80 MHz
Return Loss
Datasheet
91
LXT9785 — Advanced 10/100 8-Port PHY
3.3
Typical Application Circuits
Figure 33 through Figure 35 show typical application circuits for the LXT9785.
Figure 33. Power and Ground Supply Connections
SGND
GNDR/GNDT
0.01µF
VCCR/VCCT
10µF
Analog Supply Plane
LXT9785
+
Ferrite
Bead
Digital Supply Plane
10µF
VCCD
+2.5V
0.01µF
GNDD
0.01µF
+ 2.5V
or +3.3V
VCCIO
+2.5V
or +3.3V
VCCPECL
0.1µF
GNDPECL
92
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Figure 34. Typical Twisted-Pair Interface
TPFOP
1
1
2
3
50 Ω
TPFON
50 Ω
4
TPFIP
50 Ω
1:1
5
LXT9785
6
50 Ω
2
To Twisted-Pair Network
RJ-45
1:1
7
50 Ω
50 Ω
8
TPFIN
.01 µF
* = 0.001 µF /
2.0 kV
* = 0.001 µF /
2.0 kV
VCCT
.01µF
0.1µF
GNDA
1. The 100Ω transmit load termination resistor typically required is integrated in the LXT9785.
2. The 100Ω receive load termination resistor typically required is integrated in the LXT9785.
Figure 35. Typical Fiber Interface
VCCPECL
+3.3V
+3.3V
27 Ω
50 Ω
0.01- 0.1uF
50 Ω
TPFONn
TD-
TPFOPn
Fiber Txcvr
LXT9785
130 Ω
SD/TPn
SD
82 Ω
To Fiber Network
TD+
VCCPECL
+3.3V
1
GNDS
TPFINn
RD-
TPFIPn
RD+
2D_2P5V
130 Ω
130 Ω
GNDPECL
3.3V
GNDS
VCCPECL
1. The SD_2P5V pin must be connected to the VCCPECL supply.
Datasheet
93
LXT9785 — Advanced 10/100 8-Port PHY
4.0
Test Specifications
Note:
Table 26 through Table 55 and Figure 36 through Figure 59 represent the target specifications of
the LXT9785. These specifications are not guaranteed and are subject to change without notice.
Minimum and maximum values listed in Table 28 through Table 55 apply over the recommended
operating conditions specified in Table 27.
Table 26. Absolute Maximum Ratings
Parameter
Sym
Min
Max
Units
VCC
-0.3
3.46
V
Ambient
TOPA
0
+85
ºC
Case
TOPC
–
+120
ºC
TST
-65
+150
ºC
Supply voltage
Operating temperature
Storage temperature
Caution:
Exceeding these values may cause permanent damage. Functional operation under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 27. Operating Conditions
Parameter
Sym
Min
Typ1
(2.5 VCCIO)
Typ1
(3.3 VCCIO)
Max
Units
Ambient
TOPA
0
–
70
ºC
Case
TOPC
0
–
108
ºC
Analog & Digital
Vcca, Vccd
2.38
2.5
2.5
2.63
V
I/O
Vccio
2.38
2.5
3.3
3.46
V
3.14
N/A
3.3
3.46
V
2.38
2.5
N/A
2.63
V
810
mA
130
160
mA
410
mA
170
200
mA
765
mA
90
mA
20
mA
4
mA
540
mA
4
mA
Operating temperature
Supply voltage2
I/O (SD_2P5V = 0)
VCCPECL
I/O (SD_2P5V = 1)
ICC
–
ICCIO
–
780
100BASE-TX
ICC
–
ICCIO
–
ICC
–
ICCIO
–
60
380
100BASE-FX
Operating Current - RMII
90
710
10BASE-T
Power-Down Mode
Hardware
ICC
–
ICCIO
–
ICC
–
ICCIO
–
30
70
20
2
3
500
Auto-Negotiation
2
4
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Voltages with respect to ground unless otherwise specified.
94
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Table 27. Operating Conditions (Continued)
Parameter
Sym
Typ1
(2.5 VCCIO)
Min
ICC
–
ICCIO
–
ICC
–
ICCIO
–
ICC
–
Typ1
(3.3 VCCIO)
800
Max
Units
830
mA
100BASE-TX
70
130
380
160
mA
410
mA
200
mA
770
mA
130
mA
50
mA
5
mA
570
mA
100BASE-FX
Operating Current - SMII
90
170
740
10BASE-T
Power-Down Mode
Hardware
ICCIO
–
ICC
–
ICCIO
–
ICC
–
60
110
50
3
5
520
Auto-Negotiation
ICCIO
–
ICC
–
ICCIO
–
ICC
–
20
30
800
30
mA
835
mA
200
mA
410
mA
100BASE-TX
90
170
380
100BASE-FX
Operating Current SS-SMII
ICCIO
–
ICC
–
ICCIO
–
ICC
–
ICCIO
–
ICC
–
ICCIO
–
90
170
740
200
mA
770
mA
180
mA
40
mA
10BASE-T
Power-Down Mode
Hardware
90
150
30
3
5
530
5
mA
570
mA
80
mA
Auto-Negotiation
50
70
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Voltages with respect to ground unless otherwise specified.
Table 28. Digital I/O Characteristics (VCCIO = 2.5V +/- 5%)
Parameter
Sym
Min
Typ1
Max
Units
Test Conditions
Input Low voltage
VIL
–
–
0.75
V
–
Input High voltage
VIH
1.75
–
–
V
–
II
-100
–
100
µA
0.0 < VI < VCC
VOL
–
–
0.2
V
IOL = 4 mA
VOL-LED
–
–
0.5
V
IOL = 10 mA
VOH
2.07
–
–
V
IOH = -4 mA
Input Low voltage SD pins
VIL-SD
–
–
0.755
V
–
Input High voltage SD pins
VIH-SD
1.58
–
–
V
–
Input current
Output Low voltage
Output Low voltage (LEDm_n pins)
Output High voltage
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Datasheet
95
LXT9785 — Advanced 10/100 8-Port PHY
Table 29. Digital I/O Characteristics (VCCIO = 3.3V +/- 5%)
Parameter
Sym
Min
Typ1
Max
Units
Test Conditions
Input Low voltage
VIL
–
–
0.8
V
–
Input High voltage
VIH
2.0
–
–
V
–
II
-100
–
100
µA
0.0 < VI < VCC
VOL
–
–
0.2
V
IOL = 4 mA
VOL-LED
–
–
0.4
V
IOL = 10 mA
VOH
2.4
–
–
V
IOH = -4 mA
Input Low voltage SD pins
VIL-SD
–
–
1.515
V
–
Input High voltage SD pins
VIH-SD
2.42
–
–
V
–
Input current
Output Low voltage
Output Low voltage (LEDm_n pins)
Output High voltage
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Table 30. Required Clock Characteristics
Sym
Min
Typ2
Max
Units
Test Conditions
SMII Input frequency
–
–
125
–
MHz
–
RMII Input frequency
F
–
50
–
MHz
–
∆f
–
–
± 50
ppm
–
Tdc
35
50
65
%
RMII selection
Tdc
40
50
60
%
SMII/SS-SMII selection
Tdc
45
50
55
%
SS-SMII only
Parameter
Input clock frequency tolerance
Input clock duty cycle
1
1
Input clock duty cycle - RefClk,TxCLK
1
Output RxClk duty cycle
1. Parameter is guaranteed by design; not subject to production testing.
2. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Table 31. 100BASE-TX Transceiver Characteristics
Sym
Min
Typ1
Max
Units
Test Conditions
Peak differential output voltage
VP
0.95
–
1.05
V
Note 2
Signal amplitude symmetry
Vss
98
–
102
%
Note 2
Signal rise/fall time
trf
3
–
5
ns
Note 2
Rise/fall time symmetry
trfs
–
–
0.5
ns
Note 2
Parameter
–
–
–
+/- 0.5
ns
Offset from 16 ns pulse width at
50% of pulse peak
Overshoot
VO
–
–
5
%
–
Jitter magnitude (measured
differentially)
ttx-jit
–
–
14
ns
–
Duty cycle distortion
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Measured at the line side of the transformer, line replaced by 100Ω (+/-1%) resistor.
96
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Table 32. 100BASE-FX Transceiver Characteristics
Parameter
Sym
Min
Typ1
Max
Units
Test Conditions
Transmitter
Peak differential output voltage
(single ended)
VOP
0.6
1.44
–
V
–
trf
–
–
1.6
ns
10 to 90%, 2.0 pF load
ttx-jit
–
–
1.4
ns
–
Signal rise/fall time
Jitter magnitude (measured
differentially)
Receiver
Peak differential input voltage
Common mode input range
VIP
0.55
–
–
V
–
VCMIR
–
–
VCC - 0.5
V
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Table 33. 10BASE-T Transceiver Characteristics
Parameter
Sym
Min
Typ1
Max
Units
Test Conditions
Transmitter
Peak differential output voltage
Link transmit period
Jitter magnitude added by the
MAU and PLS sections 3, 4
VOP
2.2
2.5
2.8
V
Note 2
–
8
–
24
ms
–
ttx-jit
–
–
11
ns
–
Receiver
ZIN
–
100
–
Ω
Between TPFIP and TPFIN
Link min receive timer
TLRmin
2
–
7
ms
–
Link max receive timer
TLRmax
50
–
150
ms
–
VDS
–
475
–
mV Peak
5 MHz square wave input
Receive input impedance3
Differential squelch threshold
1.
2.
3.
4.
Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Parameter is guaranteed by design; not subject to production testing.
IEEE 802.3 specifies maximum jitter addition at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and 3.5 ns from the MAU.
After line model specified by IEEE 802.3 for 10BASE-T MAU.
Datasheet
97
LXT9785 — Advanced 10/100 8-Port PHY
Figure 36. SMII - 100BASE-TX Receive Timing
REFCLK
t5
t6
SYNC
t1
t2
RXD
t3
t4
TPFI
Table 34. SMII - 100BASE-TX Receive Timing Parameters
Parameter
Sym
Min
Typ1
Max
Units
RXD output delay from REFCLK rising
edge
t1
1.5
–
5
ns
RXD Rise/Fall Time
t2
–
1.0
–
ns
Receive start of /J/ to CRS asserted
t3
–
21
29
BT2
Synchronous sampling of
SMII
Receive start of /T/ to CRS deasserted
t4
–
25
30
BT2
Synchronous sampling of
SMII
SYNC setup to REFCLK rising edge
t5
1.5
–
–
ns
–
SYNC hold from REFCLK rising edge
t6
1.0
–
–
ns
–
Test Conditions
Minimum CL = 5 pF
Maximum CL = 20 pF
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASETX or 100BASE-FX).
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Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Figure 37. SMII - 100BASE-TX Transmit Timing
REFCLK
t1
t2
SYNC
t1
t2
TXD
t3
TPFO
Table 35. SMII - 100BASE-TX Transmit Timing Parameters
Sym
Min
Typ1
Max
Units
Test
Conditions
SYNC setup to REFCLK rising edge and
TXD setup to REFCLK rising edge
t1
1.5
–
–
ns
–
SYNC hold from REFCLK rising edge and
TXD hold from REFCLK rising edge
t2
1.0
–
–
ns
–
TXEN sampled to start of /J/
t3
–
11
14
BT2
–
Parameter
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASETX or 100BASE-FX).
Datasheet
99
LXT9785 — Advanced 10/100 8-Port PHY
Figure 38. SMII - 100BASE-FX Receive Timing
REFCLK
t5
t6
SYNC
t1
t2
RXD
t3
t4
TPFI
Table 36. SMII - 100BASE-FX Receive Timing Parameters
Parameter
Sym
Min
Typ1
Max
Units
Test Conditions
RXD output delay from REFCLK rising
edge
t1
1.5
–
5
ns
Minimum CL = 5 pF
Maximum CL = 20 pF
RXD Rise/Fall Time
t2
–
1
–
ns
–
Receive start of /J/ to CRS asserted
t3
–
18
26
BT2
Synchronous
sampling of SMII
Receive start of /T/ to CRS deasserted
t4
–
23
27
BT2
Synchronous
sampling of SMII
SYNC setup to REFCLK rising edge
t5
1.5
–
–
ns
–
SYNC hold from REFCLK rising edge
t6
1.0
–
–
ns
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASETX or 100BASE-FX).
100
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Figure 39. SMII - 100BASE-FX Transmit Timing
REFCLK
t1
t2
SYNC
t1
t2
TXD
t3
TPFO
Table 37. SMII - 100BASE-FX Transmit Timing Parameters
Parameter
Sym
Min
Typ1
Max
Units
Test Conditions
SYNC setup to REFCLK rising edge and
TXD setup to REFCLK rising edge
t1
1.5
–
–
ns
–
SYNC hold from REFCLK rising edge
and TXD hold from REFCLK rising edge
t2
1.0
–
–
ns
–
TXEN sampled to start of /J/
t3
–
10
13
BT2
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASETX or 100BASE-FX).
Datasheet
101
LXT9785 — Advanced 10/100 8-Port PHY
Figure 40. SMII - 10BASE-T Receive Timing
REFCLK
t5
t6
SYNC
t1
t2
RXD
t3
t4
TPFI
Table 38. SMII - 10BASE-T Receive Timing Parameters
Sym
Min
Typ1
Max
Units
RXD output delay from
REFCLK rising edge
t1
1.5
–
5
ns
Parameter
Test Conditions
Minimum CL = 5 pF
Maximum CL = 20 pF
RXD Rise/Fall Time
t2
–
1
–
ns
Receive Start-of-Frame to CRS
asserted
–
t3
–
17
18
BT3
Synchronous sampling of SMII2
Receive Start-of-Idle to CRS
de-asserted
t4
–
17
18
BT3
Synchronous sampling of SMII2
SYNC setup to REFCLK rising
edge
t5
1.5
–
–
ns
–
SYNC hold from REFCLK rising
edge
t6
1.0
–
–
ns
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. Assumes each SMII segment is sampled for CRS.
3. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASETX or 100BASE-FX).
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Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Figure 41. SMII - 10BASE-T Transmit Timing
REFCLK
t1
t2
SYNC
t1
t2
TXD
t3
TPFO
Table 39. SMII-10BASE-T Transmit Timing Parameters
Sym
Min
Typ1
Max
Units
Test
Conditions
SYNC setup to REFCLK rising edge and
TXD setup to REFCLK rising edge
t1
1.5
–
–
ns
–
SYNC hold to REFCLK rising edge and
TXD hold from REFCLK rising edge
t2
1.0
–
–
ns
–
TXEN sampled to start-of-frame
t3
–
10
12.5
BT2
–
Parameter
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASETX or 100BASE-FX).
Datasheet
103
LXT9785 — Advanced 10/100 8-Port PHY
Figure 42. Source Synchronous SMII 100BASE-TX Receive Timing
REFCLK
t1
RX_CLK
t2
RX_SYNC
t3
t3
t3
RXD
t4
t5
TPFI
Table 40. Source Synchronous SMII 100BASE-TX Receive Timing Parameters
Sym
Min
Typ1
Max
Units
Test Conditions
REFCLK rising edge to RX_CLK
rising edge
t1
–
1.5
–
ns
–
RXD/RX_SYNC output delay from
RX_CLK rising edge
t2
1.5
–
5
ns
Minimum CL = 5 pF
Maximum CL = 40 pF
RXD/RX_SYNC Rise/Fall time
t3
–
1.0
–
ns
–
Receive start of /J/ to CRS
asserted
t4
–
21
25
BT2
–
Receive start of /T/ to CRS
deasserted
t5
–
25
30
BT2
–
Parameter
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASETX or 100BASE-FX).
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Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Figure 43. Source Synchronous SMII 100BASE-TX Transmit Timing
TX_CLK
t1
t2
TX_SYNC
t1
t2
TXD
t3
TPFO
Table 41. Source Synchronous SMII 100BASE-TX Transmit Timing
Sym
Min
Typ1
Max
Units
Test
Conditions
SYNC setup to TX_CLK rising edge and
TXD setup to TX_CLK rising edge
t1
1.5
–
–
ns
–
SYNC hold from TX_CLK rising edge and
TXD hold to TX_CLK rising edge
t2
1.0
–
–
ns
–
TXEN sampled to start of /J/
t3
–
11
14
BT2
–
Parameter
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASETX or 100BASE-FX).
Datasheet
105
LXT9785 — Advanced 10/100 8-Port PHY
Figure 44. Source Synchronous SMII - 100BASE-FX Receive Timing
REFCLK
t1
RX_CLK
t2
RX_SYNC
t3
t3
t3
RXD
t4
t5
TPFI
Table 42. Source Synchronous SMII - 100BASE-FX Receive Timing Parameters
Parameter
Sym
Min
Typ1
REFCLK rising edge to RxCLK rising edge
t1
–
1.5
RXD/RX_SYNC output delay from
RX_CLK rising edge
t2
1.5
–
RXD/RX_SYNC Rise/Fall time
t3
–
1
Receive start of /J/ to CRS asserted
Receive start of /T/ to CRS deasserted
t4
t5
–
–
18
21
Max
Units
Test Conditions
ns
–
5
ns
Minimum CL = 5 pF
Maximum CL = 40 pF
–
ns
–
23
26
BT
2
–
BT
2
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASETX or 100BASE-FX).
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Datasheet
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Figure 45. Source Synchronous SMII - 100BASE-FX Transmit Timing
TX_CLK
t1
t2
TX_SYNC
t1
t2
TXD
t3
TPFO
Table 43. Source Synchronous SMII - 100BASE-FX Transmit Timing Parameters
Sym
Min
Typ1
Max
Units
Test Conditions
SYNC setup to REFCLK rising edge and
TXD setup to REFCLK rising edge
t1
1.5
–
–
ns
–
SYNC hold from REFCLK rising edge and
TXD hold to REFCLK rising edge
t2
1.0
–
–
ns
–
TXD to TPFO Latency
t3
–
11
13
BT2
–
Parameter
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASETX or 100BASE-FX).
Datasheet
107
LXT9785 — Advanced 10/100 8-Port PHY
Figure 46. Source Synchronous SMII - 10BASE-T Receive Timing
REFCLK
t1
RX_CLK
t2
RX_SYNC
t3
RXD
t4
t5
TPFI
Table 44. Source Synchronous SMII - 10BASE-T Receive Timing Parameters
Sym
Min
Typ1
Max
Units
Test Conditions
REFCLK rising edge to RX_CLK rising
edge
t1
–
1.5
–
ns
–
RXD/RX_SYNC output delay from
RX_CLK rising edge
t2
1.5
–
5
ns
RXD/RX_SYNC Rise/Fall time
t3
–
1
–
ns
–
Parameter
Minimum CL = 5 pF
Maximum CL = 40 pF
Receive Start-of-Frame to CRS asserted
t4
–
10
11
BT3
Synchronous sampling of
SMII2
Receive Start-of-Idle to CRS de-asserted
t5
–
18
19
BT3
Synchronous sampling of
SMII2
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. Assumes each SMII segment is sampled for CRS.
3. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASETX or 100BASE-FX).
108
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Figure 47. Source Synchronous SMII - 10BASE-T Transmit Timing
TX_CLK
t1
t2
TX_SYNC
t1
t2
TXD
t3
TPFO
Table 45. Source Synchronous SMII - 10BASE-T Transmit Timing Parameters
Sym
Min
Typ1
Max
Units
Test
Conditions
TX_SYNC setup to TX_CLK rising edge and
TXD setup to TX_CLK rising edge
t1
1.5
–
–
ns
–
TX_SYNC hold to TX_CLK rising edge and
TXD hold from TX_CLK rising edge
t2
1.0
–
–
ns
–
TXD to TPFO Latency
t3
–
10
12.5
BT2
–
Parameter
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASETX or 100BASE-FX).
Datasheet
109
LXT9785 — Advanced 10/100 8-Port PHY
Figure 48. RMII - 100BASE-TX Receive Timing
REFCLK
t1
t5
t2
t6
RXD(1:0)
TPFI
t3
t4
CRS_DV
Table 46. RMII - 100BASE-TX Receive Timing Parameters
Sym
Min
Typ1
Max
Units
Test
Conditions
RXD<1:0>/CRS_DV output delay from REFCLK
rising edge3
t1
2
–
14
ns
–
Receive start of /J/ to CRS_DV asserted
t2
–
20
27
BT2
–
27
2
–
Parameter
Receive start of /T/ to CRS_DV de-asserted
t3
–
20
BT
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASETX or 100BASE-FX).
3. Values and conditions from RMII Specification, Rev. 1.2.
110
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Figure 49. RMII - 100BASE-TX Transmit Timing
REFCLK
t1
t2
TXD(1:0)
TPFO
t1
t3
t2
TX_EN
Table 47. RMII - 100BASE-TX Transmit Timing Parameters
Parameter
Sym
Min
Typ1
Max
Units
Test
Conditions
TXD<1:0>/TX_EN setup to REFCLK rising edge
t1
4
–
–
ns
–
TXD<1:0>/TX_EN hold from REFCLK rising
edge
t2
2
–
–
ns
–
TX_EN sampled to TPFO out (Tx latency)
t3
–
12
13
BT2
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASETX or 100BASE-FX).
Datasheet
111
LXT9785 — Advanced 10/100 8-Port PHY
Figure 50. RMII - 100BASE-FX Receive Timing
REFCLK
t1
t1
RXD(1:0)
TPFI
t2
t3
CRS_DV
Table 48. RMII - 100BASE-FX Receive Timing Parameters
Parameter
Sym
Min
Typ1
Max
Units
Test
Conditions
RXD<1:0>/CRS_DV output delay from REFCLK
rising edge3
t1
2
–
14
ns
–
Receive start of /J/ to CRS_DV asserted
t2
–
18
25
BT2
–
25
2
–
Receive start of /T/ to CRS_DV de-asserted
t3
–
18
BT
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASETX or 100BASE-FX).
3. Values and conditions from RMII Specification, Rev. 1.2.
112
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Figure 51. RMII - 100BASE-FX Transmit Timing
REFCLK
t1
t2
TXD(1:0)
TPFO
t1
t3
t2
TX_EN
Table 49. RMII - 100BASE-FX Transmit Timing Parameters
Parameter
Sym
Min
Typ1
Max
Units
Test
Conditions
TXD<1:0>/TX_EN setup to REFCLK rising edge
t1
4
–
–
ns
–
TXD<1:0>/TX-EN hold from REFCLK rising edge
t2
2
–
–
ns
–
TX_EN sampled to TPFO out (Tx latency)
t3
–
10
12
BT
2
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASETX or 100BASE-FX).
Datasheet
113
LXT9785 — Advanced 10/100 8-Port PHY
Figure 52. RMII - 10BASE-T Receive Timing
REFCLK
t1
t1
RXD(1:0)
TPFI
t2
t3
CRS_DV
Table 50. RMII - 10BASE-T Receive Timing Parameters
Sym
Min
Typ1
Max
Units
Test
Conditions
RXD<1:0>/CRS_DV output delay from REFCLK
rising edge3
t1
2
–
14
ns
–
TPFI in to CRS_DV asserted
t2
1.5
3
4
BT2
–
2
–
Parameter
TPFI quiet to CRS_DV de-asserted
t3
14
15
16
BT
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASETX or 100BASE-FX).
3. Values and conditions from RMII Specification, Rev. 1.2.
114
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Figure 53. RMII - 10BASE-T Transmit Timing
REFCLK
t1
t2
TXD(1:0)
TPFO
t1
t3
t2
TX_EN
Table 51. RMII - 10BASE-T Transmit Timing Parameters
Parameter
Sym
Min
Typ1
Max
Units
Test
Conditions
TXD<1:0>/TX_EN setup to REFCLK rising edge
t1
4
–
–
ns
–
TXD<1:0>/TX_EN hold from REFCLK rising
edge
t2
2
–
–
ns
–
TX_EN sampled to TPFO out (Tx latency)
t3
–
8.5
10.5
BT2
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASETX or 100BASE-FX).
Datasheet
115
LXT9785 — Advanced 10/100 8-Port PHY
Figure 54. Auto-Negotiation and Fast Link Pulse Timing
Clock Pulse
Data Pulse
t1
t1
Clock Pulse
TPFOP
t2
t3
Figure 55. Fast Link Pulse Timing
FLP Burst
FLP Burst
TPFOP
t4
t5
Table 52. Auto-Negotiation and Fast Link Pulse Timing Parameters
Sym
Min
Typ1
Max
Units
Test Conditions
Clock/Data pulse width
t1
–
100
–
ns
–
Clock pulse to Data pulse
t2
55.5
–
69.5
µs
–
Clock pulse to Clock pulse
t3
111
–
139
µs
–
FLP burst width
t4
–
–
–
ms
–
FLP burst to FLP burst
t5
8
–
24
ms
–
Clock/Data pulses per burst
–
17
–
33
ea
–
Parameter
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
116
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Figure 56. MDIO Write Timing (MDIO Sourced by MAC)
MDC
t2
t1
MDIO
Figure 57. MDIO Read Timing (MDIO Sourced by PHY)
MDC
t3
MDIO
Table 53. MDIO Timing Parameters
Parameter
Sym
Min
Typ1
Max
Units
Test Conditions
MDIO setup before MDC, sourced by
STA
t1
10
–
–
ns
–
MDIO hold after MDC,
sourced by STA
t2
10
–
–
ns
–
MDC to MDIO output delay, sourced
by PHY
t3
0
–
40
ns
–
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production
testing.
Datasheet
117
LXT9785 — Advanced 10/100 8-Port PHY
Figure 58. Power-Up Timing
v1
VCC
tPDR
MDIO,etc
Table 54. Power-Up Timing Parameters
Parameter
Sym
Voltage Threshold
Power-Up recovery time
Min
Typ1
Max
Units
Test Conditions
v1
2.1
–
–
V
–
tPDR
100
–
–
ms
–
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production
testing.
Figure 59. Reset Recovery Timing
tPW
RESET
tRcdly
MDIO,etc
Table 55. Reset Recovery Timing Parameters
Parameter
Reset pulse width
Reset recovery delay
Sym
Min
Typ1
Max
Units
Test Conditions
tPW
10
–
–
ns
–
tRcdly
0.4
–
–
ms
–
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production
testing.
118
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
5.0
Register Definitions
The LXT9785 register set includes multiple 16-bit registers, 17 registers per port. Table 56 presents
a complete register listing. Table 57 through Table 72 define individual registers and Table 74
provides a consolidated memory map of all registers.
Base registers (0 through 8) are defined in accordance with the “Reconciliation Sublayer and
Media Independent Interface” and “Physical Layer Link Signalling for 10/100Mbps AutoNegotiation” sections of the IEEE 802.3 standard.
Additional registers (16 through 20) are defined in accordance with the IEEE 802.3 standard for
adding unique chip functions.
Table 56. Register Set
Address
Bit Assignments
0
Control Register
Refer to Table 57 on page 120
1
Status Register
Refer to Table 58 on page 121
2
PHY Identification Register 1
Refer to Table 59 on page 122
3
PHY Identification Register 2
Refer to Table 60 on page 122
4
Auto-Negotiation Advertisement Register
Refer to Table 61 on page 123
5
Auto-Negotiation Link Partner Base Page Ability Register
Refer to Table 62 on page 124
6
Auto-Negotiation Expansion Register
Refer to Table 63 on page 125
7
Auto-Negotiation Next Page Transmit Register
Refer to Table 64 on page 125
8
Auto-Negotiation Link Partner Next Page Receive Register
Refer to Table 65 on page 126
9
1000BASE-T/100BASE-T2 Control Register
Not Implemented
10
1000BASE-T/100BASE-T2 Status Register
Not Implemented
15
Extended Status Register
Not Implemented
16
Port Configuration Register
Refer to Table 66 on page 127
17
Quick Status Register
Refer to Table 67 on page 128
18
Interrupt Enable Register
Refer to Table 68 on page 128
19
Interrupt Status Register
Refer to Table 69 on page 130
20
LED Configuration Register
Refer to Table 70 on page 131
21
Receive Error Count Register
Refer to Table 71 on page 132
22
Reserved
23 - 24
Reserved
25
RMII Out-of-Band Signalling Register
26
Reserved
27
Trim Enable Register
28-31
Datasheet
Register Name
Refer to Table 72 on page 133
Refer to Table 73 on page 133
Reserved
119
LXT9785 — Advanced 10/100 8-Port PHY
Table 57. Control Register (Address 0)
Bit
Name
0.15
Reset
0.14
Loopback
Description
Type 2
Default
1 = PHY reset
R/W
0 = normal operation
SC
1 = Enable loopback mode
0 = Disable loopback mode
R/W
0
R/W
LHR3
R/W
LHR3
0.6
0.13
1
1
0
0
1 = Reserved
0 = 1000Mbps (not allowed)
1 = 100Mbps
0 = 10Mbps
01
0.134
Speed Selection
0.124
Auto-Negotiation
Enable
0.11
Power-Down
1 = power-down
0 = normal operation
R/W
0
0.10
Isolate
1 = Electrically isolate PHY from RMII or SMII interface
0 = normal operation
R/W
0
0.9
Restart
Auto-Negotiation
0.84
Duplex Mode
0.7
Collision Test
1 = Enable Auto-Negotiation Process
0 = Disable Auto-Negotiation Process
1 = Restart Auto-Negotiation Process
0 = normal operation
1 = Full Duplex
0 = Half Duplex
R/W
SC
01
R/W
LHR3
R/W
0
R/W
00
R/W
00000
This bit is ignored by the LXT9785
1 = Enable COL signal test
0 = Disable COL signal test
0.6
0.13
1 = Reserved
0 = 1000Mbps (not allowed)
1 = 100Mbps
0 = 10Mbps
0.6
Speed Selection
1000 Mb/s
1
1
0
0
0.5:0
Reserved
Write as 0, ignore on Read
1. During a hardware reset, all LHR information is latched in from the pins. During a software reset (0.15), the
LHR information is not re-read from the pins. This information reverts back to the information that was read
in during the hardware reset. During a hardware rest, register information is unavailable from 1 ms after deassertion of the reset. During a software reset (0.15) the registers are available for reading. The reset bit
should be polled to see when the part has completed reset.
2. R/W = Read/Write, RO = Read Only, SC = Self Clearing when read.
3. LHR = Latched on Hardware Reset. Bits 0.12, 0.13, and 0.8 are initialized based on the pin configuration
value.
4. Default value of bits 0.12, 0.13, and 0.8 are determined by hardware pins.
120
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Table 58. Status Register (Address 1)
Bit
Name
Description
Type 1
Default
1.15
100BASE-T4
1 = PHY able to perform 100BASE-T4
0 = PHY not able to perform 100BASE-T4
RO
0
1.14
100BASE-X Full
Duplex
1 = PHY able to perform full-duplex 100BASE-X
0 = PHY not able to perform full-duplex 100BASE-X
RO
1
1.13
100BASE-X Half
Duplex
1 = PHY able to perform half-duplex 100BASE-X
0 = PHY not able to perform half-duplex 100BASE-X
RO
1
1.12
10Mbps Full Duplex
1 = PHY able to operate at 10Mbps in full-duplex mode
0 = PHY not able to operate at 10Mbps full-duplex
mode
RO
1
1.11
10Mbps Half Duplex
1 = PHY able to operate at 10Mbps in half-duplex mode
0 = PHY not able to operate at 10Mbps in half-duplex
RO
1
1.10
100BASE-T2 Full
Duplex
1 = PHY able to perform full-duplex 100BASE-T2
0 = PHY not able to perform full-duplex 100BASE-T2
RO
0
1.9
100BASE-T2 Half
Duplex
1 = PHY able to perform half duplex 100BASE-T2
0 = PHY not able to perform half-duplex 100BASE-T2
RO
0
1.8
Extended Status
1 = Extended status information in register 15
0 = No extended status information in register 15
RO
0
1.7
Reserved
1 = Ignore on read
RO
0
1.6
MF Preamble
Suppression
1 = PHY accepts management frames with preamble
suppressed
0 = PHY will not accept management frames with
preamble suppressed
RO
0
1.5
Auto-Negotiation
complete
1 = Auto-negotiation complete
0 = Auto-negotiation not complete
RO
0
1.4
Remote Fault
1 = Remote fault condition detected
0 = No remote fault condition detected
1.3
Auto-Negotiation
Ability
1 = PHY is able to perform Auto-Negotiation
0 = PHY is not able to perform Auto-Negotiation
1.2
Link Status
1 = Link is up
0 = Link is down
1.1
Jabber Detect
1 = Jabber condition detected
0 = Jabber condition not detected
1.0
Extended Capability
1 = Extended register capabilities
0 = Basic register capabilities
RO/LH
Note 2
RO
RO/LL
Note 2
RO/LH
Note 2
RO
0
1
0
0
1
1. RO = Read Only
2. Bits that Latch High (LH) or Latch Low (LL) automatically clear when read.
Datasheet
121
LXT9785 — Advanced 10/100 8-Port PHY
Table 59. PHY Identification Register 1 (Address 2)
Bit
Name
Description
Type 1
Default
2.15:0
PHY ID Number
The PHY identifier composed of bits 3 through 18 of the
OUI
RO
0013 hex
1. RO = Read Only
Table 60. PHY Identification Register 2 (Address 3)
Type 1
Default
The PHY identifier composed of bits 19
through 24 of the OUI
RO
011110
Manufacturer’s
Model Number
6 bits containing manufacturer’s part number
RO
Manufacturer’s
Revision
Number
4 bits containing manufacturer’s revision
number
RO
Bit
Name
Description
3.15:10
PHY ID Number
3.9:4
3.3:0
001111
XXXX
(See Table 3 in
Specification
Update)
1. RO = Read Only
Figure 60. PHY Identifier Bit Mapping
a
b
r
c
s
x
18 19
24
Organizationally Unique Identifier
1
2
3
0
I/G
0
1
3
15
0
10
15
PHY ID Register #1 (Address 2)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
9
4
0
2
1
0
1
1
1
B
1
1
0
X
X
X
X
X
20
The Level One OUI is 00207B hex.
122
0
X
X
0
3
X
X
X
7
5
00
3
PHY ID Register #2 (Address 3)
7B
Manufacturer’s
Model Number
0
Revision
Number
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Table 61. Auto-Negotiation Advertisement Register (Address 4)4
Type 1
Default
1 = Port has ability to send multiple pages
0 = Port has no ability to send multiple pages
R/W
0
Reserved
Ignore on read
RO
0
4.13
Remote Fault
1 = Remote fault
0 = No remote fault
R/W
0
4.12
Reserved
Ignore
R/W
0
4.11
Asymmetric
Pause
Pause operation defined in Clause 40 and 27
R/W
0
4.10
Pause
1 = Pause operation enabled for full-duplex links
0 = Pause operation disabled
R/W
Note 2 &
Note 3
R/W
0
Bit
Name
4.15
Next Page
4.14
Description
1 = 100BASE-T4 capability is available
0 = 100BASE-T4 capability is not available
4.9
100BASE-T4
(The LXT9785 does not support 100BASE-T4 but allows this
bit to be set to advertise in the Auto-Negotiation sequence for
100BASE-T4 operation. An external 100BASE-T4 transceiver
could be switched in if this capability is desired.)
4.8
100BASE-TX
full duplex
1 = Port is 100BASE-TX full duplex capable
0 = Port is not 100BASE-TX full duplex capable.
R/W
Note 3
4.7
100BASE-TX
1 = Port is 100BASE-TX capable
0 = Port is not 100BASE-TX capable
R/W
Note 3
4.6
10BASE-T
full duplex
R/W
Note 3
4.5
10BASE-T
R/W
Note 3
R/W
00001
4.4:0
Selector
Field,
S<4:0>
1 = Port is 10BASE-T full duplex capable
0 = Port is not 10BASE-T full duplex capable
1 = Port is 10BASE-T capable
0 = Port is not 10BASE-T capable
<00001> = IEEE 802.3
<00010> = IEEE 802.9 ISLAN-16T
<00000> = Reserved for future Auto-Negotiation development
<11111> = Reserved for future Auto-Negotiation development
Unspecified or reserved combinations should not be
transmitted
1. R/W = Read/Write, RO = Read Only
2. The default setting of bit 4.10 (PAUSE) is determined by pin 50. Pause operation is only valid for full-duplex
modes.
3. Default settings for bits 4.5:8 are determined by CFG pins as described in Table 18 on page 62.
4. Restart Auto-Negotiation process whenever Reg 4. is written/modified.
Datasheet
123
LXT9785 — Advanced 10/100 8-Port PHY
Table 62. Auto-Negotiation Link Partner Base Page Ability Register (Address 5)
Bit
Name
Description
Type 1
Default
5.15
Next Page
1 = Link Partner has ability to send multiple pages
0 = Link Partner has no ability to send multiple pages
RO
0
5.14
Acknowledge
1 = Link Partner has received Link Code Word from the
LXT9785.
0 = Link Partner has not received Link Code Word from the
the LXT9785
RO
0
5.13
Remote Fault
1 = Remote fault
0 = No remote fault
RO
0
5.12
Reserved
Ignore on read
RO
0
5.11
Asymmetric
Pause
RO
0
5.10
Pause
1 = Link Partner is Pause capable
0 = Link Partner is not Pause capable
RO
0
5.9
100BASE-T4
1 = Link Partner is 100BASE-T4 capable
0 = Link Partner is not 100BASE-T4 capable
RO
0
5.8
100BASE-TX
full duplex
1 = Link Partner is 100BASE-TX full duplex capable
0 = Link Partner is not 100BASE-TX full duplex capable
RO
0
5.7
100BASE-TX
1 = Link Partner is 100BASE-TX capable
0 = Link Partner is not 100BASE-TX capable
RO
0
1 = Link Partner is 10BASE-T full duplex capable
0 = Link Partner is not 10BASE-T full duplex capable
RO
0
10BASE-T
1 = Link Partner is 10BASE-T capable
0 = Link Partner is not 10BASE-T capable
RO
0
Selector Field
S<4:0>
<00001> = IEEE 802.3
<00010> = IEEE 802.9 ISLAN-16T
<00000> = Reserved for future Auto-Negotiation development
<11111> = Reserved for future Auto-Negotiation development
Unspecified or reserved combinations shall not be transmitted
RO
00000
5.6
5.5
5.4:0
10BASE-T
full duplex
Pause operation defined in Clause 40 and 27
1 = Link Partner is Pause capable
0 = Link Partner is not Pause capable
1. RO = Read Only
124
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Table 63. Auto-Negotiation Expansion (Address 6)
Bit
6.15:6
6.5
Type 1
Default
Ignore on read
RO
0
This bit indicates the status of the Auto-Negotiation
variable, base page. It flags synchronization with the AutoNegotiation state diagram allowing detection of interrupted
links. This bit is only used if bit 16.1 (Alternate NP feature)
is set.
RO/
LH
0
Name
Reserved
Base Page
Description
1 = base_page = true
0 = base_page = false
6.4
Parallel
Detection Fault
1 = Parallel detection fault has occurred.
0 = Parallel detection fault has not occurred.
RO/
LH
0
6.3
Link Partner
Next Page Able
1 = Link partner is next page able
0 = Link partner is not next page able
RO
0
6.2
Next Page Able
1 = Local device is next page able
0 = Local device is not next page able
RO
1
RO
LH
0
RO
0
Indicates that a new page has been received and the
received code word has been loaded into register 5 or
register 8 as specified in clause 28 of 802.3.
6.1
Page Received
1 = Three identical and consecutive link code words have
been received from link partner
0 = Three identical and consecutive link code words have
not been received from link partner
6.0
Link Partner A/
N Able
1 = Link partner is auto-negotiation able
0 = Link partner is not auto-negotiation able
1. RO = Read Only, LH = Latching High cleared when read
Table 64. Auto-Negotiation Next Page Transmit Register (Address 7)
Bit
7.15
7.14
7.13
7.12
7.11
7.10:0
Type 1
Default
R/W
0
RO
0
R/W
1
R/W
0
1 = Previous value of the transmitted Link Code Word
equalled logic zero
0 = Previous value of the transmitted Link Code Word
equalled logic one
R/W
0
MP = 1: Code interpreted as “message page”
MP = 0: Code interpreted as “unformatted page”
R/W
00000000001
Name
Description
Next Page
1 = Additional next pages follow
(NP)
0 = Last page
Reserved
Write as 0, ignore on read
Message Page
1 = Message page
(MP)
0 = Unformatted page
Acknowledge 2
1 = Complies with message
(ACK2)
0 = Cannot comply with message
Toggle
(T)
Message/
Unformatted
Code Field
1. R/W = Read Write, RO = Read Only
Datasheet
125
Advanced 10/100 8-Port PHY — LXT9785
Table 65. Auto-Negotiation Link Partner Next Page Receive Register (Address 8)
Bit
8.15
8.14
8.13
8.12
8.11
8.10:0
Name
Type 1
Default
RO
0
RO
0
RO
0
RO
0
1 = Previous value of the transmitted Link Code Word
equalled logic zero
0 = Previous value of the transmitted Link Code Word
equalled logic one
RO
0
MP = 1: Code interpreted as “message page”
MP = 0: Code interpreted as “unformatted page”
RO
00000000000
Description
Next Page
1 = Link Partner has additional next pages to send
(NP)
0 = Link Partner has no additional next pages to send
Acknowledge
1 = Link Partner has received Link Code Word from
the LXT9785
(ACK)
Message Page
0 = Link Partner has not received Link Code Word
from the LXT9785
1 = Page sent by the Link Partner is a Message Page
(MP)
0 = Page sent by the Link Partner is an Unformatted
Page
Acknowledge 2
1 = Link Partner will comply with the message
(ACK2)
0 = Link Partner cannot comply with the message
Toggle
(T)
Message/
Unformatted
Code Field
1. RO = Read Only
Product Specification
126
Advanced 10/100 8-Port PHY — LXT9785
Table 66. Port Configuration Register (Address 16, Hex 10)
Bit
Name
Description
Type 1
Default
0
16.15
Reserved
Write as 0, ignore on read
R/W
16.14
Link Disable
1 = Force Link pass. Sets appropriate registers and LEDs
to Pass.
0 = Normal operation
R/W
16.13
Transmit Disable
1 = Disable Twisted-Pair transmitter
0 = Normal Operation
R/W
0
16.12
Bypass Scramble
(100BASE-TX)
1 = Bypass Scrambler and Descrambler
0 = Normal Operation
R/W
0
16.11
Bypass 4B5B
(100BASE-TX)
1 = Bypass 4B5B encoder and decoder
0 = Normal Operation
R/W
0
16.10
Jabber
(10BASE-T)
1 = Disable Jabber
0 = Normal operation
R/W
0
16.9
SQE
(10BASE-T)
16.8
TP Loopback
(10BASE-T)
1 = Disable TP loopback during half duplex operation
0 = Normal Operation
R/W
1
16.7
Reserved
Write as one. Ignore on read
R/W
1
16.6
FIFO Size
This bit is ignored by the LXT9785
1 = Enable Heart Beat
0 = Disable Heart Beat
0 = FIFO allows packets up to 2 KBytes
1 = FIFO allows packets up to 9 KBytes
Packet sizes assume a 100 ppm difference between the
reference clock and the recovered clock.
0
0
R/W
0
R/W
Preamble Enable. The implementation of this bit is
10BASE-T only.
0
16.5
PRE_EN
0 = Set RX_DV high coincident with SFD
1 = Set RX_DV high and RXD=preamble when CRS is
asserted.
R/W
16.4
Reserved
Write as zero. Ignore on read
R/W
0
16.3
Reserved
Write as zero. Ignore on read
R/W
0
16.2
Far End Fault
Transmission
Enable
1 = Enable Far End Fault Transmission
0 = Disable Far End Fault Transmission
R/W
16.1
Alternate NP
Feature
1 = Enable alternate auto-negotiate next page feature
0 = Disable alternate auto-negotiate next page feature
R/W
0
16.0
Fiber Select
1 = Select fiber mode for this port
0 = Select TP mode for this port
R/W
Note 2
1
1. R/W = Read/Write
2. The default value of bit 16.0 is determined by the G_FX/TP pin for the respective port.
If G_FX/TPn is tied Low, the default value of bit 16.0 = 0. If G_FX/TPn is not tied Low, the default value of
bit 16.0 = 1.
Datasheet
127
Table 67. Quick Status Register (Address 17, Hex 11)
Bit
17.15
Name
Description
Type 1
Default
Reserved
Always 0
RO
0
17.14
10/100 Mode
1 = The LXT9785 is operating in 100BASE-TX mode.
0 = The LXT9785 is not operating 100BASE-TX mode.
RO
0
17.13
Transmit Status
1 = The LXT9785 is transmitting a packet
0 = The LXT9785 is not transmitting a packet
RO
LH
0
17.12
Receive Status
1 = The LXT9785 is receiving a packet
0 = The LXT9785 is not receiving a packet
RO
LH
0
17.11
Collision Status
1 = Collision is occurring
0 = No collision
RO
LH
0
17.10
Link
1 = Link is up
0 = Link is down
RO
0
17.9
Duplex Mode
1 = Full duplex
0 = Half duplex
RO
0
17.8
Auto-Negotiation
1 = The LXT9785 is in Auto-Negotiation Mode
0 = The LXT9785 is in manual mode
RO
0
17.7
Auto-Negotiation
Complete
RO
0
17.6
FIFO Error
RO
LH
0
17.5
Polarity
1 = Polarity is reversed
0 = Polarity is not reversed
RO
0
17.4
Pause
1 = The LXT9785 is Pause capable
0 = The LXT9785 is Not Pause capable
RO
0
17:3
Error
1 = Error Occurred (Remote Fault, RxERCntFUL, FIFO
error, Jabber, Parallel Detect Fault)
0 = No error occurred
RO
LH
0
17:2
Reserved
Reserved
RO
0
17:1
Reserved
Ignore
RO
0
17.0
Reserved
Always 0
RO
0
1 = Auto-negotiation process completed
0 = Auto-negotiation process not completed
This bit is only valid when auto-negotiate is enabled, and is
equivalent to bit 1.5.
1 = FIFO error has occurred (Overflow or Underflow)
0 = No FIFO error has occurred
1. RO = Read Only, LH = Latching High cleared when read.
Table 68. Interrupt Enable Register (Address 18, Hex 12)
Bit
18.15:9
Name
Reserved
Description
Write as 0, ignore on read
Type 1
Default
R/W
0
R/W
0
R/W
0
Mask for Counter Full
18.8
CNTRMSK
18.7
ANMSK
1 = Enable event to cause interrupt
0 = Do not allow event to cause interrupt
Mask for Auto-Negotiate Complete
1. R/W = Read/Write
1 = Enable event to cause interrupt
0 = Do not allow event to cause interrupt
Advanced 10/100 8-Port PHY — LXT9785
Table 68. Interrupt Enable Register (Address 18, Hex 12) (Continued)
Bit
Name
Type 1
Default
R/W
0
R/W
0
R/W
0
1 = Enable event to cause interrupt
0 = Do not allow event to cause interrupt
R/W
0
Description
Mask for Speed Interrupt
18.6
SPEEDMSK
18.5
DUPLEXMSK
18.4
LINKMSK
18.3
ISOLMSK
18.2
Reserved
Write as 0, ignore on read
R/W
0
18.1
INTEN
1 = Enable interrupts on this port
0 = Disable interrupts on this port
R/W
0
18.0
TINT
1 = Test Force interrupt on MDINT
0 = Normal operation
R/W
0
1 = Enable event to cause interrupt
0 = Do not allow event to cause interrupt
Mask for Duplex Interrupt
1 = Enable event to cause interrupt
0 = Do not allow event to cause interrupt
Mask for Link Status Interrupt
1 = Enable event to cause interrupt
0 = Do not allow event to cause interrupt
Mask for Isolate Interrupt
1. R/W = Read/Write
Datasheet
129
LXT9785 — Advanced 10/100 8-Port PHY
Table 69. Interrupt Status Register (Address 19, Hex 13)
Bit
19.15:9
Name
Reserved
Description
Ignore on read
Type 1
Default
RO
0
RxER Counter Full Status
19.8
RxERCntFUL
19.7
ANDONE
1 = One of the internal counters has reached its maximum
value
0 = The internal counters have not reached maximum values
RO/SC
0
Auto-Negotiation Status
1= Auto-Negotiation has completed
0= Auto-Negotiation has not completed
RO/SC
N/A
RO/SC
0
RO/SC
0
RO/SC
0
RO/SC
0
RO/SC
0
Speed Change Status
19.6
SPEEDCHG
1 = A Speed Change has occurred since last reading this
register
0 = A Speed Change has not occurred since last reading this
register
Duplex Change Status
19.5
DUPLEXCHG
1 = A Duplex Change has occurred since last reading this
register
0 = A Duplex Change has not occurred since last reading
this register
Link Status Change Status
19.4
LINKCHG
1 = A Link Change has occurred since last reading this
register
0 = A Link Change has not occurred since last reading this
register
MII Isolate Change Status
19.3
Isolate
1 = A Isolate change has occurred since last reading this
register
0 = A Isolate change has not occurred since last reading this
register
1 = RMII/SMII/SS-SMII interrupt pending
19.2
MDINT
19.1
Reserved
Ignore on read
RO/SC
0
19.0
Reserved
Ignore on read
RO
0
0 = No RMII/SMII/SS-SMII interrupt pending
1. R/W = Read/Write, RO = Read Only, SC = Self Clearing - cleared when read
130
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Table 70. LED Configuration Register (Address 20, Hex 14)
Bit
Name
LED1
20.15:12
Programming
bits
LED2
20.11:8
Programming
bits
Type 1
Default
0000 = Display Speed Status (Continuous, Default)
0001 = Display Transmit Status (Stretched)
0010 = Display Receive Status (Stretched)
0011 = Display Collision Status (Stretched)
0100 = Display Link Status (Continuous)
0101 = Display Duplex Status (Continuous)
0110 = Display Isolate Status (Continuous)
0111 = Display Receive or Transmit Activity (Stretched)
1000 = Test mode- turn LED on (Continuous)
1001 = Test mode- turn LED off (Continuous)
1010 = Test mode- blink LED fast (Continuous)
1011 = Test mode- blink LED slow (Continuous)
1100 = Display Link and Receive Status combined 2
(Stretched)3
1101 = Display Link and Activity Status combined 2
(Stretched)3
1110 = Display Duplex and Collision Status combined 4
(Stretched)3
1111 = Display Link and Rx_ERR Status combined 2 (Blink)
R/W
0000
0000 = Display Speed Status
0001 = Display Transmit Status
0010 = Display Receive Status
0011 = Display Collision Status
0100 = Display Link Status
0101 = Display Duplex Status
0110 = Display Isolate Status
0111 = Display Receive or Transmit Activity
1000 = Test mode- turn LED on
1001 = Test mode- turn LED off
1010 = Test mode- blink LED fast
1011 = Test mode- blink LED slow
1100 = Display Link and Receive Status combined 2
(Stretched)3
1101 = Display Link and Activity Status combined 2
(Default)(Stretched)3
1110 = Display Duplex and Collision Status combined 4
(Stretched)3
1111 = Display Link and Rx_ERR Status combined 2 (Blink)
R/W
1101
Description
1. R/W = Read/Write, RO = Read Only, LH = Latching High.
2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up.
The secondary LED driver (Receive, Activity, or Error) causes the LED to change state (blink).
3. Combined event LED settings are not affected by Pulse Stretch bit 20.1. These display settings are
stretched regardless of the value of 20.1.
4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full duplex.
Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.
Datasheet
131
LXT9785 — Advanced 10/100 8-Port PHY
Table 70. LED Configuration Register (Address 20, Hex 14) (Continued)
Bit
Type 1
Default
0000 = Display Speed Status
0001 = Display Transmit Status
0010 = Display Receive Status
0011 = Display Collision Status
0100 = Display Link Status
0101 = Display Duplex Status
0110 = Display Isolate Status
0111 = Display Receive or Transmit Activity
1000 = Test mode- turn LED on
1001 = Test mode- turn LED off
1010 = Test mode- blink LED fast
1011 = Test mode- blink LED slow
1100 = Display Link and Receive Status combined 2
(Stretched)3
1101 = Display Link and Activity Status combined 2
(Stretched)3
1110 = Display Duplex and Collision Status combined 4
(Default) (Blink)3
1111 = Display Link and Rx_ERR Status combined 2 (Blink)
R/W
1110
Name
LED3
Description
20.7:4
Programming
bits
20.3:2
LEDFREQ
00 = Stretch LED events to 30 ms
01 = Stretch LED events to 60 ms
10 = Stretch LED events to 100 ms
11 = Reserved
R/W
00
20.1
PULSESTRETCH
1 = Enable pulse stretching of all LEDs
0 = Disable pulse stretching of all LEDs 2
R/W
1
20.0
Reserved
Reserved
R/W
0
1. R/W = Read/Write, RO = Read Only, LH = Latching High.
2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up.
The secondary LED driver (Receive, Activity, or Error) causes the LED to change state (blink).
3. Combined event LED settings are not affected by Pulse Stretch bit 20.1. These display settings are
stretched regardless of the value of 20.1.
4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full duplex.
Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.
Table 71. Receive Error Count Register (Address 21)
Bit
21.15:0
Name
Description
Receive Error
Count
A 16-bit counter value indicating the number of times a
receive packet with errors occurred. Only one event gets
counted per packet. When maximum count is reached, the
16-bit counter remains full until cleared. Refer to the
discussion of “Out-of-Band Signalling” on page 74 for
details.
Type 1
RO/
SC
Default
0
1. RO = Read Only
S/C = Self Clearing when read
132
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Table 72. RMII Out-of-Band Signalling Register (Address 25)
Bit
25:15:7
Name
Reserved
Description
Reserved
Type 1
Default
R/W
0
R/W
000
R/W
000
R/W
0
These three bits select which status information is
available on the RXD(1) bit of the RMII bus.
000 = Link
001 = Speed
010 = Duplex
25:6:4
BIT1
011 = Auto-negotiation complete
100 = Polarity reversed
101 = Jabber detected
110 = Interrupt pending
111 = Isolate
These three bits select which status information is
available on the RXD(0) bit of the RMII bus.
000 = Link
001 = Speed
010 = Duplex
25.3:1
BIT0
011 = Auto-negotiation complete
100 = Polarity reversed
101 = Jabber detected
110 = Interrupt pending
111 = Isolate
25.0
PROGRMII
1 = Enable programmable RMII Out-of-Band
signalling. When enabled, bits 6:1 specify which
status bits are available on the RMII RXD data bus.
0 = Disable Out-of-Band signalling.
1. R/W = Read/Write
RO = Read Only
Table 73. Trim Enable Register (Address 27)
00 = 3.3 ns (default is pins SLEWCTRL<1:0>
27.11:10
Per-Port
Rise Time
Control
01 = 3.6 ns
10 = 3.9 ns
R/W
00
R/W
0
R/W
Note 2
R/W
0
11 = 4.2 ns
27.9
AMDIX_EN
27.8
MDIX
0 = Disable auto MDIX (default is pin auto_mdix_en)
1 = Enable auto MDIX
Manual MDI/MDIX selection:
0 = MDI, transmit on pair A and receive on pair B
1 = MDIX transmit on pair B and receive on pair A
27.7
Analog
Loop back
1 = Enable analog loop back (transmits on twisted-pair)
0 = Disable analog loop back
1. The default setting of register bit 27.8 is determined by pin 59.
Datasheet
133
Bit Fields
Reg Title
Addr
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Control Register
Control
Reset
Loopback
Speed
Select
A/N
Enable
Power
Down
Isolate
Re-start
A/N
Duplex
Mode
COL Test
Speed
Select
0
Reserved
Status Register
Status
100Base-T4
100BaseX Full
Duplex
100Base-X
Half Duplex
10Mbps
Full
Duplex
10Mbps
Half
Duplex
100BaseT2 Full
Duplex
100Base-T2
Half Duplex
Extended
Status
Reserved
MF
Preamble
Suppress
A/N
Complete
Remote
Fault
A/N Ability
Link Status
Jabber
Detect
Extended
Capability
1
6
5
4
3
2
1
0
2
PHY ID Registers
PHY ID 1
15
14
PHY ID2
13
12
11
10
9
8
PHY ID No
7
MFR Model No
3
MFR Rev No
Auto-Negotiation Advertisement Register
A/N
Advertise
Next Page
Reserved
Remote
Fault
Reserved
Asymm
Pause
Pause
100Base-T4
100BaseTX Full
Duplex
100BaseTX
10Base-T
Full Duplex
10Base-T
IEEE Selector Field
4
IEEE Selector Field
5
Auto-Negotiation Link Partner Base Page Ability Register
A/N Link
Ability
Next Page
Ack
Remote
Fault
Reserved
Asymm
Pause
Pause
100Base-T4
100BaseTX Full
Duplex
100BaseTX
10Base-T
Full Duplex
10Base-T
Auto-Negotiation Expansion Register
A/N
Expansion
Reserved
Base Page
Parallel
Detect
Fault
Link Partner
Next Page
Able
Next Page
Able
Page
Received
Link
Partner
A/N Able
6
Auto-Negotiation Next Page Transmit Register
A/N Next
Page
Txmit
Next Page
Reserved
Message
Page
Ack 2
Toggle
Message / Unformatted Code Field
7
Auto-Negotiation Link Partner Next Page Ability Register
Datasheet
A/N Link
Next Page
Next Page
Ack
Message Page
Ack 2
Toggle
Message / Unformatted Code Field
8
LXT9785 — Advanced 10/100 8-Port PHY
134
Table 74. Register Bit Map
Table 74. Register Bit Map (Continued)
Datasheet
Bit Fields
Reg Title
Addr
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
FIFO Size
PRE_EN
Reserved
Reserved
Remote
Fault
Enable
Alternate
Next Page
Fiber
Select
16
FIFO Error
Polarity
Pause
Error
Reserved
Reserved
Reserved
17
Speed
Mask
Duplex
Mask
Link Mask
Isolate
Mask
Reserved
Interrupt
Enable
Test
Interrupt
18
Speed
Change
Duplex
Change
Link
Change
Isolate
Change
MD Interrupt
Reserved
Reserved
19
Pulse
Stretch
Reserved
20
Port Configuration Register
Port
Config
Reserved
Link
Disable
Txmit
Disable
Bypass
Scrambler
(100TX)
Bypass
4B/5B
(100TX)
Jabber
(10T)
SQE
(10T)
TP
Loopback
(10T)
Reserved
Quick Status Register
Quick
Status
Reserved
10/100
Mode
Transmit
Status
Receiver
Status
Collision
Status
Duplex
Mode
Link
Auto-Neg
Auto-Neg
Complete
Interrupt Enable Register
Interrupt
Enable
Counter
Mask
Reserved
Auto-Neg
Mask
Interrupt Status Register
Interrupt
Status
Rx_ER
Counter
Full
Reserved
Auto-Neg
Done
LED Configuration Register
LED1
LED2
LED3
LED Freq
Receive Error Count Register
Rcv Error
Count
21
Receive Error Count
False Carrier Counter Register
Reserved
22
Reserved
Programmable RMII Out-of-Band Signalling Register
RMII OOB
Signalling
Reserved
Bit 1
Bit 0
Program
RMII
25
Programmable RMII Out-of-Band Signalling Register
135
Trim
Enable
Reserved
Per Port Slew
Control
Auto-MDIX
Manual
MDIX
Analog
Loop
Reserved
27
Advanced 10/100 8-Port PHY — LXT9785
LED
Config
LXT9785 — Advanced 10/100 8-Port PHY
6.0
Package Specifications
Figure 61. LXT9785 208-Pin PQFP Plastic Package Specification
208-Pin Plastic Quad Flat Package
• Part Number LXT9785HC
• Commercial Temperature Range (0°C to 70°C)
Millimeters
Dim
Min
Max
A
-
4.10
A1
0.25
-
A2
3.20
3.60
b
0.17
0.27
D
30.30
30.90
D1
27.70
28.30
E
30.30
30.90
E1
27.70
28.30
D
D1
e
E1
E
e
/2
e
L
θ2
A2
θ
A1
0.75
1.30 REF
q
0°
7°
θ2
5°
16°
θ3
5°
16°
θ3
L
136
0.50
L1
L1
A
.50 BASIC
b
Datasheet
Advanced 10/100 8-Port PHY — LXT9785
Figure 62. LXT9785 241-Ball PBGA Package Specification (LXT9785BC)
Datasheet
137