Preliminary This product is under development and its specification might be changed without any notice. R1LA1616R Series REJ03C0100-0002Z Rev.0.02 2003.10.24 16Mb superSRAM (1M wordx16bit) Description The R1LA1616R Series is a family of low voltage 16-Mbit static RAMs organized as 1048576-words by 16-bit, fabricated by Renesas's high-performance 0.15um CMOS and TFT technologies. The R1LA1616R Series is suitable for memory applications where a simple interfacing , battery operating and battery backup are the important design objectives. The R1LA1616R Series is packaged in a 52pin micro thin small outline mount device[µ TSOP / 10.79mm x 10.49mm with the pin-pitch of 0.4mm] or a 48balls fine pitch ball grid array [f-BGA / 7.5mmx8.5mm with the ball-pitch of 0.75mm and 6x8 array] . It gives the best solution for a compaction of mounting area as well as flexibility of wiring pattern of printed circuit boards. Features • Single 1.65-2.3V power supply • Small stand-by current:3µA (1.8V, typ.) • Smaller stand-by current by "Data retention mode"(“CS2"='L') : 1µA (1.8V, typ.) • Data retention supply voltage =1.5V • No clocks, No refresh • Easy memory expansion by CS1#, CS2, LB# and UB# • Common Data I/O • Three-state outputs: OR-tie capability • OE# prevents data contention on the I/O bus • Process technology: 0.15um CMOS Rev.0.02 2003.10.24 page 1 of 16 Preliminary R1LA1616R Series This product is under development and its specification might be changed without any notice. Ordering Information Type No. Access time R1LA1616RSD-7SI 70 ns R1LA1616RSD-8SI 85 ns R1LA1616RBG-7SI 70 ns R1LA1616RBG-8SI 85 ns Rev.0.02 2003.10.24 page 2 of 16 Package 350-mil 52-pin plastic µ - TSOP(II) (normal-bend type) (52PTG) 7.5mmx8.5mm f-BGA 0.75mm pitch 48ball Preliminary R1LA1616R Series This product is under development and its specification might be changed without any notice. Pin Arrangement 52-pin µ TSOP 48-pin fBGA A15 1 52 A16 A14 2 51 BYTE# A13 3 50 UB# A12 4 49 A11 5 48 Vss LB# A10 6 47 DQ15 A9 7 46 DQ7 A8 8 45 DQ14 A19 9 44 DQ6 CS1# 10 43 DQ13 WE# 11 42 DQ5 NC 12 41 DQ12 NC 13 40 DQ4 Vcc 14 39 NC CS2 15 38 DQ11 NC 16 37 DQ3 NC 17 36 DQ10 A18 18 35 DQ2 A17 19 34 A7 20 33 DQ9 DQ1 A6 21 32 DQ8 A5 22 31 DQ0 A4 23 30 OE# A3 24 29 A2 25 28 Vss NC 26 27 A0 A1 1 2 3 4 5 6 A LB# OE# A0 A1 A2 CS2 B DQ15 UB# A3 A4 CS1# DQ0 C DQ13 DQ14 A5 A6 DQ1 DQ2 D Vss DQ12 A17 A7 DQ3 Vcc E Vcc DQ11 Vss or NC A16 DQ4 Vss F DQ10 DQ9 A14 A15 DQ6 DQ5 G DQ8 A19 A12 A13 WE# DQ7 H A18 A8 A9 A10 A11 N.C. Pin Description Pin name Function A0 to A19 Address input DQ 0 to DQ15 Data input/output CS1# &CS2 Chip select WE# Write enable OE# Output enable LB# Lower byte select UB# Upper byte select Vcc Power supply Vss Ground BYTE# Byte control mode enable input NC Non connection Rev.0.02 2003.10.24 page 3 of 16 Preliminary R1LA1616R Series This product is under development and its specification might be changed without any notice. Block Diagram (Supplying voltage to internal circuits) UB# x8/x16 SWITCHING CIRCUIT BYTE#* OUTPUT BUFFER DATA SELECTOR OUTPUT BUFFER DATA INPUT BUFFER LB# DATA INPUT BUFFER CLOCK GENERATOR CS1# DATA SELECTOR CS2 SENSE AMPLIFIER 1048576WORDS X 16 BITS or 2097152WORDS X 8 BITS DQ0 SENSE AMPLIFIER A19 MEMORY ARRAY DECODER A0 ADDRESS BUFFER INTERNAL VOLTAGE SUPPLY CIRCUIT DQ7 DQ8 DQ15 / A-1 Vcc Vss WE# OE# Note, BYTE# pin supported by only TSOP type. Rev.0.02 2003.10.24 page 4 of 16 Preliminary R1LA1616R Series This product is under development and its specification might be changed without any notice. Operating Table CS1# H X X L CS2* 3 BYTE#* 2 H L H H X X X H LB# UB# X X H L X X H H WE# OE# X X X L X X X X DQ0~7 DQ8~14 DQ15 Operation High-Z High-Z High-Z Din High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Stand-by Data retention Stand-by Write in lower byte L H H L H H L Dout High-Z High-Z Read from lower byte L H H L H H H High-Z High-Z High-Z Output disable L H H H L L X High-Z Din Din L H H H L H L High-Z Dout Dout Write in upper byte Read from upper byte L L H H H H H L L L H L H X High-Z Din High-Z Din High-Z Din Output disable L H H L L H L Dout Dout Dout Read L H H L L H H High-Z High-Z High-Z Output disable L H L L L L X Din High-Z A-1 Write L H L L L H L Dout High-Z A-1 Read L H L L L H H High-Z High-Z A-1 Output disable Write Note 1,H:VIH L:VIL X: VIH or VIL 2, BYTE# pin supported by only TSOP type. When apply BYTE# =“L” ,please assign LB#=UB#=“L”. *3 Notification about a new function of CS2 signal R1LA1616R Series use CS2 signal to control the internal voltage for as 'Data retention mode'. In case of conventional SRAM products, both CS1# and CS2 signals are used as control signals for device operation of active and stand-by modes. In terms of R1LA1616R Series, CS1# is an ordinary function that controls device operation, but CS2 function is to make a switch device status between 'Stand-by mode' and 'Data retention mode', based on the input level of CS2 signal. In the concrete, when setting CS2 at a high level, a device status is changed from 'Data retention mode' to 'Stand-by mode'. And when setting CS2 at a low level, it's changed from 'Stand-by mode' to 'Data retention mode'. The latter is a new function. During 'Data retention mode' with CS2='L', the reduction of current consumption is achieved by turning off the internal voltage supply except memory cell array. Therefore in case of using with CS2 signal as for 'back up control with battery' , it will be realized the most suitable system. With regard to the detailed specifications for CS2 signal, please refer to the item of "Timing diagram" in p.11~p.14 and that of "Data retention characteristics" in p.15. Absolute Maximum Ratings Parameter Symbol Value Power supply voltage relative to Vss Vcc -0.5 to +2.7 Unit V Terminal voltage on any pin relation toVss VT -0.5*1 to Vcc+0.3* 2 V Power dissipation PT 0.7 W Operation temperature Topr -40 to + 85 ºC Storage temperature range Tstg -65 to + 150 ºC Storage temperature range under bias Tbias -40 to + 85 ºC Note 1: -1.0V in case of AC (Pulse width ≤ 30ns) 2:Maximum voltage is +2.7V Rev.0.02 2003.10.24 page 5 of 16 This product is under development and its specification might be changed without any notice. Preliminary R1LA1616R Series DC Operating Conditions Parameter Symbol Min Typ Max Unit Vcc 1.65 1.80 2.30 V Vss 0 0 0 Input high voltage VIH 0.7 x Vcc Vcc+0.2 V V Input low voltage VIL -0.2 0.4 V Ambient temperature range Ta -40 85 ºC Supply voltage Note 1 Note 1 –1.0V in case of AC (Pulse width ≤ 30ns) DC Characteristics Parameter Input leakage current Symbol |ILI| Min Typ*1 Max Unit Test conditions*2 1 µA Vin=Vss to Vcc 1 µA Output leakage current |IL0| Operating current Icc 1.5 3 mA Average operating current Icc1 20 40 mA Icc2 1.5 8 mA ISB ISB1 0.1 0.3 mA 3 5 µA 5 10 µA 20 µA 40 µA Standby current Standby current Output hige voltage Output Low voltage VOH VOL 1.3 0.2 CS1# =VIH or CS2=VIL or OE# = VIH or WE# =VIL or LB# =UB# =VIH,VI/O=Vss to Vcc CS1#=VIL , CS2=VIH Others = VIH / VIL I I/O = 0 mA Min. cycle, duty =100% I I/O = 0 mA,CS1# =VIL, CS2=VIH Others = VIH / VIL Cycle time = 1µs,duty=100% I I/O = 0 mA,CS1# =VIL, CS2=VIH Others = VIH / VIL CS1#=CS2=VIH ~+25ºC 0V≤Vin CS2 ≥ VCC-0.2V ~+40ºC (1)CS1# ≥ Vcc-0.2V or ~+70ºC (2)LB# = UB# ≥ Vcc-0.2V CS1# ≤ 0.2V ~+85ºC V IOH = -0.1mA V IOL = 0.1mA Note 1: Typical parameter indicates the value for the center of distribution at 1.8V (Ta=25ºC), and not 100% tested. 2: BYTE# pin supported by only TSOP type. BYTE# ≥ Vcc-0.2V or BYTE# ≤ 0.2V Rev.0.02 2003.10.24 page 6 of 16 This product is under development and its specification might be changed without any notice. Preliminary R1LA1616R Series Capacitance (Ta=+25ºC, f=1MHz) Parameter Symbol Min Typ Max Unit Test conditions Note Input capacitance C in 10 pF V in =0V 1 Input / output capacitance C I/O 10 pF V I/O=0V 1 Note 1: This parameter is sampled and not 100% tested. AC Characteristics Test Conditions ( Vcc=1.65V~2.3V , Ta = - 40~+85 ºC) • Input pulse levels : VIL= 0.2V, VIH=Vcc - 0.2V • Input rise and fall time : 5ns • Input and output timing reference levels : 0.9V • Output load : See figures (Including scope and jig) Vcc 1210Ω DQ CL 1008Ω CL=30pF CL=5FpF (for tCLZ, tBLZ, tOLZ, tCHZ, tCLZ, tBHZ, tOHZ, tOWZ, tOHZ, tWHZ) Rev.0.02 2003.10.24 page 7 of 16 Preliminary R1LA1616R Series This product is under development and its specification might be changed without any notice. Read Cycle R1LA1616R**-7SI Parameter Read cycle time Address access time Chip select access time Output enable to output valid Output hold from address change LB#,UB# access time Chip select to output in low-Z LB#,UB# enable to low-Z Output enable to output in low-Z Chip deselect to output in high-Z LB#,UB# disable to high-Z Output disable to output in high-Z Rev.0.02 2003.10.24 page 8 of 16 Symbol tRC tAA tACS tOE tOH tBA tCLZ tBLZ tOLZ tCHZ tBHZ tOHZ Min Max 70 R1LA1616R**-8SI Min Max 85 Unit ns 70 85 ns 70 85 ns 35 45 ns 10 10 70 Notes ns 85 ns 10 10 ns 2,3 5 5 ns 2,3 5 5 ns 2,3 0 25 0 30 ns 1,2,3 0 25 0 30 ns 1,2,3 0 25 0 30 ns 1,2,3 Preliminary R1LA1616R Series This product is under development and its specification might be changed without any notice. Write Cycle R1LA1616R**-7SI Parameter Write cycle time Address valid to end of write Chip selection to end of write Write pulse width LB#,UB# valid to end of write Address setup time Write recovery time Data to write time overlap Data hold from write time Output active from end of write Output disable to output in high -Z Write to output in high-Z Symbol tWC tAW tCW tWP tBW tAS tWR tDW tDH tOW tOHZ tWHZ Min Max R1LA1616R**-8SI Min Max Unit Notes 70 85 ns 65 70 ns 65 70 ns 5 55 60 ns 4 65 70 ns 0 0 ns 6 0 0 ns 7 35 40 ns 0 0 ns 5 5 ns 2 0 25 0 30 ns 1,2 0 25 0 30 ns 1,2 Note1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2.This parameter is sampled and not 100% tested. 3.AT any given temperature and voltage condition, tHZ max is less than tHZ min both for a given device and form device to device. 4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write begins at the latest transition among CS1# going low, WE# going low and LB# going low or UB# going low . A write ends at the earliest transition among CS1# going high, WE# going high and LB# going high or UB# going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1# going low to end of write. 6. tAS is measured the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1# or WE# going high to the end of write cycle. Rev.0.02 2003.10.24 page 9 of 16 Preliminary R1LA1616R Series This product is under development and its specification might be changed without any notice. Byte Control R1LA1616R**-7SI Parameter Symbol tBS tBR Byte setup time Byte recovery time Min Max tBS BYTE# Rev.0.02 2003.10.24 page 10 of 16 Min Max Unit 5 5 ms 5 5 ms BYTE# Timing Waveform CS1# R1LA1616R**-8SI tBR Notes Preliminary R1LA1616R Series This product is under development and its specification might be changed without any notice. Timing Waveform Read Cycle tRC A 0~19 (Word Mode) Valid address A -1~19 tAA tBA (Byte Mode) tOH LB#,UB# tBHZ tACS CS1# tCHZ tPR* CS2 tOE OE# tOLZ WE# = "H" level tCLZ tBLZ DQ0~15 (Word Mode) DQ0~7 (Byte Mode) Note , About tPR, See Data Retention Characteristics p.15 Rev.0.02 2003.10.24 page 11 of 16 tOHZ Valid data Preliminary R1LA1616R Series Write Cycle (1) (WE# Clock) This product is under development and its specification might be changed without any notice. tWC A 0~19 (Word Mode) Valid address A -1~19 (Byte Mode) tBW LB#,UB# tCW CS1# tPR* CS2 tAW tAS tWR tWP tWHZ WE# tOW DQ0~15 Valid data (Word Mode) DQ0~7 tDW (Byte Mode) tDH Note , About tPR, See Data Retention Characteristics p.15 Rev.0.02 2003.10.24 page 12 of 16 Preliminary R1LA1616R Series This product is under development and its specification might be changed without any notice. Write Cycle (2) (CS1# ,CS2 Clock, OE#=VIH) tWC A 0~19 (Word Mode) Valid address A -1~19 (Byte Mode) tBW LB#,UB# CS1# tAS tCW tWR tPR* CS2 tWP WE# tDW DQ0~15 tDH (Word Mode) Valid data DQ0~7 (Byte Mode) Note , About tPR, See Data Retention Characteristics p.15 Rev.0.02 2003.10.24 page 13 of 16 Preliminary R1LA1616R Series This product is under development and its specification might be changed without any notice. Write Cycle (3) ( LB#,UB# Clock, OE#=VIH) tWC A 0~19 (Word Mode) Valid address A -1~19 tAS (Byte Mode) tBW tWR LB#,UB# tCW CS1# tPR* CS2 WE# tWP tDW DQ0~15 tDH (Word Mode) Valid data DQ0~7 (Byte Mode) Note , About tPR, See Data Retention Characteristics p.15 Rev.0.02 2003.10.24 page 14 of 16 Preliminary R1LA1616R Series This product is under development and its specification might be changed without any notice. Data Retention Characteristics *1 Parameter Symbol Min 1.5V VDR Vcc for data retention Typ*2 Max Unit 2.3V V (Ta= -40~+85ºC) Test conditions*3,4 V in ≥ 0V 0V≤CS2≤0.2V Data retention current IccDR tCDR tR tPS tPR Chip deselect to data retention time Operation recovery time Power off setup time Power supply recovery time 1.0 3.0 µA ~+25ºC 3.0 8.0 µA ~+40ºC Vcc=1.8V V in ≥ 0V 17 µA ~+70ºC CS2≤0.2V 37 µA ~+85ºC 0 ns 5 0 ms 200 µs ns See retention waveform See retention waveform Note 1. Different from conventional SRAM products, this is the reduction mode of Data retention current when CS2 is low. During CS2 low , Internal voltage supply circuit is turned off except memory cell array. 2.Typical parameter of ICCDR indicates the value for the center of distribution at Vcc=1.8V and not 100% tested. 3. BYTE# pin supported by TSOP type. BYTE# ≥ Vcc-0.2V or BYTE# ≤ 0.2V 4. Also CS2 controls address buffer, WE# buffer ,CS1# buffer ,OE# buffer ,LB# ,UB# buffer and Din buffer . In the data retention mode (0V ≤ CS2 ≤ 0.2V) , Vin levels (address, WE# ,OE#,CS1#,LB#,UB#,I/O) can be in the high impedance state. Data Retention timing Waveform (1) (LB#,UB# Controlled) Vcc CS2 tCDR 1.65V tR 0.7 X Vcc 0.7 X Vcc tPS LB# UB# tPR *5 0V ≤ CS2 ≤ 0.2V Data Retention timing Waveform (2) (CS1# Controlled) Vcc CS2 tCDR 1.65V tR 0.7 X Vcc 0.7 X Vcc tPS CS1# tPR *5 0V ≤ CS2 ≤ 0.2V Note 5. On the UB#,LB# control mode or the CS1# control mode ,when recovering from the Data retention mode , the level of UB# and LB# or CS1# during Rev.0.02 2003.10.24 page 15 of 16 tPR period must be fixed 0.7V x Vcc ~ Vcc. Preliminary R1LA1616R Series This product is under development and its specification might be changed without any notice. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. http://www.renesas.com Copyright © 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan. Rev.0.02 2003.10.24 page 16 of 16 REVISION HISTORY Rev. R1LA1616R Series Data Sheet Description Date Summary Page 0.01 Jul. 04, 2003 0.02 Oct. 24, 2003 First edition issued 9 Revise Removed “CS2 signal operation” from Note 4,5 & 7 as follows. Note 4. Former A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.A write begins at the latest transition among CS1# going low, CS2 going high , WE# going low and LB# going low or UB# going low . A write ends at the earliest transition among CS1# going high ,CS2 going low, WE# going high and LB# going high or UB# going high. tWP is measured from the beginning of write to the end of write. Note 4. Revision A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.A write begins at the latest transition among CS1# going low, WE# going low and LB# going low or UB# going low . A write ends at the earliest transition among CS1# going high , WE# going high and LB# going high or UB# going high. tWP is measured from the beginning of write to the end of write. Note 5. Former tCW is measured from the later of CS1# going low or CS2 going high to end of write Note 5. Revision tCW is measured from the later of CS1# going low to end of write. Note 7. Former tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle. Note 7. Revision tWR is measured from the earliest of CS1# or WE# going high to the end of write cycle. 5 In “Note 2” , Add instructions “When apply BYTE# =“L” ,please assign LB#=UB#=“L”.” 3 Change Pin name “I/O 0 to I/O15” to “DQ 0 to DQ15” in “Pin Description”. (1/1)