ETC R8C/TINY

REJ09B0001-0100Z
R8C/Tiny Series
16
Software Manual
RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER
Before using this material, please visit our website to confirm that this is the most
current document available.
Rev. 1.00
Revision date: Jun. 19, 2003
www.renesas.com
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Using This Manual
This manual is written for the R8C/Tiny series software. This manual can be used for all
types of microcomputers having the R8C/Tiny series CPU core.
The reader of this manual is expected to have the basic knowledge of electric and logic
circuits and microcomputers.
This manual consists of six chapters. The following lists the chapters and sections to be
referred to when you want to know details on some specific subject.
• To understand the outline of the R8C/Tiny series
and its features ................................................................................... Chapter 1, “Overview”
• To understand the operation of each addressing mode .................. Chapter 2, “Addressing Modes”
• To understand instruction functions
(Syntax, operation, function, selectable src/dest (label), flag changes, description example,
related instructions) .............................................................................. Chapter 3, “Functions”
• To understand instruction code and cycles ......... Chapter 4, “Instruction Code/Number of Cycles”
• To understand instruction interrupt ..................................................... Chapter 5, “Interrupt”
• To understand calculation number of cycles ................. Chapter 6, “Calculation Number of Cycles”
This manual also contains quick references immediately after the Table of Contents. These
quick references will help you quickly find the pages for the functions or instruction code/
number of cycles you want to know.
• To find pages from mnemonic .................................. Quick Reference in Alphabetic Order
• To find pages from function and mnemonic ......................... Quick Reference by Function
• To find pages from mnemonic and addressing ................ Quick Reference by Addressing
A table of Q&A, symbols, a glossary, and an index are appended at the end of this manual.
M16C Family Documents
M16C family supports the following documents;
Type of documents
Short sheet
Contents
Overview of hardware
Data sheet
Hardware Manual
Overview of hardware, electrical characteristics
Hardware specifications (pin assignment, memory map, specifica-
Software Manual
tions of peripheral functions, electrical characteristics, timing chart)
Detailed description about operation of instruction (assembly lan-
Application Note
guage)
Application example of peripheral function
Sample program
Method for creating programs using assembly and C languages
Table of Contents
Chapter 1
Overview ___________________________________________________
1.1 Features of R8C/Tiny series ....................................................................................................... 2
1.1.1 Features of R8C/Tiny series ............................................................................................... 2
1.1.2 Speed performance ............................................................................................................ 2
1.2 Address Space ........................................................................................................................... 3
1.3 Register Configuration ................................................................................................................ 4
1.3.1 Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3) ............................................... 4
1.3.2 Address registers (A0 and A1) ............................................................................................ 5
1.3.3 Frame base register (FB) .................................................................................................... 5
1.3.4 Program counter (PC) ......................................................................................................... 5
1.3.5 Interrupt table register (INTB) ............................................................................................. 5
1.3.6 User stack pointer (USP) and interrupt stack pointer (ISP) ................................................ 5
1.3.7 Static base register (SB) ..................................................................................................... 5
1.3.8 Flag register (FLG) ............................................................................................................. 5
1.4 Flag Register (FLG) .................................................................................................................... 6
1.4.1 Bit 0: Carry flag (C flag) ...................................................................................................... 6
1.4.2 Bit 1: Debug flag (D flag) .................................................................................................... 6
1.4.3 Bit 2: Zero flag (Z flag) ........................................................................................................ 6
1.4.4 Bit 3: Sign flag (S flag) ........................................................................................................ 6
1.4.5 Bit 4: Register bank select flag (B flag) ............................................................................... 6
1.4.6 Bit 5: Overflow flag (O flag) ................................................................................................. 6
1.4.7 Bit 6: Interrupt enable flag (I flag) ....................................................................................... 6
1.4.8 Bit 7: Stack pointer select flag (U flag) ................................................................................ 6
1.4.9 Bits 8-11: Reserved area .................................................................................................... 6
1.4.10 Bits 12-14: Processor interrupt priority level (IPL) ............................................................ 7
1.4.11 Bit 15: Reserved area ....................................................................................................... 7
1.5 Register Bank ............................................................................................................................. 8
1.6 Internal State after Reset is Cleared ........................................................................................... 9
1.7 Data Types ............................................................................................................................... 10
1.7.1 Integer ............................................................................................................................... 10
1.7.2 Decimal ............................................................................................................................. 11
1.7.3 Bits .................................................................................................................................... 12
1.7.4 String ................................................................................................................................ 15
A-1
1.8 Data Arrangement .................................................................................................................... 16
1.8.1 Data Arrangement in Register .......................................................................................... 16
1.8.2 Data Arrangement in Memory ........................................................................................... 17
1.9 Instruction Format ..................................................................................................................... 18
1.9.1 Generic format (:G) ........................................................................................................... 18
1.9.2 Quick format (:Q) .............................................................................................................. 18
1.9.3 Short format (:S) ............................................................................................................... 18
1.9.4 Zero format (:Z) ................................................................................................................. 18
1.10 Vector Table ........................................................................................................................... 19
1.10.1 Fixed Vector Table .......................................................................................................... 19
1.10.2 Variable Vector Table ..................................................................................................... 20
Chapter 2
Addressing Modes ___________________________________________
2.1 Addressing Modes .................................................................................................................... 22
2.1.1 General instruction addressing ......................................................................................... 22
2.1.2 Special instruction addressing .......................................................................................... 22
2.1.3 Bit instruction addressing .................................................................................................. 22
2.2 Guide to This Chapter ............................................................................................................... 23
2.3 General Instruction Addressing ................................................................................................ 24
2.4 Special Instruction Addressing ................................................................................................. 27
2.5 Bit Instruction Addressing ......................................................................................................... 30
Chapter 3
Functions ___________________________________________________
3.1 Guide to This Chapter ............................................................................................................... 34
3.2 Functions ................................................................................................................................. 39
Chapter 4
Instruction Code/Number of Cycles ______________________________
4.1 Guide to This Chapter ............................................................................................................. 136
4.2 Instruction Code/Number of Cycles ........................................................................................ 138
Chapter 5
Interrupt ____________________________________________________
5.1 Outline of Interrupt .................................................................................................................. 246
5.1.1 Types of Interrupts .......................................................................................................... 246
5.1.2 Software Interrupts ......................................................................................................... 247
5.1.3 Hardware Interrupts ........................................................................................................ 248
A-2
5.2 Interrupt Control ...................................................................................................................... 249
5.2.1 I Flag ............................................................................................................................... 249
5.2.2 IR Bit ............................................................................................................................... 249
5.2.3 ILVL2 to ILVL0 bis, IPL ................................................................................................... 250
5.2.4 Rewrite the interrupt control register ............................................................................... 251
5.3 Interrupt Sequence ................................................................................................................. 252
5.3.1 Interrupt Response Time ................................................................................................ 253
5.3.2 Changes of IPL When Interrupt Request Acknowledged ............................................... 253
5.3.3 Saving Registers ............................................................................................................. 254
5.4 Return from Interrupt Routine ................................................................................................. 255
5.5 Interrupt Priority ...................................................................................................................... 256
5.6 Multiple Interrupts ................................................................................................................... 257
5.7 Precautions for Interrupts ....................................................................................................... 259
5.7.1 Reading address 0000016 .............................................................................................. 259
5.7.2 Setting the stack pointer ................................................................................................. 259
5.7.3 Rewrite the interrupt control register ............................................................................... 259
Chapter 6
Calculation Number of Cycles ___________________________________
6.1 Instruction queue buffer .......................................................................................................... 262
A-3
Quick Reference in Alphabetic Order
Mnemonic
ABS
ADC
ADCF
ADD
ADJNZ
AND
BAND
BCLR
BMCnd
BMEQ/Z
BMGE
BMGEU/C
BMGT
BMGTU
BMLE
BMLEU
BMLT
BMLTU/NC
BMN
BMNE/NZ
BMNO
BMO
BMPZ
BNAND
BNOR
BNOT
BNTST
BNXOR
BOR
BRK
BSET
BTST
BTSTC
BTSTS
BXOR
CMP
DADC
DADD
DEC
DIV
See page for
function
39
40
41
42
44
45
47
48
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
50
51
52
53
54
55
56
57
58
59
60
61
62
64
65
66
67
See page for
instruction code
/number of cycles
138
138
140
140
146
147
150
150
152
152
152
152
152
152
152
152
152
152
152
152
152
152
152
153
154
154
155
156
156
157
157
158
159
160
160
161
165
167
169
170
Mnemonic
DIVU
DIVX
DSBB
DSUB
ENTER
EXITD
EXTS
FCLR
FSET
INC
INT
INTO
JCnd
JEQ/Z
JGE
JGEU/C
JGT
JGTU
JLE
JLEU
JLT
JLTU/NC
JN
JNE/NZ
JNO
JO
JPZ
JMP
JMPI
JSR
JSRI
LDC
LDCTX
LDE
LDINTB
LDIPL
MOV
MOVA
Quick Reference-1
See page for
function
68
69
70
71
72
73
74
75
76
77
78
79
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
81
82
83
84
85
86
87
88
89
90
92
See page for
instruction code
/number of cycles
171
172
173
175
177
178
178
179
180
180
181
182
182
182
182
182
182
182
182
182
182
182
182
182
182
182
182
183
185
187
188
189
191
191
192
193
193
200
Quick Reference in Alphabetic Order
Mnemonic
MOVDir
MOVHH
MOVHL
MOVLH
MOVLL
MUL
MULU
NEG
NOP
NOT
OR
POP
POPC
POPM
PUSH
PUSHA
PUSHC
PUSHM
REIT
RMPA
ROLC
RORC
See page for
function
93
93
93
93
93
94
95
96
97
98
99
101
102
103
104
105
106
107
108
109
110
111
See page for
instruction code
/number of cycles
201
201
201
201
201
203
205
207
207
208
209
211
213
213
214
216
216
217
217
218
218
219
Mnemonic
ROT
RTS
SBB
SBJNZ
SHA
SHL
SMOVB
SMOVF
SSTR
STC
STCTX
STE
STNZ
STZ
STZX
SUB
TST
UND
WAIT
XCHG
XOR
Quick Reference-2
See page for
function
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
129
130
131
132
133
See page for
instruction code
/number of cycles
220
221
222
224
225
228
230
231
231
232
233
233
235
235
236
236
239
241
241
242
243
Quick Reference by Function
Function
Mnemonic
Content
See page for See page for
instruction code
function
/number of cycles
Transfer
Bit
manipulation
Shift
Arithmetic
MOV
MOVA
MOVDir
POP
POPM
PUSH
PUSHA
PUSHM
LDE
STE
STNZ
STZ
STZX
XCHG
BAND
BCLR
BMCnd
BNAND
BNOR
BNOT
BNTST
BNXOR
BOR
BSET
BTST
BTSTC
BTSTS
BXOR
Transfer
Transfer effective address
Transfer 4-bit data
Restore register/memory
Restore multiple registers
Save register/memory/immediate data
Save effective address
Save multiple registers
Transfer from extended data area
Transfer to extended data area
Conditional transfer
Conditional transfer
Conditional transfer
Exchange
Logically AND bits
Clear bit
Conditional bit transfer
Logically AND inverted bits
Logically OR inverted bits
Invert bit
Test inverted bit
Exclusive OR inverted bits
Logically OR bits
Set bit
Test bit
Test bit & clear
Test bit & set
Exclusive OR bits
90
92
93
101
103
104
105
107
87
123
124
125
126
132
47
48
49
50
51
52
53
54
55
57
58
59
60
61
193
200
201
211
213
214
216
217
191
233
235
235
236
242
150
150
152
153
154
154
155
156
156
157
158
159
160
160
ROLC
RORC
ROT
SHA
SHL
ABS
ADC
ADCF
ADD
CMP
DADC
Rotate left with carry
Rotate right with carry
Rotate
Shift arithmetic
Shift logical
Absolute value
Add with carry
Add carry flag
Add without carry
Compare
Decimal add with carry
110
111
112
116
117
39
40
41
42
62
64
218
219
220
215
228
138
138
140
140
161
165
Quick Reference-3
Quick Reference by Function
Function
Mnemonic
Content
See page for See page for
instruction code
function
/number of cycles
Arithmetic
Logical
Jump
String
Other
DADD
DEC
DIV
DIVU
DIVX
DSBB
DSUB
EXTS
INC
MUL
MULU
NEG
RMPA
SBB
SUB
AND
NOT
OR
TST
XOR
ADJNZ
SBJNZ
JCnd
JMP
JMPI
JSR
JSRI
RTS
SMOVB
SMOVF
SSTR
BRK
ENTER
EXITD
FCLR
FSET
INT
INTO
LDC
LDCTX
LDINTB
Decimal add without carry
Decrement
Signed divide
Unsigned divide
Singed divide
Decimal subtract with borrow
Decimal subtract without borrow
Extend sign
Increment
Signed multiply
Unsigned multiply
Two’s complement
Calculate sum-of-products
Subtract with borrow
Subtract without borrow
Logical AND
Invert all bits
Logical OR
Test
Exclusive OR
Add & conditional jump
Subtract & conditional jump
Jump on condition
Unconditional jump
Jump indirect
Subroutine call
Indirect subroutine call
Return from subroutine
Transfer string backward
Transfer string forward
Store string
Debug interrupt
Build stack frame
Deallocate stack frame
Clear flag register bit
Set flag register bit
Interrupt by INT instruction
Interrupt on overflow
Transfer to control register
Restore context
Transfer to INTB register
Quick Reference-4
65
66
67
68
69
70
71
74
77
94
95
96
109
114
127
45
98
99
129
133
44
115
80
81
82
83
84
113
118
119
120
56
72
73
75
76
78
79
85
86
88
167
169
170
171
172
173
175
178
180
203
205
207
218
222
236
147
208
209
239
243
146
224
182
184
185
187
188
221
230
231
231
157
177
178
179
180
181
182
189
189
192
Quick Reference by Function
Function
Mnemonic
Content
See page for See page for
instruction code
function
/number of cycles
Other
LDIPL
NOP
POPC
PUSHC
REIT
STC
STCTX
UND
WAIT
Set interrupt enable level
No operation
Restore control register
Save control register
Return from interrupt
Transfer from control register
Save context
Interrupt for undefined instruction
Wait
Quick Reference-5
89
97
102
106
108
121
122
130
131
193
207
213
216
216
232
233
241
241
Quick Reference by Addressing (general instruction addressing)
See page See page for
for function instruction
code
/number of
cycles
#IMM
#IMM20
#IMM16
#IMM8
abs16
dsp:16[SB]
dsp:16[An]
dsp:8[SB/FB]
[An]
An
R1H/R3
R1L/R2
R0H/R1
R0L/R0
dsp:8[An]
Addressing
Mnemonic
ABS
39
138
ADC
40
138
ADCF
41
140
ADD*1
42
140
ADJNZ*1
44
146
AND
45
147
CMP
62
161
DADC
64
165
DADD
65
167
DEC
66
169
DIV
67
170
DIVU
68
171
DIVX
69
172
DSBB
70
173
DSUB
71
175
ENTER
72
177
74
178
77
180
INT
78
181
JMPI*1
82
185
JSRI*1
83
187
LDC*1
85
189
LDE*1
87
191
LDINTB
88
192
LDIPL
89
193
*2
EXTS
INC
*3
*4
*1 Has special instruction addressing.
*2 Only R1L can be selected.
*3 Only R0L can be selected.
*4 Only R0H can be selected.
Quick Reference-6
Quick Reference by Addressing (general instruction addressing)
See page See page for
for function instruction
code
/number of
cycles
#IMM
#IMM20
#IMM16
#IMM8
abs16
dsp:16[SB]
dsp:16[An]
dsp:8[SB/FB]
[An]
An
R1H/R3
R1L/R2
R0H/R1
R0L/R0
dsp:8[An]
Addressing
Mnemonic
MOV*1
90
193
MOVA
92
200
MOVDir
93
201
MUL
94
203
MULU
95
205
NEG
96
207
NOT
98
208
OR
99
209
POP
101
211
POPM*1
103
213
PUSH
104
214
PUSHA
105
216
PUSHM*1
107
217
ROLC
110
218
RORC
111
219
ROT
112
220
SBB
114
222
SBJNZ*1
115
224
SHA*1
116
225
SHL*1
117
228
STC*1
121
232
STCTX*1
122
233
STE*1
123
233
STNZ
124
235
STZ
125
235
*1 Has special instruction addressing.
Quick Reference-7
Quick Reference by Addressing (general instruction addressing)
See page See page for
for function instruction
code
/number of
cycles
#IMM
#IMM20
#IMM16
#IMM8
abs16
dsp:16[SB]
dsp:16[An]
dsp:8[SB/FB]
[An]
An
R1H/R3
R1L/R2
R0H/R1
R0L/R0
dsp:8[An]
Addressing
Mnemonic
STZX
126
236
SUB
127
236
TST
129
239
XCHG
132
242
XOR
133
243
Quick Reference-8
Quick Reference by Addressing (special instruction addressing)
See page See page for
for function instruction
code
/number of
cycles
PC
INTBL/INTBH
FLG
ISP/USP
SB/FB
label
dsp:8[SP]
A1A0
R2R0/R3R1
abs20
dsp:20[A1]
dsp:20[A0]
[A1A0]
Addressing
Mnemonic
ADD*1
42
140
ADJNZ*1
44
146
JCnd
80
182
JMP
81
184
82
185
JSR
83
187
JSRI*1
84
188
LDC*1
85
189
LDCTX
86
189
LDE*1
87
191
88
192
MOV*1
90
193
POPC
102
213
POPM*1
103
213
PUSHC
106
216
PUSHM*1
107
217
115
224
SHA*1
116
225
SHL*1
117
228
121
232
122
233
123
233
JMPI
*1
*4
LDINTB
SBJNZ
*1
STC*1
STCTX
*1
STE*1
*1 Has general instruction addressing.
*2 INTBL and INTBH cannot be set simultaneously when using the LDINTB instruction.
Quick Reference-9
Quick Reference by Addressing (bit instruction addressing)
U/I/O/B/S/Z/D/C
bit,base:11
bit,base:16
bit,base:16[SB]
base:16[An]
bit,base:8[SB/FB]
[An]
bit,An
bit,Rn
base:8[An]
Addressing
Mnemonic
See page See page for
for function instruction
code
/number of
cycles
BAND
47
150
BCLR
48
150
BMCnd
49
152
BNAND
50
153
BNOR
21
154
BNOT
52
154
BNTST
53
155
BNXOR
54
156
BOR
55
156
BSET
57
157
BTST
58
158
BTSTC
59
159
BTSTS
60
160
BXOR
61
160
FCLR
75
179
FSET
76
180
Quick Reference-10
Chapter 1
Overview
1.1 Features of R8C/Tiny series
1.2 Address Space
1.3 Register Configuration
1.4 Flag Register (FLG)
1.5 Register Bank
1.6 Internal State after Reset is Cleared
1.7 Data Types
1.8 Data Arrangement
1.9 Instruction Format
1.10 Vector Table
Chapter 1 Overview
1.1 Features of R8C/Tiny Series
1.1 Features of R8C/Tiny Series
The R8C/Tiny series is single-chip microcomputer developed for built-in applications where the microcomputer is built into applications equipment.
The R8C/Tiny series support instructions suitable for the C language with frequently used instructions
arranged in one- byte op-code. Therefore, it allows you for efficient program development with few memory
capacity regardless of whether you are using the assembly language or C language. Furthermore, some
instructions can be executed in clock cycle, making fast arithmetic processing possible.
Its instruction set consists of 89 discrete instructions matched to the R8C’s abundant addressing modes.
This powerful instruction set allows to perform register-register, register-memory, and memory-memory
operations, as well as arithmetic/logic operations on bits and 4-bit data.
Some R8C/Tiny series models incorporate a multiplier, allowing for high-speed computation.
1.1.1 Features of R8C/Tiny series
●Register configuration
Data registers
Four 16-bit registers (of which two registers can be used as 8-bit registers)
Address registers Two 16-bit registers
Base registers
Two 16-bit registers
●Versatile instruction set
C language-suited instructions (stack frame manipulation): ENTER, EXITD, etc.
Register and memory-indiscriminated instructions: MOV, ADD, SUB, etc.
Powerful bit manipulate instructions: BNOT, BTST, BSET, etc.
4-bit transfer instructions: MOVLL, MOVHL, etc.
Frequently used 1-byte instructions: MOV, ADD, SUB, JMP, etc.
High-speed 1-cycle instructions: MOV, ADD, SUB, etc.
●Fast instruction execution time
Shortest 1-cycle instructions: 89 instructions include 20 1-cycle instructions.
(Approximately 75% of instructions execute in five cycles or under.)
1.1.2 Speed performance
Register-register transfer 0.1 µs
Register-memory transfer
0.1 µs
Register-register addition/subtraction 0.1 µs
8 bits x 8 bits register-register operation 0.2 µs
16 bits x 16 bits register-register operation 0.250 µs
16 bits / 8 bits register-register operation 0.904 µs
32 bits / 16 bits register-register operation 1.248 µs
•Conditions
-Products with built-in Multiplier
-Clock frequency 20 MHz
2
Chapter 1 Overview
1.2 Address Space
1.2 Address Space
Fig. 1.2.1 shows an address space.
Addresses 0000016 through 002FF16 make up an SFR (special function register) area. In individual models
of the R8C/Tiny series, the SFR area extends from 002FF16 toward lower addresses.
Addresses from 0040016 on make up a memory area. In individual models of the R8C/Tiny series, a RAM
area extends from address 0040016 toward higher addresses, and a ROM area extends from 0FFFF16
toward lower addresses. Addresses 0FFDC16 through 0FFFF16 make up a fixed vector area.
The SFR area in each
model extends toward
lower-address locations
as much as available.
00000 16
SFR area
002FF 16
00400 16
Internal RAM area
Internal ROM area
0FFDC16
0FFFF 16
Fixed vector area
Extention area
FFFFF16
Figure 1.2.1 Address space
3
The RAM area in each
model extends toward
higher-address locations as much as
available.
The ROM area in each
model extends toward
lower-address locations
as much as available.
Chapter 1 Overview
1.3 Register Configuration
1.3 Register Configuration
The central processing unit (CPU) contains the 13 registers shown in Figure 1.3.1. Of these registers, R0,
R1, R2, R3, A0, A1, and FB each consist of two sets of registers configuring two register banks.
b31
b15
b8 b7
b0
R2
R0H (High-order of R0)
R0L (Low-order of R0)
R3
R1H (High-order of R1)
R1L (Low-order of R1)
Data register (Note)
R2
R3
A0
Address register (Note)
A1
FB
b19
Frame base register (Note)
b15
b0
INTBL
INTBH
Interrupt table register
INTBH is the high-order 4 bits of INTB.
INTBL is the low-order 16 bits of INTB.
b19
b0
PC
Program counter
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
AA
AAAAAAA
AA
A
AA
AA
AA
AA
A
AA
AA
AAAAAAAAAAAAAAAAAAAA
A
FLG
b15
b8
IPL
b7
Flag register
b0
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Note: These registers configure register banks.This register
banks consist of two sets.
Figure 1.3.1 CPU register configuration
1.3.1 Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
The data registers (R0, R1, R2, and R3) consist of 16 bits, and are used primarily for transfers and
arithmetic/logic operations.
Registers R0 and R1 can be halved into separate high-order (R0H, R1H) and low-order (R0L, R1L) parts
for use as 8-bit data registers. For some instructions, moreover, you can combine R2 and R0 or R3 and
R1 to configure a 32-bit data register (R2R0 or R3R1).
4
Chapter 1 Overview
1.3 Register Configuration
1.3.2 Address registers (A0 and A1)
The address registers (A0 and A1) consist of 16 bits, and have the similar functions as the data registers. These registers are used for address register-based indirect addressing and address registerbased relative addressing.
For some instructions, registers A1 and A0 can be combined to configure a 32-bit address register
(A1A0).
1.3.3 Frame base register (FB)
The frame base register (FB) consists of 16 bits, and is used for FB-based relative addressing.
1.3.4 Program counter (PC)
The program counter (PC) consists of 20 bits, indicating the address of an instruction to be executed
next.
1.3.5 Interrupt table register (INTB)
The interrupt table register (INTB) consists of 20 bits, indicating the initial address of an interrupt vector
table.
1.3.6 User stack pointer (USP) and interrupt stack pointer (ISP)
There are two types of stack pointers: user stack pointer (USP) and interrupt stack pointer (ISP), each
consisting of 16 bits.
The stack pointer (USP/ISP) you want can be switched by a stack pointer select flag (U flag).
The stack pointer select flag (U flag) is bit 7 of the flag register (FLG).
1.3.7 Static base register (SB)
The static base register (SB) consists of 16 bits, and is used for SB-based relative addressing.
1.3.8 Flag register (FLG)
The flag register (FLG) consists of 11 bits, and is used as a flag, one bit for one flag. For details about
the function of each flag, see Section 1.4, “Flag Register (FLG).”
5
Chapter 1 Overview
1.4 Flag Register (FLG)
1.4 Flag Register (FLG)
Figure 1.4.1 shows a configuration of the flag register (FLG). The function of each flag is detailed below.
1.4.1 Bit 0: Carry flag (C flag)
This flag holds a carry, borrow, or shifted-out bit that has occurred in the arithmetic/logic unit.
1.4.2 Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is set (= 1), a single-step interrupt is generated after an instruction is executed. When an
interrupt is acknowledged, this flag is cleared to 0.
1.4.3 Bit 2: Zero flag (Z flag)
This flag is set when an arithmetic operation resulted in 0; otherwise, this flag is 0.
1.4.4 Bit 3: Sign flag (S flag)
This flag is set when an arithmetic operation resulted in a negative value; otherwise, this flag is 0.
1.4.5 Bit 4: Register bank select flag (B flag)
This flag selects a register bank. If this flag is 0, register bank 0 is selected; if the flag is 1, register bank
1 is selected.
1.4.6 Bit 5: Overflow flag (O flag)
This flag is set when an arithmetic operation resulted in overflow.
1.4.7 Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
When this flag is 0, the interrupt is disabled; when the flag is 1, the interrupt is enabled. When the
interrupt is acknowledged, this flag is cleared to 0.
1.4.8 Bit 7: Stack pointer select flag (U flag)
When this flag is 0, the interrupt stack pointer (ISP) is selected; when the flag is 1, the user stack pointer
(USP) is selected.
This flag is cleared to 0 when a hardware interrupt is acknowledged or an INT instruction of software
interrupt numbers 0 to 31 is executed.
1.4.9 Bits 8-11: Reserved area
6
Chapter 1 Overview
1.4 Flag Register (FLG)
1.4.10 Bits 12-14: Processor interrupt priority level (IPL)
The processor interrupt priority level (IPL) consists of three bits, allowing you to specify eight processor
interrupt priority levels from level 0 to level 7. If a requested interrupt’s priority level is higher than the
processor interrupt priority level (IPL), this interrupt is enabled.
1.4.11 Bit 15: Reserved area
b15
b0
IPL
U
I
O
B
S
Z
D
C
Flag register (FLG)
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Figure 1.4.1 Configuration of flag register (FLG)
7
Chapter 1 Overview
1.5 Register Bank
1.5 Register Bank
The R8C/Tiny has two register banks, each configured with data registers (R0, R1, R2, and R3), address
registers (A0 and A1), and frame base register (FB). These two register banks are switched over by the
register bank select flag (B flag) of the flag register (FLG).
Figure 1.5.1 shows a configuration of register banks.
Register bank 0 (B flag = 0)
b15
b8b7
Register bank 1 (B flag = 1)
b0
b15
b8b7
b0
R0
H
L
R0
H
L
R1
H
L
R1
H
L
R2
R2
R3
R3
A0
A0
A1
A1
FB
FB
Figure 1.5.1 Configuration of register banks
8
Chapter 1 Overview
1.6 Internal State after Reset is Cleared
1.6 Internal State after Reset is Cleared
The following lists the content of each register after a reset is cleared.
• Data registers (R0, R1, R2, and R3): 000016
• Address registers (A0 and A1): 000016
• Frame base register (FB): 000016
• Interrupt table register (INTB): 0000016
• User stack pointer (USP): 000016
• Interrupt stack pointer (ISP): 000016
• Static base register (SB): 000016
• Flag register (FLG): 000016
9
Chapter 1 Overview
1.7 Data Types
1.7 Data Types
There are four data types: integer, decimal, bit, and string.
1.7.1 Integer
An integer can be a signed or an unsigned integer. A negative value of a signed integer is represented
by two’s complement.
b7
Signed byte (8 bit) integer
b0
S
b7
b0
Unsigned byte (8 bit) integer
b15
Signed word (16 bit) integer
b0
S
b15
b0
Unsigned word (16 bit) integer
b31
Signed long word (32 bit) integer
b0
S
b31
Unsigned long word (32 bit) integer
S: Sign bit
Figure 1.7.1 Integer data
10
b0
Chapter 1 Overview
1.7 Data Types
1.7.2 Decimal
This type of data can be used in DADC, DADD, DSBB, and DSUB.
b7
Pack format
b0
(2 digits)
Pack format
b15
b0
(4 digits)
Figure 1.7.2 Decimal data
11
Chapter 1 Overview
1.7 Data Types
1.7.3 Bits
●Register bits
Figure 1.7.3 shows register bit specification.
Register bits can be specified by register direct (bit, Rn or bit, An). Use bit, Rn to specify a bit in data
register (Rn); use bit, An to specify a bit in address register (An).
Bits in each register are assigned bit numbers 0-15, from LSB to MSB. For bit in bit, Rn and bit, An, you
can specify a bit number in the range of 0 to 15.
Rn
b15
b0
An
b15
bit,Rn
(bit: 0 to 15, n: 0 to 3)
b0
bit,An
(bit: 0 to 15, n: 0 to 1)
Figure 1.7.3 Register bit specification
●Memory bits
Figure 1.7.4 shows addressing modes used for memory bit specification. Table 1.7.1 lists the address
range in which you can specify bits in each addressing mode. Be sure to observe the address range in
Table 1.7.1 when specifying memory bits.
Addressing modes
bit,base:8
bit,base:16
bit,base:16
Absolute addressing
SB-based relative
addressing
bit,base:8[SB]
bit,base:11[SB]
bit,base:16[SB]
FB-based relative
addressing
Address register-based indirect
addressing
Address register-based relative
addressing
bit,base:8[FB]
[An]
base:8[An]
base:16[An]
Figure 1.7.4 Addressing modes used for memory bit specification
Table 1.7.1 Bit-Specifying Address Range
Addressing
bit,base:16
bit,base:8[SB]
bit,base:11[SB]
bit,base:16[SB]
bit,base:8[FB]
[An]
base:8[An]
base:16[An]
Specification range
Lower limit (address) Upper limit (address)
0000016
01FFF16
[SB]
[SB]+0001F16
[SB]
[SB]+000FF16
[SB]
[SB]+01FFF16
[FB]–0001016
[FB]+0000F16
0000016
01FFF16
base:8
base:8+01FFF16
base:16
base:16+01FFF16
12
Remarks
The access range is 0000016 to 0FFFF16.
The access range is 0000016 to 0FFFF16.
The access range is 0000016 to 0FFFF16.
The access range is 0000016 to 0FFFF16.
The access range is 0000016 to 020FE16.
The access range is 0000016 to 0FFFF16.
Chapter 1 Overview
1.7 Data Types
(1) Bit specification by bit, base
Figure 1.7.5 shows the relationship between memory map and bit map.
Memory bits can be handled as an array of consecutive bits. Bits can be specified by a given combination of bit and base. Using bit 0 of the address that is set to base as the reference (= 0), set the desired
bit position to bit. Figure 1.7.6 shows examples of how to specify bit 2 of address 0000A16.
Address
b7
b0
0
n-1
n
n+1
nÅ{1
n+1
b7
nn
b0b7
nÅ|1
n–1
b0b7
0
b0
b7
b0
Bit map
Memory map
Figure 1.7.5 Relationship between memory map and bit map
Address 0000A16
BSET
2,AH
b7
b2
b0
b15
b10 b8b7
;
Address 0000916
BSET
10,9H
b0
;
These specification examples all
specify bit 2 of
address 0000A16.
Address 0000816
BSET
18,8H
b23
b18 b16b15
b8b7
b87
b82 b80b79
b72
b0
;
Address 0000016
BSET
82,0H
b7
;
Figure 1.7.6 Examples of how to specify bit 2 of address 0000A16
13
b0
Chapter 1 Overview
1.7 Data Types
(2) SB/FB relative bit specification
For SB/FB-based relative addressing, use bit 0 of the address that is the sum of the address set to
static base register (SB) or frame base register (FB) plus the address set to base as the reference (=
0), and set your desired bit position to bit.
(3) Address register indirect/relative bit specification
For address register-based indirect addressing, use bit 0 of address 0000016 as the reference (= 0)
and set your desired bit position to address register (An).
For address register-based relative addressing, use bit 0 of the address set to base as the reference
(= 0) and set your desired bit position to address register (An).
14
Chapter 1 Overview
1.7 Data Types
1.7.4 String
String is a type of data that consists of a given length of consecutive byte (8-bit) or word (16-bit) data.
This data type can be used in three types of string instructions: character string backward transfer
(SMOVB instruction), character string forward transfer (SMOVF instruction), and specified area initialize
(SSTR instruction).
Byte (8-bit) data
Word (16-bit) data
b7
b0
b15
b0
b7
b0
b15
b0
•
•
•
•
b7
•
•
•
•
b0
b15
Figure 1.7.7 String data
15
b0
Chapter 1 Overview
1.8 Data Arrangement
1.8 Data Arrangement
1.8.1 Data Arrangement in Register
Figure 1.8.1 shows the relationship between a register’s data size and bit numbers.
b3
b0
Nibble (4-bit) data
b7
b0
Byte (8-bit) data
b15
b0
Word (16-bit) data
b31
b0
Long word (32-bit) data
MSB
LSB
Figure 1.8.1 Data arrangement in register
16
Chapter 1 Overview
1.8 Data Arrangement
1.8.2 Data Arrangement in Memory
Figure 1.8.2 shows data arrangement in memory. Figure 1.8.3 shows some examples of operation.
b7
b0
N
N+1
N+2
N+3
b7
DATA
N
N+1
N+2
N+3
Byte (8-bit) data
b7
N
N+1
N+2
N+3
b0
DATA(L)
DATA(H)
Word (16-bit) data
b0
b7
DATA(L)
DATA(M)
DATA(H)
N
N+1
N+2
N+3
b0
DATA(LL)
DATA(LH)
DATA(HL)
DATA(HH)
Long Word (32-bit) data
20-bit (Address) data
Figure 1.8.2 Data arrangement in memory
MOV.B
N,R0H
b7
N
N+1
N+2
N+3
Does not change.
b0
DATA
b15
b0
DATA
H
R0
L
Byte (8-bit) data
MOV.W
N,R0
b7
N
N+1
N+2
N+3
b0
DATA(L)
DATA(H)
b15
R0
b0
DATA(H)
H
Word (16-bit) data
Figure 1.8.3 Examples of operation
17
DATA(L)
L
Chapter 1 Overview
1.9 Instruction Format
1.9 Instruction Format
The instruction format can be classified into four types: generic, quick, short, and zero. The number of
instruction bytes that can be chosen by a given format is least for the zero format, and increases successively for the short, quick, and generic formats in that order.
The following describes the features of each format.
1.9.1 Generic format (:G)
Op-code in this format consists of two bytes. This op-code contains information on operation and src*1
and dest*2 addressing modes.
Instruction code here is comprised of op-code (2 bytes), src code (0-3 bytes), and dest code (0-3 bytes).
1.9.2 Quick format (:Q)
Op-code in this format consists of two bytes. This op-code contains information on operation and immediate data and dest addressing modes. Note however that the immediate data in this op-code is a
numeric value that can be expressed by -7 to +8 or -8 to +7 (varying with instruction).
Instruction code here is comprised of op-code (2 bytes) containing immediate data and dest code (0-2
bytes).
1.9.3 Short format (:S)
Op-code in this format consists of one byte. This op-code contains information on operation and src and
dest addressing modes.Note however that the usable addressing modes are limited.
Instruction code here is comprised of op-code (1 byte), src code (0-2 bytes), and dest code (0-2 bytes).
1.9.4 Zero format (:Z)
Op-code in this format consists of one byte. This op-code contains information on operation (plus
immediate data) and dest addressing modes. Note however that the immediate data is fixed to 0, and
that the usable addressing modes are limited.
Instruction code here is comprised of op-code (1 byte) and dest code (0-2 bytes).
*1 src is the abbreviation of “source.”
*2 dest is the abbreviation of “destination.”
18
Chapter 1 Overview
1.10 Vector Table
1.10 Vector Table
There is an interrupt vector table as the vector table. In the interrupt vector table, there are the fixed vector
table and the variable vector table.
1.10.1 Fixed Vector Table
The fixed vector table is an address-fixed vector table. The part of the interrupt vector table is allocated
to addresses 0FFDC16 through 0FFFF16. Figure 1.10.1 shows a fixed vector table.
The interrupt vector table is comprised of four bytes per table. Each vector table must contain the
interrupt handler routine’s entry address.
FFFDC16
0FFDC16
Interrupt
vector table
0FFFF 16
FFFE016
Undefined instruction
Overflow
FFFE416
BRK instruction
FFFE816
Address match
FFFEC16
FFFF016
FFFF416
Figure 1.10.1 Fixed vector table
19
Single step
Oscillation stop detection/
Watchdog timer
FFFF816
(Reserved)
(Reserved)
FFFFC16
Reset
Chapter 1 Overview
1.10 Vector Table
1.10.2 Variable Vector Table
The variable vector table is an address-variable vector table. Specifically, this vector table is a 256-byte
interrupt vector table that uses the value indicated by the interrupt table register (INTB) as the entry
address (IntBase). Figure 1.10.2 shows a variable vector table.
The variable vector table is comprised of four bytes per table. Each vector table must contain the
interrupt handler routine’s entry address.
Each vector table has software interrupt numbers (0 to 63). The INT instruction uses these software
interrupt numbers.
Interrupts from the peripheral functions built in each M16C model are allocated to software interrupt
numbers 0 through 31.
b19
INTB
b0
IntBase
IntBase+4
0
IntBase+8
1
31
32
33
IntBase+252
63
Figure 1.10.2 Variable vector table
20




























Vectors accommodating peripheral I/O
interrupts
Software interrupt
numbers
Chapter 2
Addressing Modes
2.1 Addressing Modes
2.2 Guide to This Chapter
2.3 General Instruction Addressing
2.4 Special Instruction Addressing
2.5 Bit Instruction Addressing
Chapter 2 Addressing Modes
2.1 Addressing Modes
2.1 Addressing Modes
This section describes addressing mode-representing symbols and operations for each addressing mode.
The R8C/Tiny series has three addressing modes outlined below.
2.1.1 General instruction addressing
This addressing accesses an area from address 0000016 through address 0FFFF16.
The following lists the name of each general instruction addressing:
• Immediate
• Register direct
• Absolute
• Address register indirect
• Address register relative
• SB relative
• FB relative
• Stack pointer relative
2.1.2 Special instruction addressing
This addressing accesses an area from address 0000016 through address FFFFF16 and control registers.
The following lists the name of each specific instruction addressing:
• 20-bit absolute
• Address register relative with 20-bit displacement
• 32-bit address register indirect
• 32-bit register direct
• Control register direct
• Program counter relative
2.1.3 Bit instruction addressing
This addressing accesses an area from address 0000016 through address 0FFFF16.
The following lists the name of each bit instruction addressing:
• Register direct
• Absolute
• Address register indirect
• Address register relative
• SB relative
• FB relative
• FLG direct
22
Chapter 2 Addressing Modes
2.2 Guide to This Chapter
2.2 Guide to This Chapter
The following shows how to read this chapter using an actual example.
(1)
Address register relative
(2)
dsp:8[A0]
dsp:8[A1]
dsp:16[A0]
dsp:16[A1]
(3)
The value indicated by displacement
(dsp) plus the content of address
register (A0/A1)—added not including the sign bits—constitutes the
effective address to be operated on.
However, if the addition resulted in
exceeding 0FFFF16, the bits above
bit 17 are ignored, and the address
returns to 0000016.
dsp
A0 / A1
address
(4)
(1) Name
Indicates the name of addressing.
(2) Symbol
Represents the addressing mode.
(3) Explanation
Describes the addressing operation and the effective address range.
(4) Operation diagram
Diagrammatically explains the addressing operation.
23
Memory
Register
Chapter 2 Addressing Modes
2.3 General Instruction Addressing
2.3 General Instruction Addressing
Immediate
#IMM
#IMM8
#IMM16
#IMM20
The immediate data indicated by #IMM
is the object to be operated on.
b7
b0
b15
b8 b7
b0
b15
b8 b7
b0
#IMM8
#IMM16
b19
#IMM20
Register direct
R0L
R0H
R1L
R1H
R0
R1
R2
R3
A0
A1
Register
The specified register is the object to
be operated on.
b0
R0L / R1L
b15
b8
R0H / R1H
R0 / R1 / R2 / b15
R3 / A0 / A1
b8 b7
b0
Absolute
Memory
abs16
The value indicated by abs16 constitutes the
effective address to be operated on.
abs16
The effective address range is 0000016 to
0FFFF16.
Address register indirect
[A0]
[A1]
The value indicated by the content of
address register (A0/A1) constitutes
the effective address to be operated
on.
Register
A0 / A1
The effective address range is 0000016
to 0FFFF16.
24
address
Memory
Chapter 2 Addressing Modes
2.3 General Instruction Addressing
Address register relative
The value indicated by displacement
(dsp) plus the content of address
dsp:8[A1] register (A0/A1)—added not including
dsp:16[A0] the sign bits—constitutes the effective
dsp:16[A1] address to be operated on.
dsp:8[A0]
Memory
dsp
Register
A0 / A1
address
However, if the addition resulted in
exceeding 0FFFF16, the bits above bit
17 are ignored, and the address
returns to 0000016.
SB relative
The address indicated by the content
dsp:8[SB] of static base register (SB) plus the
dsp:16[SB] value indicated by displacement
Memory
Register
(dsp)—added not including the sign
bits—constitutes the effective address
to be operated on.
SB
address
address
dsp
However, if the addition resulted in
exceeding 0FFFF16, the bits above bit
17 are ignored, and the address
returns to 0000016.
FB relative
Memory
dsp:8[FB] The address indicated by the content
If the dsp value is negative
of frame base register (FB) plus the
value indicated by displacement
(dsp)—added including the sign bits—
constitutes the effective address to be
operated on.
dsp
Register
FB
However, if the addition resulted in
exceeding 0000016- 0FFFF16, the bits
above bit 17 are ignored, and the
address returns to 0000016 or
0FFFF16.
address
address
dsp
If the dsp value is positive
25
AAA
Chapter 2 Addressing Modes
2.3 General Instruction Addressing
Stack pointer relative
dsp:8[SP] The address indicated by the content of stack
pointer (SP) plus the value indicated by
displacement (dsp)—added including the sign
bits—constitutes the effective address to be
operated on. The stack pointer (SP) here is
the one indicated by the U flag.
Memory
If the dsp value is negative
dsp
Register
However, if the addition resulted in exceeding
0000016- 0FFFF16, the bits above bit 17 are
ignored, and the address returns to 0000016
or 0FFFF16.
This addressing can be used in MOV
instruction.
SP
address
dsp
If the dsp value is positive
26
AAA
Chapter 2 Addressing Modes
2.4 Special Instruction Addressing
2.4 Special Instruction Addressing
20-bit absolute
abs20
The value indicated by abs20 constitutes
the effective address to be operated on.
Memory
The effective address range is 0000016 to
FFFFF16.
abs20
This addressing can be used in LDE, STE,
JSR, and JMP instructions.
Address register relative with
LDE, STE instructions
20-bit displacement
dsp:20[A0] The address indicated by displacement
(dsp) plus the content of address register
dsp:20[A1] (A0/A1)—added not including the sign
bits—constitutes the effective address to
be operated on.
Register
A0
However, if the addition resulted in exceeding FFFFF16, the bits above bit 21 are
ignored, and the address returns to
0000016.
Memory
dsp
address
JMPI, JSRI instructions
Memory
dsp
Register
A0 / A1
address
This addressing can be used in LDE, STE,
JMPI, and JSRI instructions.
PC
The following lists the addressing mode and
instruction combinations that can be used.
dsp:20[A0]
LDE, STE, JMPI, and JSRI instructions
dsp:20[A1]
JMPI and JSRI instructions
32-bit address register indirect
[A1A0]
A1
The address indicated by 32 concatenated bits of address registers (A0
and A1) constitutes the effective
address to be operated on.
Register
A0
b31
b16 b15
b0
address-H
address-L
However, if the concatenated register
value exceeds FFFFF16, the bits
above bit 21 are ignored.
This addressing can be used in LDE
and STE instructions.
Memory
address
27
Chapter 2 Addressing Modes
2.4 Special Instruction Addressing
32-bit register direct
SHL, SHA instructions
R2R0
R3R1
The 32-bit concatenated register content of two
specified registers is the object to be operated
on.
A1A0
b16 b15
R2R0 b31
R3R1
b0
This addressing can be used in SHL, SHA,
JMPI, and JSRI instructions.
JMPI, JSRI instructions
The following lists the register and instruction
combinations that can be used.
R2R0 b31
R3R1
A1A0
R2R0, R3R1
SHL, SHA, JMPI, and JSRI instructions
A1A0
JMPI and JSRI instructions
b16 b15
b0
PC
Control register direct
Register
INTBL
INTBH
The specified control register is the
object to be operated on.
ISP
SP
This addressing can be used in LDC,
STC, PUSHC, and POPC instructions.
SB
FB
If you specify SP, the stack pointer
indicated by the U flag is the object to
be operated on.
FLG
b0
b15
INTBL
b15
b4 b3
b0
INTBH
b15
b0
b15
b0
b15
b0
b15
b0
b15
b0
ISP
USP
SB
FB
FLG
28
Chapter 2 Addressing Modes
2.4 Special Instruction Addressing
Program counter relative
label
• If the jump length specifier (.length)
is (.S)...
the base address plus the value
indicated by displacement (dsp)—
added not including the sign bits—
constitutes the effective address.
Memory
Base address
dsp
This addressing can be used in JMP
instruction.
label
+0
dsp +7
*1 The base address is the (start address of instruction + 2).
• If the jump length specifier (.length) is
(.B) or (.W)...
the base address plus the value indicated
by displacement (dsp)—added including
the sign bits—constitutes the effective
address.
However, if the addition resulted in
exceeding 0000016- FFFFF16, the bits
above bit 21 are ignored, and the address
returns to 0000016 or FFFFF16.
This addressing can be used in JMP and
JSR instructions.
Memory
If the dsp value is negative
dsp
Base address
dsp
If the dsp value is positive
label
AAA
label
If the specifier is (.B), -128 ≤ dsp ≤ +127
If the specifier is (.W), -32768 ≤ dsp ≤ +32767
*2 The base address varies with each instruction.
29
Chapter 2 Addressing Modes
2.5 Bit Instruction Addressing
2.5 Bit Instruction Addressing
This addressing can be used in the following instructions:
BCLR, BSET, BNOT, BTST, BNTST, BAND, BNAND, BOR, BNOR, BXOR, BNXOR, BMCnd, BTSTS,
BTSTC
Register direct
bit,R0
bit,R1
bit,R2
bit,R3
bit,A0
The specified register bit is the object
to be operated on.
bit , R0
For the bit position (bit) you can
specify 0 to 15.
R0
b15
b0
bit,A1
Bit position
Absolute
bit,base:16 The bit that is as much away from bit
0 at the address indicated by base as
the number of bits indicated by bit is
the object to be operated on.
b0
b7
base
Bits at addresses 0000016 through
01FFF16 can be the object to be
operated on.
Bit position
Address register indirect
[A0]
[A1]
The bit that is as much away from bit 0 at
address 0000016 as the number of bits
indicated by address register (A0/A1) is
the object to be operated on.
b7
0000016
Bits at addresses 0000016 through
01FFF16 can be the object to be operated
on.
Bit position
30
b0
Chapter 2 Addressing Modes
2.5 Bit Instruction Addressing
Address register relative
base:8[A0]
base:8[A1]
base:16[A0]
base:16[A1]
The bit that is as much away
from bit 0 at the address indicated by base as the number of
bits indicated by address register
(A0/A1) is the object to be
operated on.
b7
However, if the address of the bit
to be operated on exceeds
0FFFF16, the bits above bit 17
are ignored and the address
returns to 0000016.
b0
base
Bit position
The address range that can be
specified by address register
(A0/A1) is 8,192 bytes from
base.
SB relative
bit,base:8[SB] The bit that is as much away from
bit 0 at the address indicated by
bit,base:11[SB] static base register (SB) plus the
Memory
bit,base:16[SB] value indicated by base (added not
b7
including the sign bits) as the
number of bits indicated by bit is the
object to be operated on.
However, if the address of the bit to
be operated on exceeds 0FFFF16,
the bits above bit 17 are ignored and
the address returns to 0000016.
The address ranges that can be
specified by bit,base: 8, bit,base:
11, and bit,base:16 respectively are
32 bytes, 256 bytes, and 8,192
bytes from the static base register
(SB) value.
31
Register
SB
address
address
base
Bit position
b0
Chapter 2 Addressing Modes
2.5 Bit Instruction Addressing
FB relative
bit,base:8[FB]
The bit that is as much away from bit 0 at
the address indicated by frame base
register (FB) plus the value indicated by
base (added including the sign bit) as the
number of bits indicated by bit is the
object to be operated on.
Memory
If the base value is negative
However, if the address of the bit to be
operated on exceeds 0000016-0FFFF16,
the bits above bit 17 are ignored and the
address returns to 0000016 or 0FFFF16.
(Bit position)
base
Register
FB
The address range that can be specified
by bit,base: 8 is 16 bytes toward lower
addresses or 15 bytes toward higher
addresses from the frame base register
(FB) value.
address
address
base
If the base value is positive
Bit position
FLG direct
U
I
The specified flag is the object to
be operated on.
O
B
This addressing can be used in
FCLR and FSET instructions.
S
Z
D
C
32
Register
b7
FLG
U
I
O
B
S
b0
Z
D
C
Chapter 3
Functions
3.1 Guide to This Chapter
3.2 Functions
Chapter 3 Functions
3.1 Guide to This Chapter
3.1 Guide to This Chapter
This chapter describes the functionality of each instruction by showing syntax, operation, function, selectable src/dest, flag changes, description examples, and related instructions.
The following shows how to read this chapter by using an actual page as an example.
Chapter 3 Functions
(1)
(2)
(3)
3.2 Functions
Transfer
MOVe
MOV
[ Syntax ]
MOV
[ Instruction Code/Number of Cycles ]
Page=193
MOV.size (:format) src,dest
G , Q , Z , S (Can be specified)
B,W
(4)
[ Operation ]
dest
(5)
[ Function ]
•
•
(6)
src
This instruction transfers src to dest.
If dest is an address register when the size specifier (.size) you selected is (.B), src is zero-expanded to transfer data in
16 bits. If src is an address register, data is transferred from the address register’s 8 low-order bits.
[ Selectable src/dest ]
(See the next page for src/dest classified by format.)
src
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
(7)
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
dest
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM
dsp:8[SP]
S
C
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
[ Flag Change ]
Flag
U
I
O
B
Z
D
Change
Conditions
S : The flag is set when the transfer resulted in MSB of dest = 1; otherwise cleared.
Z : The flag is set when the transfer resulted in 0; otherwise cleared.
(8)
(9)
[ Description Example ]
MOV.B:S
#0ABH,R0L
MOV.W
#-1,R2
[ Reated Instruction]
LDE,STE,XCHG
92
34
R1H/R3
[A1]
dsp:8[FB]
abs16
dsp:8[SP]
Chapter 3 Functions
3.1 Guide to This Chapter
(1) Mnemonic
Indicates the mnemonic explained in this page.
(2) Instruction code/Number of Cycles
Indicates the page in which instruction code/number of cycles is listed.
Refer to this page for instruction code and number of cycles.
(3) Syntax
Indicates the syntax of the instruction using symbols. If (:format) is omitted, the assembler chooses the
optimum specifier.
MOV.size (: format) src , dest
(a) (b)
(c)
G,Q,S,Z
(f)
B,W
(e)
(d)
(a) Mnemonic MOV
Describes the mnemonic.
(b) Size specifier size
Describes the data size in which data is handled. The following lists the data sizes that can be speci
fied:
.B
Byte (8 bits)
.W
Word (16 bits)
.L
Long word (32 bits)
Some instructions do not have a size specifier.
(c) Instruction format specifier (: format)
Describes the instruction format. If (.format) is omitted, the assembler chooses the optimum speci
fier. If (.format) is entered, its content is given priority. The following lists the instruction formats that
can be specified:
:G Generic format
:Q Quick format
:S Short format
:Z Zero format
Some instructions do not have an instruction format specifier.
(d) Operand src, dest
Describes the operand.
(e) Indicates the data size you can specify in (b).
(f) Indicates the instruction format you can specify in (c).
35
Chapter 3 Functions
3.1 Guide to This Chapter
Chapter 3 Functions
(1)
(2)
(3)
3.2 Functions
Transfer
MOVe
MOV
[ Syntax ]
MOV
[ Instruction Code/Number of Cycles ]
Page=193
MOV.size (:format) src,dest
G , Q , Z , S (Can be specified)
B,W
(4)
[ Operation ]
dest
(5)
[ Function ]
This instruction transfers src to dest.
If dest is an address register when the size specifier (.size) you selected is (.B), src is zero-expanded to transfer data in
16 bits. If src is an address register, data is transferred from the address register’s 8 low-order bits.
•
•
(6)
src
[ Selectable src/dest ]
(See the next page for src/dest classified by format.)
src
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
(7)
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
dest
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM
dsp:8[SP]
S
C
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
[ Flag Change ]
Flag
U
I
O
B
Z
D
Change
Conditions
S :
Z :
(8)
(9)
The flag is set when the transfer resulted in MSB of dest = 1; otherwise cleared.
The flag is set when the transfer resulted in 0; otherwise cleared.
[ Description Example ]
MOV.B:S
#0ABH,R0L
MOV.W
#-1,R2
[ Reated Instruction]
LDE,STE,XCHG
92
36
R1H/R3
[A1]
dsp:8[FB]
abs16
dsp:8[SP]
Chapter 3 Functions
3.1 Guide to This Chapter
(4) Operation
Explains the operation of the instruction using symbols.
(5) Function
Explains the function of the instruction and precautions to be taken when using the instruction.
(6) Selectable src / dest (label)
If the instruction has an operand, this indicates the format you can choose for the operand.
(a)
src
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
dest
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
R1H/R3
[A1]
dsp:8[FB]
abs16
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
dsp:20[A1]
R3R1
abs20
A1A0
#IMM
dsp:20[A0] dsp:20[A1] abs20
dsp:8[SP] R2R0
R3R1
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
(b)
dsp:8[SP]
(d)
(a) Items that can be selected as src(source).
(c)
(e)
(b) Items that can be selected as dest(destination).
(c) Addressing that can be selected.
(d) Addressing that cannot be selected.
(e) Shown on the left side of the slash (R0H) is the addressing when data is handled in bytes (8 bits).
Shown on the right side of the slash (R1) is the addressing when data is handled in words (16 bits).
(7) Flag change
Indicates a flag change that occurs after the instruction is executed. The symbols in the table mean the
following:
“—” The flag does not change.
“O” The flag changes depending on condition.
(8) Description example
Shows a description example for the instruction.
(9) Related instructions
Shows related instructions that cause an operation similar or opposite that of this instruction.
37
Chapter 3 Functions
3.1 Guide to This Chapter
The following explains the syntax of each jump instruction—JMP, JPMI, JSR, and JSRI by using an actual
example.
Chapter 3 Functions
JMP
(1)
(2)
3.2 Functions
Unconditional jump
JuMP
[ Syntax ]
(3)
JMP
[ Instruction Code/Number of Cycles ]
Page=183
JMP (.length) label
S, B, W, A (Can be specified)
(3) Syntax
Indicates the instruction syntax using a symbol.
JMP (.length) label
S, B, W, A
(a)
(b)
(d)
(c)
(a) Mnemonic JMP
Describes the mnemonic.
(b) Jump distance specifier .length
Describes the distance of jump. If (.length) is omitted in JMP or JSR instruction, the assembler
chooses the optimum specifier. If (.length) is entered, its content is given priority.
The following lists the jump distances that can be specified:
.S
3-bit PC forward relative (+2 to +9)
.B
8-bit PC relative
.W
16-bit PC relative
.A
20-bit absolute
(c) Operand label
Describes the operand.
(d) Shows the jump distance that can be specified in (b).
38
Chapter 3
Functions
3.2
Absolute value
ABSolute
ABS
[ Syntax ]
ABS.size
Functions
ABS
[ Instruction Code/Number of Cycles ]
Page=138
dest
B,W
[ Operation ]
dest
dest
[ Function ]
• This instruction takes on an absolute value of dest and stores it in dest.
[ Selectable dest ]
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
dest
R0H/R1
R1L/R2
A1/A1
[A0]
dsp:8[A1]
dsp:8[SB]
dsp:16[A1] dsp:16[SB]
dsp:20[A1] abs20
R3R1
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
O : The flag is set (= 1) when dest before the operation is –128 (.B) or –32768 (.W); otherwise cleared (= 0).
S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.
Z : The flag is set when the operation resulted in 0; otherwise cleared.
C : The flag is indeterminate.
[ Description Example ]
ABS.B
ABS.W
R0L
A0
39
Chapter 3
Functions
3.2
Add with carry
ADdition with Carry
ADC
[ Syntax ]
ADC.size
Functions
ADC
[ Instruction Code/Number of Cycles ]
Page=138
src,dest
B,W
[ Operation ]
dest
src
+
dest
+
C
[ Function ]
• This instruction adds dest, src, and C flag together and stores the result in dest.
• If dest is an A0 or A1 when the size specifier (.size) you selected is (.B), src is zero-expanded to
perform calculation in 16 bits. If src is an A0 or A1, operation is performed on the eight low-order bits
of the A0 or A1.
[ Selectable src/dest ]
src
R0L/R0
A0/A0*1
R0H/R1
R1L/R2
*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
dest
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1H/R3
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
[A1]
dsp:8[FB]
abs16
#IMM
R0L/R0
*1
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
*1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
R1H/R3
[A0]
[A1]
dsp:8[SB] dsp:8[FB]
dsp:16[SB] abs16
abs20
A1A0
*1 If you specify (.B) for the size specifier (.size), you cannot choose A0 or A1 for src and dest simultaneously.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
O : The flag is set when a signed operation resulted in exceeding +32767 (.W) or –32768 (.W) or
+127 (.B) or –128 (.B); otherwise cleared.
S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.
Z : The flag is set when the operation resulted in 0; otherwise cleared.
C : The flag is set when an unsigned operation resulted in exceeding +65535 (.W) or +255 (.B);
otherwise cleared.
[ Description Example ]
ADC.B
ADC.W
ADC.B
ADC.B
#2,R0L
A0,R0
A0,R0L
R0L,A0
[ Related Instructions ]
; A0’s 8 low-order bits and R0L are added.
; R0L is zero-expanded and added with A0.
ADCF,ADD,SBB,SUB
40
Chapter 3
Functions
3.2
Add carry flag
ADdition Carry Flag
ADCF
[ Syntax ]
ADCF.size
Functions
ADCF
[ Instruction Code/Number of Cycles ]
Page=140
dest
B,W
[ Operation ]
dest
dest
+
C
[ Function ]
This instruction adds dest and C flag together and stores the result in dest.
[ Selectable dest ]
dest
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
O : The flag is set when a signed operation resulted in exceeding +32767 (.W) or –32768 (.W) or
+127 (.B) or –128 (.B); otherwise cleared.
S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.
Z : The flag is set when the operation resulted in 0; otherwise cleared.
C : The flag is set when an unsigned operation resulted in exceeding +65535 (.W) or +255 (.B);
otherwise cleared.
[ Description Example ]
ADCF.B
ADCF.W
R0L
Ram:16[A0]
[ Related Instructions ]
ADC,ADD,SBB,SUB
41
Chapter 3
Functions
3.2
Add without carry
ADDition
ADD
[ Syntax ]
ADD.size (:format)
[ Operation ]
dest
dest
ADD
[ Instruction Code/Number of Cycles ]
Page=140
G , Q , S (Can be specified)
B,W
src,dest
+
Functions
src
[ Function ]
• This instruction adds dest and src together and stores the result in dest.
• If dest is an A0 or A1 when the size specifier (.size) you selected is (.B), src is zero-expanded to
perform calculation in 16 bits. If src is an A0 or A1, operation is performed on the eight low-order bits
of the A0 or A1.
• If dest is a stack pointer when the size specifier (.size) you selected is (.B), src is sign extended to
perform calculation in 16 bits.
(See the next page for src/dest classified by format.)
[ Selectable src/dest ]
src
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
R0L/R0
R0H/R1
R1L/R2
R1H/R3
*1
*1
*1
*1
A0/A0
A1/A1
[A0]
[A1]
A0/A0
A1/A1
[A0]
[A1]
dsp:8[A0] dsp:8[A1]
dsp:8[SB]
dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB]
dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16
dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16
dsp:20[A0] dsp:20[A1] abs20
#IMM
dsp:20[A0] dsp:20[A1] abs20
SP/SP*2
R2R0
R3R1
A1A0
R2R0
R3R1
A1A0
*1 If you specify (.B) for the size specifier (.size), you cannot choose A0 or A1 for src and dest simultaneously.
*2 Operation is performed on the stack pointer indicated by the U flag. You can choose only #IMM for src.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
O : The flag is set when a signed operation resulted in exceeding +32767 (.W) or –32768 (.W) or
+127 (.B) or –128 (.B); otherwise cleared.
S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.
Z : The flag is set when the operation resulted in 0; otherwise cleared.
C : The flag is set when an unsigned operation resulted in exceeding +65535 (.W) or +255 (.B);
otherwise cleared.
[ Description Example ]
ADD.B
ADD.B
ADD.B
ADD.W
A0,R0L
R0L,A0
Ram:8[SB],R0L
#2,[A0]
[ Related Instructions ]
; A0’s 8 low-order bits and R0L are added.
; R0L is zero-expanded and added with A0.
ADC,ADCF,SBB,SUB
42
Chapter 3
Functions
3.2
Functions
[src/dest Classified by Format]
G format
src
R0L/R0
A0/A0*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1*1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
dest
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM
R0L/R0
A0/A0*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1*1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
SP/SP*2
*1 If you specify (.B) for the size specifier (.size), you cannot choose A0 or A1 for src and dest simultaneously.
*2 Operation is performed on the stack pointer indicated by the U flag. You can choose only #IMM for src.
Q format
src
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
dest
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM*3
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
SP/SP*2
*2 Operation is performed on the stack pointer indicated by the U flag. You can choose only #IMM for src.
*3 The range of values that can be taken on is –8 < #IMM < +7.
S format*4
src
R0L
abs16
R0L*5
abs16
R0H
#IMM
R0H*5
#IMM
dsp:8[SB]
dsp:8[SB]
dest
dsp:8[FB] R0L
abs16
dsp:8[FB] R0L*5
abs16
*4 You can only specify (.B) for the size specifier (.size).
*5 You cannot choose the same register for src and dest.
43
R0H
A0
R0H*5
A0
dsp:8[SB]
A1
dsp:8[SB]
A1
dsp:8[FB]
dsp:8[FB]
Chapter 3
Functions
3.2
Add & conditional jump
ADdition then Jump on Not Zero
ADJNZ
[ Syntax ]
ADJNZ.size src,dest,label
Functions
ADJNZ
[ Instruction Code/Number of Cycles ]
Page=146
B,W
[ Operation ]
dest
dest + src
if dest 0 then jump label
[ Function ]
• This instruction adds dest and src together and stores the result in dest.
• If the addition resulted in any value other than 0, control jumps to label. If the addition resulted in 0,
the next instruction is executed.
• The op-code of this instruction is the same as that of SBJNZ.
[ Selectable src/dest/label ]
src
dest
R0L/R0
R1H/R3
[A0]
dsp:8[A1]
dsp:16[A0]
abs16
#IMM*1
R0H/R1
A0/A0
[A1]
dsp:8[SB]
dsp:16[A1]
label
R1L/R2
A1/A1
dsp:8[A0]
dsp:8[FB]
dsp:16[SB]
*1 The range of values that can be taken on is –8 < #IMM < +7.
*2 PC indicates the start address of the instruction.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
[ Description Example ]
ADJNZ.W #–1,R0,label
[ Related Instructions ]
SBJNZ
44
PC*2–126
label
PC*2+129
Chapter 3
Functions
3.2
Logically AND
AND
AND
[ Syntax ]
AND.size (:format) src,dest
[ Operation ]
dest
src
Functions
AND
[ Instruction Code/Number of Cycles ]
Page=147
G , S (Can be specified)
B,W
dest
[ Function ]
• This instruction logically ANDs dest and src together and stores the result in dest.
• If dest is an A0 or A1 when the size specifier (.size) you selected is (.B), src is zero-expanded to
perform calculation in 16 bits. If src is an A0 or A1, operation is performed on the eight low-order bits
of the A0 or A1.
(See the next page for src/dest classified by format.)
[ Selectable src/dest ]
src
R0L/R0
A0/A0*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1*1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
dest
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM
R0L/R0
A0/A0*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1*1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
SP/SP
*1 If you specify (.B) for the size specifier (.size), you cannot choose A0 or A1 for src and dest simultaneously.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.
Z : The flag is set when the operation resulted in 0; otherwise cleared.
[ Description Example ]
AND.B
AND.B:G
AND.B:G
AND.B:S
Ram:8[SB],R0L
A0,R0L
R0L,A0
#3,R0L
[ Related Instructions ]
; A0’s 8 low-order bits and R0L are ANDed.
; R0L is zero-expanded and ANDed with A0.
OR,XOR,TST
45
Chapter 3
Functions
3.2
Functions
[src/dest Classified by Format]
G format
src
R0L/R0
A0/A0*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1*1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
dest
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM
R0L/R0
A0/A0*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1*1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
SP/SP
*1 If you specify (.B) for the size specifier (.size), you cannot choose A0 or A1 for src and dest simultaneously.
S format*2
src
R0L
abs16
R0L*3
abs16
R0H
#IMM
R0H*3
#IMM
dsp:8[SB]
dsp:8[SB]
dest
dsp:8[FB] R0L
abs16
dsp:8[FB] R0L*3
abs16
*2 You can only specify (.B) for the size specifier (.size).
*3 You cannot choose the same register for src and dest.
46
R0H
A0
R0H*3
A0
dsp:8[SB]
A1
dsp:8[SB]
A1
dsp:8[FB]
dsp:8[FB]
Chapter 3
Functions
3.2
Logically AND bits
Bit AND carry flag
BAND
[ Syntax ]
BAND src
Functions
BAND
[ Instruction Code/Number of Cycles ]
Page=150
[ Operation ]
C
src
C
[ Function ]
• This instruction logically ANDs the C flag and src together and stores the result in the C flag.
[ Selectable src ]
bit,R0
bit,A0
base:8[A0]
base:16[A0]
C
src
bit,R1
bit,R2
bit,R3
bit,A1
[A0]
[A1]
base:8[A1]
bit,base:8[SB] bit,base:8[FB]
base:16[A1] bit,base:16[SB] bit,base:16
bit,base:11[SB]
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
C : The flag is set when the operation resulted in 1; otherwise cleared.
[ Description Example ]
BAND
flag
BAND
4,Ram
BAND
16,Ram:16[SB]
BAND
[A0]
[ Related Instructions ]
BOR,BXOR,BNAND,BNOR,BNXOR
47
Chapter 3
Functions
3.2
Clear bit
Bit CLeaR
BCLR
[ Syntax ]
BCLR (:format)
Functions
BCLR
[ Instruction Code/Number of Cycles ]
Page=150
G , S (Can be specified)
dest
[ Operation ]
dest
0
[ Function ]
• This instruction stores 0 in dest.
[ Selectable dest ]
bit,R0
bit,A0
base:8[A0]
base:16[A0]
C
dest
bit,R1
bit,R2
bit,R3
bit,A1
[A0]
[A1]
base:8[A1]
bit,base:8[SB] bit,base:8[FB]
base:16[A1] bit,base:16[SB] bit,base:16
bit,base:11[SB]*1
*1 This dest can only be selected when in S format.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
[ Description Example ]
BCLR
flag
BCLR
4,Ram:8[SB]
BCLR
16,Ram:16[SB]
BCLR
[A0]
[ Related Instructions ]
BSET,BNOT,BNTST,BTST,BTSTC,BTSTS
48
Chapter 3
Functions
3.2
Conditional bit transfer
Bit Move Condition
BMCnd
[ Syntax ]
BMCnd
dest
[ Operation ]
if true then
else
dest
dest
Functions
BMCnd
[ Instruction Code/Number of Cycles ]
Page=152
1
0
[ Function ]
• This instruction transfers the true or false value of the condition indicated by Cnd to dest. If the
condition is true, 1 is transferred; if false, 0 is transferred.
• There are following kinds of Cnd.
Cnd
Condition
Expression
GEU/C C=1
EQ/Z
GTU
PZ
GE
GT
O
Equal to or greater than
C flag is 1.
Z=1
Equal to
Z flag is 1.
____
C Z=1
Greater than
S=0
Positive or zero
A
S O=0
Equal to or greater than
(signed value)
A
(S O) Z=0 Greater than (signed value)
O=1
O flag is 1.
Cnd
Condition
LTU/NC C=0
=
0
Smaller than
C flag is 0.
NE/NZ Z=0
Not equal
Z flag is 0.
____
LEU
C Z=0
Equal to or smaller than
N
S=1
Negative
A
LE
(S O) Z=1 Equal to or smaller than
(signed value)
A
LT
S O=1
Smaller than (signed value)
NO
O=0
O flag is 0.
Expression
≠
0
[ Selectable dest ]
bit,R0
bit,A0
base:8[A0]
base:16[A0]
C
dest
bit,R1
bit,R2
bit,R3
bit,A1
[A0]
[A1]
base:8[A1]
bit,base:8[SB] bit,base:8[FB]
base:16[A1] bit,base:16[SB] bit,base:16
bit,base:11[SB]
[ Flag Change ]
Flag
U
I
O
B
S
Z
Change
D
C
*1
*1 The flag changes if you specified the C flag for dest.
[ Description Example ]
BMN
3,Ram:8[SB]
BMZ
C
[ Related Instructions ]
JCnd
49
Chapter 3
Functions
3.2
Logically AND inverted bits
Bit Not AND carry flag
BNAND
[ Syntax ]
BNAND
BNAND
[ Instruction Code/Number of Cycles ]
Page=153
src
[ Operation ]
______
C
src
Functions
C
[ Function ]
• This instruction logically ANDs the C flag and inverted src together and stores the result in the C flag.
[ Selectable src ]
bit,R0
bit,A0
base:8[A0]
base:16[A0]
C
src
bit,R1
bit,R2
bit,R3
bit,A1
[A0]
[A1]
base:8[A1]
bit,base:8[SB] bit,base:8[FB]
base:16[A1] bit,base:16[SB] bit,base:16
bit,base:11[SB]
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Condition
C : The flag is set when the operation resulted in 1; otherwise cleared.
[ Description Example ]
BNAND
BNAND
BNAND
BNAND
flag
4,Ram
16,Ram:16[SB]
[A0]
[ Related Instructions ]
BAND,BOR,BXOR,BNOR,BNXOR
50
Chapter 3
Functions
3.2 Functions
Logically OR inverted bits
Bit Not OR carry flag
BNOR
[ Syntax ]
BNOR src
BNOR
[ Instruction Code/Number of Cycles ]
Page=154
[ Operation ]
______
C
src
C
[ Function ]
• This instruction logically ORs the C flag and inverted src together and stores the result in the C flag.
[ Selectable src ]
bit,R0
bit,A0
base:8[A0]
base:16[A0]
C
src
bit,R1
bit,R2
bit,R3
bit,A1
[A0]
[A1]
base:8[A1]
bit,base:8[SB] bit,base:8[FB]
base:16[A1] bit,base:16[SB] bit,base:16
bit,base:11[SB]
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Condition
C : The flag is set when the operation resulted in 1; otherwise cleared.
[ Description Example ]
BNOR
flag
BNOR
4,Ram
BNOR
16,Ram:16[SB]
BNOR
[A0]
[ Related Instructions ]
BAND,BOR,BXOR,BNAND,BNXOR
51
Chapter 3
Functions
3.2 Functions
Invert bit
Bit NOT
BNOT
[ Syntax ]
BNOT(:format)
BNOT
[ Instruction Code/Number of Cycles ]
Page=154
(Can be specified)
dest
G ,S
[ Operation ]
________
dest
dest
[ Function ]
• This instruction inverts dest and stores the result in dest.
[ Selectable dest ]
bit,R0
bit,A0
base:8[A0]
base:16[A0]
C
dest
bit,R1
bit,R2
bit,R3
bit,A1
[A0]
[A1]
base:8[A1]
bit,base:8[SB] bit,base:8[FB]
base:16[A1] bit,base:16[SB] bit,base:16
bit,base:11[SB]*1
*1 This dest can only be selected when in S format.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
[ Description Example ]
BNOT
flag
BNOT
4,Ram:8[SB]
BNOT
16,Ram:16[SB]
BNOT
[A0]
[ Related Instructions ]
BCLR,BSET,BNTST,BTST,BTSTC,BTSTS
52
Chapter 3
Functions
3.2 Functions
Test inverted bit
Bit Not TeST
BNTST
[ Syntax ]
BNTST
BNTST
[ Instruction Code/Number of Cycles ]
Page=155
src
[ Operation ]
Z
src
______
C
src
[ Function ]
• This instruction transfers inverted src to the Z flag and inverted src to the C flag.
[ Selectable src ]
bit,R0
bit,A0
base:8[A0]
base:16[A0]
C
src
bit,R1
bit,R2
bit,R3
bit,A1
[A0]
[A1]
base:8[A1]
bit,base:8[SB] bit,base:8[FB]
base:16[A1] bit,base:16[SB] bit,base:16
bit,base:11[SB]
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
Z : The flag is set when src is 0; otherwise cleared.
C : The flag is set when src is 0; otherwise cleared.
[ Description Example ]
BNTST
flag
BNTST
4,Ram:8[SB]
BNTST
16,Ram:16[SB]
BNTST
[A0]
[ Related Instructions ]
BCLR,BSET,BNOT,BTST,BTSTC,BTSTS
53
Chapter 3
Functions
3.2 Functions
Exclusive OR inverted bits
Bit Not eXclusive OR carry flag
BNXOR
[ Syntax ]
BNXOR
[ Instruction Code/Number of Cycles ]
Page=156
src
[ Operation ]
______ A
C
src
BNXOR
C
[ Function ]
• This instruction exclusive ORs the C flag and inverted src and stores the result in the C flag.
[ Selectable src ]
bit,R0
bit,A0
base:8[A0]
base:16[A0]
C
src
bit,R1
bit,R2
bit,R3
bit,A1
[A0]
[A1]
base:8[A1]
bit,base:8[SB] bit,base:8[FB]
base:16[A1] bit,base:16[SB] bit,base:16
bit,base:11[SB]
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
C : The flag is set when the operation resulted in 1; otherwise cleared.
[ Description Example ]
BNXOR
flag
BNXOR
4,Ram
BNXOR
16,Ram:16[SB]
BNXOR
[A0]
[ Related Instructions ]
BAND,BOR,BXOR,BNAND,BNOR
54
Chapter 3
Functions
3.2 Functions
Logically OR bits
Bit OR carry flag
BOR
[ Syntax ]
BOR src
BOR
[ Instruction Code/Number of Cycles ]
Page=156
[ Operation ]
C
src
C
[ Function ]
• This instruction logically ORs the C flag and src together and stores the result in the C flag.
[ Selectable src ]
bit,R0
bit,A0
base:8[A0]
base:16[A0]
C
src
bit,R1
bit,R2
bit,R3
bit,A1
[A0]
[A1]
base:8[A1]
bit,base:8[SB] bit,base:8[FB]
base:16[A1] bit,base:16[SB] bit,base:16
bit,base:11[SB]
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
C : The flag is set when the operation resulted in 1; otherwise cleared.
[ Description Example ]
BOR
BOR
BOR
BOR
flag
4,Ram
16,Ram:16[SB]
[A0]
[ Related Instructions ]
BAND,BXOR,BNAND,BNOR,BNXOR
55
Chapter 3
Functions
3.2 Functions
Debug interrupt
BReaK
BRK
[ Syntax ]
BRK
BRK
[ Instruction Code/Number of Cycles ]
Page=157
[ Operation ]
SP
M(SP)
SP
M(SP)
PC
SP – 2
(PC + 1)H, FLG
SP – 2
(PC + 1)ML
M(FFFE416)
[ Function ]
• This instruction generates a BRK interrupt.
• The BRK interrupt is a nonmaskable interrupt.
[ Flag Change ]*1
Flag
U
I
O
B
S
Z
D
Change
Conditions
U : The flag is cleared.
I : The flag is cleared.
D : The flag is cleared.
C
*1 The flags are saved to the stack area before the BRK instruction is executed. After the interrupt, the flags
change state as shown on the left.
[ Description Example ]
BRK
[ Related Instructions ]
INT,INTO
56
Chapter 3
Functions
3.2 Functions
Set bit
Bit SET
BSET
[ Syntax ]
BSET (:format)
BSET
[ Instruction Code/Number of Cycles ]
Page=157
G , S (Can be specified)
dest
[ Operation ]
dest
1
[ Function ]
• This instruction stores 1 in dest.
[ Selectable dest ]
bit,R0
bit,A0
base:8[A0]
base:16[A0]
C
dest
bit,R1
bit,R2
bit,R3
bit,A1
[A0]
[A1]
base:8[A1]
bit,base:8[SB] bit,base:8[FB]
base:16[A1] bit,base:16[SB] bit,base:16
bit,base:11[SB]*1
*1 This dest can only be selected when in S format.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
[ Description Example ]
BSET
flag
BSET
4,Ram:8[SB]
BSET
16,Ram:16[SB]
BSET
[A0]
[ Related Instructions ]
BCLR,BNOT,BNTST,BTST,BTSTC,BTSTS
57
Chapter 3
Functions
3.2 Functions
BTST
Test bit
Bit TeST
[ Syntax ]
BTST (:format)
[ Instruction Code/Number of Cycles ]
Page=158
G , S (Can be specified)
src
[ Operation ]
______
Z
src
C
src
[ Function ]
• This instruction transfers inverted src to the Z flag and non-inverted src to the C flag.
[ Selectable src ]
bit,R0
bit,A0
base:8[A0]
base:16[A0]
C
src
bit,R1
bit,R2
bit,R3
bit,A1
[A0]
[A1]
base:8[A1]
bit,base:8[SB] bit,base:8[FB]
base:16[A1] bit,base:16[SB] bit,base:16
bit,base:11[SB]*1
*1 This src can only be selected when in S format.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
Z : The flag is set when src is 0; otherwise cleared.
C : The flag is set when src is 1; otherwise cleared.
[ Description Example ]
BTST
BTST
BTST
BTST
flag
4,Ram:8[SB]
16,Ram:16[SB]
[A0]
[ Related Instructions ]
BCLR,BSET,BNOT,BNTST,BTSTC,BTSTS
58
BTST
Chapter 3
Functions
3.2 Functions
Test bit & clear
Bit TeST & Clear
BTSTC
[ Syntax ]
BTSTC
BTSTC
[ Instruction Code/Number of Cycles ]
Page=159
dest
[ Operation ]
________
Z
dest
C
dest
dest
0
[ Function ]
• This instruction transfers inverted dest to the Z flag and non-inverted dest to the C flag. Then it
stores 0 in dest.
[ Selectable dest ]
bit,R0
bit,A0
base:8[A0]
base:16[A0]
C
dest
bit,R1
bit,R2
bit,R3
bit,A1
[A0]
[A1]
base:8[A1]
bit,base:8[SB] bit,base:8[FB]
base:16[A1] bit,base:16[SB] bit,base:16
bit,base:11[SB]
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
Z : The flag is set when dest is 0; otherwise cleared.
C : The flag is set when dest is 1; otherwise cleared.
[ Description Example ]
BTSTC
flag
BTSTC
4,Ram
BTSTC
16,Ram:16[SB]
BTSTC
[A0]
[ Related Instructions ]
BCLR,BSET,BNOT,BNTST,BTST,BTSTS
59
Chapter 3
Functions
3.2 Functions
Test bit & set
Bit TeST & Set
BTSTS
[ Syntax ]
BTSTS
BTSTS
[ Instruction Code/Number of Cycles ]
Page=160
dest
[ Operation ]
________
Z
dest
C
dest
dest
1
[ Function ]
• This instruction transfers inverted dest to the Z flag and non-inverted dest to the C flag. Then it stores
1 in dest.
[ Selectable dest ]
bit,R0
bit,A0
base:8[A0]
base:16[A0]
C
dest
bit,R1
bit,R2
bit,R3
bit,A1
[A0]
[A1]
base:8[A1]
bit,base:8[SB] bit,base:8[FB]
base:16[A1] bit,base:16[SB] bit,base:16
bit,base:11[SB]
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
Z : The flag is set when dest is 0; otherwise cleared.
C : The flag is set when dest is 1; otherwise cleared.
[ Description Example ]
BTSTS
BTSTS
BTSTS
BTSTS
flag
4,Ram
16,Ram:16[SB]
[A0]
[ Related Instructions ]
BCLR,BSET,BNOT,BNTST,BTST,BTSTC
60
Chapter 3
Functions
3.2 Functions
Exclusive OR bits
Bit eXclusive OR carry flag
BXOR
[ Syntax ]
BXOR src
BXOR
[ Instruction Code/Number of Cycles ]
Page=160
[ Operation ]
C
src
A
C
[ Function ]
• This instruction exclusive ORs the C flag and src together and stores the result in the C flag.
[ Selectable src ]
bit,R0
bit,A0
base:8[A0]
base:16[A0]
C
src
bit,R1
bit,R2
bit,R3
bit,A1
[A0]
[A1]
base:8[A1]
bit,base:8[SB] bit,base:8[FB]
base:16[A1] bit,base:16[SB] bit,base:16
bit,base:11[SB]
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
C : The flag is set when the operation resulted in 1; otherwise cleared.
[ Description Example ]
BXOR
BXOR
BXOR
BXOR
flag
4,Ram
16,Ram:16[SB]
[A0]
[ Related Instructions ]
BAND,BOR,BNAND,BNOR,BNXOR
61
Chapter 3
Functions
3.2 Functions
Compare
CoMPare
CMP
[ Syntax ]
CMP.size (:format) src,dest
CMP
[ Instruction Code/Number of Cycles ]
Page=161
G , Q , S (Can be specified)
B,W
[ Operation ]
dest – src
[ Function ]
• Each flag bit of the flag register varies depending on the result of subtraction of src from dest.
• If dest is an A0 or A1 when the size specifier (.size) you selected is (.B), src is zero-expanded to
perform operation in 16 bits. If src is an A0 or A1, operation is performed on the 8 low-order bits of A0
or A1.
(See the next page for src/dest classified by format.)
[ Selectable src/dest ]
src
R0L/R0
A0/A0*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1*1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
dest
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM
R0L/R0
A0/A0*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1*1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
SP/SP
*1 If you specify (.B) for the size specifier (.size), you cannot choose A0 or A1 for src and dest simultaneously.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
O : The flag is set when a signed operation resulted in exceeding +32767 (.W) or –32768 (.W), or
+127 (.B) or –128 (.B); otherwise cleared.
S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.
Z : The flag is set when the operation resulted in 0; otherwise cleared.
C : The flag is set when an unsigned operation resulted in any value equal to or greater than 0;
otherwise cleared.
[ Description Example ]
CMP.B:S
#10,R0L
CMP.W:G R0,A0
CMP.W
#–3,R0
CMP.B
#5,Ram:8[FB]
CMP.B
A0,R0L
; A0’s 8 low-order bits and R0L are compared.
62
Chapter 3
Functions
3.2 Functions
[src/dest Classified by Format]
G format
src
R0L/R0
A0/A0*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1*1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
dest
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM
R0L/R0
A0/A0*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1*1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
SP/SP
*1 If you specify (.B) for the size specifier (.size), you cannot choose A0 or A1 for src and dest simultaneously.
Q format
src
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
dest
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM*2
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
SP/SP
*2 The range of values that can be taken on is –8 < #IMM < +7.
S format*3
src
R0L
abs16
R0L*4
abs16
R0H
#IMM
R0H*4
#IMM
dsp:8[SB]
dsp:8[SB]
dest
dsp:8[FB] R0L
abs16
dsp:8[FB] R0L*4
abs16
*3 You can only specify (.B) for the size specifier (.size).
*4
You cannot choose the same register for src and dest.
63
R0H
A0
R0H*4
A0
dsp:8[SB]
A1
dsp:8[SB]
A1
dsp:8[FB]
dsp:8[FB]
Chapter 3
Functions
3.2 Functions
Decimal add with carry
Decimal ADdition with Carry
DADC
[ Syntax ]
DADC.size
DADC
[ Instruction Code/Number of Cycles ]
Page=165
src,dest
B,W
[ Operation ]
dest
src
+
dest
+
C
[ Function ]
• This instruction adds dest, src, and C flag together in decimal and stores the result in dest.
[ Selectable src/dest ]
src
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
dest
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM
S
C
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
[ Flag Change ]
Flag
U
I
O
B
Z
D
Change
Conditions
S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.
Z : The flag is set when the operation resulted in 0; otherwise cleared.
C : The flag is set when the operation resulted in exceeding +9999 (.W) or +99 (.B); otherwise
cleared.
[ Description Example ]
DADC.B
#3,R0L
DADC.W
R1,R0
[ Related Instructions ]
DADD,DSUB,DSBB
64
Chapter 3
Functions
3.2 Functions
Decimal add without carry
Decimal ADDition
DADD
[ Syntax ]
DADD.size
DADD
[ Instruction Code/Number of Cycles ]
Page=167
src,dest
B,W
[ Operation ]
dest
src
+
dest
[ Function ]
• This instruction adds dest and src together in decimal and stores the result in dest.
[ Selectable src/dest ]
src
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
dest
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM
S
C
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
[ Flag Change ]
Flag
U
I
O
B
Z
D
Change
Conditions
S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.
Z : The flag is set when the operation resulted in 0; otherwise cleared.
C : The flag is set when the operation resulted in exceeding +9999 (.W) or +99 (.B); otherwise
cleared.
[ Description Example ]
DADD.B
#3,R0L
DADD.W
R1,R0
[ Related Instructions ]
DADC,DSUB,DSBB
65
Chapter 3
Functions
3.2 Functions
Decrement
DECrement
DEC
[ Syntax ]
DEC.size
DEC
[ Instruction Code/Number of Cycles ]
Page=169
dest
B,W
[ Operation ]
dest
dest
–
1
[ Function ]
• This instruction decrements 1 from dest and stores the result in dest.
[ Selectable dest ]
*1
R0L
abs16*1
R0H
A0*2
*1
dest
dsp:8[SB]*1
A1*2
dsp:8[FB]*1
*1 You can only specify (.B) for the size specifier (.size).
*2 You can only specify (.W) for the size specifier (.size).
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.
Z : The flag is set when the operation resulted in 0; otherwise cleared.
[ Description Example ]
DEC.W
A0
DEC.B
R0L
[ Related Instructions ]
INC
66
Chapter 3
Functions
3.2 Functions
Signed divide
DIVide
DIV
[ Syntax ]
DIV.size
DIV
[ Instruction Code/Number of Cycles ]
Page=170
src
B,W
[ Operation ]
If the size specifier (.size) is (.B)
R0L (quotient), R0H (remainder) R0
If the size specifier (.size) is (.W)
R0 (quotient), R2 (remainder) R2R0
src
src
[ Function ]
• This instruction divides R2R0 (R0)*1 by signed src and stores the quotient in R0 (R0L)*1 and the remainder in R2 (R0H)*1. The remainder has the same sign as the dividend. Shown in ( )*1 are the
registers that are operated on when you selected (.B) for the size specifier (.size).
• If src is an A0 or A1 when the size specifier (.size) you selected is (.B), operation is performed on the
8 low-order bits of A0 or A1.
• If you specify (.B) for the size specifier (.size), the O flag is set when the operation resulted in the
quotient exceeding 8 bits or the divisor is 0. At this time, R0L and R0H are indeterminate.
• If you specify (.W) for the size specifier (.size), the O flag is set when the operation resulted in the
quotient exceeding 16 bits or the divisor is 0. At this time, R0 and R2 are indeterminate.
[ Selectable src ]
src
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM
S
C
[ Flag Change ]
Flag
U
I
O
B
Z
D
Change
Conditions
O : The flag is set when the operation resulted in the quotient exceeding 16 bits (.W) or 8 bits (.B) or
the divisor is 0; otherwise cleared.
[ Description Example ]
DIV.B
DIV.B
DIV.W
A0
#4
R0
[ Related Instructions ]
;A0’s 8 low-order bits is the divisor.
DIVU,DIVX,MUL,MULU
67
Chapter 3
Functions
3.2 Functions
Unsigned divide
DIVide Unsigned
DIVU
[ Syntax ]
DIVU.size
DIVU
[ Instruction Code/Number of Cycles ]
Page=171
src
B,W
[ Operation ]
If the size specifier (.size) is (.B)
R0L (quotient), R0H (remainder) R0
If the size specifier (.size) is (.W)
R0 (quotient), R2 (remainder) R2R0
src
src
[ Function ]
• This instruction divides R2R0 (R0)*1 by unsigned src and stores the quotient in R0 (R0L)*1 and the
remainder in R2 (R0H)*1. Shown in ( )*1 are the registers that are operated on when you selected (.B)
for the size specifier (.size).
• If src is an A0 or A1 when the size specifier (.size) you selected is (.B), operation is performed on the
8 low-order bits of A0 or A1.
• If you specify (.B) for the size specifier (.size), the O flag is set when the operation resulted in the
quotient exceeding 8 bits or the divisor is 0. At this time, R0L and R0H are indeterminate.
• If you specify (.W) for the size specifier (.size), the O flag is set when the operation resulted in the
quotient exceeding 16 bits or the divisor is 0. At this time, R0 and R2 are indeterminate.
[ Selectable src ]
src
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A0] dsp:20[A1]
R2R0
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM
S
C
[ Flag Change ]
Flag
U
I
O
B
Z
D
Change
Conditions
O : The flag is set when the operation resulted in the quotient exceeding 16 bits (.W) or 8 bits (.B) or
the divisor is 0; otherwise cleared.
[ Description Example ]
DIVU.B
DIVU.B
DIVU.W
A0
#4
R0
[ Related Instructions ]
;A0’s 8 low-order bits is the divisor.
DIV,DIVX,MUL,MULU
68
Chapter 3
Functions
3.2 Functions
Singed divide
DIVide eXtension
DIVX
[ Syntax ]
DIVX.size
DIVX
[ Instruction Code/Number of Cycles ]
Page=172
src
B,W
[ Operation ]
If the size specifier (.size) is (.B)
R0L (quotient), R0H (remainder) R0
If the size specifier (.size) is (.W)
R0 (quotient), R2 (remainder) R2R0
src
src
[ Function ]
• This instruction divides R2R0 (R0)*1 by signed src and stores the quotient in R0 (R0L)*1 and the remainder in R2
(R0H)*1. The remainder has the same sign as the divisor. Shown in ( )*1 are the registers that are operated on
when you selected (.B) for the size specifier (.size).
• If src is an A0 or A1 when the size specifier (.size) you selected is (.B), operation is performed on the
8 low-order bits of A0 or A1.
• If you specify (.B) for the size specifier (.size), the O flag is set when the operation resulted in the
quotient exceeding 8 bits or the divisor is 0. At this time, R0L and R0H are indeterminate.
• If you specify (.W) for the size specifier (.size), the O flag is set when the operation resulted in the
quotient exceeding 16 bits or the divisor is 0. At this time, R0 and R2 are indeterminate.
[ Selectable src ]
src
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A0] dsp:20[A1]
R2R0
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
R1H/R3
[A1]
dsp:8[FB]
abs16
abs20
A1A0
#IMM
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
O : The flag is set when the operation resulted in the quotient exceeding 16 bits (.W) or 8 bits (.B) or
the divisor is 0; otherwise cleared.
[ Description Example ]
DIVX.B
DIVX.B
DIVX.W
A0
#4
R0
[ Related Instructions ]
;A0’s 8 low-order bits is the divisor.
DIV,DIVU,MUL,MULU
69
Chapter 3
Functions
3.2 Functions
Decimal subtract with borrow
Decimal SuBtract with Borrow
DSBB
[ Syntax ]
DSBB.size
DSBB
[ Instruction Code/Number of Cycles ]
Page=173
src,dest
B,W
[ Operation ]
dest
dest
____
–
src
–
C
[ Function ]
• This instruction subtracts src and inverted C flag from dest in decimal and stores the result in dest.
[ Selectable src/dest ]
src
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
dest
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM
S
C
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
[ Flag Change ]
Flag
U
I
O
B
Z
D
Change
Conditions
S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.
Z : The flag is set when the operation resulted in 0; otherwise cleared.
C : The flag is set when the operation resulted in any value equal to or greater than 0; otherwise
cleared.
[ Description Example ]
DSBB.B
DSBB.W
#3,R0L
R1,R0
[ Related Instructions ]
DADC,DADD,DSUB
70
Chapter 3
Functions
3.2 Functions
Decimal subtract without borrow
Decimal SUBtract
DSUB
[ Syntax ]
DSUB.size
DSUB
[ Instruction Code/Number of Cycles ]
Page=175
src,dest
B,W
[ Operation ]
dest
dest
–
src
[ Function ]
• This instruction subtracts src from dest in decimal and stores the result in dest.
[ Selectable src/dest ]
src
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
dest
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM
S
C
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
[ Flag Change ]
Flag
U
I
O
B
Z
D
Change
Conditions
S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.
Z : The flag is set when the operation resulted in 0; otherwise cleared.
C : The flag is set when the operation resulted in any value equal to or greater than 0; otherwise
cleared.
[ Description Example ]
DSUB.B
DSUB.W
#3,R0L
R1,R0
[ Related Instructions ]
DADC,DADD,DSBB
71
Chapter 3
Functions
3.2 Functions
Build stack frame
ENTER function
ENTER
[ Syntax ]
ENTER
[ Instruction Code/Number of Cycles ]
Page=177
src
[ Operation ]
SP
M(SP)
FB
SP
ENTER
SP
FB
SP
SP
–
2
–
src
[ Function ]
• This instruction generates a stack frame. src represents the size of the stack frame.
• The diagrams below show the stack area status before and after the ENTER instruction is executed at
the beginning of a called subroutine.
Before instruction execution
After instruction execution
SP
Auto variable area
Direction in
which address
increases
SP
FB
FB (H)
Return address (L)
Return address (M)
Return address (L)
Return address (M)
Return address (H)
Return address (H)
Argument of function
Argument of function
[ Selectable src ]
src
#IMM8
[ Flag Change ]
Flag
U
FB (L)
I
O
B
S
Z
D
C
Change
[ Description Example ]
ENTER
#3
[ Related Instructions ]
EXITD
72
Number of bytes
indicated by src
Chapter 3
Functions
3.2 Functions
Deallocate stack frame
EXITD
EXIT and Deallocate stack frame
EXITD
[ Instruction Code/Number of Cycles ]
Page=178
[ Syntax ]
EXITD
[ Operation ]
SP
FB
SP
PCML
SP
PCH
SP
FB
M(SP)
SP +
M(SP)
SP +
M(SP)
SP +
2
2
1
[ Function ]
• This instruction deallocates the stack frame and exits from the subroutine.
• Use this instruction in combination with the ENTER instruction.
• The diagrams below show the stack area status before and after the EXITD instruction is executed
at the end of a subroutine in which an ENTER instruction was executed.
Before instruction execution
After instruction execution
SP
Auto variable area
Direction in which
address increases
FB (L)
FB (H)
FB
Return address (L)
Return address (M)
Return address (H)
SP
Argument of function
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
[ Description Example ]
EXITD
[ Related Instructions ]
ENTER
73
Argument of function
Chapter 3
Functions
3.2 Functions
Extend sign
EXTend Sign
EXTS
[ Syntax ]
EXTS.size
EXTS
[ Instruction Code/Number of Cycles ]
Page=178
dest
B,W
[ Operation ]
dest
EXT(dest)
[ Function ]
• This instruction sign extends dest and stores the result in dest.
• If you selected (.B) for the size specifier (.size), dest is sign extended to 16 bits.
• If you selected (.W) for the size specifier (.size), R0 is sign extended to 32 bits. In this case, R2 is used
for the upper bytes.
[ Selectable dest ]
dest
R0L/R0
R0H/R1
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
S : If you selected (.B) for the size specifier (.size), the flag is set when the operation resulted in MSB
= 1; otherwise cleared. The flag does not change if you selected (.W) for the size specifier (.size).
Z : If you selected (.B) for the size specifier (.size), the flag is set when the operation resulted in 0;
otherwise cleared. The flag does not change if you selected (.W) for the size specifier (.size).
[ Description Example ]
EXTS.B
EXTS.W
R0L
R0
74
Chapter 3
Functions
3.2 Functions
Clear flag register bit
Flag register CLeaR
FCLR
[ Syntax ]
FCLR dest
FCLR
[ Instruction Code/Number of Cycles ]
Page=179
[ Operation ]
dest
0
[ Function ]
• This instruction stores 0 in dest.
[ Selectable dest ]
C
D
Z
dest
S
B
[ Flag Change ]
Flag
U
Change *1
I
O
B
S
Z
D
C
*1
*1
*1
*1
*1
*1
*1
*1 The selected flag is cleared to 0.
[ Description Example ]
FCLR
FCLR
I
S
[ Related Instructions ]
FSET
75
O
I
U
Chapter 3
Functions
3.2 Functions
Set flag register bit
Flag register SET
FSET
[ Syntax ]
FSET dest
FSET
[ Instruction Code/Number of Cycles ]
Page=180
[ Operation ]
dest
1
[ Function ]
• This instruction stores 1 in dest.
[ Selectable dest ]
C
D
Z
S
dest
B
[ Flag Change ]
Flag
U
Change *1
I
O
B
S
Z
D
C
*1
*1
*1
*1
*1
*1
*1
*1 The selected flag is set (= 1).
[ Description Example ]
FSET
FSET
I
S
[ Related Instructions ]
FCLR
76
O
I
U
Chapter 3
Functions
3.2 Functions
Increment
INCrement
INC
[ Syntax ]
INC.size
INC
[ Instruction Code/Number of Cycles ]
Page=180
dest
B,W
[ Operation ]
dest
dest
+
1
[ Function ]
• This instruction adds 1 to dest and stores the result in dest.
[ Selectable dest ]
*1
R0L
abs16*1
*1
R0H
A0*2
dest
dsp:8[SB]*1
A1*2
dsp:8[FB]*1
*1 You can only specify (.B) for the size specifier (.size).
*2 You can only specify (.W) for the size specifier (.size).
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.
Z : The flag is set when the operation resulted in 0; otherwise cleared.
[ Description Example ]
INC.W
A0
INC.B
R0L
[ Related Instructions ]
DEC
77
Chapter 3
Functions
3.2 Functions
Interrupt by INT instruction
INTerrupt
INT
[ Syntax ]
INT
src
[ Operation ]
SP
M(SP)
SP
M(SP)
PC
SP – 2
(PC + 2)H, FLG
SP – 2
(PC + 2)ML
M(IntBase + src
INT
[ Instruction Code/Number of Cycles ]
Page=181
4)
[ Function ]
• This instruction generates a software interrupt specified by src. src represents a software interrupt
number.
• If src is 31 or smaller, the U flag is cleared to 0 and the interrupt stack pointer (ISP) is used.
• If src is 32 or larger, the stack pointer indicated by the U flag is used.
• The interrupts generated by the INT instruction are nonmaskable interrupts.
[ Selectable src ]
src
#IMM*1*2
*1 #IMM denotes a software interrupt number.
*2 The range of values that can be taken on is 0 < #IMM < 63.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
Change
C
*3 The flags are saved to the stack area before the INT instruction is executed. After the interrupt, the flags
change state as shown on the left.
Conditions
U : The flag is cleared if the software interrupt number is 31 or smaller. The flag does not change if
the software interrupt number is 32 or larger.
I : The flag is cleared.
D : The flag is cleared.
[ Description Example ]
INT
#0
[ Related Instructions ]
BRK,INTO
78
Chapter 3
Functions
3.2 Functions
Interrupt on overflow
INTerrupt on Overflow
INTO
[ Syntax ]
INTO
INTO
[ Instruction Code/Number of Cycles ]
Page=182
[ Operation ]
SP
M(SP)
SP
M(SP)
PC
SP – 2
(PC + 1)H, FLG
SP – 2
(PC + 1)ML
M(FFFE016)
[ Function ]
• If the O flag is 1, this instruction generates an overflow interrupt. If the flag is 0, the next instruction is
executed.
• The overflow interrupt is a nonmaskable interrupt.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
Change
Conditions
U : The flag is cleared.
I : The flag is cleared.
D : The flag is cleared.
C *1 The flags are saved to the stack area before the INTO
instruction is executed. After the interrupt, the flags
change state as shown on the left.
[ Description Example ]
INTO
[ Related Instructions ]
BRK,INT
79
Chapter 3
Functions
3.2 Functions
Jump on condition
Jump on Condition
JCnd
[ Syntax ]
JCnd label
JCnd
[ Instruction Code/Number of Cycles ]
Page=182
[ Operation ]
if true then jump label
[ Function ]
• This instruction causes program flow to branch off after checking the execution result of the preceding
instruction against the following condition. If the condition indicated by Cnd is true, control jumps to
label. If false, the next instruction is executed.
• The following conditions can be used for Cnd:
Cnd
Condition
Cnd
Expression
GEU/C C=1
EQ/Z
GTU
PZ
GE
GT
O
Equal to or greater than
C flag is 1.
Z=1
Equal to
Z flag is 1.
____
C Z=1
Greater than
S=0
Positive or zero
A
S O=0
Equal to or greater than
(signed value)
A
(S O) Z=0 Greater than (signed value)
O=1
O flag is 1.
Condition
LTU/NC C=0
=
NE/NZ
LEU
N
LE
0
LT
NO
Smaller than
C flag is 0.
Z=0
Not equal
Z flag is 0.
____
C Z=0
Equal to or smaller than
S=1
Negative
A
(S O) Z=1 Equal to or smaller than
(signed value)
A
S O=1
Smaller than (signed value)
O=0
O flag is 0.
[ Selectable label ]
Cnd
label
*1
PC –127
PC*1–126
label
label
*1
PC +128
PC*1+129
GEU/C,GTU,EQ/Z,N,LTU/NC,LEU,NE/NZ,PZ
LE,O,GE,GT,NO,LT
*1 PC indicates the start address of the instruction.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
[ Description Example ]
JEQ
label
JNE
label
[ Related Instructions ]
Expression
BMCnd
80
≠
0
Chapter 3
Functions
3.2 Functions
Unconditional jump
JuMP
JMP
[ Syntax ]
JMP(.length) label
[ Instruction Code/Number of Cycles ]
Page=184
S , B , W , A (Can be specified)
[ Operation ]
PC
label
[ Function ]
• This instruction causes control to jump to label.
[ Selectable label ]
.length
.S
.B
.W
.A
label
*1
PC +2
label
PC*1+9
PC*1–127
label
PC*1+128
*1
PC –32767
label
PC*1+32768
abs20
*1 The PC indicates the start address of the instruction.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
[ Description Example ]
JMP
JMP
label
[ Related Instructions ]
JMPI
81
Chapter 3
Functions
3.2 Functions
Jump indirect
JuMP Indirect
JMPI
[ Syntax ]
JMPI.length
JMPI
[ Instruction Code/Number of Cycles ]
Page=185
src
W,A
[ Operation ]
When jump distance specifier (.length) is (.W)
PC
PC
src
When jump distance specifier (.length) is (.A)
PC
src
[ Function ]
• This instruction causes control to jump to the address indicated by src. If src is memory, specify the
address at which the low-order address is stored.
• If you selected (.W) for the jump distance specifier (.length), control jumps to the start address of the instruction
plus the address indicated by src (added including the sign bits). If src is memory, the required memory
capacity is 2 bytes.
• If src is memory when you selected (.A) for the jump distance specifier (.length), the required memory
capacity is 3 bytes.
[ Selectable src ]
If you selected (.W) for the jump distance specifier (.length)
src
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
If you selected (.A) for the jump distance specifier (.length)
src
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
S
C
[ Flag Change ]
Flag
U
I
O
B
Z
D
Change
[ Description Example ]
JMPI.A
JMPI.W
A1A0
R0
[ Related Instructions ]
JMP
82
Chapter 3
Functions
3.2 Functions
Subroutine call
Jump SubRoutine
JSR
[ Instruction Code/Number of Cycles ]
Page=187
W , A (Can be specified)
[ Syntax ]
JSR(.length) label
[ Operation ]
SP
SP – 1
M(SP)
(PC + n)H
SP
SP – 2
M(SP)
(PC + n)ML
PC
label
*1 n denotes the number of instruction bytes.
[ Function ]
• This instruction causes control to jump to a subroutine indicated by label.
[ Selectable label ]
.length
.W
.A
label
*1
PC –32767
abs20
PC*1+32768
label
*1 The PC indicates the start address of the instruction.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
[ Description Example ]
JSR.W
JSR.A
JSR
func
func
[ Related Instructions ]
JSRI
83
Chapter 3
Functions
3.2 Functions
Indirect subroutine call
Jump SubRoutine Indirect
JSRI
[ Syntax ]
JSRI.length src
JSRI
[ Instruction Code/Number of Cycles ]
Page=188
W,A
[ Operation ]
When jump distance specifier (.length) is (.W)
SP
SP – 1
M(SP)
(PC + n)H
SP
SP – 2
M(SP)
(PC + n)ML
PC
PC
src
*1 n denotes the number of instruction bytes.
When jump distance specifier (.length) is (.A)
SP
SP – 1
M(SP)
(PC + n)H
SP
SP – 2
M(SP)
(PC + n)H
PC
src
[ Function ]
• This instruction causes control to jump to a subroutine at the address indicated by src. If src is
memory, specify the address at which the low-order address is stored.
• If you selected (.W) for the jump distance specifier (.length), control jumps to a subroutine at the start
address of the instruction plus the address indicated by src (added including the sign bits). If src is
memory, the required memory capacity is 2 bytes.
• If src is memory when you selected (.A) for the jump distance specifier (.length), the required memory
capacity is 3 bytes.
[ Selectable src ]
If you selected (.W) for the jump distance specifier (.length)
src
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
If you selected (.A) for the jump distance specifier (.length)
src
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
S
C
[ Flag Change ]
Flag
U
I
O
B
Z
D
Change
[ Description Example ]
JSRI.A
JSRI.W
A1A0
R0
[ Related Instructions ]
JSR
84
Chapter 3
Functions
3.2 Functions
Transfer to control register
LoaD Control register
LDC
[ Syntax ]
LDC src,dest
LDC
[ Instruction Code/Number of Cycles ]
Page=189
[ Operation ]
dest
src
[ Function ]
• This instruction transfers src to the control register indicated by dest. If src is memory, the required
memory capacity is 2 bytes.
• If the destination is INTBL or INTBH, make sure that bytes are transferred in succession.
• No interrupt requests are accepted immediately after this instruction.
[ Selectable src/dest ]
src
R0L/R0
R0H/R1
A0/A0
A1/A1
dsp:8[A0] dsp:8[A1]
dsp:16[A0] dsp:16[A1]
dsp:20[A0] dsp:20[A1]
R2R0
R3R1
dest
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
FB
[A1]
FLG
dsp:8[FB]
abs16
#IMM
SB
INTBH
SP*1
INTBL
ISP
*1 Operation is performed on the stack pointer indicated by the U flag.
[ Flag Change ]
Flag
U
Change *2
I
O
B
S
Z
D
C
*2
*2
*2
*2
*2
*2
*2
*2 The flag changes only when dest is FLG.
[ Description Example ]
LDC
LDC
R0,SB
A0,FB
[ Related Instructions ]
POPC,PUSHC,STC,LDINTB
85
Chapter 3
Functions
3.2 Functions
Restore context
LoaD ConTeXt
LDCTX
[ Syntax ]
LDCTX
LDCTX
[ Instruction Code/Number of Cycles ]
Page=189
abs16,abs20
[ Function ]
• This instruction restores task context from the stack area.
• Set the RAM address that contains the task number in abs16 and the start address of table data in abs20.
• The required register information is specified from table data by the task number and the data in the stack area
is transferred to each register according to the specified register information. Then the SP correction value is
added to the stack pointer (SP). For this SP correction value, set the number of bytes you want to the transferred.
• Information on transferred registers is configured as shown below. Logic 1 indicates a register to be
transferred and logic 0 indicates a register that is not transferred.
LSB
MSB
FB SB A1 A0 R3 R2 R1 R0
Transferred sequentially
beginning with R0
• The table data is comprised as shown below.The address indicated by abs20 is the base address of
the table. The data stored at an address apart from the base address as much as twice the content of
abs16 indicates register information, and the next address contains the stack pointer correction value.
Base address
of table
abs20
Register information for the task whose task number = 0.
SP correction value for the task whose task number = 0.
Register information for the task whose task number = 1.
SP correction value for the task whose task number = 1.
Direction in
which address
increases
(See the above diagram.)
(See the above diagram.)
(See the above diagram.)
(See the above diagram.)
Register information for the task whose task number = n*1. (See the above diagram.)
SP correction value for the task whose task number = n*1. (See the above diagram.)
*1
n=0 to 255
Z
D
[ Flag Change ]
Flag
U
I
O
B
S
C
Change
[ Description Example ]
LDCTX
Ram,Rom_TBL
[ Related Instructions ]
STCTX
86
abs16 2
Chapter 3
Functions
3.2 Functions
Transfer from extended data area
LoaD from EXtra far data area
LDE
[ Syntax ]
LDE.size
LDE
[ Instruction Code/Number of Cycles ]
Page=191
src,dest
B,W
[ Operation ]
dest
src
[ Function ]
• This instruction transfers src from extended area to dest.
• If dest is an A0 or A1 when the size specifier (.size) you selected is (.B), src is zero-expanded to
transfer data in 16 bits.
[ Selectable src/dest ]
src
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
dest
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM
[A1A0]
S
C
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
[ Flag Change ]
Flag
U
I
O
B
Z
D
Change
Conditions
S : The flag is set when the transfer resulted in MSB of dest = 1; otherwise cleared.
Z : The flag is set when the transfer resulted in dest = 0; otherwise cleared.
[ Description Example ]
LDE.W
LDE.B
[A1A0],R0
Rom_TBL,A0
[ Related Instructions ]
STE,MOV,XCHG
87
R1H/R3
[A1]
dsp:8[FB]
abs16
Chapter 3
Functions
3.2 Functions
Transfer to INTB register
LoaD INTB register
LDINTB
[ Syntax ]
LDINTB
src
[ Operation ]
INTBHL
src
[ Instruction Code/Number of Cycles ]
Page=192
[ Function ]
• This instruction transfers src to INTB.
• The LDINTB instruction is a macro-instruction consisting of the following:
LDC
LDC
#IMM, INTBH
#IMM, INTBL
[ Selectable src ]
src
#IMM20
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
[ Description Example ]
LDINTB
LDINTB
#0F0000H
[ Related Instructions ]
LDC,STC,PUSHC,POPC
88
Chapter 3
Functions
3.2 Functions
Set interrupt enable level
LoaD Interrupt Permission Level
LDIPL
[ Syntax ]
LDIPL src
[ Instruction Code/Number of Cycles ]
Page=193
[ Operation ]
IPL
src
[ Function ]
• This instruction transfers src to IPL.
[ Selectable src ]
src
*1
#IMM
*1
The range of values that can be taken on is 0 < #IMM < 7
[ Flag Change ]
Flag
U
LDIPL
I
O
B
S
Z
D
C
Change
[ Description Example ]
LDIPL
#2
89
Chapter 3 Functions
3.2 Functions
Transfer
MOVe
MOV
[ Syntax ]
MOV.size (:format) src,dest
MOV
[ Instruction Code/Number of Cycles ]
Page=193
G , Q , Z , S (Can be specified)
B,W
[ Operation ]
dest
src
[ Function ]
• This instruction transfers src to dest.
• If dest is an A0 or A1 when the size specifier (.size) you selected is (.B), src is zero-expanded to
transfer data in 16 bits. If src is an A0 or A1, data is transferred from the 8 low-order bits of A0 or A1.
(See the next page for src/dest classified by format.)
[ Selectable src/dest ]
R0L/R0
A0/A0*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
src
R0H/R1
R1L/R2
*1
A1/A1
[A0]
dsp:8[A1]
dsp:8[SB]
dsp:16[A1] dsp:16[SB]
dsp:20[A1] abs20
R3R1
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM*2
dsp:8[SP]*3
R0L/R0
A0/A0*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
dest
R0H/R1
R1L/R2
*1
A1/A1
[A0]
dsp:8[A1] dsp:8[SB]
dsp:16[A1] dsp:16[SB]
dsp:20[A1] abs20
R3R1
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
dsp:8[SP]*2 *3
*1 If you specify (.B) for the size specifier (.size), you cannot choose A0 or A1 for src and dest simultaneously.
*2 If src is #IMM, you cannot choose dsp:8 [SP] for dest.
*3 Operation is performed on the stack pointer indicated by the U flag. You cannot choose dsp:8 [SP] for
src and dest simultaneously.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
S : The flag is set when the transfer resulted in MSB of dest = 1; otherwise cleared.
Z : The flag is set when the transfer resulted in 0; otherwise cleared.
[ Description Example ]
MOV.B:S
MOV.W
#0ABH,R0L
#–1,R2
[ Related Instructions ]
LDE,STE,XCHG
90
Chapter 3 Functions
3.2 Functions
[src/dest Classified by Format]
G format
R0L/R0
A0/A0*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
src
R0H/R1
R1L/R2
*1
A1/A1
[A0]
dsp:8[A1]
dsp:8[SB]
dsp:16[A1] dsp:16[SB]
dsp:20[A1] abs20
R3R1
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM*2
dsp:8[SP]*3
R0L/R0
A0/A0*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
dest
R0H/R1
R1L/R2
*1
A1/A1
[A0]
dsp:8[A1] dsp:8[SB]
dsp:16[A1] dsp:16[SB]
dsp:20[A1] abs20
R3R1
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
SP/SP
dsp:8[SP]*2*3
*1 If you specify (.B) for the size specifier (.size), you cannot choose A0 or A1 for src and dest simultaneously.
*2 If src is #IMM, you cannot choose dsp:8 [SP] for dest.
*3 Operation is performed on the stack pointer indicated by the U flag. You cannot choose dsp:8 [SP] for
src and dest simultaneously.
Q format
src
R0L/R0
R0H/R1
R1L/R2
A0/A0
A1/A1
[A0]
dsp:8[A0] dsp:8[A1]
dsp:8[SB]
dsp:16[A0] dsp:16[A1] dsp:16[SB]
dsp:20[A0] dsp:20[A1] abs20
R2R0
R3R1
A1A0
dest
R1H/R3
R0L/R0
R0H/R1
R1L/R2
[A1]
A0/A0
A1/A1
[A0]
dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB]
abs16
dsp:16[A0] dsp:16[A1] dsp:16[SB]
*4
#IMM
dsp:20[A0] dsp:20[A1] abs20
R2R0
R3R1
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
SP/SP
*4 The range of values that can be taken on is –8 < #IMM < +7.
S format
R0L*5*6*7
abs16*5
R0L*5*6
abs16
R0L
abs16
*5
*6
*7
*8
*9
R0H*5*6*8
#IMM
R0H*5*6
#IMM
R0H
#IMM*9
src
dsp:8[SB]*5 dsp:8[FB]*5 R0L*5*6
abs16
dsp:8[SB]
dsp:8[FB] R0L*5*6
abs16*5
dsp:8[SB]
dsp:8[FB] R0L*5
abs16*5
R0H*5*6
A0*5*8
R0H*5*6
A0
R0H*5
A0*9
dest
dsp:8[SB] dsp:8[FB]
A1*5*7
dsp:8[SB]*5 dsp:8[FB]*5
A1
dsp:8[SB]*5 dsp:8[FB]*5
A1*9
You can only specify (.B) for the size specifier (.size).
You cannot choose the same register for src and dest.
If src is R0L, you can only choose A1 for dest as the address register.
If src is R0H, you can only choose A0 for dest as the address register.
You can specify (.B) and (.W) for the size specifier (.size).
Z format
R0L
abs16
R0H
#0
src
dsp:8[SB]
dsp:8[FB] R0L
abs16
91
R0H
A0
dest
dsp:8[SB]
A1
dsp:8[FB]
Chapter 3 Functions
3.2 Functions
Transfer effective address
MOVe effective Address
MOVA
[ Syntax ]
MOVA
MOVA
[ Instruction Code/Number of Cycles ]
Page=200
src,dest
[ Operation ]
dest
EVA(src)
[ Function ]
• This instruction transfers the affective address of src to dest.
[ Selectable src/dest ]
src
R0L/R0
R0H/R1
R1L/R2
A0/A0
A1/A1
[A0]
dsp:8[A0] dsp:8[A1]
dsp:8[SB]
dsp:16[A0] dsp:16[A1] dsp:16[SB]
dsp:20[A0] dsp:20[A1] abs20
R2R0
R3R1
A1A0
dest
R1H/R3
R0L/R0
R0H/R1
R1L/R2
[A1]
A0/A0
A1/A1
[A0]
dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB]
abs16
dsp:16[A0] dsp:16[A1] dsp:16[SB]
#IMM
dsp:20[A0] dsp:20[A1] abs20
R2R0
R3R1
A1A0
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
[ Description Example ]
MOVA
Ram:16[SB],A0
[ Related Instructions ]
PUSHA
92
R1H/R3
[A1]
dsp:8[FB]
abs16
Chapter 3 Functions
3.2 Functions
Transfer 4-bit data
MOVe nibble
MOVDir
[ Syntax ]
MOVDir
MOVDir
[ Instruction Code/Number of Cycles ]
Page=201
src,dest
[ Operation ]
Dir
HH
HL
LH
LL
Operation
H4:dest
H4:src
L4:dest
H4:src
H4:dest
L4:src
L4:dest
L4:src
[ Function ]
• Be sure to choose R0L for either src or dest.
Dir
Function
HH
Transfers src’s 4 high-order bits to dest’s 4 high-order bits.
HL
Transfers src’s 4 high-order bits to dest’s 4 low-order bits.
LH
Transfers src’s 4 low-order bits to dest’s 4 high-order bits.
LL
Transfers src’s 4 low-order bits to dest’s 4 low-order bits.
[ Selectable src/dest ]
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
src
R0H/R1
R1L/R2
A1/A1
[A0]
dsp:8[A1]
dsp:8[SB]
dsp:16[A1] dsp:16[SB]
dsp:20[A1] abs20
R3R1
A1A0
R0H/R1
R1L/R2
A1/A1
[A0]
dsp:8[A1]
dsp:8[SB]
dsp:16[A1] dsp:16[SB]
dsp:20[A1] abs20
R3R1
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R1H/R3
R0L/R0
[A1]
A0/A0
dsp:8[FB] dsp:8[A0]
abs16
dsp:16[A0]
#IMM
dsp:20[A0]
R2R0
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
[ Description Example ]
MOVHH
R0L,[A0]
MOVHL
R0L,[A0]
93
dest
R0H/R1
R1L/R2
A1/A1
[A0]
dsp:8[A1] dsp:8[SB]
dsp:16[A1] dsp:16[SB]
dsp:20[A1] abs20
R3R1
A1A0
R0H/R1
R1L/R2
A1/A1
[A0]
dsp:8[A1] dsp:8[SB]
dsp:16[A1] dsp:16[SB]
dsp:20[A1] abs20
R3R1
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
R1H/R3
[A1]
dsp:8[FB]
abs16
Chapter 3 Functions
3.2 Functions
Signed multiply
MULtiple
MUL
[ Syntax ]
MUL.size
MUL
[ Instruction Code/Number of Cycles ]
Page=203
src,dest
B,W
[ Operation ]
dest
dest
src
[ Function ]
• This instruction multiplies src and dest together including the sign bits and stores the result in dest.
• If you selected (.B) for the size specifier (.size), src and dest both are operated on in 8 bits and the
result is stored in 16 bits. If you specified an A0 or A1 for either src or dest, operation is performed on
the 8 low-order bits of A0 or A1.
• If you selected (.W) for the size specifier (.size), src and dest both are operated on in 16 bits and the
result is stored in 32 bits. If you specified R0, R1, or A0 for dest, the result is stored in R2R0, R3R1, or
A1A0 accordingly.
[ Selectable src/dest ]
src
R0L/R0
R0H/R1
R1L/R2
*1
*1
A0/A0
A1/A1
[A0]
dsp:8[A0] dsp:8[A1]
dsp:8[SB]
dsp:16[A0] dsp:16[A1] dsp:16[SB]
dsp:20[A0] dsp:20[A1] abs20
R2R0
R3R1
A1A0
dest
R1H/R3
R0L/R0
R0H/R1
R1L/R2
*1
[A1]
A0/A0
A1/A1
[A0]
dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB]
abs16
dsp:16[A0] dsp:16[A1] dsp:16[SB]
#IMM
dsp:20[A0] dsp:20[A1] abs20
R2R0
R3R1
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
*1 If you specify (.B) for the size specifier (.size), you cannot choose A0 or A1 for src and dest simultaneously.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
[ Description Example ]
MUL.B
A0,R0L
MUL.W
#3,R0
MUL.B
R0L,R1L
MUL.W
A0,Ram
[ Related Instructions ]
; R0L and A0’s 8 low-order bits are multiplied.
DIV,DIVU,DIVX,MULU
94
Chapter 3 Functions
3.2 Functions
Unsigned multiply
MULtiple Unsigned
MULU
[ Syntax ]
MULU.size
MULU
[ Instruction Code/Number of Cycles ]
Page=205
src,dest
B,W
[ Operation ]
dest
dest
src
[ Function ]
• This instruction multiplies src and dest together not including the sign bits and stores the result in dest.
• If you selected (.B) for the size specifier (.size), src and dest both are operated on in 8 bits and the
result is stored in 16 bits. If you specified an A0 or A1 for either src or dest, operation is performed on
the 8 low-order bits of A0 or A1.
• If you selected (.W) for the size specifier (.size), src and dest both are operated on in 16 bits and the
result is stored in 32 bits. If you specified R0, R1, or A0 for dest, the result is stored in R2R0, R3R1, or
A1A0 accordingly.
[ Selectable src/dest ]
src
R0L/R0
R0H/R1
R1L/R2
R1H/R3
*1
*1
A0/A0
A1/A1
[A0]
[A1]
dsp:8[A0] dsp:8[A1]
dsp:8[SB]
dsp:8[FB]
dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16
dsp:20[A0] dsp:20[A1] abs20
#IMM
R2R0
R3R1
A1A0
*1 If you specify (.B) for the size specifier (.size),
neously.
R0L/R0
A0/A0*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
you cannot
dest
R0H/R1
R1L/R2
R1H/R3
A1/A1
[A0]
[A1]
dsp:8[A1] dsp:8[SB] dsp:8[FB]
dsp:16[A1] dsp:16[SB] abs16
dsp:20[A1] abs20
R3R1
A1A0
choose A0 or A1 for src and dest simulta-
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
[ Description Example ]
MULU.B
A0,R0L
MULU.W
MULU.B
MULU.W
#3,R0
R0L,R1L
A0,Ram
[ Related Instructions ]
; R0L and A0’s 8 low-order bits are multiplied.
DIV,DIVU,DIVX,MUL
95
Chapter 3 Functions
3.2 Functions
Two’s complement
NEGate
NEG
[ Syntax ]
NEG.size
NEG
[ Instruction Code/Number of Cycles ]
Page=207
dest
B,W
[ Operation ]
dest
0
–
dest
[ Function ]
• This instruction takes the 2’s complement of dest and stores the result in dest.
[ Selectable dest ]
dest
R0L/R0
R0H/R1
R1L/R2
A0/A0
A1/A1
[A0]
dsp:8[A0] dsp:8[A1]
dsp:8[SB]
dsp:16[A0] dsp:16[A1] dsp:16[SB]
dsp:20[A0] dsp:20[A1] abs20
R2R0
R3R1
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
O : The flag is set when dest before the operation is –128 (.B) or –32768 (.W); otherwise cleared.
S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.
Z : The flag is set when the operation resulted in 0; otherwise cleared.
C : The flag is set when the operation resulted in 0; otherwise cleared.
[ Description Example ]
NEG.B
NEG.W
R0L
A1
[ Related Instructions ]
NOT
96
Chapter 3 Functions
3.2 Functions
No operation
No OPeration
NOP
[ Syntax ]
NOP
[ Instruction Code/Number of Cycles ]
Page=207
[ Operation ]
PC
PC
+
1
[ Function ]
• This instruction adds 1 to PC.
[ Flag Change ]
Flag
U
NOP
I
O
B
S
Z
D
C
Change
[ Description Example ]
NOP
97
Chapter 3 Functions
3.2 Functions
Invert all bits
NOT
NOT
[ Syntax ]
NOT.size (:format) dest
NOT
[ Instruction Code/Number of Cycles ]
Page=208
G , S (Can be specified)
B,W
[ Operation ]
________
dest
dest
[ Function ]
• This instruction inverts dest and stores the result in dest.
[ Selectable dest ]
dest
R0L /R0
R0H /R1
R1L/R2
A0/A0
A1/A1
[A0]
dsp:8[A0] dsp:8[A1]
dsp:8[SB]*1
dsp:16[A0] dsp:16[A1] dsp:16[SB]
dsp:20[A0] dsp:20[A1] abs20
R2R0
R3R1
A1A0
*1
*1
R1H/R3
[A1]
dsp:8[FB]*1
abs16*1
*1 Can be selected in G and S formats.
In other cases, dest can be selected in G format.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.
Z : The flag is set when the operation resulted in 0; otherwise cleared.
[ Description Example ]
NOT.B
NOT.W
R0L
A1
[ Related Instructions ]
NEG
98
Chapter 3 Functions
3.2
Functions
Logically OR
OR
OR
[ Syntax ]
OR.size (:format)
src,dest
[ Operation ]
dest
src
dest
OR
[ Instruction Code/Number of Cycles ]
Page=209
G , S (Can be specified)
B,W
[ Function ]
• This instruction logically ORs dest and src together and stores the result in dest.
• If dest is an A0 or A1 when the size specifier (.size) you selected is (.B), src is zero-expanded to
perform operation in 16 bits. If src is an A0 or A1, operation is performed on the 8 low-order bits of A0
or A1.
(See the next page for src/dest classified by format.)
[ Selectable src/dest ]
src
R0L/R0
A0/A0*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1*1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
dest
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM
R0L/R0
A0/A0*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1*1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
SP/SP
*1 If you specify (.B) for the size specifier (.size), you cannot choose A0 or A1 for src and dest simultaneously.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.
Z : The flag is set when the operation resulted in 0; otherwise cleared.
[ Description Example ]
OR.B
Ram:8[SB],R0L
OR.B:G
A0,R0L
OR.B:G
R0L,A0
OR.B:S
#3,R0L
[ Related Instructions ]
; A0’s 8 low-order bits and R0L are ORed.
; R0L is zero-expanded and ORed with A0.
AND,XOR,TST
99
Chapter 3
Functions
3.2
Functions
[src/dest Classified by Format]
G format
src
R0L/R0
A0/A0*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1*1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
dest
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM
R0L/R0
A0/A0*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1*1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
SP/SP
*1 If you specify (.B) for the size specifier (.size), you cannot choose A0 or A1 for src and dest simultaneously.
S format*2
src
R0L
abs16
R0L*3
abs16
R0H
#IMM
R0H*3
#IMM
dsp:8[SB]
dsp:8[SB]
dest
dsp:8[FB] R0L
abs16
dsp:8[FB] R0L*3
abs16
*2 You can only specify (.B) for the size specifier (.size).
*3 You cannot choose the same register for src and dest.
100
R0H
A0
R0H*3
A0
dsp:8[SB]
A1
dsp:8[SB]
A1
dsp:8[FB]
dsp:8[FB]
Chapter 3 Functions
3.2
Restore register/memory
POP
POP
Functions
POP
[ Instruction Code/Number of Cycles ]
Page=211
G , S (Can be specified)
B,W
[ Syntax ]
POP.size (:format) dest
[ Operation ]
If the size specifier (.size) is (.W)
dest
M(SP)
SP
SP + 2
If the size specifier (.size) is (.B)
dest
M(SP)
SP
SP + 1
[ Function ]
• This instruction restores dest from the stack area.
[ Selectable dest ]
dest
R0L*1/R0
R0H*1/R1
A0/A0
A1/A1*1
dsp:8[A0] dsp:8[A1]
dsp:16[A0] dsp:16[A1]
dsp:20[A0] dsp:20[A1]
R2R0
R3R1
*1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
*1 Can be selected in G and S formats.
In other cases, dest can be selected in G format.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
[ Description Example ]
POP.B
POP.W
R0L
A0
[ Related Instructions ]
PUSH,POPM,PUSHM
101
Chapter 3
Functions
3.2
Restore control register
POP Control register
POPC
[ Syntax ]
POPC
dest
[ Operation ]
dest
SP*1
M(SP)
SP +
Functions
POPC
[ Instruction Code/Number of Cycles ]
Page=213
2
*1 When dest is SP or when the U flag = “0” and dest is ISP, the value 2 is not added to SP.
[ Function ]
• This instruction restores from the stack area to the control register indicated by dest.
• When restoring the interrupt table register, always be sure to restore INTBH and INTBL in succession.
• No interrupt requests are accepted immediately after this instruction.
[ Selectable dest ]
FB
SB
*2
SP
dest
ISP FLG INTBH INTBL
*2 Operation is performed on the stack pointer indicated by the U flag.
[ Flag Change ]
Flag
U
Change *3
I
O
B
S
Z
D
C
*3
*3
*3
*3
*3
*3
*3
*3 The flag changes only when dest is FLG.
[ Description Example ]
POPC
SB
[ Related Instructions ]
PUSHC,LDC,STC,LDINTB
102
Chapter 3 Functions
3.2
Restore multiple registers
POP Multiple
POPM
[ Syntax ]
POPM
dest
[ Operation ]
dest
SP
M(SP)
SP +
POPM
[ Instruction Code/Number of Cycles ]
Page=213
N*1
2
*1 Number of registers to be restored
[ Function ]
• This instruction restores the registers selected by dest collectively from the stack area.
• Registers are restored from the stack area in the following order:
FB SB A1 A0 R3 R2 R1 R0
Restored sequentially beginning with R0
[ Selectable dest ]
dest*2
R0 R1 R2 R3 A0 A1 SB FB
*2 You can choose multiple dest.
[ Flag Change ]
Flag
U
I
O
Functions
B
S
Z
D
C
Change
[ Description Example ]
POPM
R0,R1,A0,SB,FB
[ Related Instructions ]
POP,PUSH,PUSHM
103
Chapter 3
Functions
3.2
Save register/memory/immediate data
PUSH
PUSH
[ Syntax ]
PUSH.size (:format)
src
If the size specifier (.size) is (.W)
SP
SP – 2
M(SP)
src
[ Function ]
• This instruction saves src to the stack area.
[ Selectable src ]
src
R0L /R0
A0/A0*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
*1
R0H /R1
A1/A1*1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM
*1 Can be selected in G and S formats.
In other cases, dest can be selected in G format.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
[ Description Example ]
PUSH.B
PUSH.W
PUSH.B
PUSH.W
#5
#100H
R0L
A0
[ Related Instructions ]
PUSH
[ Instruction Code/Number of Cycles ]
Page=214
G , S (Can be specified)
B,W
[ Operation ]
If the size specifier (.size) is (.B)
SP
SP – 1
M(SP)
src
*1
Functions
POP,POPM,PUSHM
104
Chapter 3 Functions
3.2
Save effective address
PUSH effective Address
PUSHA
[ Syntax ]
PUSHA
src
[ Operation ]
SP
M(SP)
SP – 2
EVA(src)
• This instruction saves the effective address of src to the stack area.
[ Selectable src ]
src
R0L/R0
R0H/R1
A0/A0
A1/A1
dsp:8[A0] dsp:8[A1]
dsp:16[A0] dsp:16[A1]
dsp:20[A0] dsp:20[A1]
R2R0
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
S
C
[ Flag Change ]
U
I
O
PUSHA
[ Instruction Code/Number of Cycles ]
Page=216
[ Function ]
Flag
Functions
B
Z
D
Change
[ Description Example ]
PUSHA
Ram:8[FB]
PUSHA
Ram:16[SB]
[ Related Instructions ]
MOVA
105
Chapter 3
Functions
3.2
Save control register
PUSH Control register
PUSHC
[ Syntax ]
PUSHC
src
[ Operation ]
SP
M(SP)
SP –
src*1
Functions
PUSHC
[ Instruction Code/Number of Cycles ]
Page=216
2
*1 When src is SP or when the U flag = “0” and src is ISP, the SP before being subtracted by 2 is saved.
[ Function ]
• This instruction saves the control register indicated by src to the stack area.
[ Selectable src ]
FB
*2
SB
*2
SP
src
ISP FLG INTBH INTBL
Operation is performed on the stack pointer indicated by the U flag.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
[ Description Example ]
PUSHC
SB
[ Related Instructions ]
POPC,LDC,STC,LDINTB
106
Chapter 3 Functions
3.2
Save multiple registers
PUSH Multiple
PUSHM
[ Syntax ]
PUSHM
src
[ Operation ]
SP
M(SP)
SP
src
PUSHM
[ Instruction Code/Number of Cycles ]
Page=217
N*1
–
2
*1 Number of registers saved.
[ Function ]
• This instruction saves the registers selected by src collectively to the stack area.
• The registers are saved to the stack area in the following order:
R0 R1 R2 R3 A0 A1 SB FB
Saved sequentially beginning with FB
[ Selectable src ]
src*2
R0 R1 R2 R3 A0 A1 SB FB
*2 You can choose multiple src.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
[ Description Example ]
PUSHM
Functions
R0,R1,A0,SB,FB
[ Related Instructions ]
POP,PUSH,POPM
107
Chapter 3
Functions
3.2
Return from interrupt
REturn from InTerrupt
REIT
[ Syntax ]
REIT
Functions
REIT
[ Instruction Code/Number of Cycles ]
Page=218
[ Operation ]
PCML
SP
PCH, FLG
SP
M(SP)
SP +
2
M(SP)
SP +
2
[ Function ]
• This instruction restores the PC and FLG that were saved when an interrupt request was accepted to
return from the interrupt handler routine.
[ Flag Change ]
Flag
U
Change *1
I
O
B
S
Z
D
C
*1
*1
*1
*1
*1
*1
*1
*1 The flags are reset to the previous FLG state before the
interrupt request was accepted.
[ Description Example ]
REIT
108
Chapter 3
Functions
3.2
Calculate sum-of-products
Repeat MultiPle & Addition
RMPA
[ Syntax ]
RMPA.size
Functions
RMPA
[ Instruction Code/Number of Cycles ]
Page=218
B,W
[ Operation ]*1
Repeat
R2R0(R0) *2
R2R0(R0) *2 +
A0 + 2 (1) *2
A1 + 2 (1) *2
R3 – 1
M(A0)
M(A1)
A0
A1
R3
R3 = 0
If you set a value 0 in R3, this instruction is ingored.
Shown in ( )*2 applies when (.B) is selected for the size specifier (.size).
Until
*1
*2
[ Function ]
• This instruction performs sum-of-product calculations, with the multiplicand address indicated by A0, the multiplier address indicated by A1, and the count of operation indicated by R3. Calculations are performed including
the sign bits and the result is stored in R2R0 (R0)*1.
• If an overflow occurs during operation, the O flag is set to terminate the operation. R2R0 (R0)*1
contains the result of the addition performed last. A0, A1 and R3 are indeterminate.
• The content of the A0 or A1 when the instruction is completed indicates the next address of the lastread data.
• If an interrupt request is received during instruction execution, the interrupt is acknowledged after a sum-ofproduct addition is completed (i.e., after the content of R3 is decremented by 1).
• Make sure that R2R0 (R0)*1 has the initial value set.
Shown in ( )*1 applies when (.B) is selected for the size specifier (.size).
[ Fl ag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
O : The flag is set when +2147483647 (.W) or –2147483648 (.W), or +32767 (.B) or –32768 (.B) is
exceeded during operation; otherwise cleared.
[ Description Example ]
RMPA.B
109
Chapter 3
Functions
3.2
Rotate left with carry
ROtate to Left with Carry
ROLC
[ Syntax ]
ROLC.size
Functions
ROLC
[ Instruction Code/Number of Cycles ]
Page=218
dest
B,W
[ Operation ]
MSB
dest
LSB
C
[ Function ]
• This instruction rotates dest one bit to the left including the C flag.
[ Selectable dest ]
dest
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
R1L/R2
R1H/R3
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
[A1]
dsp:8[FB]
abs16
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.
Z : The flag is set when the operation resulted in dest = 0; otherwise cleared.
C : The flag is set when the shifted-out bit is 1; otherwise cleared.
[ Description Example ]
ROLC.B
ROLC.W
R0L
R0
[ Related Instructions ]
RORC,ROT,SHA,SHL
110
Chapter 3
Functions
3.2
Rotate right with carry
ROtate to Right with Carry
RORC
[ Syntax ]
RORC.size
Functions
RORC
[ Instruction Code/Number of Cycles ]
Page=219
dest
B,W
[ Operation ]
MSB
dest
LSB
C
[ Function ]
• This instruction rotates dest one bit to the right including the C flag.
[ Selectable dest ]
dest
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
R1L/R2
R1H/R3
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
[A1]
dsp:8[FB]
abs16
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.
Z : The flag is set when the operation resulted in dest = 0; otherwise cleared.
C : The flag is set when the shifted-out bit is 1; otherwise cleared.
[ Description Example ]
RORC.B
RORC.W
R0L
R0
[ Related Instructions ]
ROLC,ROT,SHA,SHL
111
Chapter 3
Functions
3.2
Rotate
ROTate
ROT
[ Syntax ]
ROT.size
Functions
ROT
[ Instruction Code/Number of Cycles ]
Page=220
src,dest
B,W
[ Operation ]
srcÅÉ0
C
dest
MSB
C
LSB
srcÅÑ0
[ Function ]
• This instruction rotates dest left or right the number of bits indicated by src. The bit overflowing from LSB
(MSB) is transferred to MSB(LSB) and the C flag.
• The direction of rotate is determined by the sign of src. If src is positive, bits are rotated left; if negative, bits
are rotated right.
• If src is an immediate, the number of rotates is –8 to –1 and +1 to +8. You cannot set values less than –8,
equal to 0, or greater than +8.
• If src is a register and you selected (.B) for the size specifier (.size), the number of rotates is –8 to +8.
Although you can set 0, no bits are rotated and no flags are changed. If you set a value less than –8 or
greater than +8, the result of rotation is indeterminate.
• If src is a register and you selected (.W) for the size specifier (.size), the number of rotates is –16 to +16.
Although you can set 0, no bits are rotated and no flags are changed. If you set a value less than –16 or
greater than +16, the result of rotation is indeterminate.
[ Selectable src/dest ]
src
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
dest
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
*1
R1H /R3
[A1]
dsp:8[FB]
abs16
#IMM*2
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
*1
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3*1
[A1]
dsp:8[FB]
abs16
*1 If src is R1H, you cannot choose R1 or R1H for dest.
*2 The range of values that can be taken on is –8 < #IMM < +8. However, you cannot set 0.
[ Flag Change ]
Flag
U
I
O
B
Change
S
Z
D
C
*1 If the number of rotates is 0, no flags are changed.
Conditions
S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.
Z : The flag is set when the operation resulted in 0; otherwise cleared.
C : The flag is set when the bit shifted out last is 1; otherwise cleared.
[ Description Example ]
ROT.B
#1,R0L
ROT.B
#–1,R0L
ROT.W
R1H,R2
[ Related Instructions ]
; Rotated left
; Rotated right
ROLC,RORC,SHA,SHL
112
Chapter 3
Functions
3.2
Return from subroutine
ReTurn from Subroutine
RTS
[ Syntax ]
RTS
SP
M(SP)
SP +
2
M(SP)
SP +
1
[ Function ]
• This instruction causes control to return from a subroutine.
[ Flag Change ]
U
RTS
[ Instruction Code/Number of Cycles ]
Page=221
[ Operation ]
PCML
SP
PCH
Flag
Functions
I
O
B
S
Z
D
C
Change
[ Description Example ]
RTS
113
Chapter 3
Functions
3.2
Subtract with borrow
SuBtract with Borrow
SBB
[ Syntax ]
SBB.size
Functions
SBB
[ Instruction Code/Number of Cycles ]
Page=222
src,dest
B,W
[ Operation ]
dest
dest
___
–
src
–
C
[ Function ]
• This instruction subtracts src and inverted C flag from dest and stores the result in dest.
• If dest is an A0 or A1 when the size specifier (.size) you selected is (.B), src is zero-expanded to
perform operation in 16 bits. If src is an A0 or A1, operation is performed on the 8 low-order bits of A0
or A1.
[ Selectable src/dest ]
src
R0L/R0
A0/A0*1
R0H/R1
R1L/R2
*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
dest
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1H/R3
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
[A1]
dsp:8[FB]
abs16
#IMM
R0L/R0
*1
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
*1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
R1H/R3
[A0]
[A1]
dsp:8[SB] dsp:8[FB]
dsp:16[SB] abs16
abs20
A1A0
*1 If you specify (.B) for the size specifier (.size), you cannot choose A0 or A1 for src and dest simultaneously.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Conditions
O : The flag is set when a signed operation resulted in exceeding +32767 (.W) or –32768 (.W), or
+127 (.B) or –128 (.B); otherwise cleared.
S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.
Z : The flag is set when the operation resulted in 0; otherwise cleared.
C : The flag is set when an unsigned operation resulted in any value equal to or greater than 0;
otherwise cleared.
[ Description Example ]
SBB.B
#2,R0L
SBB.W
A0,R0
SBB.B
A0,R0L
SBB.B
R0L,A0
[ Related Instructions ]
; A0’s 8 low-order bits and R0L are operated on.
; R0L is zero-expanded and operated with A0.
ADC,ADCF,ADD,SUB
114
Chapter 3
Functions
3.2
Subtract & conditional jump
SuBtract then Jump on Not Zero
SBJNZ
[ Syntax ]
SBJNZ.size src,dest,label
Functions
SBJNZ
[ Instruction Code/Number of Cycles ]
Page=224
B,W
[ Operation ]
dest
dest – src
if dest ≠ 0 then jump label
[ Function ]
• This instruction subtracts src from dest and stores the result in dest.
• If the operation resulted in any value other than 0, control jumps to label. If the operation resulted in
0, the next instruction is executed.
• The op-code of this instruction is the same as that of ADJNZ.
[ Selectable src/dest/label ]
src
dest
R0L/R0
R1H/R3
#IMM
R0H/R1
A0/A0
label
R1L/R2
A1/A1
[A0]
[A1]
dsp:8[A0]
dsp:8[A1] dsp:8[SB] dsp:8[FB]
dsp:16[A0] dsp:16[A1] dsp:16[SB]
abs16
*1
*1 The range of values that can be taken on is –7 < #IMM < +8.
*2 The PC indicates the start address of the instruction.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
[ Description Example ]
SBJNZ.W
#1,R0,label
[ Related Instructions ]
ADJNZ
115
PC*2–126 < label < PC*2+129
Chapter 3
Functions
3.2
Shift arithmetic
SHift Arithmetic
SHA
[ Syntax ]
SHA.size
Functions
SHA
[ Instruction Code/Number of Cycles ]
Page=225
src,dest
B,W,L
[ Operation ]
When src < 0
When src > 0
C
MSB
dest
LSB
C
MSB
dest
LSB
0
[ Function ]
overflowing from LSB (MSB) is transferred to the C flag.
• The direction of shift is determined by the sign of src. If src is positive, bits are shifted left; if negative,
bits are shifted right.
• If src is an immediate, the number of shifts is –8 to –1 and +1 to +8. You cannot set values less than
–8, equal to 0, or greater than +8.
• If src is a register and you selected (.B) for the size specifier (.size), the number of shifts is –8 to +8.
Although you can set 0, no bits are shifted and no flags are changed. If you set a value less than –8 or
greater than +8, the result of shift is indeterminate.
• If src is a register and you selected (.W) or (.L) for the size specifier (.size), the number of shifts is –16
to +16. Although you can set 0, no bits are shifted and no flags are changed. If you set a value less
than –16 or greater than +16, the result of shift is indeterminate.
[ Selectable src/dest ]
src
R0L/R0
R0H/R1
A0/A0
A1/A1
dsp:8[A0] dsp:8[A1]
dsp:16[A0] dsp:16[A1]
dsp:20[A0] dsp:20[A1]
R2R0
R3R1
dest
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H*1/R3
[A1]
dsp:8[FB]
abs16
#IMM*2
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0*3
R0H/R1*1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1*3
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3*1
[A1]
dsp:8[FB]
abs16
*1 If src is R1H, you cannot choose R1 or R1H for dest.
*2 The range of values that can be taken on is –8 < #IMM < +8. However, you cannot set 0.
*3 You can only specify (.L) for the size specifier (.size). For other dest, you can specify (.B) or (.W).
[ Flag Change ]
Flag
Change
U
I
O
B
S
Z
D
C
*1 If the number of shifts is 0, no flags are changed.
Conditions
O : The flag is set when the operation resulted in MSB changing its state from 1 to 0 or from 0 to 1; otherwise
cleared. However, the flag does not change if you selected (.L) for the size specifier (.size).
S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.
Z : The flag is set when the operation resulted in 0; otherwise cleared. However, the flag is indeterminate if you
selected (.L) for the size specifier (.size).
C : The flag is set when the bit shifted out last is 1; otherwise cleared. However, the flag is indeterminate if you
selected (.L) for the size specifier (.size).
[ Description Example ]
SHA.B
#3,R0L
SHA.B
#–3,R0L
SHA.L
R1H,R2R0
[ Related Instructions ]
; Arithmetically shifted left
; Arithmetically shifted right
ROLC,RORC,ROT,SHL
116
Chapter 3
Functions
3.2
Shift logical
SHift Logical
SHL
[ Syntax ]
SHL.size
Functions
SHL
[ Instruction Code/Number of Cycles ]
Page=228
src,dest
B,W,L
[ Operation ]
When src < 0
0
MSB
dest
LSB
C
C
MSB
dest
LSB
0
When src > 0
[ Function ]
• This instruction logically shifts dest left or right the number of bits indicated by src. The bit overflowing
from LSB (MSB) is transferred to the C flag.
• The direction of shift is determined by the sign of src. If src is positive, bits are shifted left; if negative,
bits are shifted right.
• If src is an immediate, the number of shifts is –8 to –1 and +1 to +8. You cannot set values less than
–8, equal to 0, or greater than +8.
• If src is a register and you selected (.B) for the size specifier (.size), the number of shifts is –8 to +8.
Although you can set 0, no bits are shifted and no flags are changed. If you set a value less than –8 or
greater than +8, the result of shift is indeterminate.
• If src is a register and you selected (.W) or (.L) for the size specifier (.size), the number of shifts is –16
to +16. Although you can set 0, no bits are shifted and no flags are changed. If you set a value less
than –16 or greater than +16, the result of shift is indeterminate.
[ Selectable src/dest ]
src
dest
*1
*1
R0L/R0
R0H/R1
R1L/R2
R1H /R3 R0L/R0
R0H/R1
R1L/R2
R1H/R3*1
A0/A0
A1/A1
[A0]
[A1]
A0/A0
A1/A1
[A0]
[A1]
dsp:8[A0] dsp:8[A1]
dsp:8[SB]
dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB]
dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16
dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16
*2
dsp:20[A0] dsp:20[A1] abs20
#IMM
dsp:20[A0] dsp:20[A1] abs20
R2R0
R3R1
A1A0
R2R0*3
R3R1*3
A1A0
*1 If src is R1H, you cannot choose R1 or R1H for dest.
*2 The range of values that can be taken on is –8 < #IMM < +8. However, you cannot set 0.
*3 You can only specify (.L) for the size specifier (.size). For other dest, you can specify (.B) or (.W).
[ Flag Change ]
Flag
U
I
O
B
Change
S
Z
D
C
*1 If the number of shifts is 0, no flags are changed.
Conditions
S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.
Z : The flag is set when the operation resulted in 0; otherwise cleared. However, the flag is
indeterminate if you selected (.L) for the size specifier (.size).
C : The flag is set when the bit shifted out last is 1; otherwise cleared. However, the flag is
indeterminate if you selected (.L) for the size specifier (.size).
[ Description Example ]
SHL.B
#3,R0L
; Logically shifted left
SHL.B
#–3,R0L
; Logically shifted right
SHL.L
R1H,R2R0
[ Related Instructions ]
ROLC,RORC,ROT,SHA
117
Chapter 3
Functions
3.2
Transfer string backward
String MOVe Backward
SMOVB
[ Syntax ]
SMOVB.size
Functions
SMOVB
[ Instruction Code/Number of Cycles ]
Page=230
B,W
[ Operation ]*1
When size specifier (.size) is (.B)
Repeat
M(A1)
M(216
*2
A0
A0 –
A1
A1 –
R3
R3 –
Until
R3 = 0
R1H + A0)
1
1
1
When size specifier (.size) is (.W)
Repeat
M(A1)
M(216 R1H + A0)
*2
A0
A0 – 2
A1
A1 – 2
R3
R3 – 1
Until
R3 = 0
*1
If you set a value 0 in R3, this instruction is ingored.
*2
If A0 underflows, the content of R1H is decremented by 1.
[ Function ]
• This instruction transfers string in successively address decrementing direction from the source address indicated by 20 bits to the destination address indicated by 16 bits.
• Set the 4 high-order bits of the source address in R1H, the 16 low-order bits of the source address in
A0, the destination address in A1, and the transfer count in R3.
• The A0 or A1 when the instruction is completed contains the next address of the last-read data.
• If an interrupt request is received during instruction execution, the interrupt is acknowledged after one
data transfer is completed.
[ Flag Change ]
Flag
Change
U
I
O
B
S
Z
D
C
[ Description Example ]
SMOVB.B
[ Related Instructions ]
SMOVF,SSTR
118
Chapter 3
Functions
3.2
Transfer string forward
String MOVe Forward
SMOVF
[ Syntax ]
SMOVF.size
Functions
SMOVF
[ Instruction Code/Number of Cycles ]
Page=231
B,W
[ Operation ]*1
When size specifier (.size) is (.B)
Repeat
M(A1)
M(216 R1H + A0)
*2*
A0
A0
+
1
A1
A1
+
1
R3
R3
–
1
Until
R3 = 0
When size specifier (.size) is (.W)
Repeat
M(A1)
M(216 R1H + A0)
*2
A0
A0 + 2
A1
A1 + 2
R3
R3 – 1
Until
R3 = 0
*1
If you set a value 0 in R3, this instruction is ingored.
*2
If A0 overflows, the content of R1H is incremented by 1.
[ Function ]
• This instruction transfers string in successively address incrementing direction from the source address indicated by 20 bits to the destination address indicated by 16 bits.
• Set the 4 high-order bits of the source address in R1H, the 16 low-order bits of the source address in
A0, the destination address in A1, and the transfer count in R3.
• The A0 or A1 when the instruction is completed contains the next address of the last-read data.
• If an interrupt request is received during instruction execution, the interrupt is acknowledged after one
data transfer is completed.
• This instruction arithmetically shifts dest left or right the number of bits indicated by src. The bit
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
[ Description Example ]
SMOVF.W
[ Related Instructions ]
SMOVB,SSTR
119
Chapter 3
Functions
3.2
Store string
String SToRe
SSTR
[ Syntax ]
SSTR.size
Functions
SSTR
[ Instruction Code/Number of Cycles ]
Page=231
B,W
[ Operation ]*1
When size specifier (.size) is (.B)
Repeat
M(A1)
R0L
A1
A1 + 1
R3
R3 – 1
Until
R3 = 0
*1
When size specifier (.size) is (.W)
Repeat
M(A1)
R0
A1
A1 + 2
R3
R3 – 1
Until
R3 = 0
If you set a value 0 in R3, this instruction is ingored.
[ Function ]
• This instruction stores string, with the store data indicated by R0, the transfer address indicated by A1,
and the transfer count indicated by R3.
• The A0 or A1 when the instruction is completed contains the next address of the last-written data.
• If an interrupt request is received during instruction execution, the interrupt is acknowledged after one
data transfer is completed.
[ Flag Change ]
Flag
Change
U
I
O
B
S
Z
D
C
[ Description Example ]
SSTR.B
[ Related Instructions ]
SMOVB,SMOVF
120
Chapter 3
Functions
3.2
Transfer from control register
STore from Control register
STC
Functions
STC
[ Instruction Code/Number of Cycles ]
Page=232
[ Syntax ]
STC src,dest
[ Operation ]
dest
src
[ Function ]
• This instruction transfers the control register indicated by src to dest. If dest is memory, specify the
address in which to store the low-order address.
• If dest is memory while src is PC, the required memory capacity is 3 bytes. If src is not PC, the
required memory capacity is 2 bytes.
[ Selectable src/dest ]
src
FB
FLG
dest
*1
SB
INTBH
SP
INTBL
ISP
PC
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R0H/R1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
*1 Operation is performed on the stack pointer indicated by the U flag.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
[ Description Example ]
STC
SB,R0
STC
FB,A0
[ Related Instructions ]
POPC,PUSHC,LDC,LDINTB
121
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
R1H/R3
[A1]
dsp:8[FB]
abs16
Chapter 3
Functions
3.2
Save context
STore ConTeXt
STCTX
[ Syntax ]
STCTX
Functions
STCTX
[ Instruction Code/Number of Cycles ]
Page=233
abs16,abs20
[ Operation ]
[ Function ]
• This instruction saves task context to the stack area.
• Set the RAM address that contains the task number in abs16 and the start address of table data in abs20.
• The required register information is specified from table data by the task number and the data in the stack area is
transferred to each register according to the specified register information. Then the SP correction value is subtracted
to the stack pointer (SP). For this SP correction value, set the number of bytes you want to the transferred.
• Information on transferred registers is configured as shown below. Logic 1 indicates a register to be
transferred and logic 0 indicates a register that is not transferred.
MSB
LSB
FB SB A1 A0 R3 R2 R1 R0
Transferred sequentially beginning with FB
• The table data is comprised as shown below. The address indicated by abs20 is the base address of
the table. The data stored at an address apart from the base address as much as twice the content of
abs16 indicates register information, and the next address contains the stack pointer correction value.
Base address
of table
abs20
Register information for the task whose task number = 0.
SP correction value for the task whose task number = 0.
Register information for the task whose task number = 1.
SP correction value for the task whose task number = 1.
Direction in
which address
increases
(See the above diagram.)
(See the above diagram.)
(See the above diagram.)
(See the above diagram.)
Register information for the task whose task number = n*1. (See the above diagram.)
SP correction value for the task whose task number = n*1. (See the above diagram.)
*1
n=0 to 255
[ Flag Change ]
Flag
Change
U
I
O
B
S
Z
D
C
[ Description Example ]
STCTX
Ram,Rom_TBL
[ Related Instructions ]
LDCTX
122
abs16 x 2
Chapter 3
Functions
3.2
Transfer to extended data area
STore to EXtra far data area
STE
[ Syntax ]
STE.size
Functions
STE
[ Instruction Code/Number of Cycles ]
Page=233
src,dest
B,W
[ Operation ]
dest
src
[ Function ]
• This instruction transfers src to dest in an extended area.
• If src is an A0 or A1 when the size specifier (.size) you selected is (.B), operation is performed on the
8 low-order bits of A0 or A1. However, the flag changes depending on the A0 or A1 status (16 bits)
before the operation is performed.
[ Selectable src/dest ]
src
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R0H/R1
[A1]
A0/A0
A1/A1
dsp:8[FB] dsp:8[A0] dsp:8[A1]
abs16
dsp:16[A0] dsp:16[A1]
#IMM
dsp:20[A0] dsp:20[A1]
R2R0
R3R1
S
C
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
[A1A0]
[ Flag Change ]
Flag
Change
U
I
O
B
Z
D
Conditions
S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.
Z : The flag is set when the operation resulted in 0; otherwise cleared.
[ Description Example ]
STE.B
R0L,[A1A0]
STE.W
R0,10000H[A0]
[ Related Instructions ]
MOV,LDE,XCHG
123
R1H/R3
[A1]
dsp:8[FB]
abs16
Chapter 3
Functions
3.2
Conditional transfer
STore on Not Zero
STNZ
[ Syntax ]
STNZ
dest
STNZ
[ Instruction Code/Number of Cycles ]
Page=235
src,dest
[ Operation ]
if Z = 0 then
Functions
src
[ Function ]
• This instruction transfers src to dest when the Z flag is 0.
[ Selectable src/dest ]
src
dest
#IMM8
R0L
R0H
dsp:8[SB]
abs16
A0
A1
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
[ Description Example ]
STNZ
#5,Ram:8[SB]
[ Related Instructions ]
STZ,STZX
124
dsp:8[FB]
Chapter 3
Functions
3.2
Conditional transfer
STore on Zero
STZ
[ Syntax ]
STZ
src,dest
[ Operation ]
if Z = 1 then
Functions
STZ
[ Instruction Code/Number of Cycles ]
Page=235
dest
src
[ Function ]
• This instruction transfers src to dest when the Z flag is 1.
[ Selectable src/dest ]
src
dest
#IMM8
R0L
R0H
dsp:8[SB]
abs16
A0
A1
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
[ Description Example ]
STZ
#5,Ram:8[SB]
[ Related Instructions ]
STNZ,STZX
125
dsp:8[FB]
Chapter 3
Functions
3.2
Conditional transfer
STore on Zero eXtention
STZX
[ Syntax ]
STZX
STZX
[ Instruction Code/Number of Cycles ]
Page=236
src1,src2,dest
[ Operation ]
If Z = 1 then
dest
else
dest
[ Function ]
Functions
src1
src2
• This instruction transfers src1 to dest when the Z flag is 1. When the Z flag is 0, it transfers src2 to
dest.
[ Selectable src/dest ]
src
dest
#IMM8
R0L
R0H
dsp:8[SB]
abs16
A0
A1
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
[ Description Example ]
STZX
#1,#2,Ram:8[SB]
[ Related Instructions ]
STZ,STNZ
126
dsp:8[FB]
Chapter 3
Functions
3.2
Subtract without borrow
SUBtract
SUB
[ Syntax ]
SUB.size (:format) src,dest
[ Operation ]
dest
dest
–
Functions
SUB
[ Instruction Code/Number of Cycles ]
Page=236
G , S (Can be specified)
B,W
src
[ Function ]
• This instruction subtracts src from dest and stores the result in dest.
• If dest is an A0 or A1 when the size specifier (.size) you selected is (.B), src is zero-expanded to
perform operation in 16 bits. If src is an A0 or A1, operation is performed on the 8 low-order bits of A0
or A1.
(See the next page for src/dest classified by format.)
[ Selectable src/dest ]
src
R0L/R0
A0/A0*1
R0H/R1
R1L/R2
*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
dest
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1H/R3
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
[A1]
dsp:8[FB]
abs16
#IMM
R0L/R0
*1
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
*1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
R1H/R3
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
[A1]
dsp:8[FB]
abs16
SP/SP
*1 If you specify (.B) for the size specifier (.size), you cannot choose A0 or A1 for src and dest simultaneously.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
O : The flag is set when a signed operation resulted in exceeding +32767 (.W) or –32768 (.W), or
+127 (.B) or –128 (.B); otherwise cleared.
S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.
Z : The flag is set when the operation resulted in 0; otherwise cleared.
C : The flag is set when an unsigned operation resulted in any value equal to or greater than 0;
otherwise cleared.
[ Description Example ]
SUB.B
A0,R0L
SUB.B
R0L,A0
SUB.B
Ram:8[SB],R0L
SUB.W
#2,[A0]
[ Related Instructions ]
; A0’s 8 low-order bits and R0L are operated on.
; R0L is zero-expanded and operated with A0.
ADC,ADCF,ADD,SBB
127
Chapter 3
Functions
3.2
Functions
[src/dest Classified by Format]
G format
src
R0L/R0
A0/A0*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1*1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
dest
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM
R0L/R0
A0/A0*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
A1/A1*1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1H/R3
[A1]
dsp:8[FB]
abs16
SP/SP
*1 If you specify (.B) for the size specifier (.size), you cannot choose A0 or A1 for src and dest simultaneously.
S format*2
src
R0L
abs16
R0L*3
abs16
R0H
#IMM
R0H*3
#IMM
dsp:8[SB]
dsp:8[SB]
dest
dsp:8[FB] R0L
abs16
dsp:8[FB] R0L*3
abs16
*2 You can only specify (.B) for the size specifier (.size).
*3 You cannot choose the same register for src and dest.
128
R0H
A0
R0H*3
A0
dsp:8[SB]
A1
dsp:8[SB]
A1
dsp:8[FB]
dsp:8[FB]
Chapter 3
Functions
3.2
Test
TeST
TST
[ Syntax ]
TST.size
Functions
TST
[ Instruction Code/Number of Cycles ]
Page=239
src,dest
B,W
[ Operation ]
dest
src
[ Function ]
• Each flag in the flag register changes state depending on the result of logical AND of src and dest.
• If dest is an A0 or A1 when the size specifier (.size) you selected is (.B), src is zero-expanded to
perform operation in 16 bits. If src is an A0 or A1, operation is performed on the 8 low-order bits of A0
or A1.
[ Selectable src/dest ]
src
R0L/R0
A0/A0*1
R0H/R1
A1/A1*1
dsp:8[A0] dsp:8[A1]
dsp:16[A0] dsp:16[A1]
dsp:20[A0] dsp:20[A1]
R2R0
R3R1
dest
R1L/R2
R1H/R3
R0L/R0
R0H/R1
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
[A1]
dsp:8[FB]
abs16
#IMM
A0/A0*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
A1/A1*1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
[A0]
[A1]
dsp:8[SB] dsp:8[FB]
dsp:16[SB] abs16
abs20
A1A0
R1H/R3
*1 If you specify (.B) for the size specifier (.size), you cannot choose A0 or A1 for src and dest simultaneously.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.
Z : The flag is set when the operation resulted in 0; otherwise cleared.
[ Description Example ]
TST.B
#3,R0L
TST.B
A0,R0L
TST.B
R0L,A0
[ Related Instructions ]
; A0's 8 low-order bits and ROL are operated on.
; R0L is zero-expanded and operated on with A0.
AND,OR,XOR
129
Chapter 3
Functions
3.2
Interrupt for undefined instruction
UNDefined instruction
UND
[ Syntax ]
UND
Functions
UND
[ Instruction Code/Number of Cycles ]
Page=241
[ Operation ]
SP
M(SP)
SP – 2
(PC + 1)H, FLG
SP
M(SP)
PC
SP – 2
(PC + 1)ML
M(FFFDC16)
[ Function ]
• This instruction generates an undefined instruction interrupt.
• The undefined instruction interrupt is a nonmaskable interrupt.
[ Flag Change ]
Flag
Change
U
I
O
B
S
Conditions
U : The flag is cleared.
I : The flag is cleared.
D : The flag is cleared.
Z
D
C
*1 The flags are saved to the stack area before the UND
instruction is executed. After the interrupt, the flag status
becomes as shown on the left.
[ Description Example ]
UND
130
Chapter 3
Functions
3.2
Wait
WAIT
WAIT
[ Syntax ]
WAIT
Functions
WAIT
[ Instruction Code/Number of Cycles ]
Page=241
[ Operation ]
[ Function ]
• This instruction halts program execution. Program execution is restarted when an interrupt of a higher
priority level than IPL is acknowledged or a reset is generated.
[ Flag Change ]
Flag
Change
U
I
O
B
S
Z
D
C
[ Description Example ]
WAIT
131
Chapter 3
Functions
3.2
Exchange
eXCHanGe
XCHG
[ Syntax ]
XCHG.size
Functions
XCHG
[ Instruction Code/Number of Cycles ]
Page=242
src,dest
B,W
[ Operation ]
dest
src
[ Function ]
• This instruction exchanges contents between src and dest.
• If dest is an A0 or A1 when the size specifier (.size) you selected is (.B), 16 bits of zero- expanded src
data are placed in the A0 or A1 and the 8 low-order bits of the A0 or A1 are placed in src.
[ Selectable src/dest ]
src
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
dest
R0H/R1
R1L/R2
R1H/R3
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
[A1]
dsp:8[FB]
abs16
#IMM
[A1A0]
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
[A0]
[A1]
dsp:8[SB] dsp:8[FB]
dsp:16[SB] abs16
abs20
A1A0
S
C
[ Flag Change ]
Flag
U
I
O
B
Z
D
Change
[ Description Example ]
XCHG.B
XCHG.W
XCHG.B
R0L,A0
R0,A1
R0L,[A0]
[ Related Instructions ]
; A0’s 8 low-order bits and R0L’s zero-expanded value are exchanged.
MOV,LDE,STE
132
Chapter 3
Functions
3.2
Exclusive OR
eXclusive OR
XOR
[ Syntax ]
XOR.size
Functions
XOR
[ Instruction Code/Number of Cycles ]
Page=243
src,dest
B,W
A
[ Operation ]
dest
dest
src
[ Function ]
• This instruction exclusive ORs src and dest together and stores the result in dest.
• If dest is an A0 or A1 when the size specifier (.size) you selected is (.B), src is zero-expanded to
perform operation in 16 bits. If src is an A0 or A1, operation is performed on the 8 low-order bits of A0
or A1.
[ Selectable src/dest ]
src
R0L/R0
A0/A0*1
R0H/R1
R1L/R2
*1
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
dest
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1H/R3
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
[A1]
dsp:8[FB]
abs16
#IMM
R0L/R0
*1
A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:20[A0]
R2R0
R0H/R1
*1
A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:20[A1]
R3R1
R1L/R2
R1H/R3
[A0]
[A1]
dsp:8[SB] dsp:8[FB]
dsp:16[SB] abs16
abs20
A1A0
*1 If you specify (.B) for the size specifier (.size), you cannot choose A0 or A1 for src and dest simultaneously.
[ Flag Change ]
Flag
U
I
O
B
S
Z
D
C
Change
Conditions
S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.
Z : The flag is set when the operation resulted in 0; otherwise cleared.
[ Description Example ]
XOR.B
XOR.B
XOR.B
XOR.W
A0,R0L
R0L,A0
#3,R0L
A0,A1
[ Related Instructions ]
; A0’s 8 low-order bits and R0L are exclusive ORed.
; R0L is zero-expanded and exclusive ORed with A0.
AND,OR,TST
133
Chapter 3
Functions
3.2
Blank for page layout
134
Functions
Chapter 4
Instruction Code/Number of Cycles
4.1 Guide to This Chapter
4.2 Instruction Code/Number of Cycles
Chapter 4 Instruction Code
4.1
Guide to This Chapter
4.1 Guide to This Chapter
This chapter describes instruction code and number of cycles for each op-code.
The following shows how to read this chapter by using an actual page as an example.
Chapter 4 Instruction Code
4.2
Instruction Code/Number of Cycles
LDIPL
(1)
(2)
(1) LDIPL #IMM
b7
(3)
(4)
b0 b7
0 1 1
1 1 1 0 1 1
b0
0 1 0
IMM4
[ Number of Bytes/Number of Cycles ]
2/2
Bytes/Cycles
(1)
(2)
MOV
(1) MOV.size:G #IMM, dest
b7
(3)
b0 b7
0 1 1
1 0 1 0 SIZE 1
.B
.W
(4)
1 0 0
0
1
R0L/R0
R0H/R1
Rn
R1L/R2
R1H/R3
A0
An
A1
[A0]
[An]
[A1]
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
An
[An]
3/2
3/2
3/3
DEST
(
dsp8
dsp16/abs16
DEST
dest
.size SIZE
dest code
b0
0000
0001
0010
0011
0100
0101
0110
0111
)
#IMM8
#IMM16
dest
dsp:8[An]
dsp:8[SB/FB]
dsp:16[An]
dsp:16[SB]
abs16
DEST
dsp:8[A0]
dsp:8[A1]
dsp:8[SB]
dsp:8[FB]
dsp:16[A0]
dsp:16[A1]
dsp:16[SB]
abs16
1000
1001
1010
1011
1100
1101
1110
1111
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB] abs16
4/3
4/3
136
5/3
5/3
5/3
Chapter 4 Instruction Code
4.1
Guide to This Chapter
(1) Mnemonic
Shows the mnemonic explained in this page.
(2) Syntax
Shows an instruction syntax using symbols.
(3) Instruction code
Shows instruction code. Entered in ( ) are omitted depending on src/dest you selected.
Content at start address
of instruction
Contents at addresses following
(start address of instruction + 2)
(See the following figure.)
b7
b0 b7
0 1 1
1 0
.B
.W
1 0 0
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
0
1
Rn
An
[An]
(
DEST
Correspondence
.size SIZE
dest code
b0
1 0 SIZE 1
Correspondence





































Content at (start address
of instruction+1)
dsp8
dsp16/abs16
)
#IMM8
#IMM16
Correspondence
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dest
dsp:8[An]
dsp:8[SB/FB]
dsp:16[An]
dsp:16[SB]
abs16
dsp:8[A0]
dsp:8[A1]
dsp:8[SB]
dsp:8[FB]
dsp:16[A0]
dsp:16[A1]
dsp:16[SB]
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
Contents at addresses following (start address of instruction + 2) are arranged as follows:
+0
b7
dsp8
#IMM8
dsp16
abs16
#IMM16
abs20
dsp20
#IMM20
+1
+2
b0
8bit
b7
b0 b7
Low-order 8bit
b7
b0
High-order 8bit
b0 b7
b0 b7
Low-order 8bit
Middle-order 8bit
0000
b0
High-order
4bit
(4) Table of cycles
Shows the number of cycles required to execute this instruction and the number of instruction bytes.
There is a chance that the number of cycles increases due to an effect of software wait.
Instruction bytes are indicated on the left side of the slash and execution cycles are indicated on the right side.
137
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
ABS
(1) ABS.size dest
b7
b0 b7
0 1 1
1 0
.size SIZE
.B
0
.W
1
1 1 SIZE 1
b0
1 1 1
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
DEST
dest code
(
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dsp8
dsp16/abs16
)
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
2/3
An
2/3
[An]
2/5
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/5
3/5
4/5
4/5
abs16
4/5
ADC
(1) ADC.size #IMM, dest
b7
b0 b7
0 1 1
1 0
.size SIZE
.B
0
.W
1
1 1 SIZE 0
Rn
An
[An]
dest code
b0
1 1 0
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
DEST
(
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dsp8
dsp16/abs16
)
#IMM8
#IMM16
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
[An] dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
Rn
An
Bytes/Cycles 3/2
3/2
3/4
4/4
4/4
5/4
5/4
*1 If the size specifier (.size) is (.W), the number of bytes above is increased by 1.
138
abs16
5/4
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
ADC
(2) ADC.size src, dest
b7
1 0 1
b0 b7
1 0
.size SIZE
.B
0
.W
1
0 0 SIZE
b0
SRC
DEST
src/dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
(
SRC/DEST
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
dest code
src code
0
1
0
1
0
1
0
1
dsp8
dsp16/abs16
)(
)
dsp8
dsp16/abs16
src/dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
SRC/DEST
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
src
dest
Rn
An
[An]
dsp:8[An]
dsp:8[SB/FB]
dsp:16[An]
dsp:16[SB]
abs16
Rn
2/2
2/2
2/3
3/3
3/3
4/3
4/3
4/3
An
2/2
2/2
2/3
3/3
3/3
4/3
4/3
4/3
[An]
2/3
2/3
2/4
3/4
3/4
4/4
4/4
4/4
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/3
3/3
4/3
4/3
3/3
3/3
4/3
4/3
3/4
3/4
4/4
4/4
4/4
4/4
5/4
5/4
4/4
4/4
5/4
5/4
5/4
5/4
6/4
6/4
5/4
5/4
6/4
6/4
5/4
5/4
6/4
6/4
139
abs16
4/3
4/3
4/4
5/4
5/4
6/4
6/4
6/4
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
ADCF
(1) ADCF.size
dest
b7
b0 b7
0 1 1
1 0 1
.size SIZE
.B
0
.W
1
1 SIZE 1
b0
1 1 0
DEST
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
dest code
(
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dsp8
dsp16/abs16
)
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
2/1
An
2/1
[An]
2/3
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/3
3/3
4/3
4/3
abs16
4/3
ADD
(1) ADD.size:G
#IMM, dest
b7
0 1 1
b0 b7
1 0 1 1 SIZE 0
.size SIZE
.B
0
.W
1
1 0 0
An
[An]
(
DEST
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
dest code
b0
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dsp8
dsp16/abs16
)
#IMM8
#IMM16
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
3/2
An
3/2
[An]
3/4
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
4/4
4/4
5/4
5/4
*1 If the size specifier (.size) is (.W), the number of bytes above is increased by 1.
140
abs16
5/4
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
ADD
(2) ADD.size:Q
#IMM, dest
b7
b0 b7
1 1 0
0 1 0 0 SIZE
.size SIZE
.B
0
.W
1
#IMM
0
+1
+2
+3
+4
+5
+6
+7
b0
IMM4
IMM4
0000
0001
0010
0011
0100
0101
0110
0111
DEST
#IMM
–8
–7
–6
–5
–4
–3
–2
–1
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
dest code
(
dsp8
dsp16/abs16
)
IMM4
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
2/1
An
2/1
[An]
2/3
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/3
3/3
4/3
4/3
141
abs16
4/3
Chapter 4
Instruction Code/Number of Cycles
4.2
ADD
(3) ADD.B:S #IMM8, dest
b7
dest code
b0
1 0 0
0 0
DEST
dest
Rn
dsp:8[SB/FB]
abs16
(
#IMM8
dsp8
abs16
DEST
R0H
R0L
dsp:8[SB]
dsp:8[FB]
abs16
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
2/1
dsp:8[SB/FB]
3/3
abs16
4/3
142
)
Instruction Code/Number of Cycles
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
ADD
(4) ADD.size:G
src, dest
b7
1 0 1
b0 b7
0 0
.size SIZE
.B
0
.W
1
0 0 SIZE
SRC
An
[An]
(
DEST
src/dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
src code
b0
SRC/DEST
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
dsp8
dsp16/abs16
dest code
)(
)
dsp8
dsp16/abs16
src/dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
SRC/DEST
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
src
dest
Rn
An
[An]
dsp:8[An]
dsp:8[SB/FB]
dsp:16[An]
dsp:16[SB]
abs16
Rn
2/2
2/2
2/3
3/3
3/3
4/3
4/3
4/3
An
2/2
2/2
2/3
3/3
3/3
4/3
4/3
4/3
[An]
2/3
2/3
2/4
3/4
3/4
4/4
4/4
4/4
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
4/3
4/3
3/3
3/3
3/3
3/3
4/3
4/3
3/4
3/4
4/4
4/4
4/4
4/4
5/4
5/4
4/4
4/4
5/4
5/4
5/4
5/4
6/4
6/4
5/4
5/4
6/4
6/4
5/4
5/4
6/4
6/4
143
abs16
4/3
4/3
4/4
5/4
5/4
6/4
6/4
6/4
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
ADD
(5) ADD.B:S src, R0L/R0H
b7
src code
b0
0 0 1
0 0 DEST SRC
(
dsp8
abs16
src
Rn
dsp:8[SB/FB]
abs16
)
dest
SRC
0 0
0 1
1 0
1 1
R0L/R0H
dsp:8[SB]
dsp:8[FB]
abs16
DEST
0
1
R0L
R0H
[ Number of Bytes/Number of Cycles ]
src
Bytes/Cycles
dsp:8[SB/FB]
Rn
1/2
2/3
abs16
3/3
ADD
(6) ADD.size:G
#IMM, SP
b7
0 1 1
b0 b7
1 1 1 0 SIZE 1
b0
1 1 0
1 0
1 1
#IMM8
#IMM16
.size SIZE
.B
0
.W
1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
3/2
*1 If the size specifier (.size) is (.W), the number of bytes above is increased by 1.
144
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
ADD
(7) ADD.size:Q
#IMM, SP
b7
b0 b7
0 1 1
1 1
1 0 1 1
b0
0 1 1
IMM4
*1 The instruction code is the same regardless of whether you selected (.B) or (.W) for the size specifier (.size).
#IMM
0
+1
+2
+3
+4
+5
+6
+7
IMM4
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
#IMM
–8
–7
–6
–5
–4
–3
–2
–1
IMM4
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/1
145
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
ADJNZ
(1) ADJNZ.size
#IMM, dest, label
b7
b0 b7
1 1 1
1 1
b0
0 0 SIZE
IMM4
DEST
dest code
(
dsp8
dsp16/abs16
label code
)
dsp8
dsp8 (label code)= address indicated by label –(start address of instruction + 2)
.size SIZE
.B
0
.W
1
#IMM
0
+1
+2
+3
+4
+5
+6
+7
Rn
An
[An]
IMM4
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
#IMM
–8
–7
–6
–5
–4
–3
–2
–1
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
IMM4
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Rn
An
[An] dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/3
3/3
3/5
4/5
4/5
5/5
5/5
Bytes/Cycles
*1 If branched to label, the number of cycles above is increased by 4.
146
abs16
5/5
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
AND
(1) AND.size:G
#IMM, dest
b7
b0 b7
0 1 1
1 0
1 1 SIZE 0
.size SIZE
.B
0
.W
1
0 1 0
An
[An]
(
DEST
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
dest code
b0
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dsp8
dsp16/abs16
)
#IMM8
#IMM16
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
3/2
An
3/2
[An]
3/4
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
4/4
4/4
5/4
5/4
abs16
5/4
*1 If the size specifier (.size) is (.W), the number of bytes above is increased by 1.
AND
(2) AND.B:S #IMM8, dest
b7
dest code
b0
1 0 0
1 0
DEST
dest
Rn
dsp:8[SB/FB]
abs16
(
#IMM8
dsp8
abs16
DEST
R0H
R0L
dsp:8[SB]
dsp:8[FB]
abs16
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
2/1
dsp:8[SB/FB]
3/3
abs16
4/3
147
)
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
AND
(3) AND.size:G
src, dest
b7
1 0 0
b0 b7
1 0 0 0 SIZE
.size SIZE
.B
0
.W
1
An
[An]
(
DEST
src/dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
src code
b0
SRC
SRC/DEST
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
dsp8
dsp16/abs16
dest code
)(
)
dsp8
dsp16/abs16
src/dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
SRC/DEST
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
src
dest
Rn
An
[An]
dsp:8[An]
dsp:8[SB/FB]
dsp:16[An]
dsp:16[SB]
abs16
Rn
2/2
2/2
2/3
3/3
3/3
4/3
4/3
4/3
An
2/2
2/2
2/3
3/3
3/3
4/3
4/3
4/3
[An]
2/3
2/3
2/4
3/4
3/4
4/4
4/4
4/4
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/3
3/3
4/3
4/3
3/3
3/3
4/3
4/3
3/4
3/4
4/4
4/4
4/4
4/4
5/4
5/4
4/4
4/4
5/4
5/4
5/4
5/4
6/4
6/4
5/4
5/4
6/4
6/4
5/4
5/4
6/4
6/4
148
abs16
4/3
4/3
4/4
5/4
5/4
6/4
6/4
6/4
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
AND
(4) AND.B:S src, R0L/R0H
b7
src code
b0
0 0 0
1 0 DEST SRC
src
Rn
dsp:8[SB/FB]
abs16
(
dsp8
abs16
)
SRC
R0L/R0H
dsp:8[SB]
dsp:8[FB]
abs16
0
0
1
1
0
1
0
1
dest
R0L
R0H
[ Number of Bytes/Number of Cycles ]
src
Bytes/Cycles
Rn
1/2
dsp:8[SB/FB]
2/3
abs16
3/3
149
DEST
0
1
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
BAND
(1) BAND
src
b7
b0 b7
0 1 1
1 1 1 1
0 0
src
bit,R0
bit,R1
bit,R2
bit,R3
bit,A0
bit,A1
[A0]
[A1]
bit,Rn
bit,An
[An]
src code
b0
1 0 0
0
0
0
0
0
0
0
0
SRC
000
001
010
011
100
101
110
111
(
SRC
)
dsp8
dsp16
src
base:8[A0]
base:8[An]
base:8[A1]
bit,base:8[SB]
bit,base:8
bit,base:8[FB]
[SB/FB]
base:16[A0]
base:16[An]
base:16[A1]
bit,base:16[SB] bit,base:16[SB]
bit,base:16
bit,base:16
1
1
1
1
1
1
1
1
SRC
000
001
010
011
100
101
110
111
[ Number of Bytes/Number of Cycles ]
src
bit,Rn bit,An
Bytes/Cycles
3/3
3/3
[An]
base:8
[An]
bit,base:8
[SB/FB]
base:16
[An]
2/7
3/7
3/4
4/7
bit,base:16
bit,base:16
[SB]
4/4
4/4
BCLR
(1) BCLR:G dest
b7
b0 b7
0 1 1
1 1 1
1 0 1
dest
bit,R0
bit,R1
bit,R2
bit,R3
bit,A0
bit,A1
[A0]
[A1]
bit,Rn
bit,An
[An]
b0
0 0 0
DEST
0000
0001
0010
0011
0100
0101
0110
0111
DEST
dest code
(
)
dsp8
dsp16
dest
base:8[A0]
base:8[An]
base:8[A1]
bit,base:8[SB]
bit,base:8
bit,base:8[FB]
[SB/FB]
base:16[A0]
base:16[An]
base:16[A1]
bit,base:16[SB] bit,base:16[SB]
bit,base:16
bit,base:16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
bit,Rn bit,An
3/2
3/2
[An]
base:8
[An]
bit,base:8
[SB/FB]
base:16
[An]
2/6
3/6
3/3
4/6
150
bit,base:16
bit,base:16
[SB]
4/3
4/3
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
BCLR
(2) BCLR:S bit, base:11[SB]
b7
0 1 0
b0
0 0
BIT
dest code
dsp8
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/3
151
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
BMCnd
(1) BMCnd
dest
b7
b0 b7
0 1 1
1 1
1 1 0 0
0 1 0
dest
bit,R0
bit,R1
bit,R2
bit,R3
bit,A0
bit,A1
[A0]
[A1]
bit,Rn
bit,An
[An]
Cnd
GEU/C
GTU
EQ/Z
N
LE
O
GE
DEST
0000
0001
0010
0011
0100
0101
0110
0111
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(
DEST
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
LTU/NC
LEU
NE/NZ
PZ
GT
NO
LT
)
dsp8
dsp16
dest
base:8[A0]
base:8[An]
base:8[A1]
bit,base:8[SB]
bit,base:8
bit,base:8[FB]
[SB/FB]
base:16[A0]
base:16[An]
base:16[A1]
bit,base:16[SB] bit,base:16[SB]
bit,base:16
bit,base:16
Cnd
CND
0
0
0
0
0
0
0
dest code
b0
CND
DEST
1000
1001
1010
1011
1100
1101
1110
1111
CND
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
bit,Rn bit,An
4/6
4/6
[An]
base:8
[An]
bit,base:8
[SB/FB]
base:16
[An]
3/10
4/10
4/7
5/10
152
bit,base:16
bit,base:16
[SB]
5/7
5/7
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
BMCnd
(2) BMCnd
C
b7
b0 b7
0 1 1
Cnd
GEU/C
GTU
EQ/Z
N
LTU/NC
LEU
NE/NZ
1 1 1 0
Cnd
CND
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1 0 1
CND
CND
PZ
LE
O
GE
GT
NO
LT
0
1
0
1
0
1
0
b0
1 1
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
1
0
0
1
0
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/1
*1 If the condition is true, the number of cycles above is increased by 1.
BNAND
(1) BNAND
src
b7
b0 b7
0 1 1
1 1
1 1 0 0
src
bit,R0
bit,R1
bit,R2
bit,R3
bit,A0
bit,A1
[A0]
[A1]
bit,Rn
bit,An
[An]
b0
1 0 1
0
0
0
0
0
0
0
0
SRC
000
001
010
011
100
101
110
111
SRC
src code
(
)
dsp8
dsp16
src
base:8[A0]
base:8[An]
base:8[A1]
bit,base:8[SB]
bit,base:8
bit,base:8[FB]
[SB/FB]
base:16[A0]
base:16[An]
base:16[A1]
bit,base:16[SB] bit,base:16[SB]
bit,base:16
bit,base:16
1
1
1
1
1
1
1
1
SRC
000
001
010
011
100
101
110
111
[ Number of Bytes/Number of Cycles ]
src
Bytes/Cycles
bit,Rn bit,An
3/3
3/3
[An]
base:8
[An]
bit,base:8
[SB/FB]
base:16
[An]
2/7
3/7
3/4
4/7
153
bit,base:16
bit,base:16
[SB]
4/4
4/4
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
BNOR
(1) BNOR
src
b7
b0 b7
0 1 1
1 1 1
1 0 0
src
bit,R0
bit,R1
bit,R2
bit,R3
bit,A0
bit,A1
[A0]
[A1]
bit,Rn
bit,An
[An]
b0
1 1 1
0
0
0
0
0
0
0
0
SRC
000
001
010
011
100
101
110
111
SRC
src code
(
)
dsp8
dsp16
src
base:8[A0]
base:8[An]
base:8[A1]
bit,base:8[SB]
bit,base:8
bit,base:8[FB]
[SB/FB]
base:16[A0]
base:16[An]
base:16[A1]
bit,base:16[SB] bit,base:16[SB]
bit,base:16
bit,base:16
1
1
1
1
1
1
1
1
SRC
000
001
010
011
100
101
110
111
[ Number of Bytes/Number of Cycles ]
src
bit,Rn bit,An
Bytes/Cycles
3/3
3/3
[An]
base:8
[An]
bit,base:8
[SB/FB]
base:16
[An]
2/7
3/7
3/4
4/7
bit,base:16
bit,base:16
[SB]
4/4
4/4
BNOT
(1) BNOT:G dest
b7
b0 b7
0 1 1
1 1 1 1
0 1
dest
bit,R0
bit,R1
bit,R2
bit,R3
bit,A0
bit,A1
[A0]
[A1]
bit,Rn
bit,An
[An]
dest code
b0
0 1 0
DEST
0000
0001
0010
0011
0100
0101
0110
0111
DEST
(
)
dsp8
dsp16
dest
base:8[A0]
base:8[An]
base:8[A1]
bit,base:8[SB]
bit,base:8
bit,base:8[FB]
[SB/FB]
base:16[A0]
base:16[An]
base:16[A1]
bit,base:16[SB] bit,base:16[SB]
bit,base:16
bit,base:16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
bit,Rn bit,An
3/2
3/2
[An]
2/6
base:8
[An]
3/6
154
bit,base:8
[SB/FB]
3/3
base:16
[An]
4/6
bit,base:16
bit,base:16
[SB]
4/3
4/3
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
BNOT
(2) BNOT:S bit, base:11[SB]
b7
dest code
b0
0 1 0
1 0
dsp8
BIT
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/3
BNTST
(1) BNTST
src
b7
b0 b7
0 1 1
1 1 1 1
0 0
src
bit,R0
bit,R1
bit,R2
bit,R3
bit,A0
bit,A1
[A0]
[A1]
bit,Rn
bit,An
[An]
b0
0 1 1
0
0
0
0
0
0
0
0
SRC
000
001
010
011
100
101
110
111
SRC
src code
(
)
dsp8
dsp16
src
base:8[A0]
base:8[An]
base:8[A1]
bit,base:8[SB]
bit,base:8
bit,base:8[FB]
[SB/FB]
base:16[A0]
base:16[An]
base:16[A1]
bit,base:16[SB] bit,base:16[SB]
bit,base:16
bit,base:16
1
1
1
1
1
1
1
1
SRC
000
001
010
011
100
101
110
111
[ Number of Bytes/Number of Cycles ]
src
Bytes/Cycles
bit,Rn bit,An
3/3
3/3
[An]
2/7
base:8
[An]
3/7
155
bit,base:8
[SB/FB]
3/4
base:16
[An]
4/7
bit,base:16
bit,base:16
[SB]
4/4
4/4
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
BNXOR
(1) BNXOR
src
b7
b0 b7
0 1 1
1 1 1 1 0 1
src
bit,R0
bit,R1
bit,R2
bit,R3
bit,A0
bit,A1
[A0]
[A1]
bit,Rn
bit,An
[An]
b0
1 0 1
0
0
0
0
0
0
0
0
SRC
000
001
010
011
100
101
110
111
SRC
src code
(
)
dsp8
dsp16
src
base:8[A0]
base:8[An]
base:8[A1]
bit,base:8[SB]
bit,base:8
bit,base:8[FB]
[SB/FB]
base:16[A0]
base:16[An]
base:16[A1]
bit,base:16[SB] bit,base:16[SB]
bit,base:16
bit,base:16
1
1
1
1
1
1
1
1
SRC
000
001
010
011
100
101
110
111
[ Number of Bytes/Number of Cycles ]
bit,Rn bit,An
src
Bytes/Cycles
3/3
3/3
[An]
base:8
[An]
bit,base:8
[SB/FB]
base:16
[An]
2/7
3/7
3/4
4/7
bit,base:16
bit,base:16
[SB]
4/4
4/4
BOR
(1) BOR
src
b7
b0 b7
0 1 1
1 1 1 1
0 0
src
bit,R0
bit,R1
bit,R2
bit,R3
bit,A0
bit,A1
[A0]
[A1]
bit,Rn
bit,An
[An]
src code
b0
1 1 0
0
0
0
0
0
0
0
0
SRC
000
001
010
011
100
101
110
111
SRC
(
)
dsp8
dsp16
src
base:8[A0]
base:8[An]
base:8[A1]
bit,base:8[SB]
bit,base:8
bit,base:8[FB]
[SB/FB]
base:16[A0]
base:16[An]
base:16[A1]
bit,base:16[SB] bit,base:16[SB]
bit,base:16
bit,base:16
1
1
1
1
1
1
1
1
SRC
000
001
010
011
100
101
110
111
[ Number of Bytes/Number of Cycles ]
src
Bytes/Cycles
bit,Rn bit,An
3/3
3/3
[An]
base:8
[An]
bit,base:8
[SB/FB]
base:16
[An]
2/7
3/7
3/4
4/7
156
bit,base:16
bit,base:16
[SB]
4/4
4/4
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
BRK
(1) BRK
b7
b0
0 0 0
0 0
0 0 0
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
1/27
*1 If you specify the target address of the BRK interrupt by use of the interrupt table register (INTB), the
number of cycles shown in the table increases by two. At this time, set FF16 in addresses FFFE416
through FFFE716.
BSET
(1) BSET:G dest
b7
b0 b7
0 1 1
1 1
1 1 0 1
dest
bit,R0
bit,R1
bit,R2
bit,R3
bit,A0
bit,A1
[A0]
[A1]
bit,Rn
bit,An
[An]
dest code
b0
0 0 1
DEST
0000
0001
0010
0011
0100
0101
0110
0111
DEST
(
)
dsp8
dsp16
dest
base:8[A0]
base:8[An]
base:8[A1]
bit,base:8[SB]
bit,base:8
bit,base:8[FB]
[SB/FB]
base:16[A0]
base:16[An]
base:16[A1]
bit,base:16[SB] bit,base:16[SB]
bit,base:16
bit,base:16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
bit,Rn bit,An
3/2
3/2
[An]
base:8
[An]
bit,base:8
[SB/FB]
base:16
[An]
2/6
3/6
3/3
4/6
157
bit,base:16
bit,base:16
[SB]
4/3
4/3
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
BSET
(2) BSET:S bit, base:11[SB]
b7
dest code
b0
0 1 0
0 1
BIT
dsp8
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/3
BTST
(1) BTST:G src
b7
b0 b7
0 1 1
1 1 1
1 0 1
src
bit,R0
bit,R1
bit,R2
bit,R3
bit,A0
bit,A1
[A0]
[A1]
bit,Rn
bit,An
[An]
src code
b0
0 1 1
0
0
0
0
0
0
0
0
SRC
000
001
010
011
100
101
110
111
SRC
(
)
dsp8
dsp16
src
base:8[A0]
base:8[An]
base:8[A1]
bit,base:8[SB]
bit,base:8
bit,base:8[FB]
[SB/FB]
base:16[A0]
base:16[An]
base:16[A1]
bit,base:16[SB] bit,base:16[SB]
bit,base:16
bit,base:16
1
1
1
1
1
1
1
1
SRC
000
001
010
011
100
101
110
111
[ Number of Bytes/Number of Cycles ]
src
Bytes/Cycles
bit,Rn bit,An
3/2
3/2
[An]
base:8
[An]
bit,base:8
[SB/FB]
base:16
[An]
2/6
3/6
3/3
4/6
158
bit,base:16
bit,base:16
[SB]
4/3
4/3
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
BTST
(2) BTST:S
bit, base:11[SB]
b7
src code
b0
0 1 0
1 1
BIT
dsp8
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/3
BTSTC
(1) BTSTC
dest
dest code
b7
b0 b7
0 1 1
1 1 1 1
0 0
dest
bit,R0
bit,R1
bit,R2
bit,R3
bit,A0
bit,A1
[A0]
[A1]
bit,Rn
bit,An
[An]
b0
0 0 0
DEST
0000
0001
0010
0011
0100
0101
0110
0111
DEST
(
)
dsp8
dsp16
dest
base:8[A0]
base:8[An]
base:8[A1]
bit,base:8[SB]
bit,base:8
bit,base:8[FB]
[SB/FB]
base:16[A0]
base:16[An]
base:16[A1]
bit,base:16[SB] bit,base:16[SB]
bit,base:16
bit,base:16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
bit,Rn bit,An
3/3
3/3
[An]
base:8
[An]
bit,base:8
[SB/FB]
base:16
[An]
2/7
3/7
3/4
4/7
159
bit,base:16
bit,base:16
[SB]
4/4
4/4
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
BTSTS
(1) BTSTS
dest
b7
b0 b7
0 1 1
1 1 1
1 0 0
dest
bit,R0
bit,R1
bit,R2
bit,R3
bit,A0
bit,A1
[A0]
[A1]
bit,Rn
bit,An
[An]
dest code
b0
0 0 1
DEST
0000
0001
0010
0011
0100
0101
0110
0111
(
DEST
)
dsp8
dsp16
dest
base:8[A0]
base:8[An]
base:8[A1]
bit,base:8[SB]
bit,base:8
bit,base:8[FB]
[SB/FB]
base:16[A0]
base:16[An]
base:16[A1]
bit,base:16[SB] bit,base:16[SB]
bit,base:16
bit,base:16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
bit,Rn bit,An
3/3
Bytes/Cycles
3/3
[An]
base:8
[An]
bit,base:8
[SB/FB]
base:16
[An]
2/7
3/7
3/4
4/7
bit,base:16
bit,base:16
[SB]
4/4
4/4
BXOR
(1) BXOR
src
b7
b0 b7
0 1 1
1 1 1
1 0 1
src
bit,R0
bit,R1
bit,R2
bit,R3
bit,A0
bit,A1
[A0]
[A1]
bit,Rn
bit,An
[An]
src code
b0
1 0 0
0
0
0
0
0
0
0
0
SRC
000
001
010
011
100
101
110
111
(
SRC
)
dsp8
dsp16
src
base:8[A0]
base:8[An]
base:8[A1]
bit,base:8[SB]
bit,base:8
bit,base:8[FB]
[SB/FB]
base:16[A0]
base:16[An]
base:16[A1]
bit,base:16[SB] bit,base:16[SB]
bit,base:16
bit,base:16
1
1
1
1
1
1
1
1
SRC
000
001
010
011
100
101
110
111
[ Number of Bytes/Number of Cycles ]
src
Bytes/Cycles
bit,Rn bit,An
3/3
3/3
[An]
base:8
[An]
bit,base:8
[SB/FB]
base:16
[An]
2/7
3/7
3/4
4/7
160
bit,base:16
bit,base:16
[SB]
4/4
4/4
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
CMP
(1) CMP.size:G
#IMM, dest
b7
b0 b7
0 1 1
1 0 1 1 SIZE 1
.size SIZE
.B
0
.W
1
Rn
An
[An]
dest code
b0
0 0 0
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
DEST
(
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dsp8
dsp16/abs16
)
#IMM8
#IMM16
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Rn
An
[An] dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/2
3/2
3/4
4/4
4/4
5/4
5/4
Bytes/Cycles
*1 If the size specifier (.size) is (.W), the number of bytes above is increased by 1.
161
abs16
5/4
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
CMP
(2) CMP.size:Q
#IMM, dest
b7
b0 b7
1 1 0
1 0
.size SIZE
.B
0
.W
1
0 0 SIZE
#IMM
0
+1
+2
+3
+4
+5
+6
+7
IMM4
IMM4
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
An
[An]
(
DEST
#IMM
–8
–7
–6
–5
–4
–3
–2
–1
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
dest code
b0
dsp8
dsp16/abs16
)
IMM4
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
2/1
An
2/1
[An]
2/3
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
4/3
3/3
3/3
4/3
162
abs16
4/3
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
CMP
(3) CMP.B:S #IMM8, dest
b7
dest code
b0
1 1 1
0 0
DEST
dest
Rn
dsp:8[SB/FB]
abs16
(
#IMM8
dsp8
abs16
DEST
R0H
R0L
dsp:8[SB]
dsp:8[FB]
abs16
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
2/1
dsp:8[SB/FB]
3/3
abs16
4/3
163
)
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
CMP
(4) CMP.size:G
src, dest
b7
1 1 0
b0 b7
0 0
.size SIZE
.B
0
.W
1
0
0 SIZE
SRC
An
[An]
(
DEST
src/dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
src code
b0
SRC/DEST
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
dsp8
dsp16/abs16
dest code
)(
)
dsp8
dsp16/abs16
src/dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
SRC/DEST
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
src
dest
Rn
An
[An]
dsp:8[An]
dsp:8[SB/FB]
dsp:16[An]
dsp:16[SB]
abs16
Rn
2/2
2/2
2/3
3/3
3/3
4/3
4/3
4/3
An
2/2
2/2
2/3
3/3
3/3
4/3
4/3
4/3
[An]
2/3
2/3
2/4
3/4
3/4
4/4
4/4
4/4
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/3
3/3
4/3
4/3
3/3
3/3
4/3
4/3
3/4
3/4
4/4
4/4
4/4
4/4
5/4
5/4
4/4
4/4
5/4
5/4
5/4
5/4
6/4
6/4
5/4
5/4
6/4
6/4
5/4
5/4
6/4
6/4
164
abs16
4/3
4/3
4/4
5/4
5/4
6/4
6/4
6/4
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
CMP
(5) CMP.B:S src, R0L/R0H
b7
0 0 1
b0
1 1 DEST SRC
src code
(
src
Rn
dsp:8[SB/FB]
abs16
dsp8
abs16
)
SRC
R0L/R0H
dsp:8[SB]
dsp:8[FB]
abs16
dest
0
1
0
1
R0L
R0H
dsp:8[SB/FB]
abs16
2/3
3/3
0
0
1
1
DEST
0
1
[ Number of Bytes/Number of Cycles ]
src
Bytes/Cycles
Rn
1/2
DADC
(1) DADC.B #IMM8, R0L
b7
0 1 1
b0 b7
1 1 1 0
0 1
b0
1 1 0
1 1
1
0
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
3/5
165
#IMM8
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
DADC
(2) DADC.W #IMM16, R0
b7
0 1 1
b0 b7
1 1 1 0
1 1
b0
1 1 0
1 1
1
0
0 1
1
0
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
4/5
DADC
(3) DADC.B R0H, R0L
b7
0 1 1
b0 b7
1 1 1
0 0 1
b0
1 1 0
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/5
166
#IMM16
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
DADC
(4) DADC.W R1, R0
b7
0 1 1
b0 b7
1 1 1 0
1 1
b0
1 1 0
0 1
1
0
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/5
DADD
(1) DADD.B #IMM8, R0L
b7
0 1 1
b0 b7
1 1
1 0 0 1
b0
1 1 0
1 1
0
0
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
3/5
167
#IMM8
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
DADD
(2) DADD.W #IMM16, R0
b7
0 1 1
b0 b7
1 1 1 0
1 1
b0
1 1 0
1 1
0
0
0 1
0
0
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
4/5
DADD
(3) DADD.B R0H, R0L
b7
0 1 1
b0 b7
1 1 1
0 0 1
b0
1 1 0
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/5
168
#IMM16
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
DADD
(4) DADD.W R1, R0
b7
0 1 1
b0 b7
1 1
1 0 1 1
b0
1 1 0
0 1
0
0
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/5
DEC
(1) DEC.B
dest
b7
1 0 1
b0
0 1
DEST
dest
Rn
dsp:8[SB/FB]
abs16
dest code
(
dsp8
abs16
)
DEST
R0H
R0L
dsp:8[SB]
dsp:8[FB]
abs16
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
1/1
dsp:8[SB/FB]
2/3
abs16
3/3
169
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
DEC
(2) DEC.W
dest
b7
b0
1 1 1
1 DEST 0
dest
1 0
DEST
0
1
A0
A1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
1/1
DIV
(1) DIV.size #IMM
b7
0 1 1
b0 b7
1 1 1 0 SIZE 1
b0
1 1 0
0 0
0
1
#IMM8
#IMM16
.size SIZE
.B
0
.W
1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
3/22
*1 If the size specifier (.size) is (.W), the number of bytes and cycles above are increased by 1 and 6,
respectively.
*2 The number of cycles may decrease when an overflow occurs or depending on the value of the divisor or
dividend.
170
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
DIV
(2) DIV.size src
b7
b0 b7
0 1 1
1 0
.size SIZE
.B
0
.W
1
1 1 SIZE 1 1
0 1
An
[An]
(
SRC
SRC
src
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
src code
b0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
dsp8
dsp16/abs16
)
src
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
1
1
1
1
1
1
1
1
SRC
000
001
010
011
100
101
110
111
[ Number of Bytes/Number of Cycles ]
src
Bytes/Cycles
Rn
2/22
An
2/22
[An]
2/24
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/24
3/24
4/24
4/24
abs16
4/24
*1 If the size specifier (.size) is (.W), the number of cycles above is increased by 6.
*2 The number of cycles may decrease when an overflow occurs or depending on the value of the divisor or
dividend.
DIVU
(1) DIVU.size #IMM
b7
0 1 1
b0 b7
1 1
1 0 SIZE 1
b0
1 1 0
0 0
0
0
#IMM8
#IMM16
.size SIZE
.B
0
.W
1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
3/18
*2 The number of cycles may decrease when an overflow occurs or depending on the value of the divisor or
dividend.
*3 If the size specifier (.size) is (.W), the number of bytes and cycles above are increased by 1 and 7,
respectively.
171
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
DIVU
(2) DIVU.size src
b7
b0 b7
0 1 1
1 0
.size SIZE
.B
0
.W
1
1
b0
1 SIZE 1 1
0 0
SRC
An
[An]
(
SRC
src
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
src code
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
dsp8
dsp16/abs16
)
src
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
1
1
1
1
1
1
1
1
SRC
000
001
010
011
100
101
110
111
[ Number of Bytes/Number of Cycles ]
src
Rn
Bytes/Cycles
2/18
An
2/18
[An]
2/20
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/20
3/20
4/20
4/20
abs16
4/20
*1 If the size specifier (.size) is (.W), the number of cycles above is increased by 7.
*2 The number of cycles may decrease when an overflow occurs or depending on the value of the divisor or
dividend.
DIVX
(1) DIVX.size #IMM
b7
0 1 1
b0 b7
1 1
1 0 SIZE 1
b0
1 1 0
0 0
1
1
#IMM8
#IMM16
.size SIZE
.B
0
.W
1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
3/22
*2 The number of cycles may decrease when an overflow occurs or depending on the value of the divisor or
dividend.
*3 If the size specifier (.size) is (.W), the number of bytes and cycles above are increased by 1 and 6,
respectively.
172
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
DIVX
(2) DIVX.size src
b7
b0 b7
0 1 1
1 0
.size SIZE
.B
0
.W
1
1
1 SIZE 1 0
0 1
An
[An]
(
SRC
SRC
src
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
src code
b0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
dsp8
dsp16/abs16
)
src
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
1
1
1
1
1
1
1
1
SRC
000
001
010
011
100
101
110
111
[ Number of Bytes/Number of Cycles ]
src
Bytes/Cycles
Rn
2/22
An
2/22
[An]
2/24
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
4/24
3/24
3/24
4/24
abs16
4/24
*1 If the size specifier (.size) is (.W), the number of cycles above is increased by 6.
*2 The number of cycles may decrease when an overflow occurs or depending on the value of the divisor or
dividend.
DSBB
(1) DSBB.B #IMM8, R0L
b7
0 1 1
b0 b7
1 1
1 0 0 1
b0
1 1 0
1 1
1
1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
3/4
173
#IMM8
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
DSBB
(2) DSBB.W #IMM16, R0
b7
0 1 1
b0 b7
1 1
1 0 1 1
b0
1 1 0
1 1
1
1
0 1
1
1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
4/4
DSBB
(3) DSBB.B R0H, R0L
b7
0 1 1
b0 b7
1 1 1 0
0 1
b0
1 1 0
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/4
174
#IMM16
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
DSBB
(4) DSBB.W R1, R0
b7
0 1 1
b0 b7
1 1
1 0 1 1
b0
1 1 0
0 1
1
1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/4
DSUB
(1) DSUB.B #IMM8, R0L
b7
0 1 1
b0 b7
1 1
1 0 0 1
b0
1 1 0
1 1
0
1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
3/4
175
#IMM8
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
DSUB
(2) DSUB.W #IMM16, R0
b7
0 1 1
b0 b7
1 1
1 0 1 1
b0
1 1 0
1 1
0
1
0 1
0
1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
4/4
DSUB
(3) DSUB.B R0H, R0L
b7
0 1 1
b0 b7
1 1
1 0 0 1
b0
1 1 0
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/4
176
#IMM16
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
DSUB
(4) DSUB.W R1, R0
b7
0 1 1
b0 b7
1 1
1 0 1 1
b0
1 1 0
0 1
0
1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/4
ENTER
(1) ENTER
#IMM8
b7
0 1 1
b0 b7
1 1
1 0 0 1
b0
1 1 1
0 0
1
0
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
3/4
177
#IMM8
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
EXITD
(1) EXITD
b7
b0 b7
0 1 1
1 1
1 0 1
1
b0
1 1 1
0 0
1
0
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/9
EXTS
(1) EXTS.B
dest
b7
b0 b7
0 1 1
1 1 1 0
dest
R0L
--R1L
------[A0]
[A1]
Rn
--[An]
0 0
b0
1 1 0
DEST
0000
0001
0010
0011
0100
0101
0110
0111
DEST
dest code
(
dsp8
dsp16/abs16
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
)
DEST
1000
1001
1010
1011
1100
1101
1110
1111
*1 Marked by --- cannot be selected.
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
[An]
2/3
2/5
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/5
3/5
4/5
4/5
178
abs16
4/5
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
EXTS
(2) EXTS.W R0
b7
b0 b7
0 1 1
1 1
1 0 0 1
b0
1 1 1
0 0
1
1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/3
FCLR
(1) FCLR
dest
b7
b0 b7
1 1 1
0 1
dest
DEST
C
D
Z
S
B
O
I
U
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 1 1 0
b0
DEST
0 1
0 1
0
1
0
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/2
179
Chapter 4
Instruction Code/Number of Cycles
FSET
(1) FSET
dest
b7
b0 b7
1 1 1
0 1
dest
DEST
C
D
Z
S
B
O
I
U
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 1 1 0
b0
DEST
0 1
0 0
0
1
0
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/2
INC
(1) INC.B
dest
b7
b0
1 0 1
0 0
DEST
dest
Rn
dsp:8[SB/FB]
abs16
dest code
(
dsp8
abs16
)
DEST
R0H
R0L
dsp:8[SB]
dsp:8[FB]
abs16
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
1/1
dsp:8[SB/FB]
2/3
abs16
3/3
180
4.2
Instruction Code/Number of Cycles
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
INC
(2) INC.W
dest
b7
b0
1 0 1
1 DEST 0 1 0
dest
DEST
0
1
A0
A1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
1/1
INT
(1) INT #IMM
b7
1 1 1
b0
0 1
0 1 1
1 1 #IMM
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/19
181
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
INTO
(1) INTO
b7
b0
1 1 1
1 0
1 1 0
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
1/1
*1 If the O flag = 1, the number of cycles above is increased by 19.
JCnd
(1) JCnd
label
b7
b0
0 1 1
0 1
CND
label code
dsp8
dsp8 = address indicated by label – (start address of instruction + 1)
Cnd
GEU/C
GTU
EQ/Z
N
Cnd
CND
0
0
0
0
0
0
1
1
0
1
0
1
LTU/NC
LEU
NE/NZ
PZ
CND
1
1
1
1
0
0
1
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/2
*2 If branched to label, the number of cycles above is increased by 2.
182
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
JCnd
(2) JCnd
label
b7
b0 b7
0 1 1
1 1
1 0 1 1
b0
1 0 0
CND
label code
dsp8
dsp8 =address indicated by label – (start address of instruction + 2)
Cnd
LE
O
GE
Cnd
CND
1 0 0 0 GT
1 0 0 1 NO
1 0 1 0 LT
CND
1100
1101
1110
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
3/2
*1 If branched to label, the number of cycles above is increased by 2.
JMP
(1) JMP.S
label
b7
0 1 1
b0
0 0
dsp
dsp = address indicated by label – (start address of instruction + 2)
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
1/5
183
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
JMP
(2) JMP.B
label
b7
b0
1 1 1
1 1 1 1
0
label code
dsp8
dsp8 = address indicated by label – (start address of instruction + 1)
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/4
JMP
(3) JMP.W
label
b7
1 1 1
b0
1 0 1 0
label code
0
dsp16
dsp16 = address indicated by label – (start address of instruction + 1)
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
3/4
184
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
JMP
(4) JMP.A
label
b7
label code
b0
1 1 1
1 1
abs20
1 0 0
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
4/4
JMPI
(1) JMPI.W
src
b7
b0 b7
0 1 1
1 1 1 0
1 0
b0
0 1 0
SRC
src code
dsp8
dsp16/abs16
dsp20
src
R0
R1
R2
R3
A0
A1
[A0]
[A1]
Rn
An
[An]
0
0
0
0
0
0
0
0
SRC
000
001
010
011
100
101
110
111
src
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:20[A0]
dsp:20[An]
dsp:20[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
1
1
1
1
1
1
1
1
SRC
000
001
010
011
100
101
110
111
[ Number of Bytes/Number of Cycles ]
src
Bytes/Cycles
Rn
2/7
An
[An]
2/7
2/11
dsp:8[An] dsp:8[SB/FB] dsp:20[An] dsp:16[SB]
3/11
4/11
3/11
5/11
185
abs16
4/11
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
JMPI
(2) JMPI.A
src
b7
b0 b7
0 1 1
1 1 1 0
1 0
b0
0 0 0
SRC
src code
dsp8
dsp16/abs16
dsp20
src
SRC
0000
0001
0010
0011
0100
0101
0110
0111
R2R0
R3R1
Rn
----A1A0
An
--[A0]
[An]
[A1]
*1 Marked by --- cannot be selected.
src
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:20[A0]
dsp:20[An]
dsp:20[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
SRC
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
src
Bytes/Cycles
Rn
2/6
An
2/6
[An]
2/10
dsp:8[An] dsp:8[SB/FB] dsp:20[An] dsp:16[SB]
3/10
3/10
5/10
4/10
186
abs16
4/10
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
JSR
(1) JSR.W
label
b7
1 1 1
b0
1 0
1 0 1
label code
dsp16
dsp16 = address indicated by label – (start address of instruction + 1)
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
3/8
JSR
(2) JSR.A
label
b7
1 1 1
b0
1 1
label code
1 0 1
abs20
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
4/9
187
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
JSRI
(1) JSRI.W
src
b7
b0 b7
0 1 1
1 1
1 0 1 0
b0
0 1 1
src code
dsp8
SRC
dsp16/abs16
dsp20
src
R0
R1
R2
R3
A0
A1
[A0]
[A1]
Rn
An
[An]
0
0
0
0
0
0
0
0
SRC
000
001
010
011
100
101
110
111
src
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:20[A0]
dsp:20[An]
dsp:20[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
1
1
1
1
1
1
1
1
SRC
000
001
010
011
100
101
110
111
[ Number of Bytes/Number of Cycles ]
src
Rn
2/11
Bytes/Cycles
An
2/11
[An]
2/15
dsp:8[An] dsp:8[SB/FB] dsp:20[An] dsp:16[SB]
3/15
3/15
5/15
4/15
abs16
4/15
JSRI
(2) JSRI.A
src
b7
b0 b7
0 1 1
1 1
1 0 1 0
b0
0 0 1
SRC
src code
dsp8
dsp16/abs16
dsp20
src
R2R0
R3R1
----A1A0
--[A0]
[A1]
Rn
An
[An]
0
0
0
0
0
0
0
0
SRC
000
001
010
011
100
101
110
111
src
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:20[A0]
dsp:20[An]
dsp:20[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
1
1
1
1
1
1
1
1
SRC
000
001
010
011
100
101
110
111
*1 Marked by --- cannot be selected.
[ Number of Bytes/Number of Cycles ]
src
Bytes/Cycles
Rn
2/11
An
2/11
[An]
2/15
dsp:8[An] dsp:8[SB/FB] dsp:20[An] dsp:16[SB]
3/15
3/15
5/15
4/15
188
abs16
4/15
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
LDC
(1) LDC #IMM16, dest
b7
b0 b7
1 1 1
0 1
dest
0 1 1 0
b0
DEST
0 0
0
#IMM16
0
DEST
--INTBL
INTBH
FLG
ISP
SP
SB
FB
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
*1 Marked by --- cannot be selected.
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
4/2
LDC
(2) LDC src, dest
b7
b0 b7
0 1 1
1 1
0 1 0 1
R0
R1
R2
R3
A0
A1
[A0]
[A1]
An
[An]
DEST
SRC
0000
0001
0010
0011
0100
0101
0110
0111
src
Rn
b0
SRC
Bytes/Cycles
Rn
2/1
An
2/1
[An]
2/3
(
dsp8
dsp16/abs16
src
dsp:8[An]
dsp:8[SB/FB]
dsp:16[An]
dsp:16[SB]
abs16
dsp:8[A0]
dsp:8[A1]
dsp:8[SB]
dsp:8[FB]
dsp:16[A0]
dsp:16[A1]
dsp:16[SB]
abs16
SRC
1000
1001
1010
1011
1100
1101
1110
1111
)
dest
--INTBL
INTBH
FLG
ISP
SP
SB
FB
DEST
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
*1 Marked by --- cannot be
selected.
[ Number of Bytes/Number of Cycles ]
src
src code
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/3
3/3
4/3
4/3
189
abs16
4/3
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
LDCTX
(1) LDCTX
abs16, abs20
b7
0 1 1
b0 b7
1 1
1 0 0 1
b0
1 1 1
0 0
0
0
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
7/11+2
m
*2 m denotes the number of transfers performed.
190
abs16
abs20
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
LDE
(1) LDE.size abs20, dest
b7
b0 b7
0 1 1
1 0
.size SIZE
.B
0
.W
1
1 0 SIZE 1
b0
0 0 0
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
DEST
src code
dest code
(
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dsp8
dsp16/abs16
)
abs20
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
5/4
An
5/4
[An]
5/5
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
6/5
6/5
7/5
7/5
abs16
7/5
LDE
(2) LDE.size dsp:20[A0], dest
b7
b0 b7
0 1 1
1 0
.size SIZE
.B
0
.W
1
1 0 SIZE 1
0 0 1
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
dest code
b0
DEST
(
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dsp8
dsp16/abs16
src code
)
dsp20
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
5/4
An
5/4
[An]
5/5
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
6/5
6/5
7/5
7/5
191
abs16
7/5
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
LDE
(3) LDE.size [A1A0], dest
b7
b0 b7
0 1 1
1 0
1 0 SIZE 1
.size SIZE
.B
0
.W
1
b0
0 1 0
DEST
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
dest code
(
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dsp8
dsp16/abs16
)
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
2/4
An
2/4
[An]
2/5
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/5
3/5
4/5
4/5
LDINTB
(1) LDINTB #IMM
b7
1 1 1
0 0 0
1 1 1
b0 b7
0 1 0 1 1 0 0 1 0
0
#IMM1
0 0 0 0
0 1 0 1 1 0 0 0 1
#IMM2
b0
0 0
0 0
0 0
0
0
0
0
0
0
*1 #IMM1 indicates the 4 high-order bits of #IMM.
#IMM2 indicates the 16 low-order bits of #IMM.
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
8/4
192
abs16
4/5
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
LDIPL
(1) LDIPL
#IMM
b7
b0 b7
0 1 1
1 1
1 0 1 1
b0
0 1 0
0
#IMM
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/2
MOV
(1) MOV.size:G
#IMM, dest
b7
b0 b7
0 1 1
1 0
.size SIZE
.B
0
.W
1
1 0 SIZE 1
Rn
An
[An]
b0
1 0 0
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
DEST
dest code
(
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dsp8
dsp16/abs16
)
#IMM8
#IMM16
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Rn
An
[An] dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/2
3/2
3/3
4/3
4/3
5/3
5/3
Bytes/Cycles
*1 If the size specifier (.size) is (.W), the number of bytes above is increased by 1.
193
abs16
5/3
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
MOV
(2) MOV.size:Q
#IMM, dest
b7
b0 b7
1 1 0
1 1 0
.size SIZE
.B
0
.W
1
0 SIZE
#IMM
0
+1
+2
+3
+4
+5
+6
+7
IMM4
0000
0001
0010
0011
0100
0101
0110
0111
An
[An]
(
DEST
#IMM
–8
–7
–6
–5
–4
–3
–2
–1
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
dest code
b0
IMM4
dsp8
dsp16/abs16
)
IMM4
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
2/1
An
2/1
[An]
2/2
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
4/2
3/2
3/2
4/2
194
abs16
4/2
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
MOV
(3) MOV.B:S #IMM8, dest
b7
dest code
b0
1 1 0
0 0
DEST
dest
Rn
dsp:8[SB/FB]
abs16
(
#IMM8
dsp8
abs16
DEST
R0H
R0L
dsp:8[SB]
dsp:8[FB]
abs16
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
2/1
dsp:8[SB/FB]
3/2
abs16
4/2
195
)
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
MOV
(4) MOV.size:S
#IMM, dest
b7
b0
1 SIZE 1
#IMM8
0 DEST 0 1 0
#IMM16
.size SIZE
.B
1
.W
0
dest
DEST
0
1
A0
A1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/1
*1 If the size specifier (.size) is (.W), the number of bytes and cycles above are increased by 1 and 1,
respectively.
MOV
(5) MOV.B:Z #0, dest
b7
b0
1 0 1
1 0
DEST
dest
Rn
dsp:8[SB/FB]
abs16
dest code
(
dsp8
abs16
)
DEST
R0H
R0L
dsp:8[SB]
dsp:8[FB]
abs16
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
1/1
dsp:8[SB/FB]
2/2
abs16
3/2
196
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
MOV
(6) MOV.size:G
src, dest
b7
0 1 1
b0 b7
1 0
.size SIZE
.B
0
.W
1
0 1 SIZE
SRC
An
[An]
(
DEST
src/dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
src code
b0
SRC/DEST
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
dsp8
dsp16/abs16
dest code
)(
)
dsp8
dsp16/abs16
src/dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
SRC/DEST
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
src
dest
Rn
An
[An]
dsp:8[An]
dsp:8[SB/FB]
dsp:16[An]
dsp:16[SB]
abs16
Rn
2/2
2/2
2/3
3/3
3/3
4/3
4/3
4/3
An
2/2
2/2
2/3
3/3
3/3
4/3
4/3
4/3
[An]
2/2
2/2
2/3
3/3
3/3
4/3
4/3
4/3
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/2
3/2
4/2
4/2
3/2
3/2
4/2
4/2
3/3
3/3
4/3
4/3
4/3
4/3
5/3
5/3
4/3
4/3
5/3
5/3
5/3
5/3
6/3
6/3
5/3
5/3
6/3
6/3
5/3
5/3
6/3
6/3
197
abs16
4/2
4/2
4/3
5/3
5/3
6/3
6/3
6/3
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
MOV
(7) MOV.B:S src, dest
b7
b0
0 0 1
1 0 DEST SRC
src code
(
abs16
src
Rn
dsp:8[SB/FB]
abs16
)
dsp8
SRC
R0L/R0H
dsp:8[SB]
dsp:8[FB]
abs16
0
0
1
1
dest
DEST
0
1
A0
A1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
src
Bytes/Cycles
dsp:8[SB/FB]
Rn
1/2
abs16
3/3
2/3
MOV
(8) MOV.B:S R0L/R0H, dest
b7
b0
0 0 0
0 0 SRC DEST
src
R0L
R0H
dest code
(
SRC
0
1
)
dsp8
abs16
dest
dsp:8[SB/FB]
abs16
DEST
dsp:8[SB]
dsp:8[FB]
abs16
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
dsp:8[SB/FB]
2/2
abs16
3/2
198
0
1
1
1
0
1
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
MOV
(9) MOV.B:S src, R0L/R0H
b7
b0
0 0 0
0 1 DEST SRC
src code
(
src
Rn
dsp:8[SB/FB]
abs16
)
dsp8
abs16
SRC
R0L/R0H
dsp:8[SB]
dsp:8[FB]
abs16
dest
0
1
0
1
R0L
R0H
dsp:8[SB/FB]
abs16
3/3
0
0
1
1
DEST
0
1
[ Number of Bytes/Number of Cycles ]
src
Rn
1/2
Bytes/Cycles
2/3
MOV
(10) MOV.size:G dsp:8[SP], dest
b7
b0 b7
0 1 1
1 0
.size SIZE
.B
0
.W
1
1 0 SIZE 1
b0
0 1 1
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
DEST
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dest code
(
dsp8
dsp16/abs16
)
src code
dsp8
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
3/2
An
3/2
[An]
3/3
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
4/3
4/3
5/3
5/3
199
abs16
5/3
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
MOV
(11) MOV.size:G src, dsp:8[SP]
b7
b0 b7
0 1 1
1 0 1 0 SIZE 0
.size SIZE
.B
0
.W
1
b0
0 1 1
SRC
src
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
(
SRC
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
dest code
src code
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
dsp8
dsp16/abs16
)
dsp8
src
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
1
1
1
1
1
1
1
1
SRC
000
001
010
011
100
101
110
111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
3/3
An
3/3
[An]
3/4
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
4/4
4/4
5/4
5/4
MOVA
(1) MOVA
src, dest
b7
b0 b7
1 1 1
0 1 0
1 1 0
src
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
b0
DEST
1
1
1
1
1
1
1
1
SRC
000
001
010
011
100
101
110
111
SRC
src code
(
dest
R0
R1
R2
R3
A0
A1
dsp8
dsp16
)
DEST
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
[ Number of Bytes/Number of Cycles ]
src
Bytes/Cycles
dsp:8[An]
3/2
dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/2
4/2
4/2
200
abs16
4/2
abs16
5/4
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
MOVDir
(1) MOVDir R0L, dest
b7
b0 b7
0 1 1
Dir
LL
LH
HL
HH
Rn
An
[An]
1 1
1 0 0 1
dest code
b0
0
DIR
DEST
(
dsp8
dsp16/abs16
)
DIR
0 0
1 0
0 1
1 1
dest
--R0H
R1L
R1H
----[A0]
[A1]
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
*1 Marked by - - - cannot be selected.
[ Number of Bytes/Number of Cycles ]
dest
MOVHH,
MOVLL
MOVHL,
MOVLH
Rn
[An]
2/4
2/5
3/5
3/5
4/5
4/5
4/5
2/7
2/8
3/8
3/8
4/8
4/8
4/8
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
201
abs16
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
MOVDir
(2) MOVDir src, R0L
b7
b0 b7
0 1 1
Dir
LL
LH
HL
HH
1 1
1 0 0 0
b0
0
DIR
SRC
dest code
(
dsp8
dsp16/abs16
)
DIR
0 0
1 0
0 1
1 1
src
SRC
R0L
0000
R0H
0001
Rn
R1L
0010
R1H
0011
--0100
An
--0101
[A0]
0110
[An]
[A1]
0111
*1 Marked by - - - cannot be selected.
src
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
SRC
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
src
MOVHH,
MOVLL
MOVHL,
MOVLH
Rn
[An]
2/3
2/5
3/5
3/5
4/5
4/5
4/5
2/6
2/8
3/8
3/8
4/8
4/8
4/8
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
202
abs16
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
MUL
(1) MUL.size #IMM, dest
b7
b0 b7
0 1 1
1 1
.size SIZE
.B
0
.W
1
1 0 SIZE 0
dest code
b0
1 0 1
DEST
(
dest
DEST
R0L/R0
0000
--- /R1
0001
Rn
R1L/--0010
--0011
A0
0100
An
--0101
[A0]
0110
[An]
[A1]
0111
*1 Marked by - - - cannot be selected.
dsp8
dsp16/abs16
)
#IMM8
#IMM16
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
3/4
An
3/4
[An]
3/5
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
4/5
4/5
5/5
5/5
abs16
5/5
*2 If dest is Rn or An while the size specifier (.size) is (.W), the number of bytes and cycles above are
increased by 1 each.
*3 If dest is neither Rn nor An while the size specifier (.size) is (.W), the number of bytes and cycles
above are increased by 1 and 2, respectively.
203
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
MUL
(2) MUL.size src, dest
b7
0 1 1
b0 b7
1 1
.size SIZE
.B
0
.W
1
0 0 SIZE
b0
SRC
DEST
src
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
src code
(
SRC
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
dest
DEST
R0L/R0
0000
--- /R1
0001
Rn
R1L/--0010
--0011
A0
0100
An
--0101
[A0]
0110
[An]
[A1]
0111
*1 Marked by - - - cannot be selected.
dsp8
dsp16/abs16
dest code
)(
dsp8
dsp16/abs16
)
src
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
1
1
1
1
1
1
1
1
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
SRC
000
001
010
011
100
101
110
111
[ Number of Bytes/Number of Cycles ]
src
dest
Rn
An
[An]
dsp:8[An]
dsp:8[SB/FB]
dsp:16[An]
dsp:16[SB]
abs16
Rn
2/4
2/4
2/6
3/6
3/6
4/6
4/6
4/6
An
2/4
2/5
2/6
3/6
3/6
4/6
4/6
4/6
[An]
2/5
2/5
2/6
3/6
3/6
4/6
4/6
4/6
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/5
3/5
4/5
4/5
3/5
3/5
4/5
4/5
3/6
3/6
4/6
4/6
4/6
4/6
5/6
5/6
4/6
4/6
5/6
5/6
5/6
5/6
6/6
6/6
5/6
5/6
6/6
6/6
5/6
5/6
6/6
6/6
abs16
4/5
4/5
4/6
5/6
5/6
6/6
6/6
6/6
*2 If src is An and dest is Rn while the size specifier (.size) is (.W), the number of cycles above is increased by 1.
*3 If src is not An and dest is Rn or An while the size specifier (.size) is (.W), the number of cycles above is
increased by 1.
*4 If dest is neither Rn nor An while the size specifier (.size) is (.W), the number of cycles above is increased by 2.
204
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
MULU
(1) MULU.size
#IMM, dest
b7
b0 b7
0 1 1
1 1
.size SIZE
.B
0
.W
1
1 0 SIZE 0
b0
1 0 0
DEST
dest code
(
dest
DEST
R0L/R0
0000
--- /R1
0001
Rn
R1L/--0010
--0011
A0
0100
An
--0101
[A0]
0110
[An]
[A1]
0111
*1 Marked by - - - cannot be selected.
dsp8
dsp16/abs16
)
#IMM8
#IMM16
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Numbera of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
3/4
An
3/4
[An]
3/5
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
4/5
4/5
5/5
5/5
abs16
5/5
*2 If dest is Rn or An while the size specifier (.size) is (.W), the number of bytes and cycles above are
increased by 1 each.
*3 If dest is neither Rn nor An while the size specifier (.size) is (.W), the number of bytes and cycles
above are increased by 1 and 2, respectively.
205
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
MULU
(2) MULU.size
src, dest
b7
0 1 1
b0 b7
1 0 0
.size SIZE
.B
0
.W
1
0 SIZE
Rn
An
[An]
Rn
An
[An]
src code
b0
SRC
(
DEST
SRC
dsp8
dsp16/abs16
dest code
)(
dsp8
dsp16/abs16
)
src
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
src
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
1
1
1
1
1
1
1
1
dest
R0L/R0
--- /R1
R1L/----A0
--[A0]
[A1]
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
SRC
000
001
010
011
100
101
110
111
*1 Marked by - - - cannot be selected.
[ Number of Bytes/Number of Cycles ]
src
dest
Rn
An
[An]
dsp:8[An]
dsp:8[SB/FB]
dsp:16[An]
dsp:16[SB]
abs16
Rn
2/4
2/4
2/6
3/6
3/6
4/6
4/6
4/6
An
2/4
2/5
2/6
3/6
3/6
4/6
4/6
4/6
[An]
2/5
2/5
2/6
3/6
3/6
4/6
4/6
4/6
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
4/5
3/5
3/5
4/5
4/5
3/5
3/5
4/5
4/6
3/6
3/6
4/6
5/6
4/6
4/6
5/6
5/6
4/6
4/6
5/6
6/6
5/6
5/6
6/6
6/6
5/6
5/6
6/6
6/6
5/6
5/6
6/6
abs16
4/5
4/5
4/6
5/6
5/6
6/6
6/6
6/6
*2 If src is An and dest is Rn while the size specifier (.size) is (.W), the number of cycles above is increased by 1.
*3 If src is not An and dest is Rn or An while the size specifier (.size) is (.W), the number of cycles above is
increased by 1.
*4 If dest is neither Rn nor An while the size specifier (.size) is (.W), the number of cycles above is increased by 2.
206
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
NEG
(1) NEG.size dest
b7
b0 b7
0 1 1
1 0
.size SIZE
.B
0
.W
1
1 0 SIZE 0
b0
1 0 1
DEST
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
dest code
(
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dsp8
dsp16/abs16
)
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
2/1
An
2/1
[An]
2/3
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/3
3/3
4/3
4/3
abs16
4/3
NOP
(1) NOP
b7
0 0 0
b0
0 0
1 0 0
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
1/1
207
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
NOT
(1) NOT.size:G
dest
b7
b0 b7
0 1 1
1 0 1 0 SIZE 0
.size SIZE
.B
0
.W
1
b0
1 1 1
DEST
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
dest code
(
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dsp8
dsp16/abs16
)
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
2/1
An
2/1
[An]
2/3
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/3
3/3
4/3
4/3
NOT
(2) NOT.B:S dest
b7
b0
1 0 1
1 1
DEST
dest
Rn
dsp:8[SB/FB]
abs16
dest code
(
dsp8
abs16
)
DEST
R0H
R0L
dsp:8[SB]
dsp:8[FB]
abs16
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
1/1
dsp:8[SB/FB]
2/3
abs16
3/3
208
abs16
4/3
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
OR
(1) OR.size:G
#IMM, dest
b7
b0 b7
0 1 1
1 0
1 1 SIZE 0
.size SIZE
.B
0
.W
1
dest code
b0
0 1 1
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
(
DEST
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dsp8
dsp16/abs16
)
#IMM8
#IMM16
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Rn
An
[An] dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
Bytes/Cycles
3/2
3/2
3/4
4/4
4/4
5/4
5/4
*1 If the size specifier (.size) is (.W), the number of bytes above is increased by 1.
abs16
5/4
OR
(2) OR.B:S
#IMM8, dest
b7
dest code
b0
1 0 0
1 1
DEST
dest
Rn
dsp:8[SB/FB]
abs16
(
#IMM8
dsp8
abs16
DEST
R0H
R0L
dsp:8[SB]
dsp:8[FB]
abs16
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
2/1
dsp:8[SB/FB]
3/3
abs16
4/3
209
)
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
OR
(3) OR.size:G
src, dest
b7
1 0 0
b0 b7
1 1
.size SIZE
.B
0
.W
1
0 0 SIZE
b0
SRC
DEST
src/dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
(
SRC/DEST
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
dest code
src code
0
1
0
1
0
1
0
1
dsp8
dsp16/abs16
)(
)
dsp8
dsp16/abs16
src/dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
SRC/DEST
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
src
dest
Rn
An
[An]
dsp:8[An]
dsp:8[SB/FB]
dsp:16[An]
dsp:16[SB]
abs16
Rn
2/2
2/2
2/3
3/3
3/3
4/3
4/3
4/3
An
2/2
2/2
2/3
3/3
3/3
4/3
4/3
4/3
[An]
2/3
2/3
2/4
3/4
3/4
4/4
4/4
4/4
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/3
3/3
4/3
4/3
3/3
3/3
4/3
4/3
3/4
3/4
4/4
4/4
4/4
4/4
5/4
5/4
4/4
4/4
5/4
5/4
5/4
5/4
6/4
6/4
5/4
5/4
6/4
6/4
5/4
5/4
6/4
6/4
210
abs16
4/3
4/3
4/4
5/4
5/4
6/4
6/4
6/4
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
OR
(4) OR.B:S
src, R0L/R0H
b7
dest code
b0
0 0 0
1 1 DEST SRC
(
src
Rn
dsp:8[SB/FB]
abs16
)
dsp8
abs16
SRC
R0L/R0H
dsp:8[SB]
dsp:8[FB]
abs16
dest
0
1
0
1
R0L
R0H
dsp:8[SB/FB]
abs16
3/3
0
0
1
1
DEST
0
1
[ Number of Bytes/Number of Cycles ]
src
Rn
1/2
Bytes/Cycles
2/3
POP
(1) POP.size:G
dest
b7
b0 b7
0 1 1
1 0
.size SIZE
.B
0
.W
1
1 0 SIZE 1
b0
1 0 1
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
DEST
dest code
(
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dsp8
dsp16/abs16
)
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
2/3
An
2/3
[An]
2/4
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/4
3/4
4/4
4/4
211
abs16
4/4
Chapter 4
Instruction Code/Number of Cycles
POP
(2) POP.B:S dest
b7
b0
1 0 0
1 DEST 0 1 0
dest
DEST
0
1
R0L
R0H
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
1/3
POP
(3) POP.W:S dest
b7
b0
1 1 0
1 DEST 0 1 0
dest
A0
A1
DEST
0
1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
1/3
212
4.2
Instruction Code/Number of Cycles
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
POPC
(1) POPC
dest
b7
b0 b7
1 1 1
0 1
dest
0 1 1 0
DEST
dest
--INTBL
INTBH
FLG
b0
DEST
0 0
1
1
DEST
ISP
SP
SB
FB
0 0 0
1 0
0 0 1
1 0
0 1 0
1 1
0 1 1
1 1
*1 Marked by - - - cannot be selected.
0
1
0
1
[ Number of Bytes/Number of Cycles ]
2/3
Bytes/Cycles
POPM
(1) POPM
dest
b7
1 1 1
b0
0 1
1 0 1
DEST
dest
FB SB A1
A0
R3 R2 R1 R0
DEST*2
*2 The bit for a selected register is 1.
The bit for a non-selected register is 0.
[ Number of Bytes/Number of Cycles ]
2/3
Bytes/Cycles
*3 If two or more registers need to be restored, the number of required cycles is 2 x m (m: number of
registers to be restored).
213
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
PUSH
(1) PUSH.size:G #IMM
b7
0 1 1
b0 b7
1 1
1 0 SIZE 1
b0
1 1 0
0 0
1
#IMM8
0
#IMM16
.size SIZE
.B
0
.W
1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
3/2
*1 If the size specifier (.size) is (.W), the number of bytes above is increased by 1.
PUSH
(2) PUSH.size:G src
b7
0 1 1
b0 b7
1 0 1 0 SIZE 0
.size SIZE
.B
0
.W
1
b0
1 0 0
src
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
SRC
0
0
0
0
0
0
0
0
src code
(
SRC
000
001
010
011
100
101
110
111
dsp8
dsp16/abs16
)
src
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
1
1
1
1
1
1
1
1
SRC
000
001
010
011
100
101
110
111
[ Number of Bytes/Number of Cycles ]
src
Bytes/Cycles
Rn
2/2
An
2/2
[An]
2/4
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/4
3/4
4/4
4/4
214
abs16
4/4
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
PUSH
(3) PUSH.B:S
src
b7
b0
1 0 0
0 SRC 0
src
1 0
SRC
0
1
R0L
R0H
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
1/2
PUSH
(4) PUSH.W:S
src
b7
b0
1 1 0
0 SRC 0 1 0
src
A0
A1
SRC
0
1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
1/2
215
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
PUSHA
(1) PUSHA
src
b7
b0 b7
0 1 1
1 1
1 0 1 1
src
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
src code
b0
0 0 1
1
1
1
1
1
1
1
1
(
SRC
dsp8
dsp16/abs16
)
SRC
000
001
010
011
100
101
110
111
[ Number of Bytes/Number of Cycles ]
src
dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/2
4/2
4/2
dsp:8[An]
3/2
Bytes/Cycles
PUSHC
(1) PUSHC
src
b7
b0 b7
1 1 1
0 1
src
--INTBL
INTBH
FLG
0 1 1 0
SRC
0
0
0
0
0
0
1
1
0
1
0
1
b0
SRC
src
ISP
SP
SB
FB
0 0
1
0
SRC
1
1
1
1
0
0
1
1
0
1
0
1
*1 Marked by - - - cannot be selected.
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/2
216
abs:16
4/2
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
PUSHM
(1) PUSHM
src
b7
1 1 1
b0
0 1 1 0
0
SRC
src
R0 R1 R2
R3
A0
A1 SB FB
*1
SRC
*1 The bit for a selected register is 1.
The bit for a non-selected register is 0.
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/2 m
*2 m denotes the number of registers to be saved.
REIT
(1) REIT
b7
1 1 1
b0
1 1
0 1 1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
1/6
217
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
RMPA
(1) RMPA.size
b7
0 1 1
b0 b7
1 1
1 0 SIZE 1
b0
1 1 1
0 0
0
1
.size SIZE
.B
0
.W
1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/4+7
m
*1 m denotes the number of operation performed.
*2 If the size specifier (.size) is (.W), the number of cycles is (6+9
m).
ROLC
(1) ROLC.size
dest
b7
0 1 1
b0 b7
1 0
.size SIZE
.B
0
.W
1
1 1 SIZE 1
b0
0 1 0
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
DEST
dest code
(
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dsp8
dsp16/abs16
)
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
2/1
An
2/1
[An]
2/3
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/3
3/3
4/3
4/3
218
abs16
4/3
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
RORC
(1) RORC.size
dest
b7
b0 b7
0 1 1
1 0
.size SIZE
.B
0
.W
1
1 1 SIZE 1
b0
0 1 1
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
DEST
dest code
(
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dsp8
dsp16/abs16
)
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
2/1
An
2/1
[An]
2/3
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/3
3/3
4/3
4/3
219
abs16
4/3
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
ROT
(1) ROT.size #IMM, dest
b7
b0 b7
1 1 1
0 0
.size SIZE
.B
0
.W
1
0 0 SIZE
#IMM
+1
+2
+3
+4
+5
+6
+7
+8
Rn
An
[An]
dest code
b0
IMM4
IMM4
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
(
DEST
#IMM
–1
–2
–3
–4
–5
–6
–7
–8
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
dsp8
dsp16/abs16
)
IMM4
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
[An] dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
Rn
An
3/2+m
3/2+m
Bytes/Cycles 2/1+m 2/1+m 2/2+m
4/2+m
4/2+m
*1 m denotes the number of rotates performed.
220
abs16
4/2+m
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
ROT
(2) ROT.size R1H, dest
b7
b0 b7
0 1 1
1 0
.size SIZE
.B
0
.W
1
1
b0
0 SIZE 0 1
1 0
DEST
dest code
(
dest
DEST
R0L/R0
0000
R0H/--0001
Rn
R1L/R2
0010
--- /R3
0011
A0
0100
An
A1
0101
[A0]
0110
[An]
[A1]
0111
*1 Marked by - - - cannot be selected.
dsp8
dsp16/abs16
)
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Rn
An
[An]
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
Bytes/Cycles 2/2+m 2/2+m 2/3+m
3/3+m
*2 m denotes the number of rotates performed.
3/3+m
4/3+m
4/3+m
abs16
4/3+m
RTS
(1) RTS
b7
1 1 1
b0
1 0 0 1
1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
1/6
221
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
SBB
(1) SBB.size #IMM, dest
b7
b0 b7
0 1 1
1 0 1 1 SIZE 0
.size SIZE
.B
0
.W
1
Rn
An
[An]
b0
1 1 1
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
DEST
dest code
(
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dsp8
dsp16/abs16
)
#IMM8
#IMM16
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Rn
An
[An] dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/2
3/2
3/4
4/4
4/4
5/4
5/4
Bytes/Cycles
*1 If the size specifier (.size) is (.W), the number of bytes above is increased by 1.
222
abs16
5/4
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
SBB
(2) SBB.size src, dest
b7
1 0 1
b0 b7
1 1
.size SIZE
.B
0
.W
1
0 0 SIZE
b0
SRC
DEST
src/dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
src code
(
SRC/DEST
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
dsp8
dsp16/abs16
dest code
)(
)
dsp8
dsp16/abs16
src/dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
SRC/DEST
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
src
dest
Rn
An
[An]
dsp:8[An]
dsp:8[SB/FB]
dsp:16[An]
dsp:16[SB]
abs16
Rn
2/2
2/2
2/3
3/3
3/3
4/3
4/3
4/3
An
2/2
2/2
2/3
3/3
3/3
4/3
4/3
4/3
[An]
2/3
2/3
2/4
3/4
3/4
4/4
4/4
4/4
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/3
3/3
4/3
4/3
3/3
3/3
4/3
4/3
3/4
3/4
4/4
4/4
4/4
4/4
5/4
5/4
4/4
4/4
5/4
5/4
5/4
5/4
6/4
6/4
5/4
5/4
6/4
6/4
5/4
5/4
6/4
6/4
223
abs16
4/3
4/3
4/4
5/4
5/4
6/4
6/4
6/4
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
SBJNZ
(1) SBJNZ.size
#IMM, dest, label
b7
b0 b7
1 1 1
1 1 0
b0
0 SIZE
IMM4
DEST
dest code
(
dsp8
dsp16/abs16
label code
)
dsp8
dsp8(label code) = address indicated by label – (start address of instruction + 2)
.size SIZE
.B
0
.W
1
#IMM
0
–1
–2
–3
–4
–5
–6
–7
IMM4
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
#IMM
+8
+7
+6
+5
+4
+3
+2
+1
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
IMM4
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
3/3
An
3/3
[An]
3/5
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
4/5
4/5
5/5
5/5
*1 If branched to label, the number of cycles above is increased by 4.
224
abs16
5/5
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
SHA
(1) SHA.size #IMM, dest
b7
b0 b7
1 1 1
b0
1 0 0 0 SIZE
.size SIZE
.B
0
.W
1
#IMM
+1
+2
+3
+4
+5
+6
+7
+8
IMM4
IMM4
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DEST
#IMM
–1
–2
–3
–4
–5
–6
–7
–8
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
dest code
(
dsp8
dsp16/abs16
)
IMM4
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/2+m
3/2+m
4/2+m
4/2+m
Bytes/Cycles 2/1+m 2/1+m 2/2+m
Rn
An
[An]
*1 m denotes the number of shifts performed.
225
abs16
4/2+m
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
SHA
(2) SHA.size R1H, dest
b7
b0 b7
0 1 1
1 0 1 0 SIZE 1
.size SIZE
.B
0
.W
1
b0
1 1 1
DEST
dest
R0L/R0
R0H/--R1L/R2
--- /R3
A0
A1
[A0]
[A1]
Rn
An
[An]
dest code
(
dsp8
dsp16/abs16
DEST
0000
0001
0010
0011
0100
0101
0110
0111
)
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
*1 Marked by - - - cannot be selected.
[ Number of Bytes/Number of Cycles ]
dest
Rn
An
[An] dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/3+m
4/3+m
4/3+m
Bytes/Cycles 2/2+m 2/2+m 2/3+m
3/3+m
*2 m denotes the number of shifts performed.
SHA
(3) SHA.L
#IMM, dest
b7
b0 b7
1 1 1
#IMM
+1
+2
+3
+4
+5
+6
+7
+8
0 1
0 1 1 1
IMM4
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
#IMM
–1
–2
–3
–4
–5
–6
–7
–8
b0
0 1 DEST
IMM4
IMM4
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
dest
R2R0
R3R1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/3+m
*2 m denotes the number of shifts performed.
226
DEST
0
1
abs16
4/3+m
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
SHA
(4) SHA.L
R1H, dest
b7
b0 b7
1 1 1
0 1 0 1
dest
R2R0
R3R1
1 0
b0
0 1 DEST 0 0
0
1
DEST
0
1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/4+m
*1 m denotes the number of shifts performed.
227
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
SHL
(1) SHL.size #IMM, dest
b7
b0 b7
1 1 1
0 1
.size SIZE
.B
0
.W
1
#IMM
+1
+2
+3
+4
+5
+6
+7
+8
IMM4
IMM4
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
An
[An]
(
DEST
#IMM
–1
–2
–3
–4
–5
–6
–7
–8
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
dest code
b0
0 0 SIZE
dsp8
dsp16/abs16
)
IMM4
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/2+m
4/2+m
4/2+m
Bytes/Cycles 2/1+m 2/1+m 2/2+m
3/2+m
*1 m denotes the number of shifts performed.
Rn
An
[An]
228
abs16
4/2+m
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
SHL
(2) SHL.size R1H, dest
b7
b0 b7
0 1 1
1 0
.size SIZE
.B
0
.W
1
1 0 SIZE 1
b0
1 1 0
DEST
dest code
(
dest
DEST
R0L/R0
0000
R0H/--0001
Rn
R1L/R2
0010
--- /R3
0011
A0
0100
An
A1
0101
[A0]
0110
[An]
[A1]
0111
*1 Marked by - - - cannot be selected.
dsp8
dsp16/abs16
)
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Rn
An
[An] dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/3+m
3/3+m
4/3+m
4/3+m
Bytes/Cycles 2/2+m 2/2+m 2/3+m
*2 m denotes the number of shifts performed.
abs16
4/3+m
SHL
(3) SHL.L
#IMM, dest
b7
b0 b7
1 1 1
#IMM
+1
+2
+3
+4
+5
+6
+7
+8
0 1 0 1
IMM4
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1 1
#IMM
–1
–2
–3
–4
–5
–6
–7
–8
b0
0 0 DEST
IMM4
IMM4
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
dest
R2R0
R3R1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/3+m
*2 m denotes the number of shifts performed.
229
DEST
0
1
Chapter 4
Instruction Code/Number of Cycles
SHL
(4) SHL.L
R1H, dest
b7
1 1 1
b0 b7
0 1
dest
R2R0
R3R1
0 1 1 0
b0
0 0 DEST 0 0
0
1
0
1
DEST
0
1
[ Number of Bytes/Number of Cycles ]
2/4+m
Bytes/Cycles
*1 m denotes the number of shifts performed.
SMOVB
(1) SMOVB.size
b7
0 1 1
b0 b7
1 1
1 0 SIZE 1
b0
1 1 0
1 0
.size SIZE
.B
0
.W
1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/5+5
m
*2 m denotes the number of transfers performed.
230
4.2
Instruction Code/Number of Cycles
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
SMOVF
(1) SMOVF.size
b7
0 1 1
b0 b7
1 1 1 0 SIZE 1
b0
1 1 0
1 0
0
0
.size SIZE
.B
0
.W
1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/5+5
m
*1 m denotes the number of transfers performed.
SSTR
(1) SSTR.size
b7
0 1 1
b0 b7
1 1 1 0 SIZE 1
b0
1 1 0
1 0
1 0
.size SIZE
.B
0
.W
1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/3+2
m
*1 m denotes the number of transfers performed.
231
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
STC
(1) STC src, dest
b7
b0 b7
0 1 1
1 1 0
src
1 1 1
dest Code
b0
SRC
(
DEST
dest
SRC
dsp16/abs16
)
DEST
0000
0001
0010
0011
0100
0101
0110
0111
R0
R1
R2
R3
A0
A1
[A0]
[A1]
0 0 0
--0 0 1
INTBL
Rn
0 1 0
INTBH
0 1 1
FLG
1 0 0
ISP
An
1 0 1
SP
1 1 0
SB
[An]
1 1 1
FB
*1 Marked by - - - cannot be selected.
dsp8
dest
dsp:8[An]
dsp:8[SB/FB]
dsp:16[An]
dsp:16[SB]
abs16
DEST
dsp:8[A0]
dsp:8[A1]
dsp:8[SB]
dsp:8[FB]
dsp:16[A0]
dsp:16[A1]
dsp:16[SB]
abs16
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
2/1
An
2/1
[An]
2/2
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/2
3/2
4/2
4/2
abs16
4/2
STC
(2) STC PC, dest
b7
b0 b7
0 1 1
1 1 1 0
0 1
b0
1 0 0
DEST
dest
DEST
R2R0
0000
R3R1
0001
Rn
--0010
--0011
A1A0
0100
An
--0101
[A0]
0110
[An]
[A1]
0111
*1 Marked by - - - cannot be selected.
dest Code
(
dsp8
dsp16/abs16
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
)
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
2/2
An
2/2
[An]
2/3
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/3
3/3
4/3
4/3
232
abs16
4/3
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
STCTX
(1) STCTX
abs16, abs20
b7
b0 b7
0 1 1
1 1
1 0 1 1
b0
1 1 1
0 0
0
abs16
0
abs20
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
7/11+2
m
*1 m denotes the number of transfers performed.
STE
(1) STE.size src, abs20
b7
b0 b7
0 1 1
1 0
.size SIZE
.B
0
.W
1
1 0 SIZE 0
b0
0 0 0
src
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
SRC
0
0
0
0
0
0
0
0
src code
(
SRC
000
001
010
011
100
101
110
111
dsp8
dsp16/abs16
dest code
)
abs20
src
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
1
1
1
1
1
1
1
1
SRC
000
001
010
011
100
101
110
111
[ Number of Bytes/Number of Cycles ]
src
Bytes/Cycles
Rn
5/3
An
5/3
[An]
5/4
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
6/4
6/4
7/4
7/4
233
abs16
7/4
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
STE
(2) STE.size src, dsp:20[A0]
b7
b0 b7
0 1 1
1 0
.size SIZE
.B
0
.W
1
1 0 SIZE 0
b0
0 0 1
SRC
An
[An]
(
SRC
src
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
src code
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
dsp8
dsp16/abs16
dest code
)
src
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
dsp20
1
1
1
1
1
1
1
1
SRC
000
001
010
011
100
101
110
111
[ Number of Bytes/Number of Cycles ]
src
Bytes/Cycles
Rn
5/3
An
5/3
[An]
5/4
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
6/4
6/4
7/4
7/4
abs16
7/4
STE
(3) STE.size src, [A1A0]
b7
b0 b7
0 1 1
1 0 1 0 SIZE 0
.size SIZE
.B
0
.W
1
b0
0 1 0
SRC
src
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
0
0
0
0
0
0
0
0
src code
(
SRC
000
001
010
011
100
101
110
111
dsp8
dsp16/abs16
)
src
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
1
1
1
1
1
1
1
1
SRC
000
001
010
011
100
101
110
111
[ Number of Bytes/Number of Cycles ]
src
Bytes/Cycles
Rn
2/3
An
2/3
[An]
2/4
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/4
3/4
4/4
4/4
234
abs16
4/4
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
STNZ
(1) STNZ
#IMM8, dest
b7
dest code
b0
1 1 0
1 0
dest
Rn
dsp:8[SB/FB]
abs16
(
#IMM8
DEST
dsp8
abs16
)
DEST
R0H
R0L
dsp:8[SB]
dsp:8[FB]
abs16
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
dest
dsp:8[SB/FB]
Rn
2/1
Bytes/Cycles
3/2
abs16
4/2
*1 If the Z flag = 0, the number of cycles above is increased by 1.
STZ
(1) STZ #IMM8, dest
b7
b0
1 1 0
0 1
DEST
dest
Rn
dsp:8[SB/FB]
abs16
(
#IMM8
dest code
dsp8
abs16
)
DEST
R0H
R0L
dsp:8[SB]
dsp:8[FB]
abs16
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
2/1
dsp:8[SB/FB]
3/2
abs16
4/2
*2 If the Z flag = 1, the number of cycles above is increased by 1.
235
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
STZX
(1) STZX
#IMM81, #IMM82, dest
b7
dest code
b0
1 1 0
1 1
DEST
#IMM81
dest
Rn
dsp:8[SB/FB]
abs16
(
)
dsp8
abs16
#IMM82
DEST
R0H
R0L
dsp:8[SB]
dsp:8[FB]
abs16
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
dest
dsp:8[SB/FB]
Rn
3/2
Bytes/Cycles
abs16
5/3
4/3
SUB
(1) SUB.size:G
#IMM, dest
b7
b0 b7
0 1 1
1 0
.size SIZE
.B
0
.W
1
1 1 SIZE 0
Rn
An
[An]
b0
1 0 1
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
DEST
dest code
(
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dsp8
dsp16/abs16
)
#IMM8
#IMM16
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Rn
An
[An] dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/2
3/2
3/4
4/4
4/4
5/4
5/4
Bytes/Cycles
*1 If the size specifier (.size) is (.W), the number of bytes above is increased by 1.
236
abs16
5/4
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
SUB
(2) SUB.B:S #IMM8, dest
b7
dest code
b0
1 0 0
0 1
DEST
dest
Rn
dsp:8[SB/FB]
abs16
#IMM8
(
dsp8
abs16
DEST
R0H
R0L
dsp:8[SB]
dsp:8[FB]
abs16
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
2/1
dsp:8[SB/FB]
3/3
abs16
4/3
237
)
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
SUB
(3) SUB.size:G
src, dest
b7
1 0 1
b0 b7
0 1
.size SIZE
.B
0
.W
1
0 0 SIZE
SRC
An
[An]
(
DEST
src/dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
src code
b0
SRC/DEST
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
dsp8
dsp16/abs16
dest code
)(
)
dsp8
dsp16/abs16
src/dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
SRC/DEST
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
src
dest
Rn
An
[An]
dsp:8[An]
dsp:8[SB/FB]
dsp:16[An]
dsp:16[SB]
abs16
Rn
2/2
2/2
2/3
3/3
3/3
4/3
4/3
4/3
An
2/2
2/2
2/3
3/3
3/3
4/3
4/3
4/3
[An]
2/3
2/3
2/4
3/4
3/4
4/4
4/4
4/4
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/3
3/3
4/3
4/3
3/3
3/3
4/3
4/3
3/4
3/4
4/4
4/4
4/4
4/4
5/4
5/4
4/4
4/4
5/4
5/4
5/4
5/4
6/4
6/4
5/4
5/4
6/4
6/4
5/4
5/4
6/4
6/4
238
abs16
4/3
4/3
4/4
5/4
5/4
6/4
6/4
6/4
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
SUB
(4) SUB.B:S src, R0L/R0H
b7
b0
0 0 1
0 1 DEST SRC
dest code
(
src
Rn
dsp:8[SB/FB]
abs16
dsp8
abs16
)
SRC
R0L/R0H
dsp:8[SB]
dsp:8[FB]
abs16
0
0
1
1
dest
DEST
0
1
R0L
R0H
0
1
0
1
[ Number of Bytes/Number of Cycles ]
src
dsp:8[SB/FB]
Rn
1/2
Bytes/Cycles
2/3
abs16
3/3
TST
(1) TST.size #IMM, dest
b7
b0 b7
0 1 1
1 0
.size SIZE
.B
0
.W
1
1 1 SIZE 0
Rn
An
[An]
b0
0 0 0
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
DEST
dest code
(
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dsp8
dsp16/abs16
)
#IMM8
#IMM16
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Rn
An
[An] dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
Bytes/Cycles
3/2
3/2
3/4
4/4
4/4
5/4
5/4
*1 If the size specifier (.size) is (.W), the number of bytes above is increased by 1.
239
abs16
5/4
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
TST
(2) TST.size src, dest
b7
1 0 0
b0 b7
0 0
.size SIZE
.B
0
.W
1
0 0 SIZE
b0
SRC
DEST
src/dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
src code
(
SRC/DEST
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
dsp8
dsp16/abs16
dest code
)(
)
dsp8
dsp16/abs16
src/dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
SRC/DEST
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
src
dest
Rn
An
[An]
dsp:8[An]
dsp:8[SB/FB]
dsp:16[An]
dsp:16[SB]
abs16
Rn
2/2
2/2
2/3
3/3
3/3
4/3
4/3
4/3
An
2/2
2/2
2/3
3/3
3/3
4/3
4/3
4/3
[An]
2/3
2/3
2/4
3/4
3/4
4/4
4/4
4/4
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/3
3/3
4/3
4/3
3/3
3/3
4/3
4/3
3/4
3/4
4/4
4/4
4/4
4/4
5/4
5/4
4/4
4/4
5/4
5/4
5/4
5/4
6/4
6/4
5/4
5/4
6/4
6/4
5/4
5/4
6/4
6/4
240
abs16
4/3
4/3
4/4
5/4
5/4
6/4
6/4
6/4
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
UND
(1) UND
b7
1 1 1
b0
1 1
1 1 1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
1/20
WAIT
(1) WAIT
b7
0 1 1
b0 b7
1 1
1 0 1 1
b0
1 1 1
0 0
1
1
[ Number of Bytes/Number of Cycles ]
Bytes/Cycles
2/3
241
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
XCHG
(1) XCHG.size
src, dest
b7
b0 b7
0 1 1
1 1 0 1 SIZE 0
.size SIZE
.B
0
.W
1
src
R0L/R0
R0H/R1
R1L/R2
R1H/R3
b0
0 SRC
An
[An]
(
dsp8
dsp16/abs16
)
SRC
0 0
0 1
1 0
1 1
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
DEST
dest code
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
2/4
An
2/4
[An]
2/5
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/5
3/5
4/5
4/5
242
abs16
4/5
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
XOR
(1) XOR.size #IMM, dest
b7
b0 b7
0 1 1
1 0
.size SIZE
.B
0
.W
1
1 1 SIZE 0
0 0 1
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
dest code
b0
DEST
(
DEST
0000
0001
0010
0011
0100
0101
0110
0111
dsp8
dsp16/abs16
)
#IMM8
#IMM16
dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
DEST
1000
1001
1010
1011
1100
1101
1110
1111
[ Number of Bytes/Number of Cycles ]
dest
Bytes/Cycles
Rn
3/2
An
3/2
[An]
3/4
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
4/4
4/4
5/4
5/4
*1 If the size specifier (.size) is (.W), the number of bytes above is increased by 1.
243
abs16
5/4
Chapter 4
Instruction Code/Number of Cycles
4.2
Instruction Code/Number of Cycles
XOR
(2) XOR.size src, dest
b7
1 0 0
b0 b7
0 1
.size SIZE
.B
0
.W
1
0 0 SIZE
b0
SRC
DEST
src/dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
Rn
An
[An]
src code
(
SRC/DEST
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
dsp8
dsp16/abs16
dest code
)(
)
dsp8
dsp16/abs16
src/dest
dsp:8[A0]
dsp:8[An]
dsp:8[A1]
dsp:8[SB]
dsp:8[SB/FB]
dsp:8[FB]
dsp:16[A0]
dsp:16[An]
dsp:16[A1]
dsp:16[SB]
dsp:16[SB]
abs16
abs16
SRC/DEST
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
[ Number of Bytes/Number of Cycles ]
src
dest
Rn
An
[An]
dsp:8[An]
dsp:8[SB/FB]
dsp:16[An]
dsp:16[SB]
abs16
Rn
2/2
2/2
2/3
3/3
3/3
4/3
4/3
4/3
An
2/2
2/2
2/3
3/3
3/3
4/3
4/3
4/3
[An]
2/3
2/3
2/4
3/4
3/4
4/4
4/4
4/4
dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB]
3/3
3/3
4/3
4/3
3/3
3/3
4/3
4/3
3/4
3/4
4/4
4/4
4/4
4/4
5/4
5/4
4/4
4/4
5/4
5/4
5/4
5/4
6/4
6/4
5/4
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Chapter 5
Interrupt
5.1 Outline of Interrupt
5.2 Interrupt Control
5.3 Interrupt Sequence
5.4 Return from Interrupt Routine
5.5 Interrupt Priority
5.6 Multiple Interrupts
5.7 Precautions for Interrupts
Chapter 5
Interrupt
5.1 Outline of Interrupt
5.1 Outline of Interrupt
When an interrupt request is acknowledged, control branches to the interrupt routine that is set to an interrupt vector table. Each interrupt vector table must have had the start address of its corresponding interrupt
routine set. For details about the interrupt vector table, refer to Section 1.10, “Vector Table”.
5.1.1 Types of Interrupts
Figure 5.1.1 lists the types of interrupts. Table 5.1.1 lists the source of interrupts (nonmaskable) and the
fixed vector tables.
Software
(Nonmaskable interrupt)
Hardware














Interrupt
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Special
(Nonmaskable interrupt)
Watchdog timer
Oscillation stop deteciont
Single step (Note 2)
Address matched
Peripheral I/O (Note 1)
(Maskable interrupt)
Note 1: Peripheral function interrupts are generated by the peripheral functions built into the
microcomputer system.
Note 2: This is dedicated interrupt for development support tools. Do not use this interrupt.
Figure 5.1.1 Classification of interrupts
•Maskable interrupt:
This type of interrupt can be controlled by using the I flag to enable (or
disable) an interrupt or by changing the interrupt priority level.
•Nonmaskable interrupt: This type of interrupt cannot be controlled by using the I flag to enable (or disable)
an interrupt or by changing the interrupt priority level.
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Chapter 5
Interrupt
5.1 Outline of Interrupt
Table 5.1.1 Interrupt Source (Nonmaskable) and Fixed Vector Table
Interrupt source
Undefined instruction
Overflow
BRK instruction
Address match
Single step (Note 1)
Watchdog timer•Oscillation stop detection
(Reserved)
(Reserved)
Reset
Vector table addresses
Remarks
Address (L) to address (H)
0FFDC16 to 0FFDF16
Interrupt generated by the UND instruction.
0FFE016 to 0FFE316
Interrupt generated by the INTO instruction.
Executed beginning from address indicated by vector in
0FFE416 to 0FFE716
variable vector table if 0FFE716 address contents are
FF16.
0FFE816 to 0FFEB16
Can be controlled by an interrupt enable bit.
0FFEC16 to 0FFEF16
Do not use this interrupt.
0FFF016 to 0FFF316
0FFF416 to 0FFF716
0FFF816 to 0FFFB16
0FFFC16 to 0FFFF16
Note 1: This is dedicated interrupt for development support tools. Do not use this interrupt.
5.1.2 Software Interrupts
Software interrupts are generated by some instruction that generates an interrupt request when executed. Software interrupts are nonmaskable interrupts.
●Undefined-instruction interrupt
This interrupt occurs when the UND instruction is executed.
●Overflow interrupt
This interrupt occurs if the INTO instruction is executed when the O flag is 1 (arithmetic result is overflow).
The following lists the instructions that cause the O flag to change:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
●BRK interrupt
This interrupt occurs when the BRK instruction is executed.
●INT instruction interrupt
This interrupt occurs when the INT instruction is executed. The software interrupt numbers which can be
specified by INT instcution are 0 to 63. Note that software interrupt numbers 4 to 31 are assigned to
peripheral function interrupts. This means that by executing the INT instruction, you can execute the
same interrupt routine as used in peripheral function interrupts.
For software interrupt numbers 0 to 31, the U flag is saved when the INT instruction is executed and the
U flag is cleared to 0 to choose the interrupt stack pointer (ISP) before executing the interrupt sequence.
The previous U flag before the interrupt occurred is restored when control returns from the interrupt
routine. For software interrupt numbers 32 to 63, when the instruction is executed, U flag does not
change but uses selected SP at the time.
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Chapter 5
Interrupt
5.1 Outline of Interrupt
5.1.3 Hardware Interrupts
There are two types in hardware interrupts; special interrupts and peripherai function interrupts.
●Special interrupts
Special interrupts are nonmaskable interrupts.
(1) Watchdog timer interrupt
This interrupt is caused by the watchdog timer. Initialize the watchdog timer after the watchdog timer
interrupt is generated. For details about the watchdog timer interrupt, refer to the R8C’s Hardware
Manual.
(2) Oscillation stop detection interrupt
This interrupt is caused by the oscillation stop detection interrupt. For details about the oscillation stop
detection interrupt, refer to the R8C’s Hardware Manual.
(3) Single-step interrupt
This interrupt is used exclusively for development support tools. Do not use this interrupt.
(4) Address-match interrupt
When any one of AIER0 bit or AIER1 bit of AIER register is “1” (address-match interrupt is enabled), the
address-match interrupt is generated just before executing the instruction of the address shown by
corresponding RMAD0 to RMAD1 registers.
●Peripheral function interrupts
These interrupts are generated by the peripheral functions built into the microcomputer system. Peripheral function interrupts are maskable interrupts.
The types of built-in peripheral functions vary with each R8C model, so do the types of interrupt causes.
For details about peripheral function interrupts, refer to the R8C’s Hardware Manual.
248
Chapter 5
Interrupt
5.2 Interrupt Control
5.2 Interrupt Control
The following explains how to enable/disable maskable interrupts and set acknowledge priority. The explanation here does not apply to non-maskable interrupts.
Maskable interrupts are enabled and disabled by using the I flag, IPL, and ILVL2 bits to ILVL0 bits of each
interrupt control register. Whether there is any interrupt requested is indicated by the IR bit of each interrupt
control register.
For details about the memory allocation and the configuration of interrupt control registers, refer to the
R8C’s Hardware Manual.
5.2.1 I Flag
The I flag is used to disable/enable maskable interrupts. When the I flag is set to 1 (enabled), all
maskable interrupts are enabled; when the I flag is cleared to 0 (disabed), they are disabled.
When the I flag is changed, the altered flag status is reflected in determining whether or not to accept an
interrupt request at the following timing:
• If the flag is changed by an REIT instruction, the changed status takes effect beginning with that
REIT instruction.
• If the flag is changed by an FCLR, FSET, POPC, or LDC instruction, the changed status takes
effect beginning with the next instruction.
When changed by REIT instruction
Interrupt request generated
Determination whether or not to
accept interrupt request
Time
Previous
instruction
Interrupt sequence
REIT
(If I flag is changed from 0 to 1 by REIT instruction)
When changed by FCLR, FSET, POPC, or LDC instruction
Determination whether or not to
accept interrupt request
Interrupt request generated
Time
Previous
instruction
FSET I
Next instruction
Interrupt sequence
(If I flag is changed from 0 to 1 by FSET instruction)
Figure 5.2.1 Timing at which changes of I flag are reflected in interrupt handling
5.2.2 IR Bit
The IR bit is set to 1 (interrupt request issued) when an interrupt request is generated. The IR bit is
cleared to 0 (no interrupt request issued)after the interrupt request is acknowledged and the program
brances to corresponding interrupt vector table.
The IR bit can be cleared to 0 by program. Do not set to 1.
249
Chapter 5
Interrupt
5.2 Interrupt Control
5.2.3 ILVL2 to ILVL0 bis, IPL
Interrupt priority levels can be set by the ILVL2 to ILVL0 bits.
Table 5.2.1 shows how interrupt priority levels are set. Table 5.2.2 shows interrupt enable levels in
relation to IPL.
The following lists the conditions under which an interrupt request is acknowledged:
• I flag
=1
• IR bit
=1
• Interrupt priority level > IPL
The I flag, ILVL2 to ILVL0 bits, and IPL are independent of each other, so they do not affect any other bit.
Table 5.2.1 Interrupt Priority Levels
ILVL2–ILVL0
Interrupt priority
level
0002
Level 0(interrupt disabled)
0012
Level 1
0102
Table 5.2.2 Interrupt priority levels enabled by IPL
Priority
order
IPL
Enabled interrupt priority
levels
0002
Interrupt levels 1 and above are enabled.
0012
Interrupt levels 2 and above are enabled.
Level 2
0102
Interrupt levels 3 and above are enabled.
0112
Level 3
0112
Interrupt levels 4 and above are enabled.
1002
Level 4
1002
Interrupt levels 5 and above are enabled.
1012
Level 5
1012
Interrupt levels 6 and above are enabled.
1102
Level 6
1102
Interrupt levels 7 and above are enabled.
1112
Level 7
1112
All maskable interrupts are disabled.
Low
High
When the IPL or the interrupt priority level of some interrupt is changed, the altered level is reflected in
interrupt handling at the following timing:
• If the IPL is changed by an REIT instruction, the changed level takes
effect beginning with the instruction that is executed two clock periods after the last clock of the REIT
instruction.
• If the IPL is changed by a POPC, LDC, or LDIPL instruction, the
changed level takes effect beginning with the instruction that is executed three clock periods after the
last clock of the instruction used.
• If the interrupt priority level of a particular interrupt is changed by an instruction such as MOV, the
changed level takes effect beginning with the instruction that is executed two clock or three clock
periods after the last clock of the instruction used.
250
Chapter 5
Interrupt
5.2 Interrupt Control
5.2.4 Changing Interrupt Control Register
(1) Each interrupt control register can only be modified while no interrupt requests corresponding to that
register are generated. If interrupt requests managed by any interrupt control register are likely to
occur, disable the interrupts before changing the interrupt control register.
(2) To modify any interrupt control register after disabling interrupts, be careful with the instructions
used.
When Changing Other Than IR Bit
If an interrupt request corresponding to that register is generated while executing the instruction, the IR
bit may not be set to “1” (interrupt requested), with the result that the interrupt request is ignored. If this
presents a problem, use the following instructions to modify the register.
Instructions to use: AND, OR, BCLR, BSET
When Changing IR Bit
Even when the IR bit is cleared to “0” (interrupt not requested), it may not actually be cleared to “0”
depending on the instruction used. Therefore, use the MOV instruction to set the IR bit to “0”.
(3) When disabling interrupts using the I flag, set the I flag according to the following sample programs.
Refer to #2 for the change of interrupt control registers in the sample programs.
Sample programs 1 to 3 are to prevent the I flag from being set to “1” (interrupt enabled) before writing
to the interrupt control registers for reasons of the internal bus or the instruction queue buffer.
Example 1: Use NOP instructions to prevent I flag being set to “1”
before interrupt control register is changed
INT_SWITCH1:
FCLR
I
; Disable interrupts
AND.B #00H, 0056H ; Set TXIC register to “0016”
NOP
NOP
FSET
I
; Enable interrupts
Example 2: Use dummy read to have FSET instruction wait
INT_SWITCH2:
FCLR
I
AND.B #00H, 0056H
MOV.W MEM, R0
FSET
I
; Disable interrupts
; Set TXIC register to “0016”
; Dummy read
; Enable interrupts
Example 3: Use POPC instruction to change I flag
INT_SWITCH3:
PUSHC FLG
FCLR
I
; Disable interrupts
AND.B #00H, 0056H ; Set TXIC register to “0016”
POPC FLG
; Enable interrupts
251
Chapter 5
Interrupt
5.3 Interrupt Sequence
5.3 Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence. Figure 5.3.1 shows the interrupt sequence executing time.
In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address
0000016. Then, the IR bit of corresponding interrupt is set to 0 (no interrupt request issued).
(2) Saves the FLG register as it was immediately before the start of interrupt sequence in the temporary
register (Note 1) within the CPU.
(3) The I flag, the D flag, and the U flag of the FLG register are as follows:
• The I flag is set to 0 (interrupt disabled)
• The D flag is set to 0 (single-step interrupt is disabled)
•The U flag is set to 0 (ISP is specified)
However, the U flag does not change when the INT instruction of the software interrupt numbers 32-63 is
executed.
(4) Saves the temporary register (Note 1) within the CPU in the stack area.
(5) Saves the PC in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
(7) The first address of the interrupt routine set to the interrupt vector is set to the PC.
After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine.
Note 1: This register cannot be utilized by the user.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CPU clock
Address bus
Data bus
RD
Address
0000016
Interrupt
information
Undefined
Undefined
SP-2
SP-1
SP-2
contents
Undefined
WR
Note: Undefined parts differ according to the states of the que buffer.
If the que buffer is in the state where an instruction can be taken, a read
cycle is generated.
Figure 5.3.1 Interrupt sequence executing time
252
SP-4
SP-1
contents
SP-4
contents
SP-3
SP-3
contents
VEC
VEC
contents
VEC+1
VEC+1
contents
VEC+2
VEC+2
contents
PC
20
Chapter 5
Interrupt
5.3 Interrupt Sequence
5.3.1 Interrupt Response Time
Figure 5.3.2 shows the interrupt resonse time. The interrupt response time means a period of time from
when an interrupt request is generated till when the first instruction of the interrupt routine is executed.
This period consists of time ((a) into Figure 5.3.1) from when an interrupt request is generated to when
the instruction then under way is completed and time (20 cycles (b)) in which an interrupt sequence is
executed.
Interrupt request generated
Interrupt request acknowledged
Time
Instruction
Interrupt sequence
(a)
Instruction in interrupt
routine
20 cycles (b)
Interrupt response time
(a) Time from when interrupt request is generated to when the instruction then under execution is
completed. Time (a) varies with each instruction being executed. The DIVX instruction requires
a maximum time that consists of 30 cycles (without wait state, cycle number in case the
divisor is register ).
(b) The address-match interrupt and the single-step interrupt are 21 cycles.
Figure 5.3.2 Interrupt response time
5.3.2 Changes of IPL When Interrupt Request Acknowledged
When an interrupt request of maskable instruction is acknowledged, the interrupt priority level of the
acknowledged interrupt is set to the IPL.
When an software interrupt request or an special interrupt request is acknowledged, the value shown in
Table 5.3.1 is set to the IPL. Table 5.3.1 shows the value of IPL when software interrupt and special
interrupt request acknowledged.
Table 5.3.1 Value of IPL when software interrupt and special interrupt request acknowledged
Interrupt sources without interrupt priority levels
Watchdog timer, Oscillation stop detection
Value that is set to IPL
7
Software, Address-match, Single-step
Not changed
253
Chapter 5
Interrupt
5.3 Interrupt Sequence
5.3.3 Saving Registers
In an interrupt sequence, the FLG register and the PC are saved to the stack area.
The order in which these contents are saved is as follows: First, the 4 high-order bits of the PC and 4
high-order bits (IPL) and 8 low-order bits of the FLG register for a total of 16 bits are saved to the stack
area. Next, the 16 low-order bits of the PC are saved. Figure 5.3.3 shows the stack status before an
interrupt request is acknowledged.
If there are any other registers you want to be saved, save them in program at the beginning of the
interrupt routine. The PUSHM instruction allows you to save all registers except the SP by a single
instruction.
Stack area
Stack area
MSB
LSB
MSB
LSB
Address
Address
m–4
m–4
PCL
m–3
m–3
PCM
m–2
m–2
FLGL
m–1
m
m–1
Content of previous stack
m+1 Content of previous stack
[SP]
SP value before
interrupt request is
acknowledged
m
FLGH
[SP]
New SP value
PCH
Content of previous stack
m+1 Content of previous stack
Stack status before interrupt request is
acknowledged
Stack status after interrupt request is acknowledged
Figure 5.3.3 Stack status before and after an interrupt request is acknowledged
Register save operation performed in an interrupt sequence is executed in four operations 8 bits at a time.
Figure 5.3.4 shows the operation to save registers.
Note 1: When the INT instruction for software interrupt numbers 32 to 63 is executed, SP is indicated by
the U flag. The others are ISP.
Address
Stack area
Sequence in which order
registers are saved
[SP]–5
[SP]–4
PCL
(3)
[SP]–3
PCM
(4)
[SP]–2
FLGL
(1)
[SP]–1
FLGH
PCH
Saved separately, 8 bits at a time
(2)
[SP]
Finished saving registers
in four operations.
Note 1: [SP] denotes the initial value of the stack pointer (SP) when
interrupt request is acknowledged. After the microcomputer
finishes saving registers, the SP content is [SP] minus 4.
Figure 5.3.4 Operations to save registers
254
Chapter 5
Interrupt
5.4 Return from Interrupt Routine
5.4 Return from Interrupt Routine
As you execute the REIT instruction at the end of the interrupt routine, the contents of the FLG register and
the PC that have been saved to the stack area immediately preceding the interrupt sequence are automatically restored. Then control returns to the routine that was under execution before the interrupt request was
acknowledged.
If there are any registers you saved via program in the interrupt routine, be sure to restore them using an
instruction (e.g., POPM instruction) before executing the REIT instruction.
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Chapter 5
Interrupt
5.5 Interrupt Priority
5.5 Interrupt Priority
When two or more interrupt requests occur while 1 instruction is executed, whichever interrupt request is
acknowledged that has the highest priority.
The priority level of maskable interrupts (Peripheral function) can be selected arbitrarily by setting the
ILVL2 to ILVL0 bits. If some maskable interrupts are assigned the same priority level, the priority between
these interrupts is resolved by the priority that is set in hardware.
Special interrupts such as the watchdog timer interrupt have their priority levels set in hardware. Figure
5.5.1 lists the interrupt priority levels of hardware interrupts.
Software interrupts are not subjected to interrupt priority. They always causes control to branch to an
interrupt routine when the relevant instruction is executed.
Reset
High
Watchdog timer
Oscillation stop detection
Peripheral function
Single step
Address match
Figure 5.5.1 Interrupt priority levels of hardware interrupts
256
Low
Chapter 5
Interrupt
5.6 Multiple interrupts
5.6 Multiple Interrupts
The following shows the internal bit states when control has branched to an interrupt routine:
• The interrupt enable flag (I flag) is cleared to 0 (interrupts disabled).
• The interrupt request bit for the acknowledged interrupt is cleared to 0.
• The processor interrupt priority level (IPL) equals the interrupt priority level of the acknowledged interrupt.
By setting the interrupt enable flag (I flag) (= 1) in the interrupt routine, you can reenable interrupts so that an
interrupt request can be acknowledged that has higher priority than the processor interrupt priority level
(IPL). Figure 5.6.1 shows how multiple interrupts are handled.
The interrupt requests that have not been acknowledged for their low interrupt priority level are kept pending. When the IPL is restored by an REIT instruction and interrupt priority is resolved against it, the pending
interrupt request is acknowledged if the following condition is met:
Interrupt priority level of
pending interrupt request
>
Restored processor interrupt
priority level (IPL)
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Chapter 5
Interrupt
5.6 Multiple interrupts
Interrupt request
generated
Time
Reset
Nesting
Main routine
I=0
Interrupt 1
IPL = 0
I=1
Interrupt priority level = 3
Interrupt 1
I=0
Interrupt 2
IPL = 3
Multiple interrupts
I=1
Interrupt priority level = 5
Interrupt 2
I=0
IPL = 5
Interrupt 3
REIT
REIT
Interrupt priority level = 2
I=1
IPL = 3
Interrupt 3
REIT
REIT
I=1
Not acknowledged because
of low interrupt priority
IPL = 0
Main routine instructions
are not executed.
Interrupt 3
I=0
IPL = 2
REIT
REIT
I=1
IPL = 0
Figure 5.6.1 Multiple interrupts
258
I : Interrupt enable flag
IPL : Processor interrupt priority level
: Automatically executed.
: Be sure to set in software.
Chapter 5
Interrupt
5.7 Precautions for Interrupts
5.7 Precautions for Interrupts
5.7.1 Reading Address 0000016
Avoid reading the address 0000016 in a program. When a maskable interrupt request is accepted, the
CPU reads interrupt information (interrupt number and interrupt request priority level) from the address
0000016 during the interrupt sequence. At this time, the IR bit for the accepted interrupt is set to “0”.
If the address 0000016 is read in a program, the IR bit for the interrupt which has the highest priority
among the enabled interrupts is set to “0”. This may cause a problem that the interrupt is canceled, or an
unexpected interrupt is generated.
5.7.2 SP Setting
Set any value in the SP before accepting an interrupt. The SP is set to “000016” after reset. Therefore, if
an interrupt is accepted before setting any value in the SP, the program may go out of control.
5.7.3 Changing Interrupt Control Register
(1) Each interrupt control register can only be modified while no interrupt requests corresponding to that
register are generated. If interrupt requests managed by any interrupt control register are likely to
occur, disable the interrupts before changing the interrupt control register.
(2) To modify any interrupt control register after disabling interrupts, be careful with the instructions
used.
When Changing Other Than IR Bit
If an interrupt request corresponding to that register is generated while executing the instruction, the IR
bit may not be set to “1” (interrupt requested), with the result that the interrupt request is ignored. If this
presents a problem, use the following instructions to modify the register.
Instructions to use: AND, OR, BCLR, BSET
When Changing IR Bit
Even when the IR bit is cleared to “0” (interrupt not requested), it may not actually be cleared to “0”
depending on the instruction used. Therefore, use the MOV instruction to set the IR bit to “0”.
(3) When disabling interrupts using the I flag, set the I flag according to the following sample programs.
Refer to #2 for the change of interrupt control registers in the sample programs.
Sample programs 1 to 3 are to prevent the I flag from being set to “1” (interrupt enabled) before writing
to the interrupt control registers for reasons of the internal bus or the instruction queue buffer.
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Chapter 5
Interrupt
Example 1: Use NOP instructions to prevent I flag being set to “1”
before interrupt control register is changed
INT_SWITCH1:
FCLR
I
; Disable interrupts
AND.B #00H, 0056H ; Set TXIC register to “0016”
NOP
NOP
FSET
I
; Enable interrupts
Example 2: Use dummy read to have FSET instruction wait
INT_SWITCH2:
FCLR
I
AND.B #00H, 0056H
MOV.W MEM, R0
FSET
I
; Disable interrupts
; Set TXIC register to “0016”
; Dummy read
; Enable interrupts
Example 3: Use POPC instruction to change I flag
INT_SWITCH3:
PUSHC FLG
FCLR
I
; Disable interrupts
AND.B #00H, 0056H ; Set TXIC register to “0016”
POPC FLG
; Enable interrupts
260
Chapter 6
Calculation Number of Cycles
6.1 Instruction queue buffer
Chapter 6
Calculation Number of Cycles
6.1 Instruction Queue Buffer
6.1 Instruction Queue Buffer
The R8C/Tiny series have 4-stage (4-byte) instruction queue buffers. If the instruction queue buffer has a
free space when the CPU can use the bus, instruction codes are taken into the instruction queue buffer.
This is referred to as “prefetch”. The CPU reads (fetches) these instruction codes from the instruction queue
buffer as it executes a program.
Explanation about the number of cycles in Chapter 4 assumes that all the necessary instruction codes are
placed in the instruction queue buffer, and that 8-bit data is read or written to the memory without software
wait. In the following cases, more cycles may be needed than the number of cycles shown in this manual:
• When not all of the instruction codes needed by the CPU are placed in the instruction queue buffer...
Instruction codes are read in until all of the instruction codes required for program execution are available. Furthermore, the number of read cycles increases in the following cases:
(1) The number of read cycles increases as many as the number of wait cycles incurred when reading
instruction codes from an area in which software wait exists.
• When reading or writing data to an area in which software wait exists...
The number of read or write cycles increases as many as the number of wait cycles incurred.
• When reading or writing 16-bit data from/to the SFR or the internal memory...
The memory is accessed twice to read or write one 16-bit data. Therefore, the number of read or write
cycles increases by one for each 16-bit data read or written.
Note that if prefetch and data access occur in the same timing, data access has priority. Also, if more than
three bytes of instruction codes exist in the instruction queue buffer, the CPU assumes there is no free
space in the instruction queue buffer and, therefore, does not prefetch instruction code.
Figures 6.1.1 shows an example when starting a read instruction (without software wait).
262
Chapter 6
Calculation Number of Cycles
Instructions
under execution
Fetch code
JMP TEST_11
73F1
64
04
04
04
04
04
04
04
04
64
0040
Fetch
73
JMP TEST_12
MOV.W
Content at jump address is
prefetched at the same time
the instruction queue buffer
is cleared.
Instruction
queue buffer
6.1 Instruction Queue Buffer
Fetch
Content at jump address is prefetched
at the same time the instruction queue
buffer is cleared.
Fetch
73
73
00
00
00
64
64
64
04
04
04
F1
F1
40
40
40
04
04
04
04
04
04
04
04
00
04
64
04
64
04
73
73
73
FF
FF
Sample programs
Address Code
0C062
64
0C063
04
0C064
04
0C065
04
0C066
04
0C067
04
0C068
TEST_11:
0C068
73F10040
0C06C
64
0C06D
04
0C06E
04
0C06F
04
0C070
04
0C071
04
0C072
TEST_12:
00
04
Jump address
High-order address from
which to read data
Low-order address from
which to read data
BCLK
Address bus
0C065
0C068 0C069 0C06A 0C06B 0C06C 0C06D 04000 04001 0C06E
RD
73
P
0C072 0C073 0C074
Content at address 400116
Content at address 400016
Data bus
0C06F
F1
00
40
64
04
AA
AA
04
04
73
FF
00
P
P
P
P
P
DR
DR
P
P
P
P
P
WR
P : Indicates a prefetch (reading from memory into the instruction queue buffer).
DR : Indicates a data read.
DW : Indicates a data write.
: Indicates the locations of the instruction queue buffer that are cleared.
Figure 6.1.1 When starting a read instruction (without software wait state)
263
Instruction
JMP
TEST_11
NOP
NOP
NOP
NOP
NOP
MOV.W 04000h, R1
JMP
TEST_12
NOP
NOP
NOP
NOP
NOP
Q&A
Information in a Q&A form to be used to make the most of the R8C/Tiny series is given below.
Usually, one question and the answer to it are given on one page; the upper section is for the question, and
the lower section is for the answer (if a pair of question and answer extends over two or more pages, a page
number is given at the lower-right corner).
Functions closely connected with the contents of a page are shown at its upper-right corner.
Q&A-1
CPU
Q
How do I distinguish between the static base register (SB) and the frame base register (FB)?
A
SB and FB function in the same manner, so you can use them as intended in programming in the
assembly language. If you write a program in C, use FB as a stack frame base register.
Q&A-2
Interrupt
Q
Is it possible to change the value of the interrupt table register (INTB) while a program is being
executed?
A
Yes. But there can be a chance that the microcomputer runs away out of control if an interrupt
request occurs in changing the value of INTB. So it is not recommended to frequently change the
value of INTB while a program is being executed.
Q&A-3
CPU
Q
What is the difference between the user stack pointer (USP) and the interrupt stack pointer (ISP)?,
What are their roles?
A
You use USP when using the OS. When several tasks run, the OS secures stack areas to save
registers of individual tasks. Also, stack areas have to be secured, task by task, to be used for
handling interrupts that occur while tasks are being executed. If you use USP and ISP in such an
instance, the stack for interrupts can be shared by these tasks; this allows you to efficiently use
stack areas.
Q&A-4
CPU
Q
How does the instruction code become if I use a bit instruction in absolute addressing ?
A
An explanation is given here by taking BSET bit,base:16 as an example.
This instruction is a 4-byte instruction. The 2 higher-order bytes of the instruction code indicate
operation code, and the 2 lower-order bytes make up addressing mode to expresse bit,base:16.
The relation between the 2 lower-order bytes and bit,base:16 is as follows.
2 lower-order bytes = base:16 8 + bit
For example, in the case of BSET 2,0AH (setting bit 2 of address 000A16 to 1), the 2 lower-order
bytes turn to A 8 + 2 = 52H.
In the case of BSET 18,8H (setting the 18th bit from bit 0 of address 000816 to 1), the 2 lower-order
bytes turn to 8 8 + 18 = 52H, which is equivalent to BSET 2,AH.
The maximum value of base:16
8 + bit, FFFFH, indicates bit 7 of address 1FFF16. This is the
maximum bit you can specify when using the bit instruction in absolute addressing.
Q&A-5
CPU
Q
What is the difference between the DIV instruction and the DIVX instruction?
A
Either of the DIV instruction and the DIVX instruction is an instruction for signed division, the sign of
the remainder is different.
The sign of the remainder left after the DIV instruction is the same as that of the dividend, on the
contrary, the sign of the remainder of the DIVX instruction is the same as that of the divisor.
In general, the following relation among quotient, divisor, dividend, and remainder holds.
dividend = divisor quotient + remainder
Since the sign of the remainder is different between these instructions, the quotient obtained either
by dividing a positive integer by a negative integer or by dividing a negative integer by a positive
integer using the DIV instruction is different from that obtained using the DIVX instruction.
For example, dividing 10 by –3 using the DIV instruction yields –3 and leaves +1, while doing the
same using the DIVX instruction yields –4 and leaves –2.
Dividing –10 by +3 using the DIV instruction yields –3 and leaves –1, while doing the same using the
DIVX instruction yields –4 and leaves +2.
Q&A-6
Glossary
Technical terms used in this software manual are explained below. They are good in this manual only.
Glossary-1
Term
Meaning
Related word
borrow
Tomove a digit to the next lower position.
carry
carry
Tomove a digit to the next higher position.
borrow
context
Registers that a program uses.
decimal addition
An addition in terms of decimal system.
displacement
The difference between the initial position and later
position.
effective address
An after-modification address to be actually used.
extention area
For the R8C/Tiny series, the area
from 1000016 through FFFFF16.
LSB
Abbreviation for Least Significant Biit
The bit occupying the lowest-order position of a data item.
Glossary-2
MSB
Term
Meaning
Related word
macro instruction
An instruction, written in a source language, to be
expressed in a number of machine instructions when
compiled into a machine code program.
MSB
Abbreviation for Most Significant Bit
The bit occupying the highest-order position of a
data item.
LSB
operand
A part of instruction code that indicates the object on
which an operation is performed.
operation code
operation
A generic term for move, comparison, bit processing,
shift, rotation, arithmetic, logic, and branch.
operation code
A part of instruction code that indicates what sort of
operation the instruction performs.
overflow
To exceed the maximum expressible value as a result
of an operation.
pack
To join data items.
unpack
Used to mean to form two 4-bit data items into one 8bit data item, to form two 8-bit data items into one 16bit data item, etc.
SFR area
Abbreviation for Special Function Area. An area in
which control bits of peripheral circuits embodied in a
microcomputer and control registers are located.
Glossary-3
operand
Term
Meaning
Related word
shift out
To move the content of a register either to the right or
left until fully overflowed.
sign bit
A bit that indicates either a positive or a negative (the
highest-order bit).
sign extension
To extend a data length in which the higher-order to be
extended are made to have the same sign of the sign
bit. For example, sign-extending FF16 results in
FFFF16, and sign-extending 0F16 results in 000F16.
stack frame
An area for automatic variables the functions of the C
language use.
string
A sequence of characters.
unpack
To restore combined items or packed information to
pack
the original form. Used to mean to separate 8-bit
information into two parts — 4 lower-order bits and
four higher-order bits, to separate 16-bit information
into two parts — 8 lower-order bits and 8 higher-order
bits, or the like.
zero extension
To extend a data length by turning higher-order bits to
0's. For example, zero-extending FF16 to 16 bits
results in 00FF16.
Glossary-4
Table of symbols
Symbols used in this software manual are explained below. They are good in this manual only.
Symbol-1
Symbol
Meaning
Transposition from the right side to the left side
Interchange between the right side and the left side
Addition
Subtraction
Multiplication
<
Division
Logical conjunction
<
Logical disjunction
A
Exclusive disjunction
Logical negation
dsp16
16-bit displacement
dsp20
20-bit displacement
dsp8
8-bit displacement
EVA( )
An effective address indicated by what is enclosed in (Å@)
EXT( )
Sign extension
(H)
Higher-order byte of a register or memory
H4:
Four higher-order bits of an 8-bit register or 8-bit memory
Absolute value
(L)
Lower-order byte of a register or memory
L4:
Four lower-order bits of an 8-bit register or 8-bit memory
LSB
Least Significant Bit
M( )
Content of memory indicated by what is enclosed in (Å@)
(M)
Middle-order byte of a register or memory
MSB
Most Significant Bit
PCH
Higher-order byte of the program counter
PCML
Middle-order byte and lower-order byte of the program counter
FLGH
Four higher-order bits of the flag register
FLGL
Eight lower-order bits of the flag register
Symbol-2
Index
Frame base register ••• 5
A
Function ••• 37
A0 and A1 ••• 5
A1A0 ••• 5
I
Address register ••• 5
Interrupt table register ••• 5
Address space ••• 3
I flag ••• 6
Addressing mode ••• 22
Instruction code ••• 138
Instruction Format ••• 18
B
Instruction format specifier ••• 35
B flag ••• 6
INTB ••• 5
Byte (8-bit) data ••• 16
Integer ••• 10
C
Interrupt enable flag ••• 6
C flag ••• 6
Interrupt stack pointer ••• 5
Carry flag ••• 6
Interrupt vector table ••• 19
Cycles ••• 138
IPL ••• 7
ISP ••• 5
D
L
D flag ••• 6
Data arrangement in memory ••• 17
Long word (32-bit) data ••• 16
Data arrangement in Register ••• 16
M
Data register ••• 4
Maskable interrupt ••• 246
Data type ••• 10
Memory bit ••• 12
Debug flag ••• 6
Mnemonic ••• 35, 38
Description example ••• 37
dest ••• 18
N
Nibble (4-bit) data ••• 16
F
Nonmaskable interrupt ••• 246
FB ••• 5
Fixed vector table ••• 19
O
Flag change ••• 37
O flag ••• 6
Flag register ••• 5
Operand ••• 35, 38
FLG ••• 5
Index-1
Operation ••• 37
U
Overflow flag ••• 6
U flag ••• 6
User stack pointer ••• 5
P
USP ••• 5
PC ••• 5
Processor interrupt priority level ••• 7
V
Program counter ••• 5
Variable vector table ••• 20
R
W
R0, R1, R2, and R3 ••• 4
Word (16-bit) data ••• 16
R0H, R1H ••• 4
Z
R0L, R1L ••• 4
R2R0 ••• 4
Z flag ••• 6
R3R1 ••• 4
Zero flag ••• 6
Register bank ••• 8
Register bank select flag ••• 6
Register bit ••• 12
Related instruction ••• 37
Reset ••• 9
S
S flag ••• 6
SB ••• 5
Selectable src / dest (label) ••• 37
Sign flag ••• 6
Size specifier ••• 35
Software interrupt number ••• 20
src ••• 18
Stack pointer ••• 5
Stack pointer select flag ••• 6
Static base register ••• 5
String ••• 15
Syntax ••• 35, 38
Index-2
REVISION HISTORY
Rev.
R8C/Tiny Series SOFTWARE MANUAL
Date
Description
Summary
Page
1.00 Jun./19/03
First Edition
B-1
RENESAS SEMICONDUCTORS
SOFTWARE MANUAL
R8C/Tiny Series Rev.1.00
Editioned by
Committee of editing of RENESAS Semiconductor Software Manual
This book, or parts thereof, may not be reproduced in any form without permission
of
©2003
R8C/Tiny Series
Software Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan