74LVQ273 Low Voltage Octal D-Type Flip-Flop General Description Features The LVQ273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. n Ideal for low power/low noise 3.3V applications n Implements patented EMI reduction circuitry n Available in SOIC JEDEC, SOIC EIAJ and QSOP packages n Guaranteed simultaneous switching noise level and dynamic threshold performance n Improved latch-up immunity n Guaranteed incident wave switching into 75Ω n 4 kV minimum ESD immunity Ordering Code: Order Number Package Number 74LVQ273SC 74LVQ273SJ 74LVQ273QSC M20B Package Description 20-Lead (0.300" Wide) Molded Small Outline Package, SOIC JEDEC M20D 20-Lead Shrink Molded Small Outline Package, SOIC EIAJ MQA20 20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP JEDEC Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Assignment for SOIC and QSOP DS011358-1 IEEE/IEC DS011358-3 Pin Descriptions Pin Names DS011358-2 © 1998 Fairchild Semiconductor Corporation DS011358 Description D0–D7 Data Inputs MR Master Reset CP Clock Pulse Input Q0–Q7 Data Outputs www.fairchildsemi.com 74LVQ273 Low Voltage Octal D-Type Flip-Flop April 1998 Absolute Maximum Ratings (Note 1) Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current (ICC or IGND) Storage Temperature (TSTG) DC Latch-up Source or Sink Current Recommended Operating Conditions (Note 2) −0.5V to +7.0V Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate ∆V/∆t VIN from 0.8V to 2.0V VCC @ 3.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V 2.0V to 3.6V 0V to VCC 0V to VCC −40˚C to +85˚C 125 mV/ns Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. ± 50 mA ± 400 mA −65˚C to +150˚C Note 2: Unused inputs must be held HIGH or LOW. They may not float. ± 300 mA DC Electrical Characteristics Symbol VIH Parameter Minimum High Level VCC TA = +25˚C (V) Typ 3.0 1.5 TA = −40˚C to +85˚C Units 2.0 2.0 V Maximum Low Level 3.0 1.5 0.8 0.8 V VOUT = 0.1V or VCC − 0.1V Input Voltage VOH VOUT = 0.1V or VCC − 0.1V Input Voltage VIL Conditions Guaranteed Limits 2.9 2.9 V IOUT = −50 µA 2.58 2.48 V VIN = VIL or VIH (Note 3) 0.1 0.1 V IOUT = 50 µA 3.0 0.36 0.44 V VIN = VIL or VIH (Note 3) 3.6 ± 0.1 ± 1.0 µA Minimum High Level 3.0 Output Voltage 3.0 Maximum Low Level 3.0 Output Voltage Maximum Input 2.99 IOH = −12 mA VOL 0.002 IOL = 12 mA IIN VI = VCC, GND Leakage Current IOLD Minimum Dynamic 3.6 36 mA VOLD = 0.8V Max (Note 5) IOHD Output Current (Note 4) 3.6 −25 mA VOHD = 2.0V Min (Note 5) Maximum Quiescent 3.6 40.0 µA VIN = VCC or GND ICC 4.0 Supply Current VOLP Quiet Output 3.3 0.4 0.8 V (Notes 6, 7) 3.3 −0.3 −0.8 V (Notes 6, 7) 3.3 1.7 2.0 V (Notes 6, 8) 3.3 1.6 0.8 V (Notes 6, 8) Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL VIHD Maximum High Level Dynamic Input Voltage VILD Maximum Low Level Dynamic Input Voltage Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for. Note 6: Worst case package. Note 7: Max number of outputs defined as (n). Data Inputs are driven 0V to 3.3V; one output at GND. Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. www.fairchildsemi.com 2 AC Electrical Characteristics Symbol VCC (V) Parameter Min fmax Maximum Clock Frequency Propagation Delay tPLH CP to Qn Propagation Delay tPHL CP to Qn Propagation Delay tPHL MR to Qn tOSHL Output to Output tOSLH Skew (Note 9) TA = +25˚C TA = −40˚C to +85˚C CL = 50 pF CL = 50 pF Typ Max Min 2.7 50 45 3.3 ± 0.3 90 75 Units Max MHz 2.7 4.0 9.6 17.6 3.0 20.0 3.3 ± 0.3 4.0 8.0 12.5 3.0 14.0 2.7 4.0 10.2 18.3 3.5 20.5 3.3 ± 0.3 4.0 8.5 13.0 3.5 14.5 2.7 4.0 10.2 18.3 3.5 20.0 3.3 ± 0.3 4.0 8.5 13.0 3.5 14.0 2.7 1.0 1.5 1.5 3.3 ± 0.3 1.0 1.5 1.5 ns ns ns ns Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design. Not tested. AC Operating Requirements Symbol Parameter VCC (V) TA = +25˚C TA = −40˚C to +85˚C CL = 50 pF CL = 50 pF Typ Setup Time, HIGH or LOW tS Dn to CP Hold Time, HIGH or LOW tH Dn to CP HIGH or LOW MR Pulse Width tW HIGH or LOW Recovery Time tW Guaranteed Minimum 2.7 6.5 8.5 3.3 ± 0.3 5.0 6.0 2.7 0.0 0.0 3.3 0.0 0.0 ± 0.3 Clock Pulse Width tW MR to CP Units 2.7 7.0 8.5 3.3 ± 0.3 5.5 6.0 2.7 7.0 8.5 3.3 ± 0.3 5.5 6.0 2.7 5.0 6.5 3.3 ± 0.3 4.0 4.5 ns ns ns ns ns Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = Open Conditions CPD (Note 10) Power Dissipation Capacitance 35 pF VCC = 3.3V Note 10: CPD is measured at 10 MHz. 3 www.fairchildsemi.com 4 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead (0.300" Wide) Molded Small Outline Package, SOIC JEDEC Package Number M20B 20-Lead Shrink Molded Small Outline Package, SOIC EIAJ Package Number M20D 5 www.fairchildsemi.com 74LVQ273 Low Voltage Octal D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP JEDEC (also known as QSOP) Package Number MQA20 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and (c) whose device or system, or to affect its safety or effectiveness. failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. Fairchild Semiconductor Corporation Americas Customer Response Center Tel: 1-888-522-5372 www.fairchildsemi.com Fairchild Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 8 141-35-0 English Tel: +44 (0) 1 793-85-68-56 Italy Tel: +39 (0) 2 57 5631 Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. 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