CS8129 5.0 V, 750 mA Low Dropout Linear Regulator with Lower RESET Threshold The CS8129 is a precision 5.0 V linear regulator capable of sourcing 750 mA. The RESET threshold voltage has been lowered to 4.2 V so that the regulator can be used with 4.0 V microprocessors. The lower RESET threshold also permits operation under low battery conditions (5.5 V plus a diode). The RESET’s delay time is externally programmed using a discrete RC network. During power up, or when the output goes out of regulation, RESET remains in the low state for the duration of the delay. This function is independent of the input voltage and will function correctly as long as the output voltage remains at or above 1.0 V. Hysteresis is included in the Delay and the RESET comparators to improve noise immunity. A latching discharge circuit is used to discharge the delay capacitor when it is triggered by a brief fault condition. The regulator is protected against a variety of fault conditions: i.e. reverse battery, overvoltage, short circuit and thermal runaway conditions. The regulator is protected against voltage transients ranging from –50 V to +40 V. Short circuit current is limited to 1.2 A (typ). The CS8129 is packaged in a 5 lead TO–220 and a 16 lead surface mount package. http://onsemi.com TO–220 FIVE LEAD T SUFFIX CASE 314D 1 TO–220 FIVE LEAD TVA SUFFIX CASE 314K 1 1 Features • 5.0 V ±3.0% Regulated Output • Low Dropout Voltage (0.6 V @ 0.5 A) • 750 mA Output Current Capability • Reduced RESET Threshold for use with 4.0 V Microprocessors • Externally Programmed RESET Delay • Fault Protection – Reverse Battery – 60 V, –50 V Peak Transient Voltage – Short Circuit – Thermal Shutdown 5 TO–220 FIVE LEAD THA SUFFIX CASE 314A 5 SO–16L DW SUFFIX CASE 751G 16 1 ORDERING INFORMATION Device Package Shipping CS8129YT5 TO–220* STRAIGHT 50 Units/Rail CS8129YTHA5 TO–220* VERTICAL 50 Units/Rail CS8129YTVA5 TO–220* HORIZONTAL 50 Units/Rail CS8129YDW16 SO–16L 46 Units/Rail CS8129YDWR16 SO–16L 1000 Tape & Reel *Five lead. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 8 of this data sheet. Semiconductor Components Industries, LLC, 2001 April, 2001 – Rev. 6 1 Publication Order Number: CS8129/D CS8129 PIN CONNECTIONS TO–220 5 LEAD 1 SO–16L VIN NC NC GND GND RESET NC Delay Pin 1. VIN 2. RESET 3. GND 4. Delay 5. VOUT 16 VOUT NC VOUT(SENSE) GND GND GND NC NC 1 VIN Over Voltage Shutdown VOUT Regulated Supply for Circuit Bias Pre–Regulator Bandgap Reference – + Charge Current Generator Delay Error Amplifier Anti–Saturation and Current Limit VOUT (SENSE) Thermal Shutdown Latching Discharge – Q S + R – + VDISCHARGE RESET Delay Comparator + – GND Figure 1. Block Diagram ABSOLUTE MAXIMUM RATINGS* Rating Input Operating Range Power Dissipation Peak Transient Voltage (46 V Load Dump @ 14 V VIN) Output Current Value Unit –0.5 to 26 V Internally Limited – –50, 60 V Internally Limited – 4.0 kV Junction Temperature –55 to +150 °C Storage Temperature Range –55 to +150 °C 260 peak 230 peak °C Electrostatic Discharge (Human Body Model) Lead Temperature Soldering: Wave Solder (through hole styles only) (Note 1.) Reflow (SMD styles only) (Note 2.) 1. 10 second maximum. 2. 60 seconds max above 183°C. *The maximum package power dissipation must be observed. http://onsemi.com 2 CS8129 ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ 125°C, –40 ≤ TJ ≤ 150°C, 6.0 ≤ VIN ≤ 26 V, 5.0 mA ≤ IOUT ≤ 500 mA, RRESET = 4.7 kΩ to VOUT unless otherwise noted.) Note 3. Characteristic Test Conditions Min Typ Max Unit – 4.85 5.0 5.15 V Output Stage (VOUT) Output Voltage Dropout Voltage IOUT = 500 mA – 0.35 0.60 V Supply Current IOUT = 10 mA IOUT = 100 mA IOUT = 500 mA – – – 2.0 6.0 55 7.0 12 100 mA mA mA Line Regulation 6.0 V ≤ VIN ≤ 26 V, IOUT = 50 mA – 5.0 50 mV Load Regulation 50 mA ≤ IOUT ≤ 500 mA, VIN = 14 V – 10 50 mV Ripple Rejection f = 120 Hz, VIN = 7.0 to 17 V, IOUT = 250 mA 54 75 – dB Current Limit – 0.75 1.20 – A Overvoltage Shutdown – 32 – 40 V Reverse Polarity Input Voltage DC VOUT ≥ –0.6 V, 10 Ω Load –15 –30 – V Thermal Shutdown Guaranteed by Design 150 180 210 °C Delay Charge Current VDELAY = 2.0 V 5.0 10 15 µA RESET Threshold VOUT Increasing, VRT(ON) VOUT Decreasing, VRT(OFF) 4.05 4.00 4.35 4.20 4.50 4.45 V V RESET Hysteresis VRH = VRT(ON) – VRT(OFF) 50 150 250 mV Delay Threshold Charge, VDC(HI) Discharge, VDC(LO) 3.25 2.85 3.50 3.10 3.75 3.35 V V 200 400 800 mV RESET and Delay Functions Delay Hysteresis – RESET Output Voltage Low 1.0 V < VOUT < VRT(L), 3.0 kΩ to VOUT – 0.1 0.4 V RESET Output Leakage VOUT > VRT(H) Current – 0 10 µA Delay Capacitor Discharge Voltage Discharge Latched “ON”, VOUT > VRT – 0.2 0.5 V Delay Time CDELAY = 0.1 µF, Note 4. 16 32 48 ms 3. To observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable. 4. Assuming ideal capacitor. CDelay VDelay Threshold Charge CDelay 3.5 105(typ) DelayTime ICharge http://onsemi.com 3 CS8129 PACKAGE LEAD DESCRIPTION PACKAGE LEAD # SO–16L TO–220 5 LEAD LEAD SYMBOL 1 1 VIN 16 5 VOUT Regulated 5.0 V output. 4, 5, 11, 12, 13 3 GND Ground Connection. 8 4 Delay Timing capacitor for RESET function. 6 2 RESET 14 N/A VOUT(SENSE) FUNCTION Unregulated supply voltage to IC. CMOS/TTL compatible output lead. RESET goes low whenever VOUT drops below 6.0% of it’s regulated value. Remote sensing of output voltage. TYPICAL PERFORMANCE CHARACTERISTICS 55 50 120 RLOAD = 25 Ω Room Temp RLOAD = 6.67 Ω 100 45 35 30 ICQ. (mA) ICQ (mA) 40 125°C 25 20 60 RLOAD = 10 Ω 40 15 25°C 10 RLOAD = 25 Ω 20 –40°C 5 0 80 RLOAD = NO LOAD 0 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 VIN (V) 4.5 4.5 4.0 4.0 3.5 3.5 3.0 125°C 2.5 2.0 8 9 10 RLOAD = 6.67 Ω 3.0 RLOAD = NO LOAD 2.5 2.0 1.5 1.5 1.0 1.0 –40°C 25°C 0.5 0 7 Room Temp 5.0 VOUT (V) VOUT (V) 5.5 RLOAD = 25 Ω 5.0 6 Figure 3. Quiescent Current vs. Input Voltage Over Load Resistance Figure 2. Quiescent Current vs. Input Voltage Over Temperature 5.5 5 VIN (V) 0 1 2 3 RLOAD = 10 Ω 0.5 4 5 6 7 8 9 0 10 0 1 2 3 4 5 6 7 8 VIN (V) VIN (V) Figure 4. Output Voltage vs. Input Voltage Over Temperature Figure 5. VOUT vs. VIN Over RLOAD http://onsemi.com 4 9 10 CS8129 TYPICAL PERFORMANCE CHARACTERISTICS 100 100 VIN = 6–26 V 80 80 40 Load Regulation (mV) Line Reg. (mV) 60 TEMP = 25°C 20 TEMP = –40°C 0 –20 –40 TEMP = 125°C –60 40 20 TEMP = 25°C 0 VIN = 14 V –20 –40 –60 TEMP = 125°C –80 –80 –100 –100 0 100 200 300 400 500 600 700 0 800 200 300 400 500 Figure 7. Load Regulation vs. Output Current 800 90 700 80 25°C 600 500 125°C 400 300 –40°C 200 100 VIN = 14 V 70 25°C 125°C 60 50 40 30 20 –40°C 10 0 0 100 200 300 400 500 600 700 800 0 100 200 300 IOUT = 250 mA 800 CO = 47/68 µF 101 ESR (ohms) 60 50 Stable Region 100 10–1 COUT = 10 µF, ESR = 1.0 Ω 30 700 102 70 40 600 103 COUT = 10 µF, ESR = 1.0 & 0.1 µF, ESR = 0 80 500 Figure 9. Quiescent Current vs. Output Current Figure 8. Dropout Voltage vs. Output Current 90 400 Output Current (mA) Output Current (mA) Rejection (dB) 800 700 Figure 6. Line Regulation vs. Output Current 100 CO = 47 µF 10–2 20 COUT = 10 µF, ESR = 1.0 Ω 10 0 600 Output Current (mA) 900 0 100 Output Current (mA) Quiescent Current (mA) Dropout Voltage (mV) TEMP = –40°C 60 100 101 102 103 104 105 106 CO = 68 µF 10–3 107 10–4 108 100 Frequency (Hz) 101 102 Output Current (mA) Figure 10. Ripple Rejection Figure 11. Output Capacitor ESR http://onsemi.com 5 103 CS8129 VOUT (1) = No Delay Capacitor (2) = With Delay Capacitor (3) = Max: RESET Voltage (1.0 V) VRH VRT(ON) VRT(OFF) RESET (1) (3) (2) VRL tDELAY DELAY VDH VDC(HI) VDC(LO) (2) VDIS Figure 12. RESET Circuit Waveform CIRCUIT DESCRIPTION The CS8129 RESET function has hysteresis on both the reset and delay comparators, a latching Delay capacitor discharge circuit, and operates down to 1.0 V. The RESET circuit output is an open collector type with ON and OFF parameters as specified. The RESET output NPN transistor is controlled by the two circuits described (see Block Diagram on page 2). condition. The circuit allows the RESET output transistor to go to the OFF (open) state only when the voltage on the Delay lead is higher than VDC(HI). VOUT VIN CIN* 100 nF CS8129 RRST 4.7 kΩ RESET Low Voltage Inhibit Circuit Delay This circuit monitors output voltage, and when output voltage is below the specified minimum causes the RESET output transistor to be in the ON (saturation) state. When the output voltage is above the specified level, this circuit permits the RESET output transistor to go into the OFF state if allowed by the RESET Delay circuit. COUT** 10 µF to 100 µF GND Delay 0.1 µF *CIN is required if regulator is far from the power source filter. **COUT is required for stability. Reset Delay Circuit Figure 13. Test & Application Circuit This circuit provides a programmable (by external capacitor) delay on the RESET output lead. The Delay lead provides source current to the external delay capacitor only when the “Low Voltage Inhibit” circuit indicates that output voltage is above VRT(ON). Otherwise, the Delay lead sinks current to ground (used to discharge the delay capacitor). The discharge current is latched ON when the output voltage is below VRT(OFF). The Delay capacitor is fully discharged anytime the output voltage falls out of regulation, even for a short period of time. This feature ensures that a controlled RESET pulse is generated following detection of an error The Delay time for the RESET function is calculated from the formula: Delay time CDelay VDelay Threshold ICharge Delay time CDelay(F) 3.2 105 If CDelay = 0.1 µF, Delay time (ms) = 32 ms ±50%: i.e. 16 ms to 48 ms. The tolerance of the capacitor must be taken into account to calculate the total variation in the delay time. http://onsemi.com 6 CS8129 APPLICATION NOTES STABILITY CONSIDERATIONS Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of ± 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above. The output or compensation capacitor helps determine three main characteristics of a linear regulator: start–up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (–25°C to –40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor COUT shown in Figure 13 should work for most applications, however it is not necessarily the optimized solution. To determine an acceptable value for COUT for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations. CALCULATING POWER DISSIPATION IN A SINGLE OUTPUT LINEAR REGULATOR The maximum power dissipation for a single output regulator (Figure 14) is: PD(max) VIN(max) VOUT(min)IOUT(max) VIN(max)IQ (1) where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RΘJA can be calculated: RJA 150°C TA PD (2) The value of RΘJA can then be compared with those in the package section of the data sheet. Those packages with RΘJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. IIN VIN SMART REGULATOR IOUT Control Features IQ Figure 14. Single Output Regulator With Key Performance Parameters Labeled http://onsemi.com 7 VOUT CS8129 HEAT SINKS where: RΘJC = the junction–to–case thermal resistance, RΘCS = the case–to–heatsink thermal resistance, and RΘSA = the heatsink–to–ambient thermal resistance. RΘJC appears in the package section of the data sheet. Like RΘJA, it too is a function of package type. RΘCS and RΘSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers. A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RΘJA. RJA RJC RCS RSA (3) MARKING DIAGRAMS TO–220 FIVE LEAD SO–16L 16 CS8129 AWLYYWW CS8129 AWLYWW 1 1 A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week http://onsemi.com 8 CS8129 PACKAGE DIMENSIONS TO–220 FIVE LEAD T SUFFIX CASE 314D–04 ISSUE E –T– –Q– SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. C B E A U L K J H G D DIM A B C D E G H J K L Q U 1234 5 5 PL 0.356 (0.014) M T Q M INCHES MIN MAX 0.572 0.613 0.390 0.415 0.170 0.180 0.025 0.038 0.048 0.055 0.067 BSC 0.087 0.112 0.015 0.025 0.990 1.045 0.320 0.365 0.140 0.153 0.105 0.117 MILLIMETERS MIN MAX 14.529 15.570 9.906 10.541 4.318 4.572 0.635 0.965 1.219 1.397 1.702 BSC 2.210 2.845 0.381 0.635 25.146 26.543 8.128 9.271 3.556 3.886 2.667 2.972 TO–220 FIVE LEAD TVA SUFFIX CASE 314K–01 ISSUE O –T– SEATING PLANE C B –Q– E W A U F L 1 2 3 4 K 5 M D 0.356 (0.014) M J 5 PL T Q M G S R http://onsemi.com 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. DIM A B C D E F G J K L M Q R S U W INCHES MIN MAX 0.560 0.590 0.385 0.415 0.160 0.190 0.027 0.037 0.045 0.055 0.530 0.545 0.067 BSC 0.014 0.022 0.785 0.800 0.321 0.337 0.063 0.078 0.146 0.156 0.271 0.321 0.146 0.196 0.460 0.475 5° MILLIMETERS MIN MAX 14.22 14.99 9.78 10.54 4.06 4.83 0.69 0.94 1.14 1.40 13.46 13.84 1.70 BSC 0.36 0.56 19.94 20.32 8.15 8.56 1.60 1.98 3.71 3.96 6.88 8.15 3.71 4.98 11.68 12.07 5° CS8129 TO–220 FIVE LEAD THA SUFFIX CASE 314A–03 ISSUE E –T– B –P– Q C E OPTIONAL CHAMFER A U F L G 5X NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 0.043 (1.092) MAXIMUM. SEATING PLANE DIM A B C D E F G J K L Q S U K 5X J S D 0.014 (0.356) T P M M INCHES MIN MAX 0.572 0.613 0.390 0.415 0.170 0.180 0.025 0.038 0.048 0.055 0.570 0.585 0.067 BSC 0.015 0.025 0.730 0.745 0.320 0.365 0.140 0.153 0.210 0.260 0.468 0.505 MILLIMETERS MIN MAX 14.529 15.570 9.906 10.541 4.318 4.572 0.635 0.965 1.219 1.397 14.478 14.859 1.702 BSC 0.381 0.635 18.542 18.923 8.128 9.271 3.556 3.886 5.334 6.604 11.888 12.827 SO–16L DW SUFFIX CASE 751G–03 ISSUE B A D 9 1 8 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. h X 45 E 0.25 16X M 14X e T A S B S L A 0.25 DIM A A1 B C D E e H h L B B SEATING PLANE A1 H 8X M B M 16 T C PACKAGE THERMAL DATA Parameter TO–220 FIVE LEAD SO–16L Unit RΘJC Typical 2.1 23 °C/W RΘJA Typical 50 105 °C/W http://onsemi.com 10 MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 10.15 10.45 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0 7 CS8129 Notes http://onsemi.com 11 CS8129 SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: [email protected] Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada N. American Technical Support: 800–282–9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor – European Support German Phone: (+1) 303–308–7140 (Mon–Fri 2:30pm to 7:00pm CET) Email: ONlit–[email protected] French Phone: (+1) 303–308–7141 (Mon–Fri 2:00pm to 7:00pm CET) Email: ONlit–[email protected] English Phone: (+1) 303–308–7142 (Mon–Fri 12:00pm to 5:00pm GMT) Email: [email protected] CENTRAL/SOUTH AMERICA: Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST) Email: ONlit–[email protected] Toll–Free from Mexico: Dial 01–800–288–2872 for Access – then Dial 866–297–9322 ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support Phone: 1–303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001–800–4422–3781 Email: ONlit–[email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2700 Email: [email protected] ON Semiconductor Website: http://onsemi.com EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781 *Available from Germany, France, Italy, UK, Ireland For additional information, please contact your local Sales Representative. http://onsemi.com 12 CS8129/D