HD66702 (Dot Matrix Liquid Crystal Display Controller/Driver) Description The HD66702 dot-matrix liquid crystal display controller and driver LSI displays alphanumerics, Japanese kana characters, and symbols. It can be configured to drive a dot-matrix liquid crystal display under the control of a 4- or 8-bit microprocessor. Since all the functions required for driving a dot-matrix liquid crystal display are internally provided on one chip, a minimal system can be interfaced with this controller/driver. A single HD66702 can display up to two 20-character lines. The low 3-V power supply of the HD66702 under development is suitable for any portable battery-driven product requiring low power dissipation. Features • 5 × 7 and 5 × 10 dot matrix possible • 80 × 8-bit display RAM (80 characters max.) • 7,200-bit character generator ROM 160 character fonts (5 × 7 dot) 32 character fonts (5 × 10 dot) • 64 × 8-bit character generator RAM 8 character fonts (5 × 7 dot) 4 character fonts (5 × 10 dot) • 16-common × 100-segment liquid crystal display driver • Programmable duty cycles 1/8 for one line of 5 × 7 dots with cursor 1/11 for one line of 5 × 10 dots with cursor 1/16 for two lines of 5 × 7 dots with cursor 227 HD66702 • Maximum display characters One line 1/8 duty cycle, 20-char. × 1-line 1/11 duty cycle, 20-char. × 1-line Two lines 1/16 duty cycle, 20-char. × 2-line • Wide range of instruction functions Display clear, cursor home, display on/off, cursor on/off, display character blink, cursor shift, display shift • Choice of power supply (VCC): 4.5 to 5.5V (standard), 2.7 to 5.5V (low voltage) • Automatic reset circuit that initializes the controller/driver after power on (standard version only) • Independent LCD drive voltage driven off of the logic power supply (VCC): 3.0 to 8.3V • Low power dissipation • LQFP2020-144-pin, chip, chip wtith bump Ordering Information Type No. Package Operating Voltage ROM Font HCD66702RA00L 144-pin-chip 2.7 to 5.5V Standard Japanese HCD66702RA00BP 144-pin-chip with bump 2.7 to 5.5V Standard Japanese HCD66702RA01L 144-pin-chip 2.7 to 5.5V Communication system HCD66702RA02L 144-pin-chip 2.7 to 5.5V European font HD66702RA00F FP-144A 4.5 to 5.5V Standard Japanese HD66702RA00FL FP-144A 2.7 to 5.5V Standard Japanese HD66702RA01F FP-144A 4.5 to 5.5V Communication font HD66702RA02F FP-144A 4.5 to 5.5V European font 228 HD66702 LCD-II Family Comparison Item LCD-II (HD44780U) Power supply voltage HD66702 HD66710 HD66712U 2.7V to 5.5V 5 V ±10 % (standard) 2.7 V to 5.5V (low voltage) 2.7V to 5.5V 2.7V to 5.5V Liquid crystal drive voltage 3.0V to 11 V 3.0V to 8.3V 3.0V to 13.0V 2.7V to 11.0V Maximum display digits per chip 8 characters × 2 lines 20 characters × 2 lines 16 characters × 2 lines/ 8 characters × 4 lines 24 characters × 2 lines/ 12 characters × 4 lines Segment display None None 40 segments 60 segments Display duty cycle 1/8, 1/11, and 1/16 1/8, 1/11, and 1/16 1/17 and 1/33 1/17 and 1/33 CGROM 9,920 bits (208 5 × 8 dot characters and 32 5 × 10 dot characters) 7,200 bits (160 5 × 7 dot characters and 32 5 × 10 dot characters) 9,600 bits (240 5 × 8 dot characters) 9,600 bits (240 5 × 8 dot characters) CGRAM 64 bytes 64 bytes 64 bytes 64 bytes DDRAM 80 bytes 80 bytes 80 bytes 80 bytes SEGRAM None None 8 bytes 16 bytes Segment signals 40 100 40 60 Common signals 16 16 33 34 Liquid crystal drive waveform A B B B Bleeder resistor for LCD power supply External (adjustable) External (adjustable) External (adjustable) External (adjustable) Clock source External resistor or External resistor or External resistor external clock external clock or external clock External resistor or external clock Rf oscillation frequency (frame frequency) 270 kHz ±30% (59 to 110 Hz for 1/8 and 1/16 duty cycle; 43 to 80 Hz for 1/11 duty cycle) 320 kHz ±30% (70 to 130 Hz for 1/8 and 1/16 duty cycle; 51 to 95 Hz for 1/11 duty cycle) 270 kHz ±30% (56 to 103 Hz for 1/17 duty cycle; 57 to 106 Hz for 1/33 duty cycle) 270 kHz ±30% (56 to 103 Hz for 1/17 duty cycle; 57 to 106 Hz for 1/33 duty cycle) Rf resistance 91 kΩ: 5-V operation; 75 kΩ: 3-V operation 68 kΩ: 5-V operation; 56 kΩ: (3-V operation) 91 kΩ: 5-V operation; 75 kΩ: 3-V operation 130 kΩ: 5-V operation 110 kΩ: 3-V operation 229 HD66702 LCD-II (HD44780) HD66702 HD66710 Liquid crystal voltage booster circuit None None 2-3 times step-up 2-3 times step-up circuit circuit Extension driver control signal Independent control signal Independent control signal Used in common with a driver output pin Reset function Power on automatic Power on automatic Power on reset reset automatic reset Power on automatic reset or Reset input Instructions LCD-II (HD44780) Fully compatible with the LCD-II Uppercompatible with the LCD-II Upper compatible with the LCD-II Number of displayed lines 1 or 2 1 or 2 1, 2, or 4 1, 2, or 4 Low power mode None None Available Available Horizontal scroll Character unit Character unit Dot unit Dot unit Bus interface 4 bits/8 bits 4 bits/8 bits 4 bits/8 bits Serial; 4 bits/8 bits CPU bus timing 2 MHz: 5-V operation; 1 MHz: 3-V operation 1 MHz 2 MHz: 5-V operation; 1 MHz: 3-V operation 2 MHz: 5-V operation; 1 MHz: 3-V operation Package QFP-1420-80 80-pin bare chip LQFP-2020-144 144-pin bare chip QFP-1420-100 TCP-128 TQFP-1414-100 128-pin bare chip 100-pin bare chip Item 230 HD66712U Independent control signal HD66702 HD66702 Block Diagram OSC1 OSC2 EXT M Reset circuit ACL Timing generator CPG 8 RS R/W E Instruction register (IR) 7 Input/ output buffer 8 16-bit shift register Common signal driver 100-bit latch circuit Segment signal driver 7 100-bit shift register 8 7 DB4 to DB7 D Display data RAM (DDRAM) 80 × 8 bits Instruction decoder MPU interface Address counter DB0 to DB3 CL1 CL2 Data register (DR) SEG1 to SEG100 100 8 8 GND 16 7 8 LCD drive voltage selector Busy flag TEST COM1 to COM16 Character generator ROM (CGROM) 7,200 bits Character generator RAM (CGRAM) 64 bytes 5 Cursor and blink controller 5 Parallel/serial converter and attribute circuit VCC V1 V2 V3 V4 V5 231 HD66702 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 HD66702 Pad Arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 (Top view) Type code HD66702 OSC1 VCC VCC V1 V2 V3 V4 V5 CL1 CL2 M D EXT TEST* GND RS R/W E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 GND OSC2 Note: * : : : : : : 232 Test pins to be grounded Power supply pins Power supply pins (ground) Input pins Output pins Input/Output pins Chip size = 5.20 × 5.20 mm Minimum pad pitch = 130 µm Pad size = 90 × 90 µm 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 COM16 COM15 COM14 COM13 COM12 COM11 HD66702 HCD66702 Pad Location Coordinates Pad No. Pad Name X (µm) Y (µm) Pad No. Pad Name 1 SEG34 –2475 X (µm) Y (µm) 2350 31 SEG4 –2475 –1600 2 SEG33 –2475 2205 32 SEG3 –2475 –1735 3 SEG32 –2475 2065 33 SEG2 –2475 –1870 4 SEG31 –2475 1925 34 SEG1 –2475 –2010 5 SEG30 –2475 1790 35 GND –2475 –2180 6 SEG29 –2475 1655 36 OSC2 –2475 –2325 7 SEG28 –2475 1525 37 OSC1 –2445 –2475 8 SEG27 –2475 1395 38 VCC –2305 –2475 9 SEG26 –2475 1265 39 VCC –2165 –2475 10 SEG25 –2475 1135 40 V1 –2025 –2475 11 SEG24 –2475 1005 41 V2 –1875 –2475 12 SEG23 –2475 875 42 V3 –1745 –2475 13 SEG22 –2475 745 43 V4 –1595 –2475 14 SEG21 –2475 615 44 V5 –1465 –2475 15 SEG20 –2475 485 45 CL1 –1335 –2475 16 SEG19 –2475 355 46 CL2 –1185 –2475 17 SEG18 –2475 225 47 M –1055 –2475 18 SEG17 –2475 95 48 D –905 –2475 19 SEG16 –2475 –35 49 EXT –775 –2475 20 SEG15 –2475 –165 50 TEST –625 –2475 21 SEG14 –2475 –295 51 GND –495 –2475 22 SEG13 –2475 –425 52 RS –345 –2475 23 SEG12 –2475 –555 53 R/: –195 –2475 24 SEG11 –2475 –685 54 E –45 –2475 25 SEG10 –2475 –815 55 DB0 85 –2475 26 SEG9 –2475 –945 56 DB1 235 –2475 27 SEG8 –2475 –1075 57 DB2 365 –2475 28 SEG7 –2475 –1205 58 DB3 515 –2475 29 SEG6 –2475 –1335 59 DB4 645 –2475 30 SEG5 –2475 –1465 60 DB5 795 –2475 233 HD66702 Pad No. Pad Name X (µm) Y (µm) Pad No. Pad Name X (µm) 61 DB6 925 –2475 91 SEG88 2475 95 62 DB7 1075 –2475 92 SEG87 2475 225 63 COM1 1205 –2475 93 SEG86 2475 355 64 COM2 1335 –2475 94 SEG85 2475 485 65 COM3 1465 –2475 95 SEG84 2475 615 66 COM4 1595 –2475 96 SEG83 2475 745 67 COM5 1725 –2475 97 SEG82 2475 875 68 COM6 1855 –2475 98 SEG81 2475 1005 69 COM7 1990 –2475 99 SEG80 2475 1135 70 COM8 2125 –2475 100 SEG79 2475 1265 71 COM9 2265 –2475 101 SEG78 2475 1395 72 COM10 2410 –2475 102 SEG77 2475 1525 73 COM11 2475 –2290 103 SEG76 2475 1655 74 COM12 2475 –2145 104 SEG75 2475 1790 75 COM13 2475 –2005 105 SEG74 2475 1925 76 COM14 2475 –1865 106 SEG73 2475 2065 77 COM15 2475 –1730 107 SEG72 2475 2205 78 COM16 2475 –1595 108 SEG71 2475 2350 79 SEG100 2475 –1465 109 SEG70 2320 2475 80 SEG99 2475 –1335 110 SEG69 2175 2475 81 SEG98 2475 –1205 111 SEG68 2035 2475 82 SEG97 2475 –1075 112 SEG67 1895 2475 83 SEG96 2475 –945 113 SEG66 1760 2475 84 SEG95 2475 –815 114 SEG65 1625 2475 85 SEG94 2475 –685 115 SEG64 1495 2475 86 SEG93 2475 –555 116 SEG63 1365 2475 87 SEG92 2475 –425 117 SEG62 1235 2475 88 SEG91 2475 –295 118 SEG61 1105 2475 89 SEG90 2475 –165 119 SEG60 975 2475 90 SEG89 2475 –35 120 SEG59 845 2475 234 Y (µm) HD66702 Pad No. Pad Name X (µm) Y (µm) Pad No. Pad Name X (µm) 121 SEG58 715 2475 133 SEG46 –845 2475 122 SEG57 585 2475 134 SEG45 –975 2475 123 SEG56 455 2475 135 SEG44 –1105 2475 124 SEG55 325 2475 136 SEG43 –1235 2475 125 SEG54 195 2475 137 SEG42 –1365 2475 126 SEG53 65 2475 138 SEG41 –1495 2475 127 SEG52 –65 2475 139 SEG40 –1625 2475 128 SEG51 –195 2475 140 SEG39 –1760 2475 129 SEG50 –325 2475 141 SEG38 –1895 2475 130 SEG49 –455 2475 142 SEG37 –2035 2475 131 SEG48 –585 2475 143 SEG36 –2175 2475 132 SEG47 –715 2475 144 SEG35 –2320 2475 Y (µm) Notes: 1. Coordinates originate from the chip center. 2. The above are preliminary specifications, and may be subject to change. 235 HD66702 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 HD66702 Pin Arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 FP-144A (Top view) OSC1 VCC VCC V1 V2 V3 V4 V5 CL1 CL2 M D EXT TEST * GND RS R/W E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 GND OSC2 Note: * : : : : : : 236 Test pins to be grounded Power supply pins Power supply pins (ground) Input pins Output pins Input/Output pins 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 COM16 COM15 COM14 COM13 COM12 COM11 HD66702 Pin Functions Table 1 Pin Functional Description Signal I/O Device Interfaced with RS I MPU Selects registers 0: Instruction register (for write) Busy flag: address counter (for read) 1: Data register (for write and read) R/: I MPU Selects read or write 0: Write 1: Read E I MPU Starts data read/write DB4 to DB7 I/O MPU Four high order bidirectional tristate data bus pins. Used for data transfer between the MPU and the HD66702. DB7 can be used as a busy flag. DB0 to DB3 I/O MPU Four low order bidirectional tristate data bus pins. Used for data transfer between the MPU and the HD66702. These pins are not used during 4-bit operation. Function CL1 O Extension driver Clock to latch serial data D sent to the extension driver CL2 O Extension driver Clock to shift serial data D M O Extension driver Switch signal for converting the liquid crystal drive waveform to AC D O Extension driver Character pattern data corresponding to each segment signal COM1 to COM16 O LCD Common signals that are not used are changed to nonselection waveforms. COM9 to COM16 are nonselection waveforms at 1/8 duty factor and COM12 to COM16 are non-selection waveforms at 1/11 duty factor. SEG1 to SEG100 O LCD Segment signals V1 to V5 — Power supply Power supply for LCD drive VCC, GND — Power supply VCC: +5V or +3V, GND: 0V TEST I — Test pin, which must be grounded EXT I — 0: Enables extension driver control signals CL1, CL2, M, and D to be output from its corresponding pins. 1: Drives CL1, CL2, M, and D as tristate, lowering power dissipation. OSC1, OSC2 — — Pins for connecting the registers of the internal clock oscillation. When the pin input is an external clock, it must be input to OSC1. 237 HD66702 Function Description Registers The HD66702 has two 8-bit registers, an instruction register (IR) and a data register (DR). The IR stores instruction codes, such as display clear and cursor shift, and address information for display data RAM (DDRAM) and character generator RAM (CGRAM). The IR can only be written from the MPU. The DR temporarily stores data to be written into DDRAM or CGRAM. Data written into the DR from the MPU is automatically written into DDRAM or CGRAM by an internal operation. The DR is also used for data storage when reading data from DDRAM or CGRAM. When address information is written into the IR, data is read and then stored into the DR from DDRAM or CGRAM by an internal operation. Data transfer between the MPU is then completed when the MPU reads the DR. After the read, data in DDRAM or CGRAM at the next address is sent to the DR for the next read from the MPU. By the register selector (RS) signal, these two registers can be selected (Table 2). Busy Flag (BF) When the busy flag is 1, the HD66702 is in the internal operation mode, and the next instruction will not be accepted. When RS = 0 and R/W = 1 (Table 2), the busy flag is output to DB7. The next instruction must be written after ensuring that the busy flag is 0. Address Counter (AC) The address counter (AC) assigns addresses to both DDRAM and CGRAM. When an address of an instruction is written into the IR, the address information is sent from the IR to the AC. Selection of either DDRAM or CGRAM is also determined concurrently by the instruction. After writing into (reading from) DDRAM or CGRAM, the AC is automatically incremented by 1 (decremented by 1). The AC contents are then output to DB0 to DB6 when RS = 0 and R/ = 1 (Table 2). : Table 2 Register Selection : RS R/ 0 0 IR write as an internal operation (display clear, etc.) 0 1 Read busy flag (DB7) and address counter (DB0 to DB6) 1 0 DR write as an internal operation (DR to DDRAM or CGRAM) 1 1 DR read as an internal operation (DDRAM or CGRAM to DR) 238 Operation HD66702 Display Data RAM (DDRAM) Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its extended capacity is 80 × 8 bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for display can be used as general data RAM. See Figure 1 for the relationships between DDRAM addresses and positions on the liquid crystal display. The DDRAM address (ADD) is set in the address counter (AC) as hexadecimal. • 1-line display (N = 0) (Figure 2) When there are fewer than 80 display characters, the display begins at the head position. For example, if using only the HD66702, 20 characters are displayed. See Figure 3. When the display shift operation is performed, the DDRAM address shifts. See Figure 3. High order bits Low order bits Example: DDRAM address 4E AC (hexadecimal) AC6 AC5 AC4 AC3 AC2 AC1 AC0 1 0 0 1 1 1 0 19 20 Figure 1 DDRAM Address Display position (digit) 1 2 3 DDRAM 00 01 address (hexadecimal) 4 02 5 03 04 79 .................. 80 4E 4F Figure 2 1-Line Display Display position 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 DDRAM address 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 For shift left 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 For shift right 4F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 Figure 3 1-Line by 20-Character Display Example 239 HD66702 • 2-line display (N = 1) (Figure 4) Case 1: When the number of display characters is less than 40 × 2 lines, the two lines are displayed from the head. Note that the first line end address and the second line start address are not consecutive. For example, when just the HD66702 is used, 20 characters × 2 lines are displayed. See Figure 5. When display shift operation is performed, the DDRAM address shifts. See Figure 5. Display position 1 2 3 00 01 DDRAM address (hexadecimal) 40 41 4 5 39 40 02 03 04 .................. 26 27 42 43 44 .................. 66 67 Figure 4 2-Line Display Display position 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DDRAM address 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 For shift left 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 27 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 For shift right 67 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 Figure 5 2-Line by 20-Character Display Example 240 HD66702 Case 2: For a 28-character × 2-line display, the HD66702 can be extended using one 40-output extension driver. See Figure 6. When display shift operation is performed, the DDRAM address shifts. See Figure 6. Display position DDRAM address 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B HD66702 display For shift left Extension driver display 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 27 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A For shift right 67 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A Figure 6 2-Line by 28-Character Display Example 241 HD66702 Character Generator ROM (CGROM) The character generator ROM generates 5 × 7 dot or 5 × 10 dot character patterns from 8-bit character codes (Table 5). It can generate 160 5 × 7 dot character patterns and 32 5 × 10 dot character patterns. User-defined character patterns are also available by mask-programmed ROM. Character Generator RAM (CGRAM) In the character generator RAM, the user can rewrite character patterns by program. For 5 × 7 dots, eight character patterns can be written, and for 5 × 10 dots, four character patterns can be written. Write the character codes at the addresses shown as the left column of Table 5 to show the character patterns stored in CGRAM. See Table 6 for the relationship between CGRAM addresses and data and display patterns. Areas that are not used for display can be used as general data RAM. Modifying Character Patterns • Character pattern development procedure The following operations correspond to the numbers listed in Figure 7: 1. Determine the correspondence between character codes and character patterns. 2. Create a listing indicating the correspondence between EPROM addresses and data. 3. Program the character patterns into the EPROM. 4. Send the EPROM to Hitachi. 5. Computer processing on the EPROM is performed at Hitachi to create a character pattern listing, which is sent to the user. 6. If there are no problems within the character pattern listing, a trial LSI is created at Hitachi and samples are sent to the user for evaluation. When it is confirmed by the user that the character patterns are correctly written, mass production of the LSI proceeds at Hitachi. 242 HD66702 Hitachi User Start Computer processing Create character pattern listing 5 Evaluate character patterns No Determine character patterns 1 Create EPROM address data listing 2 Write EPROM 3 EPROM → Hitachi 4 OK? Yes Art work M/T Masking Trial Sample Sample evaluation OK? 6 No Yes Mass production Note: For a description of the numbers used in this figure, refer to the preceding page. Figure 7 Character Pattern Development Procedure 243 HD66702 • Programming character patterns This section explains the correspondence between addresses and data used to program character patterns in EPROM. The HD66702 character generator ROM can generate 160 5 × 7 dot character patterns and 32 5 × 10 dot character patterns for a total of 192 different character patterns. 5 × 7 dot character pattern EPROM address data and character pattern data correspond with each other to form a 5 × 7 dot character pattern (Table 3). Table 3 Example of Correspondence between EPROM Address Data and Character Pattern (5 × 7 dots) EPROM Address Data A 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 1 0 1 0 0 Character code Notes: 1. 2. 3. 4. 5. 6. 244 1 0 LSB O 4 O3 O2 O1 O0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 0 1 0 1 1 1 1 1 1 0 1 0 0 1 0 1 0 0 1 0 1 1 0 0 1 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 0 0 Line position Fill line 8 (cursor position) with 0s EPROM addresses A10 to A3 correspond to a character code. EPROM addresses A2 to A0 specify a line position of the character pattern. EPROM data O4 to O0 correspond to character pattern data. A lit display position (black) corresponds to a 1. Line 8 (cursor position) of the character pattern must be blanked with 0s. EPROM data O5 to O7 are not used. HD66702 5 × 10 dot character pattern EPROM address data and character pattern data correspond with each other to form a 5 × 10 dot character pattern (Table 4). Handling unused character patterns 1. EPROM data outside the character pattern area: Ignored by the character generator ROM for display operation so 0 or 1 is arbitrary. 2. EPROM data in CGRAM area: Ignored by the character generator ROM for display operation so 0 or 1 is arbitrary. 3. EPROM data used when the user does not use any HD66702 character pattern: According to the user application, handled in one of the two ways listed as follows. a. When unused character patterns are not programmed: If an unused character code is written into DDRAM, all its dots are lit. By not programing a character pattern, all of its bits become lit. (This is due to the EPROM being filled with 1s after it is erased.) b. When unused character patterns are programmed as 0s: Nothing is displayed even if unused character codes are written into DDRAM. (This is equivalent to a space.) Table 4 Example of Correspondence between EPROM Address Data and Character Pattern (5 × 10 dots) EPROM Address Data A 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 LSB O 4 O3 O2 O1 O0 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 0 0 1 0 0 0 1 1 0 1 1 0 0 0 1 1 1 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 Character code Line position Fill line 11 (cursor position) with 0s Notes: 1. EPROM addresses A10 to A3 correspond to a character code. Set A8 and A9 of character pattern lines 9, 10, and 11 to 0s. 2. EPROM addresses A2 to A0 specify a line position of the character pattern. 3. EPROM data O4 to O0 correspond to character pattern data. 4. A lit display position (black) corresponds to a 1. 5. Blank out line 11 (cursor position) of the character pattern with 0s. 6. EPROM data O5 to O7 are not used. 245 HD66702 Table 5 Correspondence between Character Codes and Character Patterns (ROM code: A00) Lower 4 Bits Upper 4 Bits 0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 xxxx0000 CG RAM (1) xxxx0001 (2) xxxx0010 (3) xxxx0011 (4) xxxx0100 (5) xxxx0101 (6) xxxx0110 (7) xxxx0111 (8) xxxx1000 (1) xxxx1001 (2) xxxx1010 (3) xxxx1011 (4) xxxx1100 (5) xxxx1101 (6) xxxx1110 (7) xxxx1111 (8) Note: The user can specify any pattern for character-generator RAM. 246 HD66702 Table 5 Correspondence between Character Codes and Character Patterns (ROM code: A01) Lower 4 Bits Upper 4 Bits 0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 xxxx0000 CG RAM (1) xxxx0001 (2) xxxx0010 (3) xxxx0011 (4) xxxx0100 (5) xxxx0101 (6) xxxx0110 (7) xxxx0111 (8) xxxx1000 (1) xxxx1001 (2) xxxx1010 (3) xxxx1011 (4) xxxx1100 (5) xxxx1101 (6) xxxx1110 (7) xxxx1111 (8) 247 HD66702 Table 5 Correspondence between Character Codes and Character Patterns (ROM code: A02) Lower 4 Bits 248 Upper 4 Bits 0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 xxxx0000 CG RAM (1) xxxx0001 (2) xxxx0010 (3) xxxx0011 (4) xxxx0100 (5) xxxx0101 (6) xxxx0110 (7) xxxx0111 (8) xxxx1000 (1) xxxx1001 (2) xxxx1010 (3) xxxx1011 (4) xxxx1100 (5) xxxx1101 (6) xxxx1110 (7) xxxx1111 (8) HD66702 Table 6 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character Patterns (CGRAM Data) For 5 × 7 dot character patterns Character Codes (DDRAM data) CGRAM Address Character Patterns (CGRAM data) 7 6 5 4 3 2 1 0 5 4 3 2 1 0 7 6 5 4 3 2 1 0 High High Low 0 0 0 0 * 0 0 0 0 0 0 0 * 0 0 1 0 0 0 0 * 1 1 1 0 0 0 0 0 1 1 1 1 Low 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 1 1 0 1 0 1 High * * * * * * * * * * * * * * * Low 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 0 1 0 0 1 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 1 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0 Character pattern Cursor position * * * Notes: 1. Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types). 2. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and its display is formed by a logical OR with the cursor. Maintain the 8th line data, corresponding to the cursor display position, at 0 as the cursor display. If the 8th line data is 1, 1 bits will light up the 8th line regardless of the cursor presence. 3. Character pattern row positions correspond to CGRAM data bits 0 to 4 (bit 4 being at the left ). Since CGRAM data bits 5 to 7 are not used for display, they can be used for general data RAM. 4. As shown Tables 5 and 6, CGRAM character patterns are selected when character code bits 4 to 7 are all 0. However, since character code bit 3 has no effect, the R display example above can be selected by either character code 00H or 08H. 5. 1 for CGRAM data corresponds to display selection and 0 to non-selection. * Indicates no effect. 249 HD66702 Table 6 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character Patterns (CGRAM Data) (cont) For 5 × 10 dot character patterns Character Codes (DDRAM data) CGRAM Address Character Patterns (CGRAM data) 7 6 5 4 3 2 1 0 5 4 3 2 1 0 7 6 5 4 3 2 1 0 High High Low 0 0 0 0 * 0 0 * 0 0 0 0 * 1 1 * 0 0 1 1 Low 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 High * * * * * * * * * * * * * * * Low 0 0 1 1 1 1 1 1 1 1 0 * 0 0 0 1 0 0 1 0 0 0 0 * 0 0 1 0 0 0 1 0 0 0 0 * 0 0 1 0 0 0 1 0 0 0 0 * 0 0 0 1 1 1 0 0 0 0 0 * Character pattern Cursor position * * * * * * * * * * * * * * * * * * * * * * * * Notes: 1. Character code bits 1 and 2 correspond to CGRAM address bits 4 and 5 (2 bits: 4 types). 2. CGRAM address bits 0 to 3 designate the character pattern line position. The 11th line is the cursor position and its display is formed by a logical OR with the cursor. Maintain the 11th line data corresponding to the cursor display positon at 0 as the cursor display. If the 11th line data is 1, 1 bits will light up the 11th line regardless of the cursor presence. Since lines 12 to 16 are not used for display, they can be used for general data RAM. 3. Character pattern row positions are the same as 5 × 7 dot character pattern positions. 4. CGRAM character patterns are selected when character code bits 4 to 7 are all 0. However, since character code bits 0 and 3 have no effect, the P display example above can be selected by character codes 00H, 01H, 08H, and 09H. 5. 1 for CGRAM data corresponds to display selection and 0 to non-selection. * Indicates no effect. 250 HD66702 Timing Generation Circuit The timing generation circuit generates timing signals for the operation of internal circuits such as DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU access are generated separately to avoid interfering with each other. Therefore, when writing data to DDRAM, for example, there will be no undesirable interferences, such as flickering, in areas other than the display area. Liquid Crystal Display Driver Circuit The liquid crystal display driver circuit consists of 16 common signal drivers and 100 segment signal drivers. When the character font and number of lines are selected by a program, the required common signal drivers automatically output drive waveforms, while the other common signal drivers continue to output non-selection waveforms. Sending serial data always starts at the display data character pattern corresponding to the last address of the display data RAM (DDRAM). Since serial data is latched when the display data character pattern corresponding to the starting address enters the internal shift register, the HD66702 drives from the head display. Cursor/Blink Control Circuit The cursor/blink control circuit generates the cursor or character blinking. The cursor or the blinking will appear with the digit located at the display data RAM (DDRAM) address set in the address counter (AC). For example (Figure 8), when the address counter is 08H, the cursor position is displayed at DDRAM address 08H. AC6 AC5 AC4 AC3 AC2 AC1 AC0 AC 0 0 0 1 0 0 0 For a 1-line display Display position 1 2 3 4 5 6 7 8 9 10 11 DDRAM address (hexadecimal) 00 01 02 03 04 05 06 07 08 09 0A cursor position For a 2-line display Display position DDRAM address (hexadecimal) 1 2 3 4 5 6 7 8 9 10 11 00 01 02 03 04 05 06 07 08 09 0A 40 41 42 43 44 45 46 47 48 49 4A cursor position Note: The cursor or blinking appears when the address counter (AC) selects the character generator RAM (CGRAM). However, the cursor and blinking become meaningless. The cursor or blinking is displayed in the meaningless position when the AC is a CGRAM address. Figure 8 Cursor/Blink Display Example 251 HD66702 Interfacing to the MPU The HD66702 can send data in either two 4-bit operations or one 8-bit operation, thus allowing interfacing with 4- or 8-bit MPUs. • For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3 are disabled. The data transfer between the HD66702 and the MPU is completed after the 4-bit data has been transferred twice. As for the order of data transfer, the four high order bits (for 8-bit operation, DB4 to DB7) are transferred before the four low order bits (for 8-bit operation, DB0 to DB3). The busy flag must be checked (one instruction) after the 4-bit data has been transferred twice. Two more 4-bit operations then transfer the busy flag and address counter data. • For 8-bit interface data, all eight bus lines (DB0 to DB7) are used. RS R/W E DB7 IR7 IR3 BF AC3 DR7 DR3 DB6 IR6 IR2 AC6 AC2 DR6 DR2 DB5 IR5 IR1 AC5 AC1 DR5 DR1 DB4 IR4 IR0 AC4 AC0 DR4 DR0 Instruction register (IR) write Busy flag (BF) and address counter (AC) read Data register (DR) read Figure 9 4-Bit Transfer Example 252 HD66702 Reset Function Initializing by Internal Reset Circuit An internal reset circuit automatically initializes the HD66702 when the power is turned on. The following instructions are executed during the initialization. The busy flag (BF) is kept in the busy state until the initialization ends (BF = 1). The busy state lasts for 15 ms after VCC rises to 4.5V, or 40 ms after VCC rises to 2.7V. 1. Display clear 2. Function set: DL = 1; 8-bit interface data N = 0; 1-line display F = 0; 5 × 7 dot character font 3. Display on/off control: D = 0; Display off C = 0; Cursor off B = 0; Blinking off 4. Entry mode set: I/D = 1; Increment by 1 S = 0; No shift Note: If the electrical characteristics conditions listed under the Table Power Supply Conditions Using Internal Reset Circuit are not met, the internal reset circuit will not operate normally and will fail to initialize the HD66702. For such a case, initial-ization must be performed by the MPU as explained in the section, Initializing by Instruction. 253 HD66702 Instructions Outline Only the instruction register (IR) and the data register (DR) of the HD66702 can be controlled by the MPU. Before starting the internal operation of the HD66702, control information is temporarily stored into these registers to allow interfacing with various MPUs, which operate at different speeds, or various peripheral control devices. The internal operation of the HD66702 is determined by signals sent from the MPU. These signals, which include register selection (RS), read/write (R/ ), and the data bus (DB0 to DB7), make up the HD66702 instructions (Table 7). There are four categories of instructions that: : • • • • Designate HD66702 functions, such as display format, data length, etc. Set internal RAM addresses Perform data transfer with internal RAM Perform miscellaneous functions Normally, instructions that perform data transfer with internal RAM are used the most. However, autoincrementation by 1 (or auto-decrementation by 1) of internal HD66702 RAM addresses after each data write can lighten the program load of the MPU. Since the display shift instruction (Table 12) can perform concurrently with display data write, the user can minimize system development time with maximum programming efficiency. When an instruction is being executed for internal operation, no instruction other than the busy flag/address read instruction can be executed. Because the busy flag is set to 1 while an instruction is being executed, check it to make sure it is 0 before sending another instruction from the MPU. Note: Be sure the HD66702 is not in the busy state (BF = 0) before sending an instruction from the MPU to the HD66702. If an instruction is sent without checking the busy flag, the time between the first instruction and next instruction will take much longer than the instruction time itself. Refer to Table 7 for the list of each instruction execution time. 254 HD66702 Table 7 Instructions : Execution Time (max) (when fcp or Code Instruction RS R/ DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description fOSC is 320 kHz) Clear display 0 0 0 0 0 0 0 0 0 1 Clears entire display and sets DDRAM address 0 in address counter. 1.28 ms Return home 0 0 0 0 0 0 0 0 1 — Sets DDRAM address 0 in address counter. Also returns display from being shifted to original position. DDRAM contents remain unchanged. 1.28 ms Entry mode 0 set 0 0 0 0 0 0 1 I/D S Sets cursor move direction and specifies display shift. These operations are performed during data write and read. 31 µs Display on/off control 0 0 0 0 0 0 1 D C B Sets entire display (D) on/off, 31 µs cursor on/off (C), and blinking of cursor position character (B). Cursor or 0 display shift 0 0 0 0 1 S/C R/L — — Moves cursor and shifts display without changing DDRAM contents. Function set 0 0 0 0 1 DL N F — — Sets interface data length 31 µs (DL), number of display lines (L), and character font (F). Set CGRAM address 0 0 0 1 ACG ACG ACG ACG ACG ACG Sets CGRAM address. CGRAM data is sent and received after this setting. 31 µs Set DDRAM address 0 0 1 ADD ADD ADD ADD ADD ADD ADD Sets DDRAM address. DDRAM data is sent and received after this setting. 31 µs Read busy flag & address 0 1 BF AC 0 µs AC AC AC AC AC AC Reads busy flag (BF) indicating internal operation is being performed and reads address counter contents. 31 µs 255 HD66702 Table 7 Instructions (cont) : Execution Time (max) (when fcp or Code Instruction RS R/ DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description fOSC is 320 kHz) Write data to CG or DDRAM 1 0 Write data Writes data into DDRAM or CGRAM. 31 µs tADD = 4.7 µs* Read data 1 from CG or DDRAM 1 Read data Reads data from DDRAM or CGRAM. 31 µs tADD = 4.7 µs* DDRAM: Display data RAM CGRAM: Character generator RAM ACG: CGRAM address ADD: DDRAM address (corresponds to cursor address) AC: Address counter used for both DD and CGRAM addresses Execution time changes when frequency changes Example: When fcp or fOSC is 270 kHz, I/D I/D S S/C S/C R/L R/L DL N F BF BF Note: = 1: = 0: = 1: = 1: = 0: = 1: = 0: = 1: = 1: = 1: = 1: = 0: Increment Decrement Accompanies display shift Display shift Cursor move Shift to the right Shift to the left 8 bits, DL = 0: 4 bits 2 lines, N = 0: 1 line 5 × 10 dots, F = 0: 5 × 7 dots Internally operating Instructions acceptable 320 = 37 µs 270 — indicates no effect. * After execution of the CGRAM/DDRAM data write or read instruction, the RAM address counter is incremented or decremented by 1. The RAM address counter is updated after the busy flag turns off. In Figure 10, tADD is the time elapsed after the busy flag turns off until the address counter is updated. Busy signal (DB7 pin) Busy state Address counter (DB0 to DB6 pins) A A+1 t ADD Note: t ADD depends on the operation frequency t ADD = 1.5/(f cp or f OSC ) seconds Figure 10 Address Counter Update 256 31 µs × HD66702 Instruction Description Clear Display Clear display writes space code 20H (character pattern for character code 20H must be a blank pattern) into all DDRAM addresses. It then sets DDRAM address 0 into the address counter, and returns the display to its original status if it was shifted. In other words, the display disappears and the cursor or blinking goes to the left edge of the display (in the first line if 2 lines are displayed). It also sets I/D to 1 (increment mode) in entry mode. S of entry mode does not change. Return Home Return home sets DDRAM address 0 into the address counter, and returns the display to its original status if it was shifted. The DDRAM contents do not change. The cursor or blinking go to the left edge of the display (in the first line if 2 lines are displayed). Entry Mode Set I/D: Increments (I/D = 1) or decrements (I/D = 0) the DDRAM address by 1 when a character code is written into or read from DDRAM. The cursor or blinking moves to the right when incremented by 1 and to the left when decremented by 1. The same applies to writing and reading of CGRAM. S: Shifts the entire display either to the right (I/D = 0) or to the left (I/D = 1) when S is 1. The display does not shift if S is 0. If S is 1, it will seem as if the cursor does not move but the display does. The display does not shift when reading from DDRAM. Also, writing into or reading out from CGRAM does not shift the display. Display On/Off Control D: The display is on when D is 1 and off when D is 0. When off, the display data remains in DDRAM, but can be displayed instantly by setting D to 1. C: The cursor is displayed when C is 1 and not displayed when C is 0. Even if the cursor disappears, the function of I/D or other specifications will not change during display data write. The cursor is displayed using 5 dots in the 8th line for 5 × 7 dot character font selection and in the 11th line for the 5 × 10 dot character font selection (Figure 13). 257 HD66702 B: The character indicated by the cursor blinks when B is 1 (Figure 13). The blinking is displayed as switching between all blank dots and displayed characters at a speed of 320-ms intervals when f cp or fOSC is 320 kHz. The cursor and blinking can be set to display simultaneously. (The blinking frequency changes according to fOSC or the reciprocal of fcp. For example, when fcp is 270 kHz, 320 × 320/270 = 379.2 ms.) Cursor or Display Shift Cursor or display shift shifts the cursor position or display to the right or left without writing or reading display data (Table 8). This function is used to correct or search the display. In a 2-line display, the cursor moves to the second line when it passes the 40th digit of the first line. Note that the first and second line displays will shift at the same time. When the displayed data is shifted repeatedly each line moves only horizontally. The second line display does not shift into the first line position. The address counter (AC) contents will not change if the only action performed is a display shift. Function Set DL: Sets the interface data length. Data is sent or received in 8-bit lengths (DB7 to DB0) when DL is 1, and in 4-bit lengths (DB7 to DB4) when DL is 0. When 4-bit length is selected, data must be sent or received twice. N: Sets the number of display lines (Table 9). F: Sets the character font (Table 9). Note: Perform the function at the head of the program before executing any instructions (except for the read busy flag and address instruction). From this point, the function set instruction cannot be executed unless the interface data length is changed. Set CGRAM Address Set CGRAM address sets the CGRAM address binary AAAAAA into the address counter. Data is then written to or read from the MPU for CGRAM. 258 HD66702 RS Clear display Code 0 RS Return home Code 0 RS Entry mode set Code 0 RS Display on/off control Code 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 * Note: * Don’t care. R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 I/D S R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 D C B Figure 11 RS Cursor or display shift Code 0 RS Function set Code 0 RS Set CGRAM address Code 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 S/C R/L * * Note: * Don’t care. R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 DL N F * * Note: * Don’t care. R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 A A Highest order bit A A A A Lowest order bit Figure 12 259 HD66702 Set DDRAM Address Set DDRAM address sets the DDRAM address binary AAAAAAA into the address counter. Data is then written to or read from the MPU for DDRAM. However, when N is 0 (1-line display), AAAAAAA can be 00H to 4FH. When N is 1 (2-line display), AAAAAAA can be 00H to 27H for the first line, and 40H to 67H for the second line. Read Busy Flag and Address Read busy flag and address reads the busy flag (BF) indicating that the system is now internally operating on a previously received instruction. If BF is 1, the internal operation is in progress. The next instruction will not be accepted until BF is reset to 0. Check the BF status before the next write operation. At the same time, the value of the address counter in binary AAAAAAA is read out. This address counter is used by both CG and DDRAM addresses, and its value is determined by the previous instruction. The address contents are the same as for instructions set CGRAM address and set DDRAM address. Table 8 Shift Function S/C R/L 0 0 Shifts the cursor position to the left. (AC is decremented by one.) 0 1 Shifts the cursor position to the right. (AC is incremented by one.) 1 0 Shifts the entire display to the left. The cursor follows the display shift. 1 1 Shifts the entire display to the right. The cursor follows the display shift. Table 9 Function Set N F No. of Display Lines 0 0 1 5 × 7 dots 1/8 0 1 1 5 × 10 dots 1/11 1 * 2 5 × 7 dots 1/16 Note: 260 * Character Font Duty Factor Remarks Indicates don’t care. Cannot display two lines for 5 × 10 dot character font. HD66702 Cursor 5 × 7 dot character font 5 × 10 dot character font Alternating display Cursor display example Blink display example Figure 13 Cursor and Blinking RS Set DDRAM address Code 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 A A A A A A Highest order bit RS Read busy flag and address Code 0 A Lowest order bit R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 BF A Highest order bit A A A A A A Lowest order bit Figure 14 261 HD66702 Write Data to CG or DDRAM Write data to CG or DDRAM writes 8-bit binary data DDDDDDDD to CG or DDRAM. To write into CG or DDRAM is determined by the previous specification of the CGRAM or DDRAM address setting. After a write, the address is automatically incremented or decremented by 1 according to the entry mode. The entry mode also determines the display shift. Read Data from CG or DDRAM Read data from CG or DDRAM reads 8-bit binary data DDDDDDDD from CG or DDRAM. The previous designation determines whether CG or DDRAM is to be read. Before entering this read instruction, either CGRAM or DDRAM address set instruction must be executed. If not executed, the first read data will be invalid. When serially executing read instructions, the next address data is normally read from the second read. The address set instructions need not be executed just before this read instruction when shifting the cursor by the cursor shift instruction (when reading out DDRAM). The operation of the cursor shift instruction is the same as the set DDRAM address instruction. After a read, the entry mode automatically increases or decreases the address by 1. However, display shift is not executed regardless of the entry mode. Note: The address counter (AC) is automatically incremented or decremented by 1 after the write instructions to CGRAM or DDRAM are executed. The RAM data selected by the AC cannot be read out at this time even if read instructions are executed. Therefore, to correctly read data, execute either the address set instruction or cursor shift instruction (only with DDRAM), then just before reading the desired data, execute the read instruction from the second time the read instruction is sent. RS Write data to CG or DDRAM Code 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 D D D D D Higher order bits RS Read data from CG or DDRAM Code 1 D D Lower order bits R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 D D Higher order bits Figure 15 262 D D D D D D Lower order bits D HD66702 Interfacing the HD66702 Interface to MPUs • Interfacing to an 8-bit MPU See Figure 17 for an example of using a I/O port (for a single-chip microcomputer) as an interface device. In this example, A0 to A7 are connected to the data bus DB0 to DB7, and C0 to C2 are connected to E, R/ , and RS, respectively. : RS R/W E Internal operation Functioning Data Busy Busy Instruction write Busy flag check Busy flag check DB7 Not busy Data Busy flag check Instruction write Figure 16 Example of Busy Flag Check Timing Sequence H8/325 HD66702 C0 C1 C2 RS R/W E DB0 to DB7 A0 to A7 8 COM1 to COM16 16 SEG1 to SEG100 100 LCD Figure 17 8-bit MPU Interface 263 HD66702 • Interfacing to a 4-bit MPU The HD66702 can be connected to the I/O port of a 4-bit MPU. If the I/O port has enough bits, 8-bit data can be transferred. Otherwise, one data transfer must be made in two operations for 4-bit data. In this case, the timing sequence becomes somewhat complex. (See Figure 18.) See Figure 19 for an interface example to the HMCS43C. Note that two cycles are needed for the busy flag check as well as for the data transfer. The 4-bit operation is selected by the program. RS R/W E Internal operation DB7 Functioning IR7 IR3 Instruction write Busy AC3 Not busy AC3 Busy flag check Busy flag check D7 D3 Instruction write Note: * IR7, IR3 are the 7th and 3rd bits of the instruction. AC3 is the 3rd bit of the address counter. Figure 18 Example of 4-Bit Data Transfer Timing Sequence HMCS43C (Hitachi 4-bit single-chip microcontroller) HD66702 D15 RS D14 R/W D13 E 4 R10 to R13 COM1 to COM16 16 LCD SEG1 to 100 DB4 to DB7 SEG100 Figure 19 Example of Interface to HMCS43C 264 HD66702 Interface to Liquid Crystal Display Character Font and Number of Lines: The HD66702 can perform two types of displays, 5 × 7 dot and 5 × 10 dot character fonts, each with a cursor. Up to two lines are displayed for 5 × 7 dots and one line for 5 × 10 dots. Therefore, a total of three types of common signals are available (Table 10). The number of lines and font types can be selected by the program. (See Table 7, Instructions.) Connection to HD66702 and Liquid Crystal Display: See Figure 20 for the connection examples. Table 10 Common Signals Number of Lines Character Font Number of Common Signals Duty Factor 1 5 × 7 dots + cursor 8 1/8 1 5 × 10 dots + cursor 11 1/11 2 5 × 7 dots + cursor 16 1/16 HD66702 COM1 COM8 SEG1 SEG100 Example of a 5 × 7 dot, 20-character × 1-line display (1/4 bias, 1/8 duty cycle) HD66702 COM1 COM11 SEG1 SEG100 Example of a 5 × 10 dot, 20-character × 1-line display (1/4 bias, 1/8 duty cycle) Figure 20 Liquid Crystal Display and HD66702 Connections 265 HD66702 Since five segment signal lines can display one digit, one HD66702 can display up to 20 digits for a 1line display and 40 digits for a 2-line display. The examples in Figure 20 have unused common signal pins, which always output non-selection waveforms. When the liquid crystal display panel has unused extra scanning lines, connect the extra scanning lines to these common signal pins to avoid any undesirable effects due to crosstalk during the floating state (Figure 21). HD66702 COM1 COM8 COM9 COM16 SEG1 SEG100 Example of a 5 × 7 dot, 20-character × 2-line display (1/5 bias, 1/16 duty cycle) Figure 20 Liquid Crystal Display and HD66702 Connections (cont) HD66702 COM1 COM8 COM9 SEG1 SEG100 5 × 7 dot, 20-character × 1-line display (1/4 bias, 1/8 duty cycle) Figure 21 Using COM9 to Avoid Crosstalk on Unneeded Scanning Line 266 HD66702 Connection of Changed Matrix Layout: In the preceding examples, the number of lines correspond to the scanning lines. However, the following display examples (Figure 22) are made possible by altering the matrix layout of the liquid crystal display panel. In either case, the only change is the layout. The display characteristics and the number of liquid crystal display characters depend on the number of common signals or on duty factor. Note that the display data RAM (DDRAM) addresses for 10 characters × 2 lines and for 40 characters × 1 line are the same as in Figure 20. HD66702 COM1 COM8 SEG1 SEG100 COM9 COM16 HD66702 5 × 7 dot, 40-character × 1-line display (1/5 bias, 1/16 duty cycle) SEG1 SEG50 COM1 COM8 SEG51 SEG100 5 × 7 dot, 10-character × 2-line display (1/4 bias, 1/8 duty cycle) Figure 22 Changed Matrix Layout Displays 267 HD66702 Power Supply for Liquid Crystal Display Drive Various voltage levels must be applied to pins V1 to V5 of the HD66702 to obtain the liquid crystal display drive waveforms. The voltages must be changed according to the duty factor (Table 11). VLCD is the peak value for the liquid crystal display drive waveforms, and resistance dividing provides voltages V1 to V5 (Figure 23). Table 11 Duty Factor and Power Supply for Liquid Crystal Display Drive Duty Factor 1/8, 1/11 1/16 Bias Power Supply 1/4 1/5 V1 VCC–1/4 VLCD VCC–1/5 VLCD V2 VCC–1/2 VLCD VCC–2/5 VLCD V3 VCC–1/2 VLCD VCC–3/5 VLCD V4 VCC–3/4 VLCD VCC–4/5 VLCD V5 VCC–VLCD VCC–VLCD VCC HD66702 VCC HD66702 VCC VCC R R R V2 VLCD V3 R V4 R V5 R V1 V1 V2 R V3 R V4 R V5 VR VR 1/4 bias (1/8, 1/11 duty cycle) VEE 1/5 bias (1/16, duty cycle) VEE Note: R changes depending on the size of liquid crystal panel. Normally, R is, 4.7 kΩ to 20kΩ. Figure 23 Drive Voltage Supply Example 268 VLCD HD66702 Relationship between Oscillation Frequency and Liquid Crystal Display Frame Frequency The liquid crystal display frame frequencies of Figure 24 apply only when the oscillation frequency is 320 kHz (one clock pulse of 3.125 µs). 1/8 duty cycle COM1 400 clocks 1 2 3 4 8 1 2 11 1 2 1 2 VCC V1 V2 (V3) V4 V5 1 frame 1 frame = 3.125 µs × 400 × 8 = 10000 µs = 10 ms 1 Frame frequency = = 100 Hz 10 ms 1/11 duty cycle COM1 400 clocks 1 2 3 4 VCC V1 V2 (V3) V4 V5 1 frame 1 frame = 3.125 µs × 400 × 11 = 13750 µs = 13.75 ms 1 Frame frequency = = 72.7 Hz 13.75 ms 1/16 duty cycle COM1 200 clocks 1 2 3 4 16 VCC V1 V2 V3 V4 V5 1 frame 1 frame = 3.125 µs × 200 × 16 = 10000 µs = 10 ms 1 Frame frequency = = 100 Hz 10 ms Figure 24 Frame Frequency 269 HD66702 Instruction and Display Correspondence • 8-bit operation, 20-digit × 1-line display with internal reset Refer to Table 12 for an example of an 8-bit × 1-line display in 8-bit operation. The HD66702 functions must be set by the function set instruction prior to the display. Since the display data RAM can store data for 80 characters, as explained before, the RAM can be used for displays such as for advertising when combined with the display shift operation. Since the display shift operation changes only the display position with DDRAM contents unchanged, the first display data entered into DDRAM can be output when the return home operation is performed. • 4-bit operation, 20-digit × 1-line display with internal reset The program must set all functions prior to the 4-bit operation (Table 13). When the power is turned on, 8-bit operation is automatically selected and the first write is performed as an 8-bit operation. Since DB0 to DB3 are not connected, a rewrite is then required. However, since one operation is completed in two accesses for 4-bit operation, a rewrite is needed to set the functions (see Table 13). Thus, DB4 to DB7 of the function set instruction is written twice. • 8-bit operation, 20-digit × 2-line display For a 2-line display, the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. Thus, if there are only 20 characters in the first line, the DDRAM address must be again set after the 20th character is completed. (See Table 14.) Note that the display shift operation is performed for the first and second lines. In the example of Table 14, the display shift is performed when the cursor is on the second line. However, if the shift operation is performed when the cursor is on the first line, both the first and second lines move together. If the shift is repeated, the display of the second line will not move to the first line. The same display will only shift within its own line for the number of times the shift is repeated. Note: When using the internal reset, the electrical characteristics in the Power Supply Conditions Using Internal Reset Circuit table must be satisfied. If not, the HD66702 must be initialized by instructions. (Because the internal reset does not function correctly when VCC is 3V, it must always be initialized by software.) See the section, Initializing by Instruction. 270 HD66702 8-Bit Operation, 20-Digit × 1-Line Display Example with Internal Reset Table 12 Step No. RS Instruction : R/ DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display Operation 1 Power supply on (the HD66702 is initialized by the internal reset circuit) Initialized. No display. 2 Function set 0 0 0 Sets to 8-bit operation and selects 1-line display and character font. (Number of display lines and character fonts cannot be changed after step #2.) 3 4 5 6 0 1 1 0 0 * * Display on/off control 0 0 0 0 0 0 1 1 1 0 Entry mode set 0 0 0 0 0 0 1 1 0 Write data to CGRAM/DDRAM 1 0 0 1 0 0 1 0 0 0 Write data to CGRAM/DDRAM 1 0 0 1 0 0 1 0 0 1 0 7 8 9 10 Writes H. DDRAM already been selected by initialization when the power was turned on. The cursor is incremented by one and shifted to the right. H_ Writes I. HI_ · · · · · Write data to CGRAM/DDRAM 1 0 0 1 0 0 1 0 0 1 Entry mode set 0 0 0 0 0 1 1 1 Write data to CGRAM/DDRAM 1 0 0 0 1 0 0 0 0 0 0 Sets mode to increment the address by one and to shift the cursor to the right at the time of write to the DD/CGRAM. Display is not shifted. _ · · · · · 0 Turns on display and cursor. Entire display is in space mode becauce of initialization. _ HITACHI_ HITACHI_ ITACHI _ Writes I. Sets mode to shift display at the time of write. Writes a space. 271 HD66702 8-Bit Operation, 20-Digit × 1-Line Display Example with Internal Reset (cont) Table 12 Step No. RS 11 Instruction : R/ DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display Write data to CGRAM/DDRAM 1 0 0 1 0 0 12 13 14 15 16 17 18 19 272 1 0 1 · · · · · Write data to CGRAM/DDRAM 1 0 0 1 0 0 1 1 1 1 Cursor or display shift 0 0 0 0 0 1 0 0 * * Cursor or display shift 0 0 0 0 0 1 0 0 * * Write data to CGRAM/DDRAM 1 0 0 1 0 0 0 0 1 1 Cursor or display shift 0 0 0 0 0 1 1 1 * * Cursor or display shift 0 0 0 0 0 1 0 1 * * Write data to CGRAM/DDRAM 1 0 0 1 0 0 1 1 0 1 MICROKO_ 0 0 Writes O. MICROKO _ Shifts only the cursor position to the left. MICROKO _ Shifts only the cursor position to the left. ICROCO _ Writes C over K. The display moves to the left. MICROCO _ Shifts the display and cursor position to the right. MICROCO_ Shifts the display and cursor position to the right. ICROCOM_ · · · · · Return home 0 0 0 Writes M. TACHI M_ · · · · · 20 21 1 Operation Writes M. · · · · · 0 0 0 1 0 HITACHI _ Returns both display and cursor to the original position(address 0). HD66702 4-Bit Operation, 20-Digit × 1-Line Display Example with Internal Reset Table 13 Step No. RS Instruction : R/ DB7 DB6 DB5 DB4 Display Operation 1 Power supply on (the HD66702 is initialized by the internal reset circuit) Initialized. No display. 2 Function set 0 0 0 0 1 0 Sets to 4-bit operation. In this case, operation is handled as 8 bits by initialization, and only this instruction completes with one write. Function set 0 0 0 0 0 0 0 0 1 * 0 * Display on/off control 0 0 0 0 0 0 1 1 0 1 0 0 Entry mode set 0 0 0 0 0 0 0 1 0 0 3 4 5 6 0 1 Write data to CGRAM/DDRAM 1 0 0 1 0 0 1 0 1 0 0 0 Sets 4-bit operation and selects1-line display and 5 × 7 dot character font. 4-bit operation starts from this step and resetting is necessary. (Number of display lines and character fonts cannot be changed after step #3.) _ _ H_ Turns on display and cursor. Entire display is in space mode because of initialization. Sets mode to increment the address by one and to shift the cursor to the right at the time of write to the DD/CGRAM. Display is not shifted. Writes H. The cursor is incremented by one and shifts to the right. Note: The control is the same as for 8-bit operation beyond step #6. 273 HD66702 8-Bit Operation, 20-Digit × 2-Line Display Example with Internal Reset Table 14 Step No. RS Instruction : R/ DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display Operation 1 Power supply on (the HD66702 is initialized by the internal reset circuit) Initialized. No display. 2 Function set 0 0 0 Sets to 8-bit operation and selects 2-line display and 5 × 7 dot character font. 3 4 5 0 1 1 1 0 * * Display on/off control 0 0 0 0 0 0 1 1 1 0 Entry mode set 0 0 0 0 0 0 1 1 0 Write data to CGRAM/DDRAM 1 0 0 1 0 0 1 0 0 0 8 274 Sets mode to increment the address by one and to shift the cursor to the right at the time of write to the DD/CGRAM. Display is not shifted. _ 0 6 7 Turns on display and cursor. All display is in space mode because of initialization. _ · · · · · · · · · · Write data to CGRAM/DDRAM 1 0 0 1 0 0 1 0 0 1 Set DDRAM address 0 0 1 1 0 0 0 0 0 Writes H. DDRAM has already been selected by initialization when the power was turned on. The cursor is incremented by one and shifted to the right. H_ 0 HITACHI_ HITACHI _ Writes I. Sets RAM address so that the cursor is positioned at the head of the second line. HD66702 8-Bit Operation, 20-Digit × 2-Line Display Example with Internal Reset (cont) Table 14 Step No. RS 9 Instruction : R/ DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display Write data to CGRAM/DDRAM 1 0 0 1 0 0 10 11 12 13 1 0 1 · · · · · Writes M. HITACHI M_ · · · · · Write data to CGRAM/DDRAM 1 0 0 1 0 0 1 1 1 1 HITACHI MICROCO_ Entry mode set 0 0 0 0 0 1 1 1 HITACHI MICROCO_ Write data to CGRAM/DDRAM 1 0 0 1 0 0 1 1 0 1 ITACHI ICROCOM_ 0 0 14 15 1 Operation · · · · · Return home 0 0 0 0 0 Writes O. Sets mode to shift display at the time of write. Writes M. Display is shifted to the right. The first and second lines both shift at the same time. · · · · · 0 0 0 1 0 HITACHI _ MICROCOM Returns both display and cursor to the original position (address 0). 275 HD66702 Initializing by Instruction If the power supply conditions for correctly operating the internal reset circuit are not met, initialization by instructions becomes necessary. Refer to Figures 25 and 26 for the procedures on 8-bit and 4-bit initializations, respectively. Power on Wait for more than 40 ms after VCC rises to 2.7V Wait for more than 15 ms after VCC rises to 4.5V RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 * * * * BF cannot be checked before this instruction. Function set (Interface is 8 bits long.) Wait for more than 4.1 ms RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 * * * * BF cannot be checked before this instruction. Function set (Interface is 8 bits long.) Wait for more than 100 µs RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 * * * * BF cannot be checked before this instruction. Function set (Interface is 8 bits long.) BF can be checked after the following instructions. When BF is not checked, the waiting time between instructions is longer than the execution instuction time. (See Table 7.) RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 N F * * 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 I/D S Function set (Interface is 8 bits long. Specify the number of display lines and character font.) The number of display lines and character font cannot be changed after this point. Display off Display clear Entry mode set Initialization ends Figure 25 8-Bit Interface 276 HD66702 Power on Wait for more than 15 ms after VCC rises to 4.5V RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1 Wait for more than 40 ms after VCC rises to 2.7V BF cannot be checked before this instruction. Function set (Interface is 8 bits long.) Wait for more than 4.1 ms RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1 BF cannot be checked before this instruction. Function set (Interface is 8 bits long.) Wait for more than 100 µs RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1 BF cannot be checked before this instruction. RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 0 BF can be checked after the following instructions. When BF is not checked, the waiting time between instructions is longer than the execution instuction time. (See Table 7.) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 1 0 0 0 0 0 F 0 0 0 0 0 1 1 0 * * 0 0 0 0 0 0 0 1 0 0 I/D S Function set (Interface is 8 bits long.) Function set (Set interface to be 4 bits long.) Interface is 8 bits in length. Function set (Interface is 4 bits long. Specify the number of display lines and character font.) The number of display lines and character font cannot be changed after this point. Display off Display clear Initialization ends Entry mode set Figure 26 4-Bit Interface 277 HD66702 [Low voltage version] Absolute Maximum Ratings* Item Symbol Unit Value Notes Power supply voltage (1) VCC V –0.3 to +7.0 1 Power supply voltage (2) VCC–V5 V –0.3 to +8.5 2 Input voltage Vt V –0.3 to VCC +0.3 1 Operating temperature Topr °C –20 to +75 Storage temperature Tstg °C –55 to +125 Note: 278 1. The operating temperature is 75°C. 2. If the LSI is used above these absolute maximum ratings, it may become permanently damaged. Using the LSI within the following electrical characteristic limits is strongly recommended for normal operation. If these electrical characteristic conditions are also exceeded, the LSI will malfunction and cause poor reliability. 3. The power supply voltage is GND = 0V. 4. Keep VCC ≥ V5 (Low), and VCC ≥ GND (Low) 4 HD66702 DC Characteristics (VCC = 2.7 to 5.5V, Ta = –20 to +75°C*3) Item Symbol Min Typ Max Unit Test Condition Notes* Input high voltage (1) (except OSC1) VIH1 0.7VCC — VCC V 6, 17 Input low voltage (1) (except OSC1) VIL1 –0.3 — 0.55 V 6, 17 Input high voltage (2) (OSC1) VIH2 0.7VCC — VCC V 15 Input low voltage (2) (OSC1) VIL2 — — 0.2VCC V 15 Output high voltage (1) VOH1 (D0–D7) 0.75VCC — — V –IOH = 0.1 mA 7 Output low voltage (1) (D0–D7) — — 0.2VCC V IOL = 0.1 mA 7 Output high voltage (2) VOH2 (except D0–D7) 0.8VCC — — V –IOH = 0.04 mA 8 Output low voltage (2) (except D0–D7) VOL2 — — 0.2VCC V IOL = 0.04 mA 8 Driver on resistance (COM) RCOM — 2 20 kΩ ±Id = 0.05 mA (COM) 13 Driver on resistance (SEG) RSEG — 2 30 kΩ ±Id = 0.05 mA (SEG) 13 Input leakage current ILI –1 — 1 µA VIN = 0 to VCC 9 Pull-up MOS current (RS, R/:, D0–D7) –Ip 10 50 120 µA VCC = 3V Power supply current ICC — 0.15 0.30 mA Rf oscillation, external clock VCC = 3V, fOSC = 320 kHz 10, 14 LCD voltage VLCD1 3.0 — 8.3 V VCC–V5, 1/5 bias 16 VLCD2 3.0 — 8.3 V VCC–V5, 1/4 bias 16 Note: * VOL1 Refer to the Electrical Characteristics Notes section following these tables. 279 HD66702 AC Characteristics (VCC = 2.7 to 5.5V, Ta = –20 to +75°C*3) Clock Characteristics Item Symbol Min Typ Max Unit External External clock frequency fcp 125 270 410 kHz clock operation External clock duty Duty 45 50 55 % External clock rise time trcp — — 0.2 µs External clock fall time tfcp — — 0.2 µs Clock oscillation frequency fOSC 240 320 390 kHz Rf oscillation Note: * Test Condition Notes* 11 Rf = 56 kΩ VCC = 3V 12 Refer to the Electrical Characteristics Notes section following these tables. Bus Timing Characteristics Write Operation Item Symbol Min Typ Max Unit Test Condition Enable cycle time tcycE 1000 Enable pulse width (high level) PWEH 450 — — ns Figure 27 — — Enable rise/fall time tEr, tEf — — 25 Address set-up time (RS, R/: to E) tAS 40 — — Address hold time tAH 20 — — Data set-up time tDSW 195 — — Data hold time tH 10 — — Item Symbol Min Typ Max Unit Test Condition Enable cycle time tcycE 1000 — — ns Figure 28 Enable pulse width (high level) PWEH 450 — — Enable rise/fall time tEr, tEf — — 25 Address set-up time (RS, R/: to E) tAS 40 — — Address hold time tAH 20 — — Data delay time tDDR — — 350 Data hold time tDHR 10 — — Read Operation 280 HD66702 Interface Timing Characteristics with External Driver Item Symbol Min Typ Max Unit Test Condition High level tCWH 800 — — ns Figure 29 Low level tCWL 800 — — Clock set-up time tCSU 500 — — Data set-up time tSU 300 — — Data hold time tDH 300 — — M delay time tDM –1000 — 1000 Clock rise/fall time tct — — 200 Clock pulse width Power Supply Conditions Using Internal Reset Circuit Item Symbol Min Typ Max Unit Test Condition Power supply rise time trCC 0.1 — 10 ms Figure 30 Power supply off time tOFF 1 — — [Standard Voltage Version] Absolute Maximum Ratings* Item Symbol Unit Value Notes Power supply voltage (1) VCC V –0.3 to +7.0 1 Power supply voltage (2) VCC–V5 V –0.3 to +8.5 2 Input voltage Vt V –0.3 to VCC +0.3 1 Operating temperature Topr °C –20 to +75 Storage temperature Tstg °C –55 to +125 Note: * 4 If the LSI is used above these absolute maximum ratings, it may become permanently damaged. Using the LSI within the following electrical characteristic limits is strongly recommended for normal operation. If these electrical characteristic conditions are also exceeded, the LSI will malfunction and cause poor reliability. Refer to the Electrical Characteristics Notes section following these tables. 281 HD66702 DC Characteristics (VCC = 5V ±10%, Ta = –20 to +75°C*3) Item Symbol Min Typ Max Unit Input high voltage (1) (except OSC1) VIH1 2.2 — VCC V 6, 17 Input low voltage (1) (except OSC1) VIL1 –0.3 — 0.6 V 6, 17 Input high voltage (2) (OSC1) VIH2 VCC–1.0 — VCC V 15 Input low voltage (2) (OSC1) VIL2 — — 1.0 V 15 Output high voltage (1) VOH1 (D0–D7) 2.4 — — V –IOH = 0.205 mA 7 Output low voltage (1) (D0–D7) — — 0.4 V IOL = 1.6 mA 7 V –IOH = 0.04 mA 8 VOL1 Test Condition Notes* Output high voltage (2) VOH2 (except D0–D7) 0.9 VCC — — Output low voltage (2) (except D0–D7) VOL2 — — 0.1 VCC V IOL = 0.04 mA 8 Driver on resistance (COM) RCOM — 2 20 kΩ ±Id = 0.05 mA (COM) 13 Driver on resistance (SEG) RSEG — 2 30 kΩ ±Id = 0.05 mA (SEG) 13 Input leakage current ILI –1 — 1 µA VIN = 0 to VCC 9 Pull-up MOS current (RS, R/:, D0–D7) –Ip 50 125 250 µA VCC = 5V Power supply current ICC — 0.35 0.60 mA Rf oscillation, external clock VCC = 5V, fOSC = 320 kHz 10, 14 LCD voltage VLCD1 3.0 — 8.3 V VCC–V5, 1/5 bias 16 VLCD2 3.0 — 8.3 V VCC–V5, 1/4 bias 16 Note: 282 * Refer to the Electrical Characteristics Notes section following these tables. HD66702 AC Characteristics (VCC = 5V ±10%, Ta = –20 to +75°C*3) Clock Characteristics Item Symbol Min Typ Max Unit Test Condition Notes* External External clock frequency fcp 125 270 410 kHz 11 clock External clock duty Duty 45 50 55 % 11 operation External clock rise time trcp — — 0.2 µs 11 External clock fall time tfcp — — 0.2 µs 11 Clock oscillation frequency fOSC 220 320 420 kHz Rf oscillation Note: * Rf = 68 kΩ VCC = 5V 12 Refer to the Electrical Characteristics Notes section following these tables. Bus Timing Characteristics Write Operation Item Symbol Min Typ Max Unit Test Condition Enable cycle time tcycE 1000 — — ns Figure 27 Enable pulse width (high level) PWEH 450 — — Enable rise/fall time tEr, tEf — — 25 Address set-up time (RS, R/:to E) tAS 40 — — Address hold time tAH 10 — — Data set-up time tDSW 195 — — Data hold time tH 10 — — Symbol Min Typ Max Unit Test Condition Enable cycle time tcycE 1000 — — ns Figure 28 Enable pulse width (high level) PWEH 450 — — Enable rise/fall time tEr, tEf — — 25 Address set-up time (RS, R/: to E) tAS 40 — — Address hold time tAH 10 — — Data delay time tDDR — — 320 Data hold time tDHR 20 — — Read Operation Item 283 HD66702 Interface Timing Characteristics with External Driver Item Symbol Min Typ Max Unit Test Condition High level tCWH 800 — — ns Figure 29 Low level tCWL 800 — — Clock set-up time tCSU 500 — — Data set-up time tSU 300 — — Data hold time tDH 300 — — M delay time tDM –1000 — 1000 Clock rise/fall time tct — — 100 Clock pulse width Power Supply Conditions Using Internal Reset Circuit Item Symbol Min Typ Max Unit Test Condition Power supply rise time trCC 0.1 — 10 ms Figure 30 Power supply off time tOFF 1 — — 284 HD66702 Electrical Characteristics Notes 1. 2. 3. 4. 5. All voltage values are referred to GND = 0V. VCC ≥ V5 must be maintained. For die products, specified up to 75°C. For die products, specified by the die shipment specification. The following four circuits are I/O pin configurations except for liquid crystal display output. Input pin Pin: E (MOS without pull-up) Output pin Pins: CL1 , CL2 , M, D Pins: RS, R/W (MOS with pull-up) VCC VCC VCC PMOS PMOS VCC PMOS PMOS NMOS NMOS (pull up MOS) NMOS I/O Pin Pins: DB0 –DB7 (MOS with pull-up) VCC (pull-up MOS) VCC (input circuit) PMOS PMOS Input enable NMOS VCC NMOS PMOS Output enable Data NMOS (output circuit) (tristate) 285 HD66702 6. Applies to input pins and I/O pins, excluding the OSC1 pin. 7. Applies to I/O pins. 8. Applies to output pins. 9. Current flowing through pull–up MOSs, excluding output drive MOSs. 10. Input/output current is excluded. When input is at an intermediate level with CMOS, the excessive current flows through the input circuit to the power supply. To avoid this from happening, the input level must be fixed high or low. 11. Applies only to external clock operation. Th Oscillator Tl OSC1 Open 0.7 VCC 0.5 VCC 0.3 VCC OSC2 trcp trcp Th × 100% Duty = Th + Tl 12. Applies only to the internal oscillator operation using oscillation resistor Rf. R f : 56 k Ω ± 2% (when VCC = 3V) R f : 68 k Ω ± 2% (when VCC = 5V) Since the oscillation frequency varies depending on the OSC1 and OSC2 pin capacitance, the wiring length to these pins should be minimized. OSC1 Rf OSC2 VCC = 3V 500 400 400 320 300 max. 200 typ. fOSC (kHz) fOSC (kHz) VCC = 5V 500 320 300 max. 200 typ. min. 100 50 (68) 100 Rf (k Ω) 286 150 100 min. 50 (56) 100 Rf (k Ω) 150 HD66702 13. RCOM is the resistance between the power supply pins (VCC, V1, V4, V5) and each common signal pin (COM1 to COM16). RSEG is the resistance between the power supply pins (VCC, V2, V3, V5) and each segment signal pin (SEG1 to SEG100). 14. The following graphs show the relationship between operation frequency and current consumption. VCC = 3V 1.8 1.6 1.6 1.4 1.4 1.2 1.0 max. 0.8 typ. 0.6 I CC (mA) I CC (mA) VCC = 5V 1.8 1.2 1.0 0.8 0.6 0.4 0.4 0.2 0.2 0.0 0.0 0 100 200 300 f OSC or f cp (kHz) 400 500 max. typ. 0 100 200 300 400 500 f OSC or f cp (kHz) 15. Applies to the OSC1 pin. 16. Each COM and SEG output voltage is within ±0.15V of the LCD voltage (VCC, V1, V2, V3, V4, V5) when there is no load. 17. The TEST pin should be fixed to GND and the EXT pin should be fixed to VCC or GND. 287 HD66702 Load Circuits Data Bus DB0 to DB7 VCC = 5V For VCC = 5V For VCC = 3V 2.4 k Ω Test point Test point 90 pF 11 k Ω 1S2074 diodes H External Driver Control Signal: CL1, CL2, D, M Test point 30 pF 288 50 pF HD66702 Timing Characteristics RS VIH1 VIL1 VIH1 VIL1 t AS R/W t AH VIL1 VIL1 PWEH t AH t Ef VIH1 VIL1 E VIH1 VIL1 t Er VIH1 VIL1 DB0 to DB7 VIL1 tH t DSW VIH1 VIL1 Valid data t cycE Figure 27 Write Operation RS VIH1 VIL1 VIH1 VIL1 t AS R/W t AH VIH1 VIH1 PWEH t AH t Ef E VIH1 VIL1 VIH1 VIL1 VIL1 t Er t DHR t DDR DB0 to DB7 VOH1 VOL1 Valid data VOH1 VOL1 t cycE Figure 28 Read Operation 289 HD66702 t ct VOH2 CL1 VOH2 VOL2 t CWH t CWH t CSU CL2 VOH2 VOL2 t CWL t ct t CSU VOH2 VOL2 D t DH t SU M VOL2 t DM Figure 29 Interface Timing with External Driver VCC 2.7V/4.5V *2 0.2V 0.2V t rcc 0.1 ms ≤ t rcc ≤ 10 ms 0.2V t OFF *1 t OFF ≥ 1 ms Notes: 1. t OFF compensates for the power oscillation period caused by momentary power supply oscillations. 2. Specified at 4.5V for 5-V operation, and at 2.7V for 3-V operation. 3. When the above condition cannot be satisfied, the internal reset circuit will not operate normally. In this case, the LSI must be initialized by software. (Refer to the Initializing by Instruction section.) Figure 30 Internal Power Supply Reset 290