www.fairchildsemi.com RM3182A ARINC 429 Differential Line Driver Features Description • • • • • • • • • The RM3182A is a complete differential line driver IC. When Data A = Data B or Sync or Clock Signal is low, the driver forces the output to a Voltage Null level (0V ± 250 mV). Designed to address the ARINC 429 standard, the RM3182A has output rise and fall times that can be adjusted by the selection of an external capacitor (CA or CB) and an output voltage range adjustable through an externally applied VREF signal. All logic inputs and sync control inputs are TTL/CMOS compatible. The device is constructed on a monolithic IC using a junction-isolated bipolar process. Sputtered SiCr resistors in the internal bias circuitry provide for stable bias currents and a tighter tolerance of output impedance. The RM3182A is available in 16-lead ceramic sidebrazed DIP. Adjustable rise and fall times Low supply current Capable of driving 30 nF || 400Ω Digitally selectable 12.5 or 100 kbit/sec data rate Adjustable output voltages swing Output overvoltage protected Short circuit protected TTL and CMOS compatible inputs Available in 16-lead ceramic sidebrazed DIP Block Diagram Cap (A) VCC 5 9 VCC 3 pF 10 Amp A Charge Pumps Data (A) Clock Sync VREF Data (B) 4 14 3 1 13 Data (A) Rate Select Cap (A) Sync ISET (A) 6 10K 10K VREF VEE Data B 16 2 Out A 37.5Ω Clock VLOGIC VLOGIC 10K 10K 10K ISET (B) 11 37.5Ω VLOGIC ISET (A) Rate Select ISET (B) CL RL VCC 10K Cap (B) Out B 10K 10K Amp B 15 3 pF 12 8 Cap B GND 7 VEE 65-5890A VEE Note: Pin numbers are for the DIP package. REV. 1.0.1 12/7/00 RM3182A PRODUCT SPECIFICATION Pin Assignments VREF VLOGIC Rate Select Amp B Sync Clock Data A Data B CA CB Out A Out B VEE Amp A VCC GND 65-4192 Functional Description The device contains three main functional blocks. The first block is a digital section used to decode the ARINC Clock, Synchronization, and Data inputs as shown in Block Dia- gram. This block takes these inputs and channels the data to the charge pump circuits. The logical relationship for these pins is presented in Table 1. Table 1. I/O Truth Table Sync Clock Data A Data B Out A Out B Comments X L X X 0V 0V Null L X X X 0V 0V Null H H L L 0V 0V Null H H L H -VREF +VREF Low H H H L +VREF -VREF High H H H H 0V 0V Null The second functional block is a charge pump circuit that is used to control the output waveform and its timing characteristics. This is achieved through charging and discharging a capacitor with a known current. The capacitor is user selectable, and is connected between CA or CB pins and ground. A rate select pin (digital input) enables to set the rise and fall time. If this pin is tied to ground, the device functions in the high rate. This mode is recommended if the user does not have an application requiring data rate switching. In the table below, recommended capacitor values are given for each possible data combination. Table 2. Rate Select Pin Truth Table CA CB (pF) 10% to 90% Rlse/Fall time (µS) Data Rate (Kbits/sec) Comments 56 1.5 100 High Rate Logic 1 56 10 12-14.5 Low Rate Logic 0 390 10 12-14.5 Low Rate Logic 1 390 N/A N/A Not Used Rate Select Logic 0 2 REV. 1.0.1 12/7/00 PRODUCT SPECIFICATION The last functional block of the device consists of a voltage follower and a high power output differential amplifier. The voltage follower buffers the signals presented at the charge caps and presents the mirrored signal to the difference amplifier to drive the ARINC line. Two different outputs are available from the differential amplifiers: Amp A, Amp B, and Out A, Out B. The outputs Amp A and Amp B are the direct outputs of the power amplifier. The outputs Out A and Out B include 37.5Ω series resistors added to minimize bus reflections by matching the power amplifier’s output impedance to the cable’s impedance of 75Ω. Amp A and Amp B may be used to customize the output impedance of the device. These outputs can also be used to enhance the device’s drive capability. For example, driving the standard 30 nF || 400Ω load defined in the ARINC specifications (see output drive capability and capacitive loads for more details). All outputs are protected from voltage spikes with diodes connected between the output pins and the supply lines. RM3182A The output as a function of frequency is given by equation 1.2. R R L + 2R OUT ( 1 + jωC L R L ) L 1.2 A OUT ( jω ) = Amp A ( jω ) ------------------------------------------------------------------ Using equation 1.2, a time constant can be determined for the given application which is shown in equation 1.3. 1.3 τ = ( R OUT || R L )C L So, for the maximum loading condition of 30nF || 400Ω the resulting time constant is 1.9 µs. This shows that with a maximum load, the output waveform is greatly affected by the low pass filter combinabon of the ROUT || RL resistor and the load capacitance. A New Option: Amp A/Amp B Output Drive Capability and Capacitive Loads The Traditional Approach The RM3182A is capable of driving a high capacitive/resistive load. If complete ARINC compliance is required then Out A and Out B pins are recommended to maintain the output impedance. In this configuration, driving the full ARINC load of 30nF || 400Ω the output characteristic takes on the transfer function of a low pass filter due to the internal 37.5Ω resistor, the line resistance and the capacitance associated with the cable. This will result in a lower rise/fall time of the device. Equation 1.1 relates the output voltage at Out A and Out B to the voltage at the power amplifier’s output. Output A is taken for this example: 1.1 The RM3182A also provides the user the option of connecting the data line directly to the power output amplifiers thus bypassing the internal 37.5Ω resistance of the device and matching the line more precisely. For example, using a 1% 37.5Ω resistor allows better control of the output impedance. By applying the load directly to the power amplifiers output pins, the resulting waveform is virtually unchanged when driving other loads. There may be applications where these pins present a more desirable result. For instance, if the line that the chip is driving is short, then the parasitic components of the line can be neglected, and power amplifier can be tied directly to the lines. This option can be utilized to achieve a greater noise immunity through bypassing the internal resistors. AmpA Z L ⁄ 2 Out A = -------------------------------------( Z L ⁄ 2 ) + R OUT Where: ROUT = 37.5Ω and ZL = RL || CL REV. 1.0.1 12/7/00 3 RM3182A PRODUCT SPECIFICATION Absolute Maximum Ratings Parameter Min. Max. Units Supply Voltage (VCC to VEE) +36 V VLOGIC Theshold Voltage +7 V +VCC V VREF Voltage Logic Input Voltage -0.3 VLOGIC + 0.3 V Storage Temperature Range -65 +150 °C Operating Temperature Range -55 +125 °C Junction Temperature -55 +175 °C +300 °C Lead Soldering Temperature (60 sec.) Thermal Characteristics (Still air, soldered into PC board) Parameter 16-Lead Sidebrazed DIP Maximum Junction Temperature +175°C Thermal Resistance, θJC 70°C/W Thermal Resistance, θJA 28°C/W(1) For TA > 50°C Derate at 14.3 mW/°C Electrical Characteristics (VCC = +15V, VEE = -15V, VREF = +5V, VLOGIC = +5V, Rate Select = 0V, RL = Open Circuit, CL = 0 pF, and -55°C < TA < +125°C) Symbol Parameters ICC Positive Supply Current Test Conditlons Data Rate = 0 to 100 Kbits/sec Min. Typ. Max. Units 4.0 5.7 6.9 mA IEE Negative Supply Current Data Rate = 0 to 100 Kbits/sec 4.0 4.9 6.9 mA ILOGIC VLOGIC Supply Current Data Rate = 0 to 100 Kbits/sec 150 214 300 µA IREF VREF Supply Current Data Rate = 0 to 100 Kbits/sec -500 -294 -100 µA VIH Input Logic Level High Dependent on VLOGIC Vlogic V VIL Input Logic Level Low 0.5 V 2.0 VOH Output Voltage High With Respect to Ground 4.75 5.0 5.25 V VOL Output Voltage Low With Respect to Ground -5.25 -5.0 -4.75 V VNULL Output Voltage Null Both Data Inputs = Logic 0 -250 0 +250 mV IIH Input Current High VIN = 2.0V 1 µA IIL Input Current Low VIN = 0.5V -645 -161 -50 nA 15 pF 100 133 156 mA 1 CI Input Capacitance ISC Output Short Circuit Current AOUT and/or BOUT shorted line to line or to GND ISCVCC VCC Short Circuit Current AOUT and/or BOUT shorted line to line or to GND 140 165 mA ISCVEE VEE Short Circuit Current AOUT and/or BOUT shorted line to line or to GND 140 165 mA Note: 1. Guaranteed by design. 4 REV. 1.0.1 12/7/00 PRODUCT SPECIFICATION RM3182A Typical Power Dissipation Characteristics (VCC = +15V, VEE = -15V, VREF = +5V, TA = + 25°C, CA = CB = 56pF) Data Rate (Kbits/sec) Load Rate Select Positive Supply Current Negative Supply Current Pin VLOGIC Supply Current Total Power Dissipatlon 0 - 100 Open Circuit Logic 1,0 5.7 mA 4.9 mA 214 µA 160 mW 12.5 - 14 Full Load1 Logic 1 19.6 mA 22.7 mA 200 µA 655 mW 100 Full Load1 Logic 0 39.1 mA 38.4 mA 200 µA 1165 mW Note: 1. RL = 400Ω, CL = 0.03 µF (see Block Diagram). Typical Performance Characteristics 7 500 I EE 400 CC 4 3 2 1 0 -55 25 I REF 300 200 I LOGIC 100 0 -55 125 Temperature ( C) 65-5955 I Current (µA) 5 65-5954 Current (mA) 6 25 125 Temperature ( C) Figure 1. Supply Current vs. Temperature (CL = 0 pF, RL = Open Circuit) Figure 2. IREF, ILOGIC vs. Temperature 4.0 2.5 3.5 1.0 65-5956 0.5 0 12.5 50 100 150 Frequency (Hz) Figure 3. AmpA, AmpB Output Impedance Typical REV. 1.0.1 12/7/00 3.0 2.5 Rate Select = 0 2.0 1.5 1.0 Rate Select = 5V 0.5 0 0 65-5957 1.5 Slew Rate (V/µS) ZO (Ohms) 2.0 50 100 150 200 250 300 350 400 450 500 External Capacitor (pF) Figure 4. Slew Rate vs. CA, CB 5 RM3182A PRODUCT SPECIFICATION Applications Power Supply Considerations Heat Sinking /Air Flow and Short Circuit Protection The user application will determine if and how much heat sinking/air flow will be required for the RM3182A. Consideration must be given to ambient temperature, load conditions and output voltage swing. In addition, power consumption increases with increased operating frequency. Use the numbers given in the Thermal Characteristics Table to determine that the maximum allowable junction temperature of 175°C is not exceeded. Outputs Out A and Out B are short circuit protected by the internal 37.5Ω back termination resistors. During a short circuit of the output to either power supply or ground, the device must be able to dissipate the generated heat. For example, if the output is shorted to ground and VCC = +15V, the device must dissipate 15V x 0.165A = 2.5W. An appropriate heat sink is required in this situation. Note that the Amp A and Amp B outputs are not short circuit protected. Shorting these pins to either power supply or ground will cause failure of the device. An added external resistor will protect the circuit by limiting the current. Each power supply pin should be decoupled to ground using a high quality 10 µF tantalum capacitor. This is especially true when driving a large capacitive or resistive loads. The decoupling capacitors should be located as close to the device pins as possible to eliminate the wiring inductance. Typical ARINC 429 Application Figure 5 shows typical switching waveform for the RM3182A in any configuration. Figure 6 depicts connections for a ARINC 429 high speed bus driver application. This circuit shows the complete configuration for a 100 Kbits/sec, 10V differential output swing using the terminated output pins. 0V Data A 0V Data B +VREF Out A or Amp A Adjust By CA or Rate Select Out B or Amp B Three power supplies are required to operate the RM3182A in a typical ARINC 429 bus application: +15V for VCC, -15V for VEE, and +5V for both VREF and VLOGIC. The differential output swing of the RM3182A is equal to 2 x VREF. Using +5V gives a differential output swing of 10V. If a different output voltage swing is required, an additional power supply is needed to set VLOGIC. Adjust By CB or Rate Select -VREF +V REF -VREF High = +VREF Differential Output Out A- Out B or Amp Out AAmp Out B 0V Null Low = -VREF Note: Outputs unloaded 65-4188 Figure 5. Switching Waveforms 6 REV. 1.0.1 12/7/00 PRODUCT SPECIFICATION RM3182A +15V +5V 10 µF Tantalum 10 µF Tantalum VCC VLOGIC Data A VREF NC Sync Clock Amp A Input Out A Out B Amp B RM3182A To Bus CB Rate Select Data B CA GND NC 56 pF VEE 56 pF 10 µF Tantalum -15V NC = No Connection 65-5891A Figure 6. ARINC 429 Bus Driver Applications (100 kb/s Mode) REV. 1.0.1 12/7/00 7 RM3182A PRODUCT SPECIFICATION Mechanical Dimensions 16-Lead SideBraze Ceramic DIP Inches Symbol A b1 b2 c1 D E e eA L L1 Q s1 s2 Notes: Millimeters Min. Max. Min. Max. — .014 .045 .008 — .200 .023 — .36 1.14 .20 — 5.08 .58 .065 .015 .860 .280 .310 .100 BSC .300 BSC .125 .200 .140 — .015 .070 .005 — .005 — Notes 7 2 1.65 .38 21.84 7 7.11 7.87 2.54 BSC 7.62 BSC 3.18 5.08 3.56 — .38 1.78 .13 — .13 — 4, 8 6 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads number 1, 8, 9 and 16 only. 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within ±.010 (.25mm) of its exact longitudinal position relative to pins 1 and 16. 5. Applies to all four corners (leads number 1, 8, 9, and 16). 6. "eA" shall be measured at the centerline of the leads. 3 5 7. All leads – Increase maximum limit by .003 (.08mm) measured at the center of the flat, when lead finish applied. 8. Fourteen spaces. D 8 1 9 16 NOTE 1 E s1 S2 eA A Q L b2 8 b1 e L1 c1 REV. 1.0.1 12/7/00 RM3182A PRODUCT SPECIFICATION Ordering Information Part Number RM3182AS Package Operating Temperature Range 16-Lead Sidebraze Ceramic DIP -55°C to +125°C LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 12/7/00 0.0m 001 Stock# DS3003182A 2000 Fairchild Semiconductor Corporation