ETC RM3183

Electronics
Semiconductor Division
RM3183
Dual ARINC 429 Line Receiver
Features
•
•
•
•
•
•
•
•
clamping diodes. Self-test logic inputs are provided for
internal system tests. These inputs force the outputs to
either a high, a low, or a null state for off-line system tests.
Converts ARINC levels to serial data
Adjustable noise filters
TTL and CMOS compatible outputs
Built-in test inputs
Input protection circuitry
Mil-Std-883B screening available
20-pin DIP and LCC packages available
Dice with Mil visual screening available
Input noise filtering is accomplished with external capacitors. Two are required for each channel and can be adjusted
for best noise immunity at a specific data rate.
Three power supplies are needed plus ground. The input
thresholds depend only on the logic supply, so a wide range
of dual supplies can be accommodated.
Description
The RM3183 is a dual line receiver designed to meet all
requirements of the ARINC 429 interface specification.
It contains two independent receiver channels which accept
differential input signals and converts them to serial TTL
data.
Input overvoltage protection is provided by special circuitry
including dielectrically-isolated thin-film resistors and
The Raytheon RM3183 line receiver is the companion chip
to the RM3182 line driver. Together they provide all the
analog functions needed for the ARINC 429 interface.
Digital data processing involving serial-to-parallel conversion and clock recovery can be accomplished using one of
the ARINC interface ICs available or by discrete or gate
array implementations.
Block Diagram
+VL
+VS
11
In 1A
In 1B
Cap 1A
Cap 1B
18
19
Test B
Cap 2B
12
C1B
20
Cap 2A
15
C1A
Out 1A
Out 1B
17
2
In 2B
Input
Protection
& Level
Shift
16
Test A
In 2A
9
Test
Interface
8
C2A
6
Input
Protection
& Level
Shift
4
7
5
C2B
Out 2A
Out 2B
3
1
-VS
14
Gnd
65-3183-01
Rev. 1.0.0
RM3183
PRODUCT SPECIFICATION
Functional Description
The RM3183 contains two discrete ARINC 429 receiver
channels. Each channel contains three main sections: a
resistor-diode input network, a window comparator, and a
logic output buffer stage. The first stage provides overvoltage protection and biases the signal using voltage dividers
and current sources which are internally connected to the
+VL logic supply. This configuration provides excellent
input common mode rejection and a stable reference voltage
for the window comparators. Because the threshold for
switching is determined by this circuitry, ±5% tolerance is
recommended for the +VL supply. The test inputs will set the
outputs to a predetermined state for built-in test capability.
The ARINC inputs must be forced to 0V when using the test
inputs. If the test inputs are not used, they should be
grounded.
The window comparator stage generates two serial data
streams, one having logic 1 states corresponding to ARINC
“High” states (OUTA), and the other having logic 1 states
corresponding to ARINC “Low” states (OUTB). An ARINC
“Null” state at the inputs forces both outputs to logic 0.
Thus, the ARINC clock signal is recovered by applying a
NOR function to OUTA and OUTB.
The output stage generates a TTL compatible logic output
capable of driving several gate inputs.
Pin Assignments
Cap2B
3
18
In1A
In2B
4
17
Cap1B
Out2B
5
16
In1B
6
15
Out1A
Cap2A
7
14
GND
Out2A
8
13
NC
+VL
9
12
Out1B
NC
10
11
+VS
In2B 4
18
In1A
Out2B 5
17
Cap1B
In2A 6
16
In1B
Cap2A 7
15
Out1A
Out2A 8
14
GND
+VL
9
In2A
19 Cap1A
Cap1A
NC 13
19
1 -VS
20 TestB
2
Out1B 12
TestA
+VS 11
TestB
3 Cap2B
20
NC 10
-VS
2 TestA
LCC
Top View
Ceramic Dip
Top View
65-3183-03
65-3183-02
Absolute Maximum Ratings
Parameter
Supply Voltage
Max.
Units
+VS
+20
VDC
–VS
–20
VDC
+VL
+7
VDC
Operating Temperature Range
-55
+125
°C
Storage Temperature Range
-65
+150
°C
± 50
V
Input Voltage Range
Output Short Circuit Duration
2
Min.
Not protected
Internal Power Dissipation
900
mW
Lead Soldering Temperature (60 seconds)
+300
°C
PRODUCT SPECIFICATION
RM3183
Thermal Characteristics
(Still air, soldered into PC board)
Ceramic DIP
LCC
+175°C
+175°C
Maximum PD TA < 50°C
1042 mW
925 mW
Thermal Resistance, θJC
60°C/W
37°C/W
Thermal Resistance, θJC
120°C/W
105°C/W
Maximum Junction Temperature
DC Electrical Characteristics
TA = -55°C to +125°C, ± 12V ≤ VS ± 15V, VL = +5V, unless otherwise noted
Symbol
Parameter
Conditlons
Min.
Typ.
Max.
Units
13
V
VIH
V(A)-V(B)
OUTA = 1
6.5
10
VIL
V(A)-V(B)
OUTB = 1
-6.5
-10
-13
V
VIN
V(A)-V(B)
OUTA and OUTB = 0
-2.5
0
+2.5
V
VIC
V(A) and V(B)-GND
Maximum common mode
frequency = 80 kHz
RI
Input resistance, Input A to Input B
(2)
30
±5
V
50
kΩ
RH
Input resistance, Input A to Gnd
19
25
kΩ
RG
Input resistance, B to Gnd
19
25
kΩ
CI(1, 2)
Input capacitance, A to B
Filter caps disconnected
3
10
pF
(1, 2)
Input capacitance, A to Gnd
Filter caps disconnected
3
10
pF
(1, 2)
Input capacitance, B to Gnd
Filter caps disconnected
3
10
pF
CH
CG
Test Inputs (TESTA, TESTB)
VIH
Logic 1 input voltage
2.7
VIL
Logic 0 input voltage
IIH
Logic 1 input current
VIH = 2.7V
IIL
Logic 0 input current
VIL = 0.0V
IOH = 100 µA
TA = 25°C
4.0
4.3
V
IOH = 2.8 mA
Full temperature range
3.5
4.0
V
IOL = 100 µA
TA = 25°C
0.02
0.08
V
IOL = 2.0 mA
Full temperature range
0.3
0.8
V
V(A) = 0V
V(B) = 0V
V
0.0
V
5
15
µA
0.5
1.0
µA
Outputs
VOH
VOL
Tr
Rise Time
CL = 50 pF, TA = 25°C
40
70
ns
Tf
Fall Time
CL = 50 pF, TA = 25°C
30
70
ns
TPLH
Propagation delay
Output low to high
CL = 50 pF, fO = 400 kHz
Filter caps = 39 pF
800
ns
TPHL
Output high to low
TA = 25°C
320
ns
3
RM3183
PRODUCT SPECIFICATION
DC Electrical Characteristics (continued)
TA = -55°C to +125°C, ±12V ≤ VS ±15V, VL = +5V, unless otherwise noted
Symbol
Parameter
Conditlons
Min.
Typ.
Max.
Units
7.0
mA
Supply Current
ICC
(+VS)
Test inputs = 0V
± VS = 15V, TA = 15°C
3.7
± VS = 12V, TA = 15°C
3.0
6.0
mA
IEE
(-VS)
Test inputs = 0V
±VS = 15V, TA = 15°C
8.7
15.0
mA
±VS = 12V, TA = 15°C
7.4
14.0
mA
IDD
(+VL)
Test inputs = 0V
±VS = 15V, TA = 15°C
9.0
20.0
mA
±VS = 12V, TA = 15°C
8.6
18.0
mA
Notes:
1. With noise filter capacitors disconnected.
2. Guaranteed by design.
Truth Table
ARINC Inputs
V(A) - V(B)
4
Test Inputs
Outputs
TESTA
TESTB
OUTA
OUTB
Null
0
0
0
0
Low
0
0
0
1
High
0
0
1
0
V(A) = 0V, V(B) = 0V
0
1
0
1
V(A) = 0V, V(B) = 0V
1
0
1
0
V(A) = 0V, V(B) = 0V
1
1
0
0
PRODUCT SPECIFICATION
RM3183
12
900
11
800
10
T PLH
600
500
T PHL
400
300
200
100
0
-60
-35
-10
15
40
65
90
-VS (I EE )
9
8
VS = 15V
VL = +5V
7
6
5
+V S (I CC )
4
3
-60
140
115
VL (I DD )
65-3183-05
700
Supply Current (mA)
1000
65-3183-04
Prop Delay (ns)
Typical Performance Characteristics
-35
-10
15
Temperature (°C)
40
65
90
115
140
Temperature (°C)
Figure 1. Propagation Delay vs. Temperature
CL = 50 pF, CFILTER = 39 pF
Figure 2. Supply Current vs. Temperature
1.00
4.5
+125°C
4.3
+125°C
+25°C
0.50
65-3183-06
0.25
+55°C
0
0
0.5
1.0
1.5
2.0
2.5
+25°C
4.1
3.9
-55°C
65-3183-07
VOH (Volts)
VOL (Volts)
0.75
3.7
3.5
3.0
0
0.5
1.0
IOL (mA)
2.5
3.0
Figure 4. Output Voltage High vs. Output Current
3.0
70
40
TF
30
65-3183-08
20
10
-10
15
40
65
90
115
Temperature (°C)
Figure 5. TR and TF vs. Temperature
140
Prop Delay (µs)
50
-35
T A = +25 C
2.5
TR
T PLH
2.0
T PHL
1.5
1.0
65-3183-09
60
Rise/Fall Time (ns)
2.0
IOH (mA)
Figure 3. Output Voltage Low vs. Output Current
0
-60
1.5
0.5
0
0
50
100
150
200
250
300
350
400
Filter Capacitance (pF)
Figure 6. Propagation Delay vs. Filter Capacitance
TA = 25°C
5
RM3183
PRODUCT SPECIFICATION
AC Test Waveforms
+10V
ARINC In
(Differential) 0V
Logic
Out
Logic Out
(A Output)
90%
90%
10%
10%
TPLH
TPHL
TF
TR
65-3183-10
65-3183-16
Figure 7. Propagation Delay
Figure 8. Rise/Fall Times
Test Circuit
+15V
VIN1
-15V
0.01 µF
0.1 µF
+5V
0.01 µF
11
18
9
1
VOUT1
15
50 pF
VIN2
6
50 pF
RM3183
16
VREF
VOUT2
12
VOUT3
8
4
50 pF
19
17
3
7
14
VOUT4
5
50 pF
39pF 39pF
39pF
39pF
Notes:
1. VIN = 400 kHz square wave, -3.5V to +3.5V.
2. Set VREF = +3.5 V to test VOUT1 and VOUT3.
Set VREF = -3.5 V to test VOUT2 and VOUT4.
3. 50 pF load capacitance includes probe and wiring capacitance.
Figure 9. AC Test Schematic Diagram
6
65-3183-11
PRODUCT SPECIFICATION
Applications Information
The standard connections for the RM3183 are shown in
Figure 1. Dual supplies from ±12 to ±15 VDC are recommended for the ±VS supplies. Decoupling of all supplies
should be done near the IC to avoid propagation of noise
spikes due to switching transients. The ground connections
should be sturdy and isolated from large switching currents
to provide as quiet a ground reference as possible.
The noise filter capacitors are optional and are added to
provide extra noise immunity by limiting the noise bandwidth of the input signal before it reaches the comparator.
Two capacitors are required for each channel and they must
all be the same value. The suggested capacitor value for a
100 KHz operation is 39 pF, which will give a noise bandwidth of approximately 800 KHz. For lower data rates, larger
values of capacitance may be used to yield better noise
performance. To get optimum performance, the following
equation should be used to calculate capacitor value for a
specific data rate:
RM3183
The RM3183 can be used with Raytheon’s RM3182 Line
Driver to provide a complete analog ARINC 429 interface.
A simple application which can be used for systems requiring a repeater-type circuit for long transmissions or test
interfaces is given in Figure 2. More RM3182 drivers may be
added to test multiple ARINC channels, as shown.
An all digital IC is available which forms a complete
receiver system when combined with the RM3183. The
Thomson EF4442 is a four channel ARINC 429 receiver IC
which contains all the digital circuitry required to interface
with an 8-bit processor. Each channel consists of a 32-bit
register, an 8-bit status word comparator, and a 24-bit latch.
A multiplexer and 8-bit data bus buffer form the interface to
the system microprocessor. Figure 3 shows a typical ARINC
application having both transmit and receive functions using
four ICs: the EF4442, the RM3182 driver and two RM3183
dual receivers.
–6
3.95 × 10
C = --------------------------FO
F O = Data Rate (bits/sec)
7
RM3183
PRODUCT SPECIFICATION
Applications
+5V
+15V
9
11
RM3183
18
ARINC
Channel
1
16
39 pF
19
17
In 1A
15
In 1B
Cap 1A
12
A
B
Channel 1
Data Out
To Logic
Cap 1B
39 pF
6
ARINC
Channel
2
4
In 2A
8
A
In 2B
39 pF
7
3
5
Cap 2A
Channel 2
Data Out
To Logic
B
Cap 2B
39 pF
2
Logic
Test
Inputs
20
Test A
Test B
1
14
65-3183-12
-15V
Figure 9. ARINC Receiver Standard Connections
ARINC
Test
Channel
Input
A
In 1A
Out 1A
Data (B)
In 1B
B
A OUT
Data (A)
A
RM3182
B
Out 2A
B OUT
1/2
RM3183
A OUT
Data (A)
A
RM3182
Data (B)
To Additional
Channels
Figure 10. Repeater Circuit
8
Test
Channel
1
B OUT
B
Test
Channel
2
65-3183-13
PRODUCT SPECIFICATION
RM3183
Applications (continued)
+5V
+15V
Inputs
VCC
+V L
VSS
V R V I Sync Clk +VS
Mode
RM3182
ARINC
Channel
0
In 1A
Out 1A
H0
In 1B
Out 1B
L0
A OUT
RM3183
ARINC
Channel
1
In 2A
Out 2A
H1
In 2B
Out 2B
L1
N1
Data (A)
N0
Data (B)
-VS
Gnd PE
+VS GND -VS
EF4442
75 pF
From
Microprocessor
IRQ
+VS GND -VS
In 1A
Out 1A
H2
R/W
In 1B
Out 1B
L2
Clock
RM3183
ARINC
Channel
3
-15V
CB
Reset
+15V
ARINC
Channel
2
CA
75 pF
-15V
ARINC
Line Out
B OUT
Microprocessor
Data Bus
D0 - D8
In 2A
Out 2A
H3
In 2B
Out 2B
L3
A0
From
Address
Decoder
A1
+VL
65-3183-14
CS
To +5V
Figure 11. Four-Channel ARINC Receiver Circuit
-15V
10 Ω
1/2 W
+15V
1
4
10K
18
5
10K
16
RM3183
6
10K
15
10K
14
8
11
9
12
10K
10K
10 Ω
1/2 W
10Ω
1/2 W
65-3183-15
+5V
+15V
Figure 12. Burn-In Circuit
9
PRODUCT SPECIFICATION
RM3183
Mechanical Dimensions
20-Lead Ceramic DIP
Symbol
Inches
Min.
A
b1
b2
c1
D
E
e
eA
L
Q
s1
α
Max.
—
.200
.014
.023
.045
.065
.008
.015
—
1.060
.220
.310
.100 BSC
.300 BSC
.125
.200
.015
.060
.005
—
90°
105°
Millimeters
Min.
Notes
Max.
—
5.08
.36
.58
1.14
1.65
.20
.38
—
25.92
5.59
7.87
2.54 BSC
7.62 BSC
3.18
5.08
.38
1.52
.13
—
90°
105°
8
2, 8
8
4
4
5, 9
7
3
6
Notes:
1. Index area: a notch or a pin one identification mark shall be located
adjacent to pin one. The manufacturer's identification shall not be
used as pin one identification mark.
2. The minimum limit for dimension "b2" may be .023(.58mm) for leads
number 1, 10, 11 and 20 only.
3. Dimension "Q" shall be measured from the seating plane to the
base plane.
4. This dimension allows for off-center lid, meniscus and glass overrun.
5. The basic pin spacing is .100 (2.54mm) between centerlines. Each
pin centerline shall be located within ±.010 (.25mm) of its exact
longitudinal position relative to pins 1 and 20.
6. Applies to all four corner's (leads number 1, 10, 11, and 20).
7. "eA" shall be measured at the center of the lead bends or at the
centerline of the leads when "α" is 90°.
8. All leads – Increase maximum limit by .003(.08mm) measured at the
center of the flat, when lead finish is applied.
9. Eighteen spaces.
D
Note 1
E
s1
eA
e
A
Q
L
b2
α
c1
b1
10
RM3183
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
20-Terminal LCC
Inches
Symbol
Notes:
Millimeters
Notes
Min.
Max.
Min.
Max.
A
A1
B1
B3
.060
.050
.022
.100
.088
1.52
1.27
.56
2.54
2.24
3, 6
3, 6
.71
.56
2
2, 5
D/E
D1/E1
D2/E2
.342
.358
.200 BSC
8.69
9.09
5.08 BSC
.100 BSC
—
.358
.050 BSC
2.54 BSC
—
9.09
1.27 BSC
.040 REF
1.02 REF
4
.020 REF
.045
.055
.51 REF
1.14
1.40
4
.075
.003
1.91
.08
.028
.022
.006
D3/E3
e
h
j
L1
L2
L3
ND/NE
N
.15
.095
.015
5
20
20
2. Unless otherwise specified, a minimum clearance of .015 inch
(0.38mm) shall be maintained between all metallized features (e.g.,
lid, castellations, terminals, thermal pads, etc.).
3. Dimension "A" controls the overall package thickness. The
maximum "A" dimension is the package height before being solder
dipped.
2.41
.38
5
1. The index feature for terminal 1 identification, optical orientation or
handling purposes, shall be within the shaded index areas shown
on planes 1 and 2. Plane 1, terminal 1 identification may be an
extension of the length of the metallized terminal which shall not be
wider than the B1 dimension.
5
4. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer's option, from that shown on the drawing. The index
corner shall be clearly unique.
5. Dimension "B3" minimum and "L3" minimum and the appropriately
derived castellation length define an unobstructed three
dimensional space traversing all of the ceramic layers in which a
castellation was designed. Dimensions "B3" and "L3" maximum
define the maximum width and depth of the castellation at any point
on its surface. Measurement of these dimensions may be made
prior to solder dripping.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
PLANE 1
PLANE 2
E
LID
E3
D
1
A1
D3
(h) X 45°
3 PLCS
4
(j) X 45°
4
A
INDEX
CORNER
E1
E2
B1
e
D2
L3
D1
B3
L2
L1
DETAIL "A"
DETAIL "A"
11
PRODUCT SPECIFICATION
RM3183
Ordering Information
Part Number
Package
Operating Temperature Range
RM3183S
20 Lead Ceramic DIP
-55°C to +125°C
RM3183L
20 Terminal Leadless Chip Carrier
-55°C to +125°C
The information contained in this data sheet has been carefully compiled; however, it shall not by implication or otherwise become part of the
terms and conditions of any subsequent sale. Raytheon’s liability shall be determined solely by its standard terms and conditions of sale.
No representation as to application or use or that the circuits are either licensed or free from patent infringement is intended or implied.
Raytheon reserves the right to change the circuitry and any other data at any time without notice and assumes no liability for errors.
LIFE SUPPORT POLICY:
Raytheon’s products are not designed for use in life support applications, wherein a failure or malfunction of the component can reasonably
be expected to result in personal injury. The user of Raytheon components in life support applications assumes all risk of such use and
indemnifies Raytheon Company against all damages.
Raytheon Electronics
Semiconductor Division
350 Ellis Street
Mountain View, CA 94043
650.968.9211
FAX 650.966.7742
8/97 0.0m
Stock# DS30003183
© Raytheon Company 1997