0.4 Ω CMOS, Dual DPDT Switch in WLCSP/LFCSP/TSSOP Packages ADG888 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V to 5.5 V operation Ultralow on resistance 0.4 Ω typical 0.6 Ω maximum at 5 V supply Excellent audio performance, ultralow distortion 0.07 Ω typical 0.14 Ω maximum RON flatness High current carrying capability 400 mA continuous 600 mA peak current at 5 V Automotive temperature range: −40°C to +125°C Rail-to-rail switching operation Typical power consumption (<0.1 μW) ADG888 S1A D1 S1B S2A D2 S2B IN1 S3A D3 S3B S4A D4 S4B APPLICATIONS SWITCHES SHOWN FOR A LOGIC 1 INPUT 05432-001 IN2 Cellular phones PDAs MP3 players Power routing Battery-powered systems PCMCIA cards Modems Audio and video signal routing Communication systems Data switching Figure 1. GENERAL DESCRIPTION The ADG888 is a low voltage, dual DPDT (double-pole, double-throw) CMOS device optimized for high performance audio switching. With its low power and small physical size, it is ideal for portable devices. This device offers ultralow on resistance of less than 0.8 Ω over the full temperature range, making it an ideal solution for applications requiring minimal distortion through the switch. The ADG888 also has the capability of carrying large amounts of current, typically 400 mA at 5 V operation. When on, each switch conducts equally well in both directions and has an input signal range that extends to the supplies. The ADG888 exhibits break-before-make switching action. The ADG888 is available in a 16-ball WLCSP, 16-lead LFCSP, and a 16-lead TSSOP. These packages make the ADG888 the ideal solution for space-constrained applications. PRODUCT HIGHLIGHTS 1. 2. 3. 4. <0.6 Ω over full temperature range of −40°C to +125°C. High current handling capability (400 mA continuous current at 5 V). Low THD + N (0.008% typical). Tiny 16-ball WLCSP, 16-lead LFCSP, and 16-lead TSSOP. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADG888 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................5 Applications....................................................................................... 1 Pin Configurations and Function Descriptions ............................6 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................7 General Description ......................................................................... 1 Test Circuits........................................................................................9 Product Highlights ........................................................................... 1 Terminology .................................................................................... 11 Revision History ............................................................................... 2 Outline Dimensions ....................................................................... 12 Specifications..................................................................................... 3 Ordering Guide .......................................................................... 13 Absolute Maximum Ratings............................................................ 5 REVISION HISTORY 12/06—Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to Table 2............................................................................ 4 Changes to Table 3............................................................................ 5 Changes to Ordering Guide .......................................................... 13 7/05—Revision 0: Initial Version Rev. A | Page 2 of 16 ADG888 SPECIFICATIONS VDD = 4.2 V to 5.5 V, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (∆RON) On Resistance Flatness (RFLAT (ON)) LEAKAGE CURRENTS Source Off Leakage IS (Off ) Channel On Leakage ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS 2 tON +25°C 0.4 0.48 0.04 0.06 0.07 0.11 B Version 1 Y Version1 Unit Test Conditions/Comments 0 to VDD V Ω typ Ω max Ω typ VDD = 4.2 V, VS = 0 V to VDD, IDS = 100 mA See Figure 16 VDD = 4.2 V, VS = 2.2 V, IDS = 100 mA 0.55 0.6 0.07 0.075 0.13 0.14 ±0.2 ±0.2 nA typ nA typ V min V max μA typ μA max pF typ VIN = VINL or VINH ±0.1 RL = 50 Ω, CL = 35 pF VS = 3 V/0 V; see Figure 19 RL = 50 Ω, CL = 35 pF VS = 3 V/0 V; see Figure 19 RL = 50 Ω, CL = 35 pF VS1 = VS2 = 3 V; see Figure 20 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 21 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 22 Adjacent channel; RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 25 Adjacent switch; RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 23 RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 3 V p-p RL = 50 Ω, CL = 5 pF; see Figure 24 RL = 50 Ω, CL = 5 pF; see Figure 24 0.005 2 Break-Before-Make Time Delay (tBBM) Charge Injection Off Isolation Channel-to-Channel Crosstalk 70 −67 −99 ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ −67 dB typ 0.008 −0.03 29 58 110 % dB typ MHz typ pF typ pF typ 0.003 μA typ μA max 33 35 18 19 5 Total Harmonic Distortion (THD + N) Insertion Loss −3 dB Bandwidth CS (Off ) CD, CS (On) POWER REQUIREMENTS IDD 1 2 VDD = 4.2 V, VS = 0 V to VDD IDS = 100 mA VDD = 5.5 V VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 17 VS = VD = 1 V or 4.5 V; see Figure 18 2.0 0.8 22 30 13 17 9 tOFF 1 Ω max Ω typ Ω max 4 VDD = 5.5 V Digital inputs = 0 V or 5.5 V Temperature range for the Y version is −40°C to +125°C for the TSSOP and LFCSP; temperature range for the B version is −40°C to +85°C for the WLCSP. Guaranteed by design, not production tested. Rev. A | Page 3 of 16 ADG888 VDD = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (∆RON) On Resistance Flatness (RFLAT (ON)) +25°C 0.5 0.7 0.045 0.072 0.16 B Version 1 Y Version1 Unit Test Conditions/Comments 0 to VDD V Ω typ Ω max Ω typ VDD = 2.7 V, VS = 0 V to VDD IS = 100 mA; see Figure 16 VDD = 2.7 V, VS = 1 V 0.75 0.8 0.077 0.083 0.262 LEAKAGE CURRENTS Source Off Leakage IS (Off ) Channel On Leakage ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS 2 tON ±0.2 ±0.2 1.3 0.8 V min V max ±0.1 μA typ μA max pF typ 2 Break-Before-Make Time Delay (tBBM) Charge Injection Off Isolation Channel-to-Channel Crosstalk 50 −67 −99 tOFF nA typ nA typ 0.005 28 43 13 20 14 47 50 21 22 5 −67 Total Harmonic Distortion (THD + N) Insertion Loss –3 dB Bandwidth CS (Off ) CD, CS (On) POWER REQUIREMENTS IDD 0.01 −0.04 29 60 115 0.003 1 1 2 Ω max Ω typ Ω max 2 IS = 100 mA VDD = 2.7 V, VS = 0 V to VDD IS = 100 mA VDD = 3.6 V VS = 1 V/2.6 V, VD = 2.6 V/1 V; see Figure 17 VS = VD = 1 V or 2.6 V; see Figure 18 VIN = VINL or VINH ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ RL = 50 Ω, CL = 35 pF; see Figure 19 VS = 1.5 V/0 V RL = 50 Ω, CL = 35 pF; see Figure 19 VS = 1.5 V/0 V RL = 50 Ω, CL = 35 pF VS1 = VS2 = 1.5 V; see Figure 20 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 21 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 22 Adjacent channel; RL = 50 V, CL = 5 pF, f = 100 kHz; see Figure 25 dB typ Adjacent switch; RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 23 % RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 1 V p-p dB typ RL = 50 Ω, CL = 5 pF; see Figure 24 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 24 pF typ pF typ VDD = 3.6 V μA typ Digital inputs = 0 V or 3.6 V μA max Temperature range for the Y version is −40°C to +125°C for the TSSOP and LFCSP; temperature range for the B version is −40°C to +85°C for the WLCSP. Guaranteed by design, not production tested. Rev. A | Page 4 of 16 ADG888 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to GND Analog Inputs, Digital Inputs1 Peak Current, S or D 5 V operation Continuous Current, S or D 5 V operation Operating Temperature Range Automotive (Y Version) TSSOP and LFCSP packages Industrial (B version) WLCSP package Storage Temperature Range Junction Temperature 16-Lead TSSOP Package θJA Thermal Impedance (4-Layer Board) θJC Thermal Impedance 16-Lead WLCSP Package θJA Thermal Impedance (4-Layer Board) 16-Lead LFCSP Package θJA Thermal Impedance (4-Layer Board) Reflow Soldering (Pb-Free) Peak Temperature Time at Peak Temperature 1 600 mA (pulsed at 1 ms, 10% duty cycle max) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 400 mA Only one absolute maximum rating can be applied at any one time. Rating −0.3 V to +6 V −0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first ESD CAUTION −40°C to +125°C −40°C to +85°C −65°C to +150°C 150°C 112°C/W 27.6°C/W 130°C/W 30.4°C/W 260(+0/−5)°C 10 sec to 40 sec Overvoltages at IN, S, or D are clamped by internal diodes. Limit current to the maximum ratings given. Rev. A | Page 5 of 16 ADG888 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS S4A S1A D1 S4B GND VDD S1B 16 S1A 2 IN1 S2B PIN 1 INDICATOR D1 1 3 S3A S2A 11 S4B S1B 2 D2 05432-002 D3 4 S2B 3 TOP VIEW D2 4 Figure 2. 16-Ball WLCSP Pin Configuration 10 S3B 9 D3 S2A 5 TOP VIEW (BALL SIDE DOWN) Not to Scale (SOLDER BALLS ON OPPOSITE SIDE) 12 D4 S3A 8 IN2 IN2 7 S3B Figure 3. 16-Lead LFCSP Pin Configuration VDD 1 16 GND S1A 2 15 S4A D1 3 ADG888 14 D4 S1B 4 TOP VIEW (Not to Scale) 13 S4B S2B 5 12 S3B D2 6 11 D3 S2A 7 10 S3A IN1 8 9 IN2 05432-004 D4 1 05432-003 D 14 GND C 13 S4A B IN1 6 A 15 VDD BALL A1 INDICATOR Figure 4. 16-Lead TSSOP Pin Configuration Table 4. Pin Function Descriptions WLCSP Ball No. 2C 2B 1B, 1C, 2A, 2D, 3A, 3D, 4B, 4C 1A, 1D, 4A, 4D 3B, 3C LFCSP Pin No. 15 14 2, 3, 5, 8, 10, 11, 13, 16 1, 4, 9, 12 6, 7 TSSOP Pin No. 1 16 2, 4, 5, 7, 10, 12, 13, 15 3, 6, 11, 14 8, 9 Mnemonic VDD GND S D IN Description Most Positive Power Supply Potential. Ground (0 V) Reference. Source Terminal. Can be an input or output. Drain Terminal. Can be an input or output. Logic Control Input. Table 5. Truth Table Logic (IN1/IN2) 0 1 Switch 1A/2A/3A/4A Off On Switch 1B/2B/3B/4B On Off Rev. A | Page 6 of 16 ADG888 TYPICAL PERFORMANCE CHARACTERISTICS 0.40 0.7 TA = 25°C IDS = 100mA VDD = 4.2V 0.35 TA = +125°C 0.6 VDD = 4.5V 0.30 TA = +85°C VDD = 3V IDS = 100mA 0.5 VDD = 5V VDD = 5.5V 0.20 RON (Ω) RON (Ω) 0.25 0.4 TA = +25°C 0.3 TA = –40°C 0.15 0.2 0.10 0 0 2 1 3 0 5 4 05432-008 0.1 05432-005 0.05 0 0.5 1.0 Figure 5. On Resistance vs. VD (VS), VDD = 4.2 V to 5.5 V 0.6 VDD = 2.7V VDD = 3V 0.5 1.5 2.0 2.5 3.0 VS, VD (V) VS, VD (V) Figure 8. On Resistance vs. VD (VS) for Different Temperatures, VDD = 3 V 400 TA = 25°C IDS = 100mA TA = 25°C 350 300 VDD = 5V 0.4 QINJ (pC) RON (Ω) 250 VDD = 3.3V 0.3 VDD = 3.6V 200 150 0.2 100 0.1 0.5 1.0 1.5 2.0 2.5 0 3.5 3.0 0 0.5 1.0 1.5 VS, VD (V) Figure 6. On Resistance vs. VD (VS), VDD = 2.7 V to 3.6 V 0.45 TA = +85°C 0.25 TA = +25°C 0.20 TA = –40°C VDD = 3V; SxB CHANNELS VDD = 5V; SxA CHANNELS 35 VDD = 5V; SxB CHANNELS 25 0.10 10 0.05 5 0 1.0 1.5 2.0 2.5 3.0 4.5 5.0 3.5 4.0 4.5 tON 20 15 0.5 4.0 VDD = 3V; SxA CHANNELS 40 0.15 0 3.5 30 TIME (ns) 0.30 05432-007 RON (Ω) 45 TA = +125°C 0.35 2.5 3.0 VD (V) Figure 9. Charge Injection vs. Source Voltage VDD = 5V IDS = 100mA 0.40 2.0 tOFF 0 –40 5.0 VS, VD (V) Figure 7. On Resistance vs. VD (VS) for Different Temperatures, VDD = 5 V VDD = 3V, 5V; SxB CHANNELS VDD = 3V, 5V; SxA CHANNELS –20 0 20 40 60 TEMPERATURE (°C) 80 Figure 10. tON/tOFF Times vs. Temperature Rev. A | Page 7 of 16 100 120 05432-010 0 05432-009 05432-006 0 VDD = 3V 50 ADG888 0.025 0 TA = 25°C VDD = 3V, VS = 2V p-p –1 0.020 –4 –5 –6 0.015 VDD = 5V, VS = 3V p-p 100k 1M FREQUENCY (Hz) 10M VDD = 5V, VS = 1V p-p 0 0 100M Figure 11. Bandwidth 2k 4k 6k 8k 10k 12k 14k FREQUENCY (Hz) 16k 18k 20k Figure 14. Total Harmonic Distortion + Noise (THD + N) 20 TA = 25°C VDD = 3V, 4.2V, 5V –20 ATTENUATION (dB) 0 –40 –60 –80 –100 TA = 25°C VDD = 3V, 4.2V, 5V NO DECOUPLING ON SUPPLIES –20 –40 –60 1k 10k 100k 1M 10M –100 100 100M FREQUENCY (Hz) –20 ADJACENT CHANNELS (S1A-S2A) ADJACENT SWITCHES (S1A-S1B) –60 –80 –100 S1A-S4A 05432-013 –120 1k 10k 100k 1M FREQUENCY (Hz) 10k 100k Figure 15. AC PSRR TA = 25°C VDD = 3V, 4.2V, 5V –140 100 1k FREQUENCY (Hz) Figure 12. Off Isolation vs. Frequency –40 05432-023 05432-012 –80 –120 100 0 05432-014 TA = 25°C VDD = 3V, 4.2V, 5V –10 10k 0 VDD = 3V, VS = 0.5V p-p 0.005 05432-011 –9 ATTENUATION (dB) VDD = 3V, VS = 1V p-p 0.010 –7 –8 ATTENUATION (dB) VDD = 5V, VS = 4V p-p –3 THD + N (%) ON RESPONSE (dB) –2 10M 100M Figure 13. Crosstalk vs. Frequency Rev. A | Page 8 of 16 1M 10M 100M ADG888 TEST CIRCUITS IDS V1 D RON = V1/IDS Figure 18. On Leakage S ID (OFF) D A VS VD 05432-016 A A VD Figure 16. On Resistance IS (OFF) D Figure 17. Off Leakage VDD 0.1μF VDD S1B S1A VS VOUT D1 RL 50Ω IN 50% VIN CL 35pF 50% 90% 90% GND tON tOFF 05432-018 VOUT Figure 19. Switching Times, tON, tOFF VDD 0.1μF 50% VDD S1B S1A VS VIN VOUT D1 80% VOUT RL IN 50% 0V CL 35pF tBBM tBBM 05432-019 50Ω 80% GND Figure 20. Break-Before-Make Time Delay, tBBM VDD SW ON S1B NC D1 S1A VOUT 1nF IN VOUT ΔVOUT QINJ = CL ⋅ ΔVOUT GND Figure 21. Charge Injection Rev. A | Page 9 of 16 05432-020 VS SW OFF VIN 05432-017 ID (ON) VS S NC 05432-015 S ADG888 VDD VDD 0.1μF 0.1μF NETWORK ANALYZER VDD S1A 50Ω 50Ω S1B 50Ω S1A VS VS D D VOUT 05432-021 RL 50Ω GND OFF ISOLATION = 20 log RL 50Ω GND VOUT INSERTION LOSS = 20 log VS Figure 22. Off Isolation VOUT 05432-022 S1B NC NETWORK ANALYZER VDD VOUT WITH SWITCH VOUT WITHOUT SWITCH Figure 24. Bandwidth VDD 0.1μF VDD RL 50Ω VOUT 50Ω RL 50Ω NC VS VOUT VS 05432-024 CHANNEL-TO-CHANNEL CROSSTALK = 20 log NC D1 50Ω S1B CHANNEL-TO-CHANNEL CROSSTALK = 20 log VOUT VS Figure 25. Channel-to-Channel Crosstalk (S1A to S2A) Figure 23. Channel-to-Channel Crosstalk (S1A to S1B) Rev. A | Page 10 of 16 NC S2B S1A 50Ω GND VS D2 S2A 50Ω D S1B 05432-025 VOUT NETWORK ANALYZER S1A ADG888 TERMINOLOGY IDD Positive supply current. tOFF Delay time between the 50% and the 90% points of the digital input and switch off condition. VD (VS) Analog voltage on Terminal D and Terminal S. RON Ohmic resistance between Terminal D and Terminal S. tBBM On or off time measured between the 80% points of both switches when switching from one to another. RFLAT (ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during on-off switching. ΔRON On resistance match between any two channels. Off Isolation A measure of unwanted signal coupling through an off switch. IS (OFF) Source leakage current with the switch off. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. This is specified for two conditions: ID, IS (ON) Channel leakage current with the switch on. • VINL Maximum input voltage for Logic 0. • VINH Minimum input voltage for Logic 1. Adjacent channel, that is, S1A to S2A, S1B to S2B, S3A to S4A, or S3B to S4B. Adjacent switch, that is, S1A to S1B, S2A to S2B, S3A to S3B, or S4A to S4B. −3 dB Bandwidth The frequency at which the output is attenuated by 3 dB. IINL (IINH) Input current of the digital input. On Response The frequency response of the on switch. CS (OFF) Off switch source capacitance. Measured with reference to ground. Insertion Loss The loss due to the on resistance of the switch. CD, CS (ON) On switch capacitance. Measured with reference to ground. THD + N The ratio of the harmonic amplitudes plus signal noise to the fundamental. CIN Digital input capacitance. tON Delay time between the 50% and the 90% points of the digital input and switch on condition. Rev. A | Page 11 of 16 ADG888 OUTLINE DIMENSIONS 0.65 0.59 0.53 SEATING PLANE D C B 1 0.36 0.32 0.28 BALL 1 IDENTIFIER 2.06 2.00 SQ 1.94 A 2 0.50 BALL PITCH 3 4 0.28 0.24 0.20 BOTTOM VIEW (BALL SIDE UP) 111105-0 TOP VIEW (BALL SIDE DOWN) 0.11 0.09 0.07 Figure 26. 16-Ball Wafer Level Chip Scale Package [WLCSP] (CB-16) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 27. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 4.00 BSC SQ PIN 1 INDICATOR 0.65 BSC TOP VIEW 12° MAX 1.00 0.85 0.80 0.60 MAX PIN 1 INDICATOR 0.60 MAX 13 12 16 1 EXPOSED PAD 3.75 BSC SQ 0.75 0.60 0.50 (BOTTOM VIEW) 4 9 8 5 0.25 MIN 1.95 BSC 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGC Figure 28. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-16-4) Dimensions shown in millimeters Rev. A | Page 12 of 16 2.25 2.10 SQ 1.95 ADG888 ORDERING GUIDE Model ADG888YRUZ 2 ADG888YRUZ-REEL2 ADG888YRUZ-REEL72 ADG888YCPZ-REEL2 ADG888YCPZ-REEL72 ADG888BCBZ-REEL2 ADG888BCBZ-REEL72 EVAL-ADG888EB 1 2 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +85°C −40°C to +85°C Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Ball Wafer Level Chip Scale Package [WLCSP] 16-Ball Wafer Level Chip Scale Package [WLCSP] Evaluation Board Branding on these packages is limited to three characters due to space constraints. Z = Pb-free part. Rev. A | Page 13 of 16 Package Option RU-16 RU-16 RU-16 CP-16-4 CP-16-4 CB-16 CB-16 Branding 1 S0D S0D S02 S02 ADG888 NOTES Rev. A | Page 14 of 16 ADG888 NOTES Rev. A | Page 15 of 16 ADG888 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05432-0-12/06(A) Rev. A | Page 16 of 16