AD AD8034AR-REEL

a
FEATURES
FET Input Amplifier
1 pA Typical Input Bias Current
Very Low Cost
High Speed
80 MHz, –3 dB Bandwidth (G = +1)
80 V/␮s Slew Rate (G = +2)
Low Noise
11 nV/√Hz (f = 100 kHz)
0.6 fA/√Hz (f = 100 kHz)
Wide Supply Voltage Range
5 V to 24 V
Low Offset Voltage, 1 mV Typical
Single-Supply and Rail-to-Rail Output
High Common-Mode Rejection Ratio –100 dB
Low Power
3.3 mA/Amplifier Typical Supply Current
No Phase Reversal
Small Packaging
SOIC-8, SOT-23-8, and SC70
Low Cost, 80 MHz
FastFET ™ Op Amps
AD8033/AD8034
CONNECTION DIAGRAMS
SOIC-8 (R)
AD8033
NC 1
SC70 (KS)
AD8033
VOUT 1
8 NC
–IN 2
7 +VS
+IN
3
6
VOUT
–VS 4
5
NC
5
+VS
4
–IN
–VS 2
+IN 3
SOIC-8 and SOT-23-8 (RT)
AD8034
APPLICATIONS
Instrumentation
Filters
Level Shifting
Buffering
VOUT1 1
8
+VS
–IN1 2
7
VOUT2
+IN1 3
6
–IN2
–VS 4
5
+IN2
24
G = +10
GENERAL DESCRIPTION
With a wide supply voltage range from 5 V to 24 V and fully
operational on a single supply, the AD8033/AD8034 amplifiers
will work in more applications than similarly priced FET
input amps. In addition, the AD8033/AD8034 have rail-to-rail
outputs for added versatility.
Despite their low cost, the amplifiers provide excellent overall
performance. They offer high common-mode rejection of
–100 dB, low input offset voltage of 2 mV max, and low noise
of 11 nV/√Hz.
The AD8033/AD8034 amplifiers only draw 3.3 mA/amplifier of
quiescent current while having the capability of delivering up to
40 mA of load current.
18
G = +5
15
12
GAIN – dB
The AD8033/AD8034 FastFET amplifiers are voltage feedback
amplifiers with FET inputs, offering ease of use and excellent
performance. The AD8033 is a single amplifier and the
AD8034 is a dual amplifier. The AD8033/AD8034 FastFET
op amps in ADI’s proprietary XFCB process offer significant
performance improvements over other low cost FET amps, such as
low noise (11 nV/√Hz and 0.6 fA/√Hz) and high speed (80 MHz
bandwidth and 80 V/µs slew rate).
VO = 200mV p-p
21
9
G = +2
6
3
G = +1
0
–3
G = –1
–6
–9
0.01
1.0
10
FREQUENCY – MHz
100
1000
Figure 1. Small Signal Frequency Response
The AD8033 is available in small packages: SOIC-8 and SC70.
The AD8034 is also available in small packages: SOIC-8 and
SOT-23-8. They are rated to work over the industrial temperature
range of –40°C to +85°C without a premium over commercial
grade products.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD8033/AD8034–SPECIFICATIONS (T = 25ⴗC, V = ⴞ5 V, R = 1 k⍀, Gain = +2, unless otherwise noted.)
A
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Input Overdrive Recovery Time
Output Overdrive Recovery Time
Slew Rate (25% to 75%)
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
Distortion
Second Harmonic
Third Harmonic
Crosstalk, Output-to-Output
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
S
Conditions
Min
Typ
G = +1, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p
G = +2, VO = 2 V p-p
–6 V to +6 V Input
–3 V to +3 V Input, G = +2
G = +2, VO = 4 V Step
G = +2, VO = 2 V Step
G = +2, VO = 8 V Step
65
80
30
21
135
135
80
95
225
MHz
MHz
MHz
ns
ns
V/µs
ns
ns
–82
–85
–70
–81
–86
11
0.7
dBc
dBc
dBc
dBc
dB
nV/√Hz
fA/√Hz
55
fC = 1 MHz, VO = 2 V p-p
RL = 500 Ω
RL = 1 kΩ
RL = 500 Ω
RL = 1 kΩ
f = 1 MHz, G = +2
f = 100 kHz
f = 100 kHz
VCM = 0 V
TMIN – TMAX
1
Input Offset Voltage Match
Input Offset Voltage Drift
Input Bias Current
Open-Loop Gain
INPUT CHARACTERISTICS
Common-Mode Input Impedance
Differential Input Impedance
Input Common-Mode Voltage Range
FET Input Range
Usable Input Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Short Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio
L
TMIN – TMAX
VO = ± 3 V
89
VCM = (–3 V to +1.5 V)
–89
± 4.75
30% Overshoot, G = +1,
VO = 400 mV p-p
4
1.5
50
92
–90
2
3.5
2.5
27
11
Unit
mV
mV
mV
µV/oC
pA
pA
dB
1000||2.3
1000||1.7
GΩ||pF
GΩ||pF
–5.0 to +2.2
–5.0 to +5.0
–100
V
V
dB
± 4.95
40
35
V
mA
pF
5
VS = ± 2 V
Max
3.3
–100
24
3.5
V
mA
dB
Specifications subject to change without notice.
–2–
REV. B
AD8033/AD8034
SPECIFICATIONS (T = 25ⴗC, V = 5 V, R = 1 k⍀, Gain = +2, unless otherwise noted.)
A
S
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Input Overdrive Recovery Time
Output Overdrive Recovery Time
Slew Rate (25% to 75%)
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
Distortion
Second Harmonic
Third Harmonic
Crosstalk, Output to Output
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
L
Conditions
Min
INPUT CHARACTERISTICS
Common-Mode Input Impedance
Differential Input Impedance
Input Common-Mode Voltage Range
FET Input Range
Usable Input Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Short Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio
Unit
80
32
21
180
200
70
100
MHz
MHz
MHz
ns
ns
V/µs
ns
fC = 1 MHz, VO = 2 V p-p
RL = 500 Ω
RL = 1 kΩ
RL = 500 Ω
RL = 1 kΩ
f = 1 MHz, G = +2
f = 100 kHz
f = 100 kHz
–80
–84
–70
–80
–86
11
0.7
dBc
dBc
dBc
dBc
dB
nV/√Hz
fA/√Hz
VCM = 0 V
TMIN – TMAX
1
TMIN – TMAX
VO = 0 V to 3 V
87
VCM = 1.0 V to 2.5 V
–80
RL = 1 kΩ
0.16 to 4.83
30% Overshoot, G = +1,
VO = 400 mV p-p
4
1
50
92
VS = ± 1 V
–80
–3–
2.0
3.5
2.5
30
10
mV
mV
mV
µV/oC
pA
pA
dB
1000||2.3
1000||1.7
GΩ||pF
GΩ||pF
0 to 2.0
0 to 5.0
–100
V
V
dB
0.04 to 4.95
30
25
V
mA
pF
5
Specifications subject to change without notice.
REV. B
Max
G = +1, VO = 0.2 V p-p
70
G = +2, VO = 0.2 V p-p
G = +2, VO = 2 V p-p
–3 V to +3 V Input
–1.5 V to +1.5 V Input, G = +2
55
G = +2, VO = 4 V Step
G = +2, VO = 2 V Step
Input Offset Voltage Match
Input Offset Voltage Drift
Input Bias Current
Open-Loop Gain
Typ
3.3
–100
24
3.5
V
mA
dB
AD8033/AD8034
SPECIFICATIONS
(TA = 25ⴗC, VS = ⴞ12 V, RL = 1 k⍀, Gain = +2, unless otherwise noted.)
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Input Overdrive Recovery Time
Output Overdrive Recovery Time
Slew Rate (25% to 75%)
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
Distortion
Second Harmonic
Third Harmonic
Crosstalk, Output to Output
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Conditions
Min
Typ
G = +1, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p
G = +2, VO = 2 V p-p
–13 V to +13 V Input
–6.5 V to +6.5 V Input, G = +2
G = +2, VO = 4 V Step
G = +2, VO = 2 V Step
G = +2, VO = 10 V Step
65
80
30
21
100
100
80
90
225
MHz
MHz
MHz
ns
ns
V/µs
ns
ns
–80
–82
–70
–82
–86
11
0.7
dBc
dBc
dBc
dBc
dB
nV/√Hz
fA/√Hz
55
fC = 1 MHz, VO = 2 V p-p
RL = 500 Ω
RL = 1 kΩ
RL = 500 Ω
RL = 1 kΩ
f = 1 MHz, G = +2
f = 100 kHz
f = 100 kHz
VCM = 0 V
TMIN – TMAX
1
Input Offset Voltage Match
Input Offset Voltage Drift
Input Bias Current
Open-Loop Gain
INPUT CHARACTERISTICS
Common-Mode Input Impedance
Differential Input Impedance
Input Common-Mode Voltage Range
FET Input Range
Usable Input Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Short Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio
TMIN – TMAX
VO = ± 8 V
88
VCM = ± 5 V
–92
± 11.52
30% Overshoot; G = +1
4
2
50
96
–85
2.0
3.5
2.5
24
12
Unit
mV
mV
mV
µV/oC
pA
pA
dB
1000||2.3
1000||1.7
GΩ||pF
GΩ||pF
–12.0 to +9.0
–12.0 to +12.0
–100
V
V
dB
± 11.84
60
35
V
mA
pF
5
VS = ± 2 V
Max
3.3
–100
24
3.5
V
mA
dB
Specifications subject to change without notice.
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . See Figure 2
Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . 26.4 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . 1.4 V
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +125°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
–4–
REV. B
AD8033/AD8034
MAXIMUM POWER DISSIPATION
2.0
MAXIMUM POWER DISSIPATION – W
The maximum safe power dissipation in the AD8033/AD8034
packages is limited by the associated rise in junction temperature
(TJ) on the die. The plastic that encapsulates the die will locally
reach the junction temperature. At approximately 150°C, which is
the glass transition temperature, the plastic will change its properties. Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, permanently shifting
the parametric performance of the AD8033/AD8034. Exceeding a
junction temperature of 175°C for an extended period of time can
result in changes in silicon devices, potentially causing failure.
The still-air thermal properties of the package and PCB (JA),
ambient temperature (TA), and the total power dissipated in the
package (PD) determine the junction temperature of the die.
The junction temperature can be calculated as follows
SOT-23-8
SOIC-8
1.0
SC70-5
0.5
0.0
–60
–40
–20
0
20
40
60
80
100
AMBIENT TEMPERATURE – C
TJ = TA + (PD × θ JA )
Figure 2. Maximum Power Dissipation vs.
Temperature for a Four-Layer Board
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the package
due to the load drive for all outputs. The quiescent power is the
voltage between the supply pins (VS) times the quiescent current (IS).
Assuming the load (RL) is referenced to midsupply, then the total
drive power is VS/2 IOUT, some of which is dissipated in the
package and some in the load (VOUT IOUT). The difference
between the total drive power and the load power is the drive
power dissipated in the package:
Airflow will increase heat dissipation, effectively reducing JA.
Also, more metal directly in contact with the package leads from
metal traces, through holes, ground, and power planes will reduce
the JA. Care must be taken to minimize parasitic capacitances at
the input leads of high speed op amps as discussed in the Layout,
Grounding, and Bypassing Considerations section.
PD = Quiescent Power + (Total Drive Power – Load Power )
[
1.5
]
[
PD = [VS × I S ] + (VS / 2) × (VOUT / RL ) – VOUT / RL
2
Figure 2 shows the maximum safe power dissipation in the
package versus the ambient temperature for the SOIC-8 (125°C/W),
SC70 (210°C/W), and SOT-23-8 (160°C/W) packages on a JEDEC
standard 4-layer board. JA values are approximations.
]
RMS output voltages should be considered. If RL is referenced
to VS–, as in single-supply operation, then the total drive power
is VS IOUT.
OUTPUT SHORT CIRCUIT
Shorting the output to ground or drawing excessive current for
the AD8033/AD8034 will likely cause catastrophic failure.
If the rms signal levels are indeterminate, consider the worst
case, when VOUT = VS /4 for RL to midsupply:
PD = (VS × IS ) + (VS / 4) / RL
2
In single-supply operation with RL referenced to VS–, worst case
is VOUT = VS /2.
ORDERING GUIDE
Model
AD8033AR
AD8033AR-REEL
AD8033AR-REEL7
AD8033AKS-REEL
AD8033AKS-REEL7
AD8034AR
AD8034AR-REEL7
AD8034AR-REEL
AD8034ART-REEL
AD8034ART -REEL7
Temperature Range
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
Package
Description
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
5-Lead SC70
5-Lead SC70
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOT-23
8-Lead SOT-23
Package Outline
R-8
R-8
R-8
KS-5
KS-5
R-8
R-8
R-8
RT-8
RT-8
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8033/AD8034 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. B
–5–
Branding
Information
H3B
H3B
HZA
HZA
WARNING!
ESD SENSITIVE DEVICE
AD8033/AD8034–Typical Performance Characteristics
Default Conditions: ⴞ5 V, CL = 5 pF, RL = 1 k⍀, Temperature = 25ⴗC
24
8
G = +10
VO = 200mV p-p
21
G = +2
7
18
G = +5
GAIN – dB
GAIN – dB
12
9
VOUT = 0.2V p-p
6
15
G = +2
6
5
VOUT = 1V p-p
4
3
3
G = +1
0
VOUT = 4V p-p
2
–3
G = –1
1
–6
–9
0.01
VOUT = 2V p-p
0
1.0
10
FREQUENCY – MHz
100
0.1
1000
TPC 1. Small Signal Frequency Response for
Various Gains
1
10
FREQUENCY – MHz
100
TPC 4. Frequency Response for Various Output
Amplitudes (See Test Circuit 2)
1
8
VS = +5V
7
0
VS = ⴞ5V
VS = ⴞ12V
–2
GAIN – dB
GAIN – dB
–1
VS = +5V
6
–3
5
VS = ⴞ5V
4
3
–4
2
–5
–6
0
0.1
1
10
FREQUENCY – MHz
100
TPC 2. Small Signal Frequency Response for
Various Supplies (See Test Circuit 1)
VS = ⴞ12V
G = +2
VO = 200mV p-p
1
G = +1
VO = 200mV p-p
0.1
1
10
FREQUENCY – MHz
TPC 5. Small Signal Frequency Response for
Various Supplies (See Test Circuit 2)
7
2
VS = ⴞ12V
G = +1
1
6
VOUT = 2V p-p
VS = ⴞ12V
0
GAIN – dB
GAIN – dB
VS = ⴞ5V
VS = +5V
5
VS = ⴞ5V
–1
VS = +5V
–2
–3
4
3
2
–4
1
–5
–6
0.1
100
1
10
FREQUENCY – MHz
G = +2
VO = 2V p-p
0
0.1
100
1
10
100
FREQUENCY – MHz
TPC 3. Large Signal Frequency Response for
Various Supplies (See Test Circuit 1)
TPC 6. Large Signal Frequency Response for
Various Supplies (See Test Circuit 2)
–6–
REV. B
AD8033/AD8034
10
8
VO = 200mV p-p
6
CL = 100pF
CL = 100pF
9
G = +1
8
CL = 100pF
RSNUB = 25⍀
2
GAIN – dB
CL = 51pF
7
GAIN – dB
4
0
CL = 33pF
6
5
CL = 33pF
4
CL = 2pF
3
–2
G = +2
CL = 2pF
2
–4
VO = 200mV p-p
1
0
0.1
–6
0.1
1
10
FREQUENCY – MHz
100
TPC 7. Small Signal Frequency Response for
Various CLOAD (See Test Circuit 1)
100
TPC 10. Small Signal Frequency Response for
Various CLOAD (See Test Circuit 2)
9
8
CF = 0pF
8
1
10
FREQUENCY – MHz
7
CF = 1pF
VO = 200mV p-p
G = +2
RL = 1k⍀
7
6
CF = 1.5pF
5
GAIN – dB
GAIN – dB
6
CF = 2pF
4
RL = 500⍀
4
3
3
2
2
VO = 200mV p-p
RF = 3k⍀
G = +2
1
0
5
0.1
1
1
10
FREQUENCY – MHz
0
0.1
100
TPC 8. Small Signal Frequency Response for
Various RF/CF (See Test Circuit 2)
100
1
10
FREQUENCY – MHz
100
TPC 11. Small Signal Frequency Response for
Various RLOAD (See Test Circuit 2)
100
180
VO = 200mV p-p
VS = ⴞ12V
80
150
G = +2
1
G = +1
120
40
90
PHASE
20
60
0
30
0.1
0.01
100
1k
10k
100k
1M
10M
–20
100
100M
FREQUENCY – Hz
TPC 9. Output Impedance vs. Frequency
(See Test Circuits 4 and 7)
REV. B
1k
10k
100k
1M
FREQUENCY – Hz
10M
TPC 12. Open-Loop Response
–7–
0
100M
PHASE – Degrees
GAIN
60
GAIN – dB
IMPEDANCE – ⍀
10
AD8033/AD8034
–40
–40
HD3 RL = 500⍀
–50
–50
–60
–60
–70
–70
–80
DISTORTION – dBc
DISTORTION – dBc
G = +2
HD3 RL = 1k⍀
–90
HD2 RL = 500⍀
–100
–110
HD2 G = +1
–80
HD3 G = +2
–90
HD2 G = +2
–100
–110
HD3 G = +1
HD2 RL = 1k⍀
–120
0.1
1
–120
0.1
5
1
FREQUENCY – MHz
FREQUENCY – MHz
TPC 13. Harmonic Distortion vs. Frequency for
Various Loads (See Test Circuit 2)
5
TPC 16. Harmonic Distortion vs. Frequency for
Various Gains
–20
–40
G = +2
HD3 VS = 5V
–50
–30
HD2 VO = 20V p-p
HD3 VO = 10V p-p
–40
–50
DISTORTION – dBc
DISTORTION – dBc
–60
–70
–80
HD2 VS = 5V
HD3 VS = 24V
–90
–100
HD3 VO = 20V p-p
–60
–70
HD2 VO = 10V p-p
–80
HD3 VO = 2V p-p
–90
–100
–110
HD2 VS = 24V
–120
0.1
–110
1
FREQUENCY – MHz
HD2 VO = 2V p-p
–120
0.1
5
1
FREQUENCY – MHz
5
TPC 17. Harmonic Distortion vs. Frequency for
Various Amplitudes (See Test Circuit 2), VS = 24 V
TPC 14. Harmonic Distortion vs. Frequency for
Various Supply Voltages (See Test Circuit 2)
80
1000
VS = +5V POSITIVE SIDE
PERCENT OVERSHOOT
NOISE – nV/ Hz
70
100
60
VS = +5V NEGATIVE SIDE
50
40
VS = ⴞ5V NEGATIVE SIDE
30
20
VS = ⴞ5V POSITIVE SIDE
10
10
10
100
1k
10k
100k
1M
10M
0
10
100M
FREQUENCY – Hz
30
50
70
CAP LOAD – pF
90
110
TPC 18. Capacitive Load vs. Percent Overshoot
G = +1 (See Test Circuit 1)
TPC 15. Voltage Noise
–8–
REV. B
AD8033/AD8034
G = +1
G = +1
38pF
80mV/DIV
20ns/DIV
25mV/DIV
VO = 20V p-p
VO = 20V p-p
VO = 8V p-p
VO = 8V p-p
VO = 2V p-p
VO = 2V p-p
320ns/DIV
TPC 23. Large Signal Transient Response G = +2
(See Test Circuit 2)
G = +1
G = –1
VIN
VOUT
VOUT
350ns/DIV
1.5V/DIV
VIN
350ns/DIV
TPC 24. Input Overdrive Recovery (See Test Circuit 1)
TPC 21. Output Overdrive Recovery (See Test Circuit 3)
REV. B
320ns/DIV
3V/DIV
TPC 20. Large Signal Transient Response G = +1
(See Test Circuit 1)
1.5V/DIV
80ns/DIV
TPC 22. Small Signal Transient Response ± 5 V
(See Test Circuit 1)
TPC 19. Small Signal Transient Response 5 V
(See Test Circuit 1)
3V/DIV
15pF
–9–
AD8033/AD8034
VIN = 1V
VIN = 1V
VOUT – 2VIN
+0.1%
+0.1%
VOUT – 2VIN
–0.1%
t=0
t=0
1.5␮s/DIV
2mV/DIV
20ns/DIV
2mV/DIV
TPC 25. Long-Term Settling Time
TPC 28. 0.1% Short-Term Settling Time
0
7.0
6.9
–5
6.8
QUIESCENT CURRENT – mA
–10
–Ib
Ib – pA
–15
–20
+Ib
–25
–30
–35
VS = ⴞ12V
6.7
6.6
6.5
VS = ⴞ5V
6.4
6.3
VS = +5V
6.2
6.1
6.0
–40
20
25
30
35
40
45 50 55 60
65
TEMPERATURE – ⴗC
70
75
80
5.9
–40
85
–20
0
20
40
TEMPERATURE – ⴗC
60
80
TPC 29. Quiescent Supply Current vs. Temperature for Various Supply Voltages
TPC 26. Ib vs. Temperature
42
–0.1%
BJT INPUT RANGE
4.0
36
–Ib
24
18
NORMALIZED OFFSET – mV
Ib = ␮A
30
3.5
+Ib
12
6
0
Ib – pA
FET INPUT RANGE
10
5
0
–5
–10
–15
–20
–25
–30
–12 –10
+Ib
–Ib
VS = ⴞ12V
3.0
2.5
2.0
1.5
1.0
VS = ⴞ5V
.50
VS = +5V
0
–.50
–8
–6
–4
–2
0
2
4
6
8
10
–1.0
–14 –12 –10 –8
12
COMMON-MODE VOLTAGE – V
TPC 27. Input Bias Current vs. Common-Mode
Voltage Range
–6 –4 –2 0
2
4
6
8
COMMON-MODE VOLTAGE – V
10
12
14
TPC 30. Input Offset Voltage vs. CommonMode Voltage
–10–
REV. B
AD8033/AD8034
–20
105
100
–30
OPEN-LOOP GAIN – dB
95
CMRR – dB
–40
–50
–60
90
RL = 500⍀
85
RL = 1k⍀
RL = 2k⍀
80
75
70
–70
65
–80
0.1
1
10
FREQUENCY – MHz
60
–12 –10
50
TPC 31. CMRR vs. Frequency (See Test Circuit 7)
–4 –2
0
2
4
OUTPUT VOLTAGE – V
6
8
10
12
–40
–50
0.8
SOT-23 A/B
VCC Ð VOH
CROSSTALK – dB
OUTPUT SATURATION – V
–6
TPC 34. Open-Loop Gain vs. Output Voltage for
Various RLOAD
1.0
0.6
0.4
VOL Ð VEE
–60
SOIC A/B
–70
SOT-23 B/A
SOIC B/A
–80
0.2
0
–8
–90
0
5
10
15
20
25
–100
0.1
30
1
FREQUENCY – MHz
ILOAD – mA
10
50
TPC 35. Crosstalk (See Test Circuit 9)
TPC 32. Output Saturation Voltage vs. Load Current
180
0
–10
150
–20
–30
FREQUENCY
PSRR – dB
–PSRR
–40
–50
–60
+PSRR
120
90
60
–70
–80
30
–90
–100
0.0001
0
0.001
0.01
0.1
1
FREQUENCY – MHz
10
–1.5
100
–0.5
0
0.5
VOS – mV
TPC 36. Initial Offset
TPC 33. PSRR vs. Frequency (See Test Circuits 6 and 8)
REV. B
–1.0
–11–
1.0
1.5
AD8033/AD8034
VOUT
VOUT
1.2V/DIV
VIN
1.2V/DIV
1␮s/DIV
VIN
TPC 37. G = +1 Response VS = ± 5 V
1␮s/DIV
TPC 38. G = +2 Response VS = ± 5 V
Test Circuits
CF
1k⍀
1k⍀
RF
VCC
VCC
1␮F
1␮F
+
+
10nF
10nF
RSNUB
VIN
AD8033/AD8034
49.9⍀
RSNUB
976⍀
VOUT
CLOAD
VIN
49.9⍀
499⍀
49.9⍀
10nF
49.9⍀
10nF
VEE
VEE
Test Circuit 2. G = +2
Test Circuit 1. G = +1
1k⍀
VOUT
CLOAD
+
1␮F
+
1␮F
VIN
976⍀
AD8033/AD8034
1k⍀
1k⍀
VCC
VCC
VCC
1␮F
+
10nF
1k⍀
1␮F
1␮F
+
+
10nF
10nF
976⍀
VOUT
AD8033/AD8034
499⍀
10nF
10nF
VSINE
0.2V p-p
+
1␮F
VEE
Test Circuit 3. G = –1
AD8033/AD8034
AD8033/AD8034
49.9⍀
+
–
+
1␮F
10nF
VSINE
0.2V p-p
+
–
+
1␮F
VEE
VEE
Test Circuit 4. Output Impedance
G = +1
–12–
Test Circuit 5. Output Impedance
G = +2
REV. B
AD8033/AD8034
–
+
1V p-p
VCC
VCC
VCC AC
1␮F
+
49.9⍀
10nF
VOUT
VOUT
AD8033/AD8034
AD8033/AD8034
10nF
+
1␮F
1V p-p
–
+
VEE
VEE AC
49.9⍀
VEE
Test Circuit 6. Positive PSRR
1k⍀
Test Circuit 8. Negative PSRR
1k⍀
1k⍀
1k⍀
VCC
VEE
1␮F
VIN
–
+
49.9⍀
10nF
976⍀
1k⍀
AD8033/AD8034
1k⍀
VIN
TO PORT 1 499⍀
+
50⍀
+ B
–
VOUT
1k⍀
VCC
49.9⍀
VEE
+
10nF
499⍀
TO PORT 2
1k⍀
+
1␮F
A
–
VCC
VEE
1k⍀
Test Circuit 7. CMRR
REV. B
Test Circuit 9. Crosstalk
–13–
1k⍀
AD8033/AD8034
THEORY OF OPERATION
The incorporation of JFET devices into Analog Devices’ high
voltage XFCB process has given the performance ability to
design the AD8033/AD8034. The AD8033/AD8034 are voltage
feedback rail-to-rail output amplifiers with FET inputs and a
bipolar-enhanced common-mode input range. The use of JFET
devices in high speed amplifiers extends the application space
into both low input bias current as well as low distortion high
bandwidth areas.
Using N-channel JFETs and a folded cascade input topology, the
common-mode input level operates from 0.2 V below the negative
rail to within 3.0 V of the positive rail. Cascading of the input stage
ensures low input bias current over the entire common-mode range
as well as CMRR and PSRR specifications that are above 90 dB.
Additionally, long-term settling issues that normally occur with
high supply voltages are minimized as a result of the cascading.
Output Stage Drive and Capacitive Load Drive
The common emitter output stage adds rail-to-rail output performance and is compensated to drive 35 pF (30% overshoot G = +1).
Additional capacitance can be driven if a small snub resistor is
put in series with the capacitive load, effectively decoupling the
load from the output stage, as shown in TPC 7. The output
stage can source and sink 20 mA of current within 500 mV of the
supply rails and 1 mA within 100 mV of the supply rails.
bipolar pair Q25 and Q27. With this configuration, the inputs
can be driven beyond the positive supply rail without any phase
inversion (see Figure 3).
As a result of entering the bipolar mode of operation, an offset and
input bias current shift will occur. See TPCs 27 and 30. After
re-entering the JFET common-mode range, the amplifier will
recover in approximately 100 ns (refer to TPC 24 for input
overload behavior). Above and below the supply rails, ESD protection diodes activate, resulting in an exponentially increasing
input bias current. If the inputs are to be driven well beyond the
rails, series input resistance should be included to limit the input
bias current to less than 10 mA.
Input Impedance
The input capacitance of the AD8033/AD8034 will form a pole
with the feedback network, resulting in peaking and ringing in the
overall response. The equivalent impedance of the feedback
network should be kept small enough to ensure that the parasitic
pole falls well beyond the –3 dB bandwidth of the gain configuration being used. If larger impedance values are desired, the
amplifier can be compensated by placing a small capacitor in
parallel with the feedback resistor. TPC 8 shows the improvement
in frequency response by including a small feedback capacitor
with high feedback resistance values.
Thermal Considerations
Because the AD8034 operates at up to ±12 V supplies in the small
SOT-23-8 package (160°C/W), power dissipation can easily exceed
package limitations, resulting in permanent shifts in device
characteristics and even failure. Likewise, high supply voltages can
cause an increase in junction temperature even with light loads,
resulting in an input bias current and offset drift penalty. The input
bias current will double for every 10°C shown in TPC 26. Refer
to the Maximum Power Dissipation section for an estimation of
die temperature based on load and supply voltage.
Input Overdrive
An additional feature of the AD8033/AD8034 is a bipolar
input pair that adds rail-to-rail common-mode input performance specifically for applications that cannot tolerate phase
inversion problems.
Under normal common-mode operation, the bipolar input pair
is kept reversed, maintaining Ib at less than 1 pA. When the
input common mode comes within 3.0 V of the positive supply
rail, I1 turns off and I4 turns on, supplying tail current to the
+VS
R3
I2
R2
V2
+
V4
–
Q4
–
Q1
Q13
Q7
Q6
VTH
+
Q14
R14
–IN
J1
D4
Q25
J2
Q27
+IN
VCC
VOUT
D5
Q11
Q9
Q29
I1
R7
I4
I3
Q28
R8
–VS
Figure 3. Simplified AD8033/AD8034 Input Stage
–14–
REV. B
AD8033/AD8034
LAYOUT, GROUNDING, AND BYPASSING
CONSIDERATIONS
Bypassing
Power supply pins are actually inputs, and care must be taken
so that a noise-free stable dc voltage is applied. The purpose of
bypass capacitors is to create low impedances from the supply to
ground at all frequencies, thereby shunting or filtering a majority
of the noise. Decoupling schemes are designed to minimize the
bypassing impedance at all frequencies with a parallel combination
of capacitors. 0.01 µF or 0.001 µF (X7R or NPO) chip capacitors
are critical and should be placed as close as possible to the
amplifier package. Larger chip capacitors, such as the 0.1 µF
capacitor, can be shared among a few closely spaced active
components in the same signal path. The 10 µF tantalum capacitor
is less critical for high frequency bypassing, and in most cases,
only one per board is needed at the supply inputs.
Grounding
A ground plane layer is important in densely packed PC boards in
order to spread the current, thereby minimizing parasitic inductances. However, an understanding of where the current flows in
a circuit is critical to implementing effective high speed circuit
design. The length of the current path is directly proportional to
the magnitude of the parasitic inductances, and thus the high
frequency impedance of the path. High speed currents in an
inductive ground return will create unwanted voltage noise. The
length of the high frequency bypass capacitor leads is most critical.
A parasitic inductance in the bypass grounding will work against
the low impedance created by the bypass capacitor. Place the
ground leads of the bypass capacitors at the same physical location.
Because load currents flow from the supplies as well, the ground
for the load impedance should be at the same physical location
as the bypass capacitor grounds. For the larger value capacitors
that are intended to be effective at lower frequencies, the current
return path distance is less critical.
leads that are driven to the same voltage potential as the inputs.
This way there is no voltage potential between the inputs and
surrounding area to set up any leakage currents. For the guard ring
to be completely effective, it must be driven by a relatively low
impedance source and should completely surround the input
leads on all sides, above, and below using a multilayer board.
Another effect that can cause leakage currents is the charge
absorption of the insulator material itself. Minimizing the amount
of material between the input leads and the guard ring will help
to reduce the absorption. Also, low absorption materials such as
Teflon® or ceramic may be necessary in some instances.
Input Capacitance
Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground.
A few pF of capacitance will reduce the input impedance at high
frequencies, in turn increasing the amplifiers’ gain and causing
peaking of the overall response or even oscillations if severe
enough. It is recommended that the external passive components
that are connected to the input pins be placed as close as possible
to the inputs to avoid parasitic capacitance. The ground and power
planes must be kept at a distance of at least 0.05 mm from the
input pins on all layers of the board.
APPLICATIONS
High Speed Peak Detector
The low input bias current and high bandwidth of the AD8033/
AD8034 make the parts ideal for a fast settling, low leakage peak
detector. The classic fast-low leakage topology with a diode in
the output is limited to 1.4 V p-p max in the case of the
AD8033/AD8034 because of the protection diodes across the
inputs, as depicted in Figure 4.
Leakage Currents
Poor PC board layout, contaminants, and the board insulator
material can create leakage currents that are much larger than the
input bias currents of the AD8033/AD8034. Any voltage differential
between the inputs and nearby runs will set up leakage currents
through the PC board insulator, for example, 1 V/100 GΩ = 10 pA.
Similarly, any contaminants on the board can create significant
leakage (skin oils are a common problem). To significantly reduce
leakages, put a guard ring (shield) around the inputs and input
REV. B
AD8033/
AD8034
VOUT
VIN
~1.4V p-p MAX
Figure 4. High Speed Peak Detector with Limited Input Range
–15–
AD8033/AD8034
Using the AD8033/AD8034, a unity gain peak detector can be
constructed that will capture a 300 ns pulse while still taking
advantage of the AD8033/AD8034’s low input bias current and
wide common-mode input range, as shown in Figure 5.
INPUT
Using two amplifiers, the difference between the peak and the
current input level is forced across R2 instead of either amplifier’s
input pins. In the event of a rising pulse, the first amplifier
compensates for the drop across D2 and D3, forcing the voltage at
Node 3 equal to Node 1. D1 is off and the voltage drop across R2
is zero. Capacitor C3 speeds up the loop by providing the charge
required by the first amplifier’s input capacitance, helping to
maintain a minimal voltage drop across R2 in the sampling mode.
A negative going edge results in D2 and D3 turning off and D1
turning on, closing the loop around the first amplifier and forcing
VOUT – VIN across R2. R4 makes the voltage across D2 zero,
minimizing leakage current and kickback from D3 from affecting
the voltage across C2.
OUTPUT
1.00V/DIV
100nS/DIV
Figure 6. Peak Detector Response 4 V 300 ns Pulse
Figure 6 shows the peak detector in Figure 5 capturing a 300 ns
4 V pulse with 10 mV of kickback and a droop rate of 5 V/s. For
larger peak-peak pulses, the time constants of R1, C1 and R3, C3
should be increased to reduce overshoot. The best droop rate will
occur by isolating parasitic resistances from Node 3. This can be
accomplished using a guard band connected to the output of the
second amplifier that surrounds its summing junction (Node 3).
The rate of the incoming edge must be limited so that the output
of the first amplifier does not overshoot the peak value of VIN
before the second amplifier’s output can provide negative feedback
at the first amplifier’s summing junction. This is accomplished
with the combination of R1 and C1, which allows the voltage at
Node 1 to settle to 0.1% of VIN in 270 ns. The selection of C2
and R3 is made by considering droop rate, settling time, and
kickback. R3 prevents overshoot from occurring at Node 3. The
time constants of R1, C1 and R3, C2 are roughly equal to achieve
the best performance. Slower time constants can be selected by
increasing C2 to minimize droop rate and kickback at the cost
of increased settling time. R1 and C1 should also be increased
to match, reducing the incoming pulse’s effect on kickback.
Increasing both time constants by a factor of 3 permits a larger
peak pulse to be captured and increases the output accuracy.
C3
10pF
R2
1k⍀
LS4148
D1
C4
4.7pF
R4
6k⍀
+VS
1/2
+VS
VIN
D3
1/2
R1
1k⍀
VOUT
AD8034
LS4148
R5
49.9⍀
AD8034
D2
–VS
C1
–VS
LS4148
C2
39pF/
120pF
180pF/560pF
R3
200⍀
Figure 5. High Speed Unity Gain Peak Detector Using AD8034
–16–
REV. B
AD8033/AD8034
0
–10
INPUT
–20
OUTPUT
REF LEVEL – dB
–30
–40
–50
–60
–70
–80
1.00V/DIV
200nS/DIV
–90
Figure 7. Peak Detector Response 5 V 1 µ s Pulse
–100
10k
Figure 7 shows a 5 V peak pulse being captured in 1 s with less
than 1 mV of kickback. With this selection of time constants, up
to a 20 V peak pulse can be captured with no overshoot.
Active Filters
The response of an active filter varies greatly depending on the
performance of the active device. Open-loop bandwidth and gain,
along with the order of the filter, will determine stop-band
attenuation as well as the maximum cutoff frequency, while input
capacitance can set a limit on which passive components are used.
Topologies for active filters are varied, and some are more
dependent on the performance of the active device than others.
The Sallen-Key topology is the least dependent on the active
device, requiring that the bandwidth be flat to beyond the stopband frequency since it is used simply as a gain block. In the
case of high Q filter stages, the peaking must not exceed the
open-loop bandwidth and linear input range of the amplifier.
Using an AD8033/AD8034, a four-pole cascaded Sallen-Key
filter can be constructed with fC = 1 MHz and over 80 dB of
stop-band attenuation, as shown in Figure 8.
1M
100k
Figure 9. Four-Pole Cascade Sallen-Key Filter Response
The common-mode input capacitance should be considered
in the component selection.
Filter cutoff frequencies can be increased beyond 1 MHz using
the AD8033/AD8034, but limited open-loop gain and input
impedance begin to interfere with the higher Q stages. This can
cause early roll-off of the overall response.
Additionally, the stop-band attenuation will decrease with
decreasing open-loop gain.
Keeping these limitations in mind, a two-pole Sallen-Key
Butterworth filter with fC = 4 MHz can be constructed that
has a relatively low Q of 0.707 while still maintaining 15 dB
of attenuation an octave above fC and 35 dB of stop-band
attenuation. The filter and response are shown in Figures 10
and 11, respectively.
C3
22pF
C3
33pF
R1
4.22k⍀
VIN
+VS
R2
6.49k⍀
R5
49.9⍀
10M
FREQUENCY – Hz
VIN
1/2
+VS
R1
2.49k⍀
R2
2.49k⍀
VOUT
–VS
C1
10pF
R5
49.9⍀
AD8034
AD8033
–VS
C1
27pF
Figure 10. Two-Pole Butterworth Active Filter
5
0
–5
C4
82pF
1/2
R3
4.99k⍀
AD8034
C2
10pF
–10
VOUT
GAIN – dB
R4
4.99k⍀
+VS
–VS
–15
–20
–25
–30
Figure 8. Four-Pole Cascade Sallen-Key Filter
–35
Component values are selected using a normalized cascaded
two-stage Butterworth filter table and Sallen-Key two-pole
active filter equations. The overall frequency response is shown
in Figure 9.
–40
–45
100k
1M
10M
100M
FREQUENCY – Hz
Figure 11. Two-Pole Butterworth Active Filter Response
REV. B
–17–
AD8033/AD8034
is eventually rolled off by the decreasing loop gain of the
amplifier. Keeping the input terminal impedances matched is
recommended to eliminate common-mode noise peaking
effects that will add to the output noise.
Wideband Photodiode Preamp
Figure 12 shows an I/V converter with an electrical model of a
photodiode.
The basic transfer function is
VOUT
Integrating the square of the output voltage noise spectral density
over frequency and then taking the square root results in the
total rms output noise of the preamp.
I
× RF
= PHOTO
1 + sCF RF
where IPHOTO is the output current of the photodiode, and the
parallel combination of RF and CF sets the signal bandwidth.
CF
The stable bandwidth attainable with this preamp is a function
of RF, the gain bandwidth product of the amplifier, and the total
capacitance at the amplifier’s summing junction, including CS
and the amplifier input capacitance. RF and the total capacitance produce a pole in the amplifier’s loop transmission that can
result in peaking and instability. Adding CF creates a zero in the
loop transmission that compensates for the pole’s effect and
reduces the signal bandwidth. It can be shown that the signal
bandwidth resulting in a 45° phase margin (f(45)) is defined by the
expression
f( 45 ) =
RF
RSH = 1011⍀
IPHOTO
CD
CM
CS
VO
CM
CF + CS
VB
fCR
2π × RF × CS
RF
Figure 12. Wideband Photodiode Preamp
fCR is the amplifier crossover frequency.
f1 =
CS is the total capacitance at the amplifier summing junction
(amplifier + photodiode + board parasitics).
f2 =
The value of CF that produces f(45) can be shown to be
CF =
CS
2π × RF × fCR
The frequency response in this case will show about 2 dB of
peaking and 15% overshoot. Doubling CF and cutting the
bandwidth in half will result in a flat frequency response, with
about 5% transient overshoot.
VOLTAGE NOISE – nV/ Hz
RF is the feedback resistor.
f3 =
1
2␲RF (CF + CS + CM + 2CD)
1
2␲RFCF
fCR
(CS + CM + 2CD + CF ) /CF
RF NOISE
f2
VEN (CF + CS + CM + 2CD) /CF
f3
f1
The preamp’s output noise over frequency is shown in Figure 13.
VEN
The pole in the loop transmission translates to a zero in the
amplifier’s noise gain, leading to an amplification of the input
voltage noise over frequency. The loop transmission zero
introduced by CF limits the amplification. The noise gain’s
bandwidth extends past the preamp signal bandwidth and
NOISE DUE TO AMPLIFIER
FREQUENCY – Hz
Figure 13. Photodiode Voltage Noise Contributions
–18–
REV. B
AD8033/AD8034
OUTLINE DIMENSIONS
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-8)
8-Lead Small Outline Transistor Package [SOT-23]
(RT-8)
Dimensions shown in millimeters
Dimensions shown in millimeters and (inches)
2.90 BSC
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
8
5
1
4
8
7
6
5
1
2
3
4
1.60 BSC
6.20 (0.2440)
5.80 (0.2284)
2.80 BSC
PIN 1
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
SEATING
0.10
PLANE
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.33 (0.0130)
0.65 BSC
0.50 (0.0196)
ⴛ 45ⴗ
0.25 (0.0099)
1.95
BSC
1.30
1.15
0.90
8ⴗ
0.25 (0.0098) 0ⴗ 1.27 (0.0500)
0.41 (0.0160)
0.19 (0.0075)
1.45 MAX
0.15 MAX
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
0.38
0.22
SEATING
PLANE
Dimensions shown in millimeters
2.00 BSC
4
1.25 BSC
2.10 BSC
1
2
3
PIN 1
0.65 BSC
1.00
0.90
0.70
0.10 MAX
1.10 MAX
0.22
0.08
0.30
0.15
0.10 COPLANARITY
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-203AA
REV. B
10ⴗ
0ⴗ
COMPLIANT TO JEDEC STANDARDS MO-178BA
5-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-5)
5
0.22
0.08
–19–
0.46
0.36
0.26
0.60
0.45
0.30
AD8033/AD8034
Revision History
Location
Page
2/03—Data Sheet changed from REV. A to REV. B.
Changes to CONNECTION DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Replaced TPC 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Changes to TPC 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
C02924–0–2/03(B)
Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to Test Circuit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8/02—Data Sheet changed from REV. 0 to REV. A.
Added AD8033 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
VOUT = 2 V p-p deleted from Default Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Added SOIC-8 (R) and SC70 (KS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to GENERAL DESCRIPTION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
New Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edits to MAXIMUM POWER DISSIPATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Change to TPC 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Change to TPC 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Change to TPC 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
New TPC 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
New TPC 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
New TPC 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
New TPC 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
New Test Circuit 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PRINTED IN U.S.A.
SC70 (KS) package added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
–20–
REV. B