APL5339 Source and Sink, 2A, Fast Transient Response Linear Regulator Features General Description • The APL5339 linear regulator is designed to provide a regulated voltage with bi-direction output current for DDR- Provide Bi-direction Currents - Sourcing or Sinking Current Up to 2A • • • • • SDRAM termination voltage. The APL5339 integrates two power transistors to source or sink load current up to 2A. Built-in Soft-Start Power-On-Reset Monitoring on VCNTL Pins It also features internal soft-start, current-limit, thermal shutdown and enable control functions into a single chip. Fast Transient Resoponse Stable with Ceramic Output Capacitors The internal soft-start controls the rising rate of the output voltage to prevent inrush current during start-up. The cur- +10mV High System Output Accuracy Over Load and Temperature Ranges • • • • • • rent-limit circuit detects the output current and limits the current during short-circuit or current overload conditions. Adjustable Output Voltage by External Resistors The on-chip thermal shutdown provides thermal protection against any combination of overload that would cre- Current-Limit Protection On-Chip Thermal Shutdown ate excessive junction temperatures. The output voltage of APL5339 is regulated to track the Shutdown for Standby or Suspend Mode Compact TDFN3x3-10 Package voltage on half voltage of VREF. An internal resistor divider is used to provide a half voltage of VREF for VOUT Lead Free and Green Devices Available (RoHS Compliant) Voltage. The VOUT output voltage is only requiring 10µF of ceramic output capacitance for stability and fast tran- Applications • • • • sient response. Pulling and holding the voltage on voltage of EN below DDRII/III/IV SDRAM Termination Voltage the enable voltage threshold shuts off the output. The APL5339 is available in TDFN3x3-10 package. Motherboard and VGA Card Power Supplies Setop Box Low Power DDRIII/IV Simplified Application Circuit VCNTL VCNTL VIN VIN VREF VOUT VOUT APL5339 EN Enable EN VOSNS GND ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2015 1 www.anpec.com.tw APL5339 Pin Configuration EN 1 10 VCNTL VOSNS 2 9 VREF VOUT 3 GND 8 VIN VOUT 4 7 VIN VOUT 5 6 VIN TDFN3X3-10 (Top View) = Exposed Pad (connected to ground plane for better heat dissipation) Ordering and Marking Information APL5339 Package Code QB : TDFN3x3-10 Assembly Material Handling Code Temperature Range Package Code APL5339 QB: APL 5339 XXXXX Operating Junction Temperature I : -40 to 85 o C Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device X - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol (Note 1) Rating Unit VCNTL Supply Voltage (VCNTL to GND) -0.3 ~ 7 V VIN Supply Voltage (VIN to GND) -0.3 ~ 4 V VREF Input Voltage (VREF to GND) -0.3 ~ 7 V VOSNS VOSNS Input Voltage (VOSNS to GND) -0.3 ~ 7 V VOUT VOUT Output Voltage (VOUT to GND) VEN EN to GND Voltage VCNTL VIN VREF TJ Parameter Junction Temperature TSTG Storage Temperature TSDR Maximum Lead Soldering Temperature (10 Seconds) -0.3 ~ VIN+0.3 V -0.3 ~ VCNTL+0.3 V 150 o -65 ~ 150 o 260 o C C C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2015 2 www.anpec.com.tw APL5339 Thermal Characteristics Symbol Parameter Junction-to-Ambient Resistance in Free Air θJA Typical Value Unit (Note 2) o TDFN3x3-10 C/W 60 Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions(Note 3) S ymbol VCNTL Pa ra mete r VCNTL Supp ly Volta ge (Note 4) V IN VIN Supp ly Voltage V REF VREF Input Vol tage VOUT VOUT Output Vo ltag e (VCNTL - VOU T > 2.3V for IOUT = 2A, TJ=25° C) IOUT VOUT Output Cu rrent C IN (No te 5 ) (Note 6) 3.0 ~ 5.5 V 1.0 ~ 3.6 V 0 ~ VIN V 0 .5 xVR EF ~ VIN – VDROP V -2 ~ +2 A 10 ~ 10 0 µF Equivalen t Ser ies Resisto r (E SR) o f Input Ca pacito r 0 ~ 2 00 mΩ Capacitance of O utp ut Multi-layer Ceramic Capacitor (ML CC) Total Output Capa ci tance TJ Unit Capa ci tan ce of Inp ut Capacitor COUT TA Range (Note 7) Ambient Tempe rature Jun ction Tempera tur e 8 ~ 47 µF 10 ~ 82 0 µF -40 ~ 85 o C -4 0 ~ 125 o C Note 3: Refer to the typical application circuit Note 4: The voltage of VCNTL must be higher than the voltage of VOUT pin. Note 5: The voltage of VREF should not be higher than the voltage of VIN when the regulator be enabled. Note 6: The symbol “+” means the VOUT sources current to load; the symbol “-” means the VOUT sinks current from load to GND. Note 7: It is necessary to use a multi-layer ceramic capacitor 8µF at least as an output capacitor. Please place the ceramic capacitor near VOUT pin as close as possible. Besides, the other kinds of capacitors (like Electrolytic, PoSCap, tantalum capacitors) can be used as the output capacitors in parallel. Electrical Characteristics Unless otherwise specified, these specifications apply over VCNTL=5V, VIN=1.8V, 1.5V or 1.35V, VREF=VIN, CIN=10µF, COUT=10µF (MLCC) and TA= -40 to 85 oC. Typical values are at TA=25oC. P arame ter APL5339 Symbol Unit Tes t Conditions Min Typ Max SUPPLY CURRENT ICN TL VCNTL Su pply Cur rent VEN =VC NTL , I OUT =0 A - 0 .5 1 mA I SD VCNTL Su pply Cur rent a t Shu tdown VEN =GND - 15 30 µA I VIN VIN Su pply Cu rrent at Shu tdo wn VEN =GND - - 1 µA VCNTL Rising 2.3 2 .6 2.9 V - 0.35 - V VIN Rising 0.4 0.6 0 .8 V - 0.2 - V POWER-ON-RES ET (POR) Risi ng VCNTL POR Th reshold VCNTL PO R Hysteresis Risi ng VIN PO R Threshold VIN POR Hystere sis Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2015 3 www.anpec.com.tw APL5339 Electrical Characteristics(Cont.) Unless otherwise specified, these specifications apply over VCNTL=5V, VIN=1.8V, 1.5V or 1.35V, VREF=VIN, CIN=10µF, COUT=10µF (MLCC) and TA= -40 to 85 oC. Typical values are at TA=25oC. P arame ter APL5339 Tes t Conditions Symbol Unit Min Typ Max - 0 .5 - V REF -10 - 10 mV - 22 - µA -1 00 - +100 nA - 12.5 - µA 0 .5 0.8 1.1 V - 0.1 - V - 3.5 - µA 0 .1 0.25 0.4 ms OUTPUT VOLTAGE V OUT VOUT O utput Voltage System A ccura cy Over Loa d, O ffse t and Tempera ture VOUT Discharg e Cur rent VC NTL=5V, VEN =0V, VOUT =0.1V VOSNS Inpu t Curren t VOSNS=VCNTL VREF In put Curre nt VR EF=5V ENABLE and INTERNAL SOFT-S TART V EN EN Logic In put Thresho ld I EN EN Pull-High Curr ent VC NTL=3V ~5.5V EN Hyste resis t SS In te rnal Soft-Start Interval VEN =GND o VR EF=1.8 V, V OUT =10% to 9 0%, T J=2 5 C DROPOUT VO LTAGES V DROP VIN-to-V OUT Dropo ut Voltage V CNTL=5 .0V, I OU T=2 A, V OUT =1.2 V o TJ=25 C o o TJ=-40 C ~12 5 C - 0.34 0.41 V - - 0.55 V PROTECTIONS o So urcing Curren t T J=25 C 2.6 3 .4 4.2 A 2.2 - - A T J=25 C -2.6 -3.4 -4.2 A T J=-40oC ~ 125 oC -2.2 - - - 170 - o C - o C o o T J=-40 C~125 C I LIM Curren t Limit L eve l o Sin king Cu rrent TSD Thermal Sh utdo wn Temper atu re T J r isin g Thermal Sh utd own Hyster esi s Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2015 - 4 50 A www.anpec.com.tw APL5339 Pin Description PIN FUNCTION NO. NAME 1 EN Active-high enable control pin. Applying and holding the voltage on this pin below the enable voltage threshold shuts down the output. When re-enabled, the IC undergoes a new soft-start process. When leave this pin open, an internal pull-up current (3µA typical) pulls the EN voltage and enables the regulator. 2 VOSNS Output voltage feedback pin. Connecting this pin to an external resistor divider receives the feedback voltage of the regulator. 3, 4, 5 VOUT Output pin of the regulator. Connect this pin to load and output capacitors (8µF at least) required for stability and improving transient response. The output voltage is regulated to track the reference voltage and capable of sourcing or sinking current up to 2A. During shutdown, the output voltage is discharged by an internal pull-low MOSFET. 6, 7, 8 VIN Main supply input pin for voltage conversions. A decoupling capacitor (≥10µF recommended) is usually connected near this pin to filter the voltage noise and improve transient response. The APL5339 sources current to VOUT pin by controlling the upper pass MOSFET, providing a current path from VIN pin. 9 VREF Reference voltage input for VOUT regulator. 10 VCNTL Bias voltage input pin for internal control circuitry. Connect this pin to a voltage source (+5V recommended). A decoupling capacitor (1µF typical) is usually connected near this pin to filter the voltage noise. The voltage at this pin is monitored for Power-On-Reset purpose. Exposed Pad GND Ground pin of the circuitry. Connect the exposed pad to the system ground plan with large copper area for dissipating heat into the ambient air. The APL5339 sinks current from VOUT pin by controlling the lower pass MOSFET, providing a current path to GND pin. Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2015 5 www.anpec.com.tw APL5339 Typical Operating Characteristics VCNTL Shutdown Current vs. Junction Temperature VCNTL Supply Current vs. Junction Temperature 30 700 VCNTL Shutdown Current, ISD (( A) VCNTL Supply Current, ICNTL (mA) VCNTL = 5V 650 600 550 500 450 400 350 VCNTL = 5V 25 20 15 10 5 300 -50 -25 0 25 75 50 100 -50 125 -25 4.2 TJ = 125°C VCNTL = 5V 3.8 Current-Limit, ILIM (A) Dropout Voltage, VDROP (mV) 125 4.0 TJ = 100°C 200 TJ = 25°C 150 TJ = - 40°C 100 Sinking Current 3.6 3.4 3.2 3.0 2.8 Sourcing Current 2.6 50 2.4 2.2 0 0 0.5 1 1.5 -50 2 -25 0 25 50 75 100 Output Current, IOUT (A) Junction Temperature, TJ ( C) Offset Voltage vs. Junction Temperature Offset Voltage vs. Junction Temperature 5 VCNTL = 5V VOUT = 0.75V 4 3 2 IOUT=-10mA 1 0 -1 -2 125 o Offset Voltage, VOFFSET (mV) Offset Voltage, VOFFSET (mV) 100 Current-Limit vs. Junction Temperature 250 4 75 Dropout Voltage vs. Output Current 300 5 50 Junction Temperature, TJ ( C) VCNTL = 5V VOUT = 1.05V 350 25 Junction Temperature, TJ (oC) o 400 0 IOUT=+10mA -3 -4 VCNTL = 3.3V VOUT = 0.75V 3 2 1 0 -1 IOUT=-10mA -2 IOUT=+10mA -3 -4 -5 -5 -50 -25 0 25 50 75 100 125 -50 o 0 25 50 75 100 125 o Junction Temperature, TJ ( C) Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2015 -25 Junction Temperature, TJ ( C) 6 www.anpec.com.tw APL5339 Typical Operating Characteristics (Cont.) Offset Voltage vs. Junction Temperature Offset Voltage vs. Junction Temperature Offset Voltage, VOFFSET (mV) 4 5 VCNTL = 5V VOUT = 0.675V 4 Offset Voltage, VOFFSET (mV) 5 3 2 IOUT=-10mA 1 0 -1 -2 -3 IOUT=+10mA VCNTL = 3.3V VOUT = 0.675V 3 2 IOUT=-10mA 1 0 -1 -2 IOUT=+10mA -3 -4 -4 -5 -5 -50 -25 0 25 50 75 100 -50 125 0 25 50 75 100 125 Junction Temperature, TJ ( C) Junction Temperature, TJ ( C) Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2015 -25 o o 7 www.anpec.com.tw APL5339 Operating Waveforms Refer to the typical application circuit. The test condition is VCNTL=5V, TA= 25oC unless otherwise specified. Power On Power Off V CNTL VCNTL 1 V IN 1 VIN 2 V REF 2 VREF 3 3 VOUT V OUT 4 4 VCNTL=5V, VIN=1.5V, IOUT =2A CH1: VCNTL, 2V/Div, DC CH2: VIN, 0.5V/Div, DC CH3: VREF, 0.5V/Div, DC CH4: VOUT , 0.2V/Div, DC TIME: 2ms/Div VCNTL=5V, VIN=1.5V, IOUT =2A CH1: VCNTL, 2V/Div, DC CH2: VIN, 0.5V/Div, DC CH3: VREF, 0.5V/Div, DC CH4: VOUT , 0.2V/Div, DC TIME: 500µs/Div Load Transient Response Load Transient Response VOUT VOUT 1 1 2 IOUT IOUT 2 IOUT=14mA to 2A to 14mA (rise / fall time = 1µs) VCNTL=5V, VIN=1.35V, VOUT=0.675V CH1: VOUT, 20mV/Div, DC offset 0.675V CH2: IOUT, 1A/Div, DC TIME: 10µs/Div Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2015 IOUT= -14mA to -2A to -14mA (rise / fall time = 1µs) VCNTL=5V, VIN=1.35V, VOUT=0.675V CH1: VOUT, 20mV/Div, DC offset 0.675V CH2: IOUT, 1A/Div, DC TIME: 5µs/Div 8 www.anpec.com.tw APL5339 Operating Waveforms(Cont.) Refer to the typical application circuit. The test condition is VCNTL=5V, TA= 25oC unless otherwise specified. Load Transient Response Load Transient Response VOUT V OUT 1 1 2 I OUT I OUT 2 IOUT=14mA to 2A to 14mA (rise / fall time = 1µs) VCNTL=5V, VIN=1.5V, VOUT=0.75V CH1: VOUT , 20mV/Div, DC offset 0.75V CH2: IOUT , 1A/Div, DC TIME: 10µs/Div VCNTL=5V, VIN=1.5V, VOUT=0.75V CH1: VOUT , 20mV/Div, DC offset 0.75V CH2: IOUT , 1A/Div, DC TIME: 5µs/Div Load Transient Response Load Transient Response VOUT VOUT 1 2 1 IOUT 2 IOUT= 2A to -2A to 2A VCNTL=5V, VIN=1.5V, VOUT=0.75V CH1: VOUT , 50mV/Div, DC offset 0.75V CH2: IOUT , 2A/Div, DC TIME: 5µs/Div IOUT= 2A to -2A to 2A VCNTL=5V, VIN=1.35V, VOUT=0.675V CH1: VOUT , 50mV/Div, DC offset 0.675V CH2: IOUT , 2A/Div, DC TIME: 5µs/Div Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2015 I OUT 9 www.anpec.com.tw APL5339 Operating Waveforms(Cont.) Refer to the typical application circuit. The test condition is VCNTL=5V, TA= 25oC unless otherwise specified. Over Current Protection Load Transient Response V IN V OUT VOUT 1 1,2 I OUT 2 IOUT 3 V IN= 1.5V, VOUT= 0.75V, IOUT = 2A to 3A CH1: VIN, 0.5V/Div, DC CH2: VOUT, 0.5V/Div, DC CH3: IOUT , 1A/Div, DC TIME: 20µs/Div, DC IOUT= 2A to -2A to 2A VCNTL=5V, VIN=1.8V, VOUT=0.9V CH1: VOUT , 50mV/Div, DC offset 0.9V CH2: IOUT , 2A/Div, DC TIME: 5µs/Div Shutdown Enable VEN VEN 1 1 VOUT VOUT IOUT 2 2 IOUT 3 3 VIN=1.8V, VREF=1.8V, IOUT=2A CH1: VEN, 5V/Div, DC CH2: VOUT, 0.2V/Div, DC CH3: IOUT, 1A/Div, DC TIME: 5µs/Div VIN=1.8V, VREF=1.8V, IOUT=2A CH1: VEN, 5V/Div, DC CH2: VOUT, 0.2V/Div, DC CH3: IOUT, 1A/Div, DC TIME: 50µs/Div Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2015 10 www.anpec.com.tw APL5339 Block Diagram VIN VCNTL VCNTL 3µA Power-OnReset Enable EN 0.8V THSD VREF Control Logic and Soft-Start POR Soft-Start Thermal Shutdown Error Amplifier VOUT RH 200kΩ RL 200kΩ Current Limit GND VOSNS Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2015 11 www.anpec.com.tw APL5339 Typical Application Circuit VOUT = 0.9V/0.75V/0.675V Application VCNTL +5V C1 1µF 10 VCNTL 6, 7, 8 VIN +1.8V/+1.5V/+1.35V C2 10µF 9 VIN VREF VOUT 3, 4, 5 C3 10µF (X5R/X7R) APL5339 1 EN EN VOSNS GND Enable VOUT C4 +0.9V/+0.75V/+0.65V 100µF -2A ~ +2A (Optional) 2 VOUT = 1 VREF 2 The ceramic capacitor C3 ( at least 8µF) is necessary for output stability. General Application VCNTL +5V C1 1µF VIN C2 10µF 10 6, 7, 8 VIN 9 VREF VREF C3 1µF VCNTL VOUT 3, 4, 5 APL5339 EN 1 EN Enable VOUT = R1 VOSNS GND VOUT C3 10µF (X5R/X7R) C4 100µF (Optional) 2 R2 1 R1 VREF 1 + 2 R2 The ceramic capacitor C3 ( at least 8µF) is necessary for output stability. Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2015 12 www.anpec.com.tw APL5339 Function Description Power-On-Reset(POR) Thermal Shutdown A Power-On-Reset (POR) circuit monitors both input voltages at VCNTL and VIN pins to prevent wrong logic An thermal shutdown circuit limits the junction temperature of the APL5339. When the junction temperature ex- controls. The POR function initiates a soft-start process after both of the supply voltages exceed their rising POR ceeds TJ = +170oC, a thermal sensor turns off the both pass transistors, allowing the device to cool. The thermal votage thresholds during powering on. sensor allows the regulator to regulate again after the junction temperature cools by 50oC, resulting in a pulsed Output Voltage Regulation output during continuous thermal overload conditions. The thermal limit designed with a 50oC hysteresis low- The output voltage on VOUT pin is regulated to track the reference voltage applied on VREF pin. Two internal Nchannel power MOSFETs controlled by high bandwidth ers the average TJ during continuous thermal overload conditions , increasing life time of the APL5339. error amplifiers regulate the output voltage by sourcing current from VIN pin or sinking current to GND pin. An internal output voltage sense pad is bonded to the VOUT pin with a bonding wire for perfect load regulation. For preventing the two power MOSFETs from shootthrough, a small voltage offset between the positive inputs of the two error amplifiers is designed. It results in higher output voltage while the regulator sinks light or heavy load current. Enable/Shutdown The APL5339 has a dedicated enable pin (EN). A logic low signal applied to this pin shuts down the output. Following a shutdown, a logic high signal re-enables the output through initiation of a new soft-start cycle. When left open, this pin is pulled up by an internal current source (3µA typical) to enable normal operation. Internal Soft-Start An internal soft-start function controls rise rate of the output voltage to limit the current surge during start-up. The typical soft-start interval is about 0.25 ms. Current-Limit Protection The APL5339 monitors the output current, both sourcing and sinking current, and limits the maximum output current to prevent damages during current overload or shortcircuit (shorten from VOUT to GND or VIN) conditions. Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2015 13 www.anpec.com.tw APL5339 Application Information Power Sequencing Where (TJ-TA) is the temperature difference between the The input sequencing of VIN and VCNTL is not necessary to be concerned. junction and ambient air. θJA is the thermal resistance o between junction and ambient air. Assuming the TA=25 C o and maximum TJ=150 C (Absolute Maximum Rating), the maximum power dissipation is calculated as: Input Capacitor Selection The APL5339 requires proper input capacitors to supply PD(max) = current surge during stepping load transients to prevent the input rail from dropping. Because the parasitic inductors from the voltage sources or other bulk capacitors to the VIN pin limit the slew rate of the input current, more (150 − 25) = 2.08(W) 60 For normal operation, do not exceed the maximum junco tion temperature of TJ = 125 C. The calculated power dis- parasitic inductance needs more input capacitance. For the APL5339, the total capacitance of input capacitors value sipation should less than: including MLCC and aluminum electrolytic capacitors should be larger than 10µF. For VCNTL pin, a capacitor of PD = 1µF (MLCC) or above is recommended for noise decoupling. (125 − 25) = 1.67( W ) 60 PCB Layout Considerations Output Capacitor Selection Figure 1 illustrates the layout. Below is a checklist for your layout: The APL5339 needs a proper output capacitor to maintain 1. Please place the input capacitors close to the VIN. 2. Please place the output capacitors close to the VOUT, circuit stability and improve transient response. In order to insure the circuit stability, a 10µF X5R or X7R MLCC a MLCC capacitor larger than 8µF must be placed near the VOUT. The distance from VOUT to output MLCC must output capacitor is sufficient at all operating temperatures and it must be placed near the VOUT. The maximum dis- be less than 2mm. 3. To place APL5339 and output capacitors near the load tance from output capacitor to VOUT must within 2mm. Total output capacitors value including MLCC and alumi- is good for load transient response. 4. Large current paths, the bold lines in Figure 1, must num electrolytic capacitors should be larger than 10µF. Table 1 provides the suitable output capacitors for have wide tracks. 5. VREF should be connected to VIN by a separate track. APL5339. VREF is the reference voltage of VOUT, so avoid any noise to get into the VREF. Table 1: Output Capacitor Guide Murata 6. Place the R1 and R2 near the APL5339 as close as possible to avoid noise coupling. Description Vendor 10µF, 6.3V, X7R, 0805, GRM21BR70J106K 7. Connect the ground of the R2 to the GND pin by using a dedicated track. 10µF, 6.3V, X5R, 0805, GRM21BR60J106K Murata website: www.murata.com 8. Connect the one pin of the R1 to the load for Kelvin sensing. Operation Region and Power Dissipation The APL5339 maximum power dissipation depends on the thermal resistance and temperature difference between the die junction and ambient air. The power dissipation PD across the device is: PD ≤ (TJ − TA ) θJA Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2015 14 www.anpec.com.tw APL5339 Application Information (Cont.) PCB Layout Considerations (Cont.) VCNTL CCNTL CIN VCNTL VIN VIN VREF VOUT VOUT APL5339 COUT VOSNS GND R1 Load R2 Figure 1. Recommanded Minimum Footprint The via diameter = 0.012 0.012 Hole size = 0.008 0.024 0.0965 0.012 0.02 0.062 Unit: Inch TDFN3x3-10 Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2015 15 www.anpec.com.tw APL5339 Package Information TDFN3x3-10 A E D b Pin 1 D2 A1 A3 NX aaa C L K E2 Pin 1 Corner e S Y M B O L TDFN3*3-10 MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 A3 0.20 REF 0.008 REF b 0.18 0.30 0.007 0.012 D 2.90 3.10 0.114 0.122 D2 2.20 2.70 0.087 0.106 0.122 0.069 E 2.90 3.10 0.114 E2 1.40 1.75 0.055 0.50 0.012 e 0.50 BSC L 0.30 K 0.20 aaa 0.020 BSC 0.020 0.008 0.08 0.003 Note:1.Followed from JEDEC MO-229 VEED-5. Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2015 16 www.anpec.com.tw APL5339 Carrier Tape & Reel Dimensions A B A B SECTION A-A Note : 1. 10 sprocket hole pitch cumulative tolerance ±0.2 SECTION B-B 2. Material: conductive polystyrene 3. Ao and Bo measured on a plane 0.3mm above the bottom of the pocket 4 Ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier Note : 1. Followed from EIA-481 Application TDFN3x3-10 A H T1 C d D 330±2.00 50 MIN. P0 P1 P2 D0 D1 4.0±0.10 8.0±0.10 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 12.4+2.00 13.0+0.50 -0.00 -0.20 1.5 MIN. W E1 20.2 MIN. 12.0±0.30 1.75±0.10 T A0 B0 F 5.5±0.05 K0 0.6+0.00 -0.40 3.30±0.20 3.30±0.20 1.00±0.20 (mm) Devices Per Unit Package Type Unit Quantity TDFN 3*3-10 Tape & Reel 3000 Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2015 17 www.anpec.com.tw APL5339 Taping Direction Information TDFN3x3-10 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2015 18 www.anpec.com.tw APL5339 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2015 19 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APL5339 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2015 20 www.anpec.com.tw