8-BIT SINGLE-CHIP MICROCONTROLLERS GMS87C4060 GMS81C4040 User’s Manual MicroElectronics Semiconductor Group of Hyundai Electronics Industrial Co., Ltd. Version 1.00 Published by MCU Application Team [email protected] [email protected] 2000 HYUNDAI Micro Electronics All right reserved. Additional information of this manual may be served by HYUNDAI Micro Electronics offices in Korea or Distributors and Representatives listed at address directory. HYUNDAI Micro Electronics reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, HYUNDAI Micro Electronics is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual. PRELIMINARY GMS81C4040/87C4060 Table of Contents OVERVIEW.......................................... 1 Description ...................................................1 Features .......................................................1 Development Tools..................................... 2 BLOCK DIAGRAM .............................. 3 PIN ASSIGNMENT .............................. 4 PACKAGE DIAGRAM ......................... 5 PIN FUNCTION .................................... 6 PORT STRUCTURES .......................... 9 RESET ................................................................ 9 TEST ................................................................... 9 XIN, XOUT ........................................................ 9 OSC1, OSC2 ..................................................... 9 R00~07, R53 ...................................................... 9 R10~15 (AN0~5) ................................................ 9 R16, 17, 20, 24, 25, 26, 27, 52, 67 ................... 10 R21/Sclk, R22/Sout .......................................... 10 R23/Sin ............................................................ 10 R40~43 (PWM0~3) .......................................... 10 R44, 45, 46, 47 (SCL, SDA, PWM) .................. 10 R50/BUZZ, R51/PWM8 .................................... 11 R54/YM, R55/YS, R56/I ................................... 11 R, G, B ............................................................. 11 ELECTRICAL CHARACTERISTICS . 12 Absolute Maximum Ratings .....................12 Recommended Operating Conditions ....12 DC Electrical Characteristics - GMS81C4040 .....................................................................12 A/D Comparator Characteristics .............14 AC Characteristics ....................................14 Typical Characteristics ............................16 MEMORY ORGANIZATION .............. 17 Registers ...................................................17 Program Memory ......................................20 PCALL→ rel ..................................................... 21 TCALL→ n ....................................................... 21 Data Memory .............................................23 User Memory .................................................... 23 Control Registers ............................................. 23 Stack Area ........................................................ 23 Addressing Mode ......................................25 (1) Register Addressing ................................... 25 (2) Immediate Addressing → #imm .................. 25 (3) Direct Page Addressing → dp ..................... 25 (4) Absolute Addressing → !abs ....................... 25 (5) Indexed Addressing .................................... 26 X indexed direct page (no offset) → {X} ........... 26 X indexed direct page, auto increment→ {X}+ . 26 Nov. 1999 Ver 1.0 X indexed direct page (8 bit offset) → dp+X ..... 26 Y indexed direct page (8 bit offset) → dp+Y ..... 27 Y indexed absolute → !abs+Y .......................... 27 Direct page indirect → [dp] ............................... 27 X indexed indirect → [dp+X] ............................. 27 Y indexed indirect → [dp]+Y ............................. 28 Absolute indirect → [!abs] ................................ 28 I/O PORTS ......................................... 29 Registers for Port ..................................... 29 Port Data Registers .......................................... 29 I/O Ports Configuration ............................ 30 R0 Ports ........................................................... 30 R1 Ports ........................................................... 30 R2 Port ............................................................. 31 R4 Port ............................................................. 31 R5 Port ............................................................. 32 R6 Port ............................................................. 32 CLOCK GENERATOR ...................... 33 TIMER ................................................ 34 Basic Interval Timer ................................. 34 Timer 0, 1 ................................................... 35 Timer / Event Counter 2, 3 ....................... 37 Timer Mode ...................................................... 39 Event counter Mode ......................................... 39 A/D Converter ................................... 42 Control .............................................................. 42 Serial I/O ........................................... 44 Control .............................................................. 44 Pulse Width Modulation (PWM) ...... 46 8bit PWM Control ............................................. 47 14bit PWM Control ........................................... 47 Interrupt interval measurement circuit ........................................................... 49 Control .............................................................. 49 Buzzer driver .................................... 51 Control .............................................................. 51 On Screen Display (OSD) ................ 53 OSDCON1 ....................................................... 55 OSDCON2 ....................................................... 55 OSDPOL .......................................................... 56 FDWSET .......................................................... 56 L1ATTR ............................................................ 57 L1VPOS ........................................................... 58 L2ATTR ............................................................ 58 L2VPOS ........................................................... 58 COLMOD ......................................................... 58 MESHCON ....................................................... 58 VRAM ............................................................... 58 Font ROM ......................................................... 60 PRELIMINARY 1 GMS81C4040/87C4060 PRELIMINARY Sprite RAM ....................................................... 60 Test Font .......................................................... 61 Response Time ................................................ 75 I2C Bus Interface .............................. 62 WATCHDOG TIMER ......................... 76 Control .............................................................. 62 I2C address register ......................................... 62 I2C data shift register [ICDR] ........................... 63 I2C status register ............................................ 63 I2C control register 1 ........................................ 64 I2C control register 2 ........................................ 64 START condition generation ............................ 65 RESTART condition generation ....................... 65 STOP condition generation .............................. 65 START / STOP condition detect ...................... 66 Address data communication ........................... 67 Watchdog Timer Control .................................. 76 Enable and Disable Watchdog ......................... 77 Watchdog Timer Interrupt ................................ 77 Minimizing Current Consumption ..................... 78 External Interrupt ..................................... 75 OSCILLATOR CIRCUIT .................... 80 RESET ............................................... 81 External Reset Input ................................. 81 Watchdog Timer Reset ............................ 82 OTP Programming ........................... 83 Interrupt Mode Register ................................... 68 GMS87C4060 OTP Programming ............ 83 .Device configuration data ...................... 84 Timing Chart ............................................. 87 Interrupt Sequence ...................................72 Assemble mnemonics ..................... 89 Interrupt acceptance ........................................ 72 Saving/Restoring General-purpose Register ... 73 Instruction Map ......................................... 89 Alphabetic order table of instruction ..... 90 Instruction Table by Function ................. 94 INTERRUPTS .................................... 68 Multi Interrupt ............................................74 2 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 GMS81C4040/GMS87C4060 CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER FOR TELEVISION 1. OVERVIEW 1.1 Description The GMS81C4040/GMS87C4060 is an advanced CMOS 8-bit microcontroller with 40K(60K) bytes of ROM. The device is one of GMS800 family. The HYUNDAI’s GMS81C4040/GMS87C4060 is a powerful microcontroller which provides a highly flexible and cost effective solution to many TV applications. The GMS81C4040/GMS87C4060 provides the following standard features: 40K(60K) bytes of ROM, 1,536 bytes of RAM, 8-bit timer/counter . Device name ROM Size RAM Size Package GMS81C4040 40K bytes Mask ROM 1,536 bytes 52SDIP GMS87C4060 60K bytes EPROM 1,536 bytes 52SDIP 1.2 Features • 40K(60K) Bytes On-chip Program Memory • 1,536 Bytes of On-chip Data RAM (Included 256 bytes stack memory) • Instruction Cycle Time (ex:NOP) - 0.5us at 8MHz • 40 Programmable I/O pins - 33 I/O and 7 Output pins • Serial I/O : 8bit x 1ch • I2C Bus interface - Multimaster (2 Pairs interface pins) • A/D Converter : 8bit x 6ch (TBD LSB) • Pulse Width Modulation - 14bit x 1ch - 8bit x 6ch • Timer - Timer/Counter : 8bit x 4ch (16bit x 2ch) Nov. 1999 Ver 1.0 - Basic interval timer : 8bit x 1ch - Watch Dog Timer • Number of Interrupt sources : 18 • On Screen Display - Number of characters : 512 (6 characters are reserved for IC test) - Character size : 12 dots(X) x 16 dots(Y) - Character display size : Large, Medium, Small - DIsplay capability : 24Characters x 16 Line (Two line VRAM buffer) - Character, Back ground color : 16kinds - Special functions : Rounding, Outline, Sprite, Shadow,... • Buzzer Driving port - 500Hz ~ 250kHz @8MHz (Duty 50%) • Operating Range : 4.5V to 5.5V PRELIMINARY 1 GMS81C4040/87C4060 PRELIMINARY 1.3 Development Tools The GMS81C4040/GMS87C4060 is supported by a fullfeatured macro assembler / linker , OSD font editor, an incircuit emulator CHOICE-DrTM. In Circuit Emulators 2 Assembler / Linker HYUNDAI’s Macro Assembler / Linker Font Editor MS-Windows GUI version Debugger MS-Windows GUI version CHOICE-Dr. (with EVA81C4xxx board) PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 2. BLOCK DIAGRAM R10 / AN0 R11 / AN1 R12 / AN2 R13 / AN3 R14 / AN4 R15 / AN5 R16 / VD R17 / HD R,G,B OSC1 OSC2 OSD Display Memory OSD (On Screen Display) Controller R50 / BUZZ R51 / PWM8 R54 / YM R52 / INT0 R55 / YS R53 R56 / I R1 R5 D a ta b u s Data Memory Stack pointer PSW Accumulator & Index X,Y ALU PC Program Memory Buzzer 8bit A/D C onvertor PWM 14bit x 1 8bit x 6 Interrupt Controller Vector Table RESET TEST System controller System Clock Controller Timing generator XIN XOUT 8-bit Basic Interval Tim er Watchdog Timer 8-bit x 4 Timer/ Counter Interrupt Interval M easure I2C Interface Serial I/O Interface Clock generator D a ta b u s VDD VSS Power Supply Nov. 1999 Ver 1.0 R0 R6 R00 R01 R02 R03 R04 R05 R06 R07 R67 / INT1 PRELIMINARY R2 R20 / INT2 R21 / Sclk R22 / Sout R23 / Sin R24 / INT3 R25 / EC2 R26 / INT4 R27 / EC3 R4 R40 R41 R42 R43 / PWM0 / PWM1 / PWM2 / PWM3 R44 / SCL0 R45 / SCL1 / PWM4 R46 / SDA0 R47 / SDA1 / PWM5 3 PRELIMINARY GMS81C4040/87C4060 3. PIN ASSIGNMENT 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 HYUNDAI GMS81C40XX R27/EC3 R26/INT4 R25/EC2 R24/INT3 R23/Sin R22/Sout R21/Sclk R20/INT2 R17/HD R16/VD RESET Vss Xout Xin R15/AN5 R14/AN4 R13/AN3 R12/AN2 R11/AN1 R10/AN0 R07 R06 R05 R04 R03 R67/INT1 PRELIMINARY 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 R40/PWM0 R41/PWM1 R42/PWM2 R43/PWM3 R44/SCL0 R45/SCL1/PWM4 R46/SDA0 R47/SDA1/PWM5 R50/BUZZ R51/PWM8 R52/INT0 R53 Vss Vdd TEST OSC1 OSC2 R54/YM R55/YS R56/I B G R R00 R01 R02 Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 4. PACKAGE DIAGRAM 52 27 13.97 15.24 0.25 0.25 HYUNDAI GMS81C40XX 0 ~ 15 26 1 0.25 4.38 Max. 0.13 0.13 0.76 0.13 3.81 45.97 0.05 UNIT: mm 1.02 0.25 1.778 0.25 3.24 0.13 0.20 0.50 Min. 0.47 Figure 4-1 52pin Shrink DIP Package Diagram Nov. 1999 Ver 1.0 PRELIMINARY 5 GMS81C4040/87C4060 PRELIMINARY 5. PIN FUNCTION VDD: Supply voltage. VSS: Circuit ground. TEST: Used for shipping inspection of the IC. For normal operation, it should not be connected . RESET: Reset the MCU. XIN: Input to the inverting oscillator amplifier and input to the internal main clock operating circuit. XOUT: Output from the inverting oscillator amplifier. OSC1: Input to the internal On Screen Display operating circuit. OSC2: Output from the inverting OSC1 amplifier. R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. R10~R17: R1 is an 8-bit CMOS bidirectional I/O port. R1 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R1 serves the functions of the various following special features. Port pin R10 R11 R12 R13 R14 R15 R16 R17 AN0 (A/D converter input 0) AN1 (A/D converter input 1) AN2 (A/D converter input 2) AN3 (A/D converter input 3) AN4 (A/D converter input 4) AN5 (A/D converter input 5) VD (Vertical Sync. input) HD (Horisontal Sync. input) R20 R21 R22 R23 R24 R25 R26 R27 6 INT2 (External interrupt input 2) Sclk (Serial communication clock) Sout (Serial communication data out) Sin (Serial communication data in) INT3 (External interrupt input 3) EC2 (Event counter input 2) INT4 (External interrupt input 4) EC3 (Event counter input 3) Port pin R40 R41 R42 R43 R44 R45 R46 R47 Alternate function PWM0 (Pulse Width Modulation output 0) PWM1 (Pulse Width Modulation output 1) PWM2 (Pulse Width Modulation output 2) PWM3 (Pulse Width Modulation output 3) SCL0 (I2C Clock 0) SCL1 (I2C Clock 1) PWM4 (Pulse Width Modulation output 4) SDA0 (I2C Data 0) SDA1 (I2C Data 1) PWM5 (Pulse Width Modulation output 5) R50~R56: R50~R53 are 4-bit CMOS bidirectional I/O and R54~R56 are CMOS output port. R5 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. Port pin R50 R51 R52 R54 R55 R56 In addition, R2 serves the functions of the various following special features. Alternate function In addition, R4 serves the functions of the various following special features. In addition, R5 serves the functions of the various following special features. Alternate function R20~R27: R2 is a 8-bit CMOS bidirectional I/O port. Each pins 1 or 0 written to the their Port Direction Register can be used as outputs or inputs. Port pin R40~R47: R40~R43 are 8-bit NMOS open drain output and R45~R47 are bidirectional CMOS Input / NMOS open drain output port. R4 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. Alternate function BUZZ (Buzzer output) PWM8 (Pulse Width Modulation output 8) INT0 (External interrupt input 0) YM (Back ground) YS (Edge) I (Intencity) R67: R67 is an 1-bit CMOS bidirectional I/O port. R67 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R67 serves the functions of the various following special features. Port pin R67 Alternate function INT1 (External interrupt input 1) R,G,B: R,G,B CMOS output port. Each pins controls Red, Green,. Blue color control. PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY PIN NAME GMS81C4040/87C4060 Pin No. In/Out Function VDD 39 - Supply voltage VSS 12, 40 - Circuit ground TEST 38 I For test purposes. Should not be connected. (N.C.) RESET 11 I Reset signal input XIN 14 I Main oscillation input XOUT 13 O Main oscillation output OSC1 37 I On screen display oscillation input OSC2 36 O On screen display osc. output R17/HD 9 I/O Horisontal Sync. input R16/VD 10 I/O Vertical Sync. input R 30 O G 31 O B 32 O Blue signal output R56/I 33 O Intencity signal output R55/YS 34 O Edge signal output R54/YM 35 O Background signal output R40/PWM0 52 O 8bit PWM R41/PWM1 51 O 8bit PWM R42/PWM2 50 O 8bit PWM R43/PWM3 49 O On screen display functions Red signal output Green signal output 8bit PWM PWM functions R45/SCL1/ PWM4 47 I/O Include I2C Serial clock 1 (SCL1) R47/SDA1/ PWM5 45 I/O Include I2C Serial data 1 (SDA1) R51/PWM8 43 I/O 14bit PWM R44/SCL0 48 I/O R46/SDA0 46 I/O R23/Sin 5 I/O R22/Sout 6 I/O R21/Sclk 7 I/O R27/EC3 1 I/O R25/EC2 3 I/O R50/Buzzer 44 I/O I2C functions I2C Serial clock 0 I2C Serial data 0 Serial data input SCI functions Serial data output Serial communication clock Timer event functions Buzzer function Event counter input 3 Event counter input 2 500Hz ~ 250KHz @8MHz Table 5-1 Port Function Description Nov. 1999 Ver 1.0 PRELIMINARY 7 PRELIMINARY GMS81C4040/87C4060 PIN NAME Pin No. In/Out Function R52/INT0 42 I/O External interrupt input 0 R67/INT1 26 I/O External interrupt input 1 R20/INT2 8 I/O R24/INT3 4 I/O External interrupt input 3 R26/INT4 2 I/O External interrupt input 4 R10/AN0 20 I/O Analog input 0 R11/AN1 19 I/O Analog input 1 R12/AN2 18 I/O R13/AN3 17 I/O R14/AN4 16 I/O Analog input 4 R15/AN5 15 I/O Analog input 5 R00 29 I/O R01 28 I/O R02 27 I/O R03 25 I/O R04 24 I/O R05 23 I/O R06 22 I/O R07 21 I/O R53 41 I/O External interrupt functions A/D conversion functions External interrupt input 2 Analog input 2 Analog input 3 Digital I/O functions Table 5-1 Port Function Description 8 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 6. PORT STRUCTURES RESET OSC1, OSC2 VDD VDD Main frequency clock RESET Noise Canceler OSC1 VSS VDD VSS OSC2 OSDON TEST VSS VDD R00~07, R53 VDD VSS XIN, XOUT DB Data Reg. DB Dir. Reg. Pin VSS VDD Main frequency clock MUX DB RD XIN R10~15 (AN0~5) VSS VDD VDD XOUT DB Data Reg. DB Dir. Reg. VSS VSS Pin VSS MUX DB RD AN0~5 Nov. 1999 Ver 1.0 PRELIMINARY 9 PRELIMINARY GMS81C4040/87C4060 R16, 17, 20, 24, 25, 26, 27, 52, 67 R23/Sin VDD DB Data Reg. DB Dir. Reg. VDD DB Data Reg. Selection Pin Pin DB Dir. Reg. VSS VSS MUX DB M UX DB RD RD HD,VD, EC2~3 INT0~INT4 Sin R21/Sclk, R22/Sout DB R40~43 (PWM0~3) DB Data Reg. Data Reg. VDD M UX Pin M UX PWM0~3 Sout, Sclk VSS Selection Selection Pin DB Dir. Reg. VSS DB R44, 45, 46, 47 (SCL, SDA, PWM) M UX DB RD Data Reg. M UX SCL,SDA PWM4,PWM5 Sclk Selection Pin DB Dir. Reg. VSS DB M UX RD SCL, SDA 10 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 R50/BUZZ, R51/PWM8 DB Data Reg. M UX VDD Buzz, PWM8 Selection Pin Dir. Reg. DB VSS M UX DB RD R54/YM, R55/YS, R56/I VDD OSD ON or Data Reg Write. DB Data Reg. Pin M UX YM, YS, I Selection VSS R, G, B VDD R, G, B i Pin OSD_ON VSS Nov. 1999 Ver 1.0 PRELIMINARY 11 PRELIMINARY GMS81C4040/87C4060 7. ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings Supply voltage ........................................... -0.3 to +6.0 V Maximum current (ΣIOL) ...................................... 80 mA Storage Temperature ................................-40 to +125 °C Maximum current (ΣIOH)...................................... 50 mA Voltage on any pin with respect to Ground (VSS) ............................................................... -0.3 to VDD+0.3 Maximum current out of VSS pin ........................100 mA Maximum current into VDD pin ............................80 mA Maximum current sunk by (IOL per I/O Pin) ........20 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum output current sourced by (IOH per I/O Pin) .................................................................................8 mA 7.2 Recommended Operating Conditions Specifications Parameter Symbol Condition Unit Min. Max. Supply Voltage VDD fXIN=8MHz fOSC=16MHz 4.5 5.5 V Operating Frequency fXIN VDD=4.5~5.5V 4 8 MHz On Screen Display Operating Frequency fOSC VDD=4.5~5.5V 8 16 MHz Operating Temperature TOPR -10 70 °C 7.3 DC Electrical Characteristics - GMS81C4040 (TA=-10~70°C, V DD=4.5~5.5V), Specifications Parameter High level input voltage Low level input voltage High level output voltage Symbol Condition Unit Min. Typ. Max. VIH1 TEST, RESET, Xin, OSC1, R17~16, R27~20, R47~44, R52, R67 0.8 VDD - VDD V VIH2 R0, R15~10, R53~50 0.7 VDD - VDD V VIL1 TEST, RESET, Xin, OSC1, R17~16, R27~20, R47~44, R52, R67 0 - 0.12 V DD V VIL2 R0, R15~10, R53~50 0 - 0.3 VDD V IOH = -5mA R0, R1, R2, R5, R67 VDD - 1 - - V IOH = -1.2mA R,G,B VDD - 1 - - V VOH Low level output voltage VOL IOL = 5mA R0, R1, R2, R4, R5, R67, R, G, B - - 1.0 V Supply current in ACTIVE mode IDD VDD - - 30 mA 12 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 Specifications Parameter Symbol Condition Unit Min. pull-up lekage current IRUP VDD = 5.5v, VPIN = 0.4V TEST High input leakage current IIZH VDD = 5.5V , VPIN = V DD All input, I/O pins except X IN, OSC1, R47~40 -5 Low input leakage current IIZL VDD = 5.5V , VPIN = 0V All input, I/O pins except XIN, OSC1, R47~44 Open drain leakage current ILOZ VDD = 5.5V , VOH = V DD, N-ch Tr. off R47~40 RAM data retention voltage VRAM VDD I2C port impedance (I/O Transistor off) RBS VDD = 4.5V , VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V SCL0:SCl1 (R44:R45) SDA0:SDA1 (R46:R47) Hysterisis Vt+ ~ Vt- TEST, RESET, Xin, OSC1, R17~16, R27~20, R47~44, R52, R67 Nov. 1999 Ver 1.0 PRELIMINARY Typ. Max. -400 µA - 5 µA -5 - 5 µA - - 10 µA 1.2 - - V - - 120 Ω 1.0 - - V -1.5 13 PRELIMINARY GMS81C4040/87C4060 7.4 A/D Comparator Characteristics (TA=-10~70°C, V DD=5.0V) Specifications Parameter Symbol Pins Analog Input Voltage Range VAIN AN0~AN5 Accuracy NFS - Unit Min. Typ. Max. VSS - VDD V - - ΤΒ∆ LSB 7.5 AC Characteristics (TA=-10~70°C, V DD=5V±10%, VSS=0V) Specifications Parameter Symbol Pins Unit Min. Typ. Max. fXIN XIN 4 - 8 MHz fOSC OSC 8 - 16 MHz tMCPW XIN 62.5 - 125 nS tSCPW SCLK 0.5 - tMRCP,tMFCP XIN - - 20 nS tSRCP,tSFCP SCLK - - 20 nS Oscillation Stabilizing Time tST XIN, XOUT - - 20 mS Interrupt Pulse Width tIW INT0~4 2 - - tSYS1 RESET Input Width tRST RESET 8 - - tSYS1 Event Counter Input Pulse Width tECW EC2, EC3 2 - - tSYS1 tREC,tFEC EC2, EC3 - - 20 nS Operating Frequency External Clock Pulse Width External Clock Transition Time Event Counter Transition Time µS 1. tSYS is one of 2/fXIN main clock operation mode, 14 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY tMCPW 1/fXIN GMS81C4040/87C4060 tMCPW VDD-0.5V XIN 0.5V tMRCP tMFCP tSCPW 1/f SCLK tSCPW VDD-0.5V SCLK 0.5V tSRCP tIW INT0 ~ 4 tSFCP tIW 0.8VDD 0.2VDD tRST RESET 0.2VDD tECW tECW 0.8VDD EC2, EC3 0.2VDD tREC tFEC Figure 7-1 Timing Chart Nov. 1999 Ver 1.0 PRELIMINARY 15 GMS81C4040/87C4060 PRELIMINARY 7.6 Typical Characteristics This data will generate after evaluation. Not available at this time. 16 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 8. MEMORY ORGANIZATION The GMS81C4040/GMS87C4060 has separate address spaces for Program memory, Data Memory and Display memory. Program memory can only be read, not written to. It can be up to 40K/60K bytes of Program memory. Data memory can be read and written to up to 1,536 bytes including the stack area. Font memory has prepared 16K bytes for OSD. 8.1 Registers This device has six registers that are the Program Counter (PC), a Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register. A ACCUMULATOR X X REGISTER Y Y REGISTER SP PCH STACK POINTER PCL PROGRAM COUNTER PSW PROGRAM STATUS WORD (save or restore). Generally, SP is automatically updated when a subroutine call is executed or an interrupt is accepted. However, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. The stack can be located at any position within 0100H to 01FFH of the internal data memory. The SP is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of "FFH" is used. Stack Address ( 0100H ~ 01FFH ) 15 8 7 01 0 SP Figure 8-1 Configuration of Registers Hardware fixed Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc. The Accumulator can be used as a 16-bit register with Y Register as shown below. Caution: The Stack Pointer must be initialized by software because its value is undefined after RESET. Example: To initialize the SP Y Y LDX TXSP A A #0FFH ; SP ← FFH Two 8-bit Registers can be used as a "YA" 16-bit Register Figure 8-2 Configuration of YA 16-bit Register X, Y Registers: In the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators. Stack Pointer: The Stack Pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. Stack Pointer identifies the location in the stack to be accessed Nov. 1999 Ver 1.0 Program Counter: The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH). Program Status Word: The Program Status Word (PSW) contains several bits that reflect the current state of the CPU. The PSW is described in Figure 8-3 . It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD operation), the Interrupt enable flag, the Zero flag, and the Carry flag. [Carry flag C] This flag stores any carry or borrow from the ALU of CPU PRELIMINARY 17 PRELIMINARY GMS81C4040/87C4060 after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction. MSB PSW N LSB V G B H I Z C RESET VALUE : 00H CARRY FLAG RECEIVES CARRY OUT NEGATIVE FLAG OVERFLOW FLAG ZERO FLAG SELECT DIRECT PAGE when G=1, page is addressed by RPR INTERRUPT ENABLE FLAG HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS BRK FLAG Figure 8-3 PSW (Program Status Word) Register [Zero flag Z] [Direct page flag G] This flag is set when the result of an arithmetic operation or data transfer is "0" and is cleared by any other result. This flag assigns RAM page for direct addressing mode. In the direct addressing mode, addressing area is from zero page 00H to 0FFH when this flag is "0". If it is set to "1", addressing area is assigned by DPGR register (address 0F8H). It is set by SETG instruction and cleared by CLRG. [Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All interrupts are disabled when cleared to "0". This flag immediately becomes "0" when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction. [Half carry flag H] After operation, this is set when there is a carry from bit 3 of ALU or there is borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V). [Break flag B] This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector address. 18 [Overflow flag V] This flag is set to "1" when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127(7FH) or -128(80 H ). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag. PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY At acceptance of interrupt At execution of a CALL/TCALL/PCALL 01FC 01FC 01FD 01FD PSW 01FE PCL 01FF PCH 01FE PCL 01FF PCH Push down GMS81C4040/87C4060 At execution of RET instruction 01FC 01FC 01FD Push down At execution of RETI instruction 01FE PCL 01FF PCH Pop up 01FD PSW 01FE PCL 01FF PCH SP before execution 01FF 01FF 01FD 01FC SP after execution 01FD 01FC 01FF 01FF At execution of PUSH instruction PUSH A (X,Y,PSW) At execution of POP instruction POP A (X,Y,PSW) 01FC 01FC 01FD 01FD 01FE 01FF Pop up 0100H Stack depth 01FE A Push down 01FF A SP before execution 01FF 01FE SP after execution 01FE 01FF Pop up 01FFH Figure 8-4 Stack Operation Nov. 1999 Ver 1.0 PRELIMINARY 19 PRELIMINARY GMS81C4040/87C4060 8.2 Program Memory A 16-bit program counter is capable of addressing up to 64K bytes, but GMS81C4040/GMS87C4060 has 40K/ 60K bytes program memory space only physically implemented. Accessing a location above FFFFH will cause a wrap-around to 0000H. Figure 8-5 , shows a map of Program Memory. After reset, the CPU begins execution from reset vector which is stored in address FFFEH and FFFFH as shown in Figure 8-6 . As shown in Figure 8-5 , each area is assigned a fixed location in Program Memory. Program Memory area contains the user program. 81C4040:6000H 81C4060:1000H PROGRAM MEMORY FEFFH FF00H FFBFH FFC0H FFDFH FFE0H FFFFH TCALL AREA PCALL AREA Example: Usage of TCALL LDA #5 TCALL 0FH : : ;1B Y TE INS T RU CT IO N ;IN S TE A D O F 2 B Y TE S ;N O R M A L CA LL ; ;TABLE CALL ROUTINE ; FUNC_A: LDA LRG0 RET ; FUNC_B: LDA LRG1 2 RET ; ;TABLE CALL ADD. AREA ; ORG 0FFC0H DW FUNC_A DW FUNC_B 1 ;TC A LL A DD R E SS A RE A The interrupt causes the CPU to jump to specific location, where it commences the execution of the service routine. The External interrupt 0, for example, is assigned to location 0FFFCH. The interrupt service locations spaces 2-byte interval: 0FFF8H and 0FFF9 H for External Interrupt 1, 0FFFCH and 0FFFDH for External Interrupt 0, etc. Any area from 0FF00H to 0FFFFH, if it is not going to be used, its service location is available as general purpose Program Memory. INTERRUPT VECTOR AREA Address Figure 8-5 Program Memory Map 0FFE0H Page Call (PCALL) area contains subroutine program to reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called, it is more useful to save program byte length. Table Call (TCALL) causes the CPU to jump to each TCALL address, where it commences the execution of the service routine. The Table Call service area spaces 2-byte for every TCALL: 0FFC0H for TCALL15, 0FFC2 H for TCALL14, etc., as shown in Figure 8-7 . Vector Area Memory I2C Bus Interface Interrupt Vector Area E2 Serial I/O Interrupt Vector Area E4 Basic Interval Timer Interrupt Vector Area E6 Watchdog Timer Interrupt Vector Area E8 External Interrupt 3/4 Vector Area EA Timer/Counter 3 Interrupt Vector Area EC Timer/Counter 1 Interrupt Vector Area EE V-Sync Interrupt Vector Area F0 1 Frame Timer Interrupt Vector Area F2 Timer/Counter 2 Interrupt Vector Area F4 Timer/Counter 0 Interrupt Vector Area F6 External Interrupt 2 Vector Area F8 External Interrupt 1 Vector Area FA On Screen Display Interrupt Vector Area FC External Interrupt 0 Vector Area FE RESET Vector Area NOTE: "-" means reserved area. Figure 8-6 Interrupt Vector Area 20 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY Address GMS81C4040/87C4060 Address Program Memory 0FFC0H C1 TCALL 15 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF PCALL Area Memory 0FF00H PCALL Area (192 Bytes) 0FFBFH TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK * NOTE: * means that the BRK software interrupt is using same address with TCALL0. Figure 8-7 PCALL and TCALL Memory Area PCALL→ → rel TCALL→ →n 4F35 4A PCALL 35H TCALL 4 4A 4F 35 ~ ~ ~ ~ ~ ~ Upper address is assumed 0FFH. 0D125H 01001010 ~ ~ Sub-routine þ Reverse PC: 11111111 11010110 FH FH DH 6 H 0FF00H 0FF35H Sub-routine 0FFFFH à 0FF00H 0FFD6H 25 0FFD7H D1 À 0FFFFH Nov. 1999 Ver 1.0 PRELIMINARY 21 GMS81C4040/87C4060 PRELIMINARY Example: The usage software example of Vector address and the initialize part. ORG 0FFE0H DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW I2C SERIAL BIT WATCHDOG INT3_4 TIMER3 TIMER1 VSYNC One_Frame TIMER2 TIMER0 INT2 INT1 OSD INT0 RESET ORG 0F000H ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; I2C Serial I/O Basic interval timer Watch dog timer Interrupt 3/4 Timer 3 Timer 1 Vertical Sync. 1 Frame interrupt Timer 2 Timer 0 Interrupt 2 Interrupt 1 On Screen Display Interrupt 0 Reset ;******************************************** ; MAIN PROGRAM * ;******************************************** ; RESET: DI ; Disable All Interrupts LDX #0 LDA #0 ; RAM Clear(!0000H->!00BFH) RAM_CLR: STA {X}+ CMPX #0C0H BNE RAM_CLR ; CALL LCD_CLR ; Clear LCD display memory ; LDX #03FH ; Stack Pointer Initialize TXSP LDM LDM : : : : 22 R0, #0 R0DD,#1000_0010B ; Normal Port 0 ; Normal Port Direction PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 8.3 Data Memory Figure 8-8 shows the internal Data Memory space available. Data Memory is divided into four groups, a user RAM, control registers, Stack, and OSD memory. 0000H 00C0H 0100H 0200H Page0 Peripheral Reg. (64 bytes) Page1 RAM (256 bytes) Page2 RAM (256 bytes) Page3 RAM (256 bytes) Page4 RAM (256 bytes) Page5 RAM (64 bytes) Page6 The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save. Refer to Figure 8-4 on page 19. 0500H 0600H 063FH Empty area 0A00H OSD RAM (192 bytes) CLCTLR,#09H ;Divide ratio ÷8 When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return instruction [RETI] restores the contents of the program counter and flags. 0300H 0400H LDM Stack Area The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. RAM (192 bytes) RAM (256 bytes) Stack area Example; To write at CKCTLR PageA 0AE0H Peripheral Reg. (32 bytes) 0C00H 0C5FH Sprite RAM (96 bytes) PageC Figure 8-8 Data Memory Map User Memory The GMS81C4040/GMS87C4060 has 1,536 × 8 bits for the user memory (RAM). Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and I/O ports. The basic control registers are in address range of 00C0H to 00FFH. And OSD control registers are assigned within 0AE0H ~ 0AFFH. Address Symbol R/W Reset Value Addressing mode 00C0H 00C1H 00C2H 00C3H 00C4H 00C5H 00C8H 00C9H 00CAH 00CBH 00CCH 00CDH 00CEH 00CFH R0 R0DD R1 R1DD R2 R2DD R4 R4DD R5 R5DD R6 R6DD FUNC1 FUNC2 R/W W R/W W R/W W R/W W R/W W R/W W W W ???????? 00000000 ???????? 00000000 ???????? 00000000 ???????? 0000---???????? ----0000 ?------0-------0000000 ---00000 byte, bit1 byte2 byte, bit byte byte, bit byte byte, bit byte byte, bit byte byte, bit byte byte byte Table 8-1Control registers Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. More detailed informations of each register are explained in each peripheral section. Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction. Nov. 1999 Ver 1.0 PRELIMINARY 23 PRELIMINARY GMS81C4040/87C4060 0D7H 0D8H 0D9H 0DAH 0DBH 0DCH 0DEH 0DFH TM0 TM2 TDR0 TDR1 TDR2 TDR3 BITR CKCTLR WDTR ICAR ICDR ICSR ICCR1 ICCR2 SIOM SIOR R/W R/W R/W R/W R/W R/W R W W R/W R/W R/W R/W R/W R/W R/W -0000000 -0000000 ???????? ???????? ???????? ???????? ???????? --010111 -0111111 00000000 11111111 000100000000000 00000000 -0000001 ???????? byte byte byte, bit byte, bit byte, bit byte, bit byte byte byte byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit 0E0H 0E1H 0E2H 0E3H 0E4H 0E5H 0E8H 0E9H 0EAH 0EBH 0EEH 0EFH PWMR0 PWMR1 PWMR2 PWMR3 PWMR4 PWMR5 PWM8H PWM8L PWMCR1 PWMCR2 BUR AIPS W W W W W W R/W R/W R/W R/W W W ???????? ???????? ???????? ???????? ???????? ???????? ???????? --?????? 00000000 --0-0000 ???????? --000000 byte byte byte byte byte byte byte, bit byte, bit byte, bit byte, bit byte byte 0F0H 0F1H 0F2H 0F3H 0F4H 0F5H 0F6H 0F7H 0F9H 0FAH 0FBH 0FCH 0FDH ADCM ADR IEDS IMOD IENL IRQL IENH IRQH IDCR IDFS IDR DPGR TMR R/W R W R/W R/W R/W R/W R/W R/W R R R/W W --011101 ???????? --000000 --000000 0000000000000000000000 00000000 0000-000 1----001 ???????? ----0000 ???????? byte, bit byte byte byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte byte byte, bit byte 0AE0H 0AE1H 0AE2H 0AE3H 0AE4H 0AE5H 0AE6H 0AE8H 0AE9H 0AF0H 0AF1H 0AF3H 0AF4H OSDcon1 OSDcon2 OSDPOL FDWSET EDGEcol OSDLN LHPOS SPVPOS SPHPOS L1ATTR L1VPOS L2ATTR L2VPOS R/W R/W W W W R W W W W W W W 00000000 -0000000 ???????? 01111010 10000111 ---00000 ???????? ???????? ???????? ???????? ???????? ???????? ???????? byte, bit byte, bit byte byte byte byte byte byte byte byte byte byte byte 0D0H 0D1H 0D2H 0D3H 0D4H 0D5H 0D6H 1. "byte, bit" means that register can be addressed by not only bit but byte manipulation instruction. 2. "byte" means that register can be addressed by only byte manipulation instruction. On the other hand, do not use any read-modify-write instruction such as bit manipulation for clearing bit. Table 8-1Control registers 24 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 8.4 Addressing Mode The GMS800 series uses six addressing modes; (3) Direct Page Addressing → dp • Register addressing In this mode, a address is specified within direct page. • Immediate addressing Example; G=0 • Direct page addressing E551: C535 35H;A ←RAM[35H] LDA • Absolute addressing • Indexed addressing 35H • Register-indirect addressing data À ~ ~ (1) Register Addressing Register addressing accesses the A, X, Y, C and PSW. ~ ~ 0E550H C5 0E551H 35 þ data → A (2) Immediate Addressing → #imm In this mode, second byte (operand) is accessed as a data immediately. (4) Absolute Addressing → !abs Example: FE10: 0435 ADC Absolute addressing sets corresponding memory data to Data , i.e. second byte(Operand I) of command becomes lower level address and third byte (Operand II) becomes upper level address. With 3 bytes command, it is possible to access to whole memory area. #35H MEMORY 0FE10H 04 A+35H+C → A 35 ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR, SBC, STA, STX, STY Example; ;A ←ROM[0F035H] F100: 0735F0 ADC!0F035H When G-flag is 1, then RAM address is defined by 16-bit address which is composed of 8-bit direct page accessable register (DPGR) and 8-bit immediate data. Example: G=1, DPGR=0CH F100: E45535 LDM 0F035H data ~ ~ data ← 55H data 0C35H ~ ~ A 35H,#55H ~ ~ 0F100H 07 0F101H 35 0F102H F0 A+data+C → A P address: 0F035 ~ ~ þ A 0F100H E4 0F101H 55 0F102H 35 Nov. 1999 Ver 1.0 PRELIMINARY 25 PRELIMINARY GMS81C4040/87C4060 X indexed direct page, auto increment→ → {X}+ The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135H regardless of G-flag and DPGR. ;A ←ROM[135H] F100: 983501 INC!0135H In this mode, a address is specified within direct page by the X register and the content of X is increased by 1. LDA, STA Example; G=0, X=35H F100: DB 135H data ~ ~ LDA {X}+ à À ~ ~ 35H data+1 → data 0F100H 98 þ 0F101H 35 address: 0135 0F102H 01 À data ~ ~ data → A ~ ~ þ 0F100H 36H → X DB (5) Indexed Addressing X indexed direct page (no offset) → {X} X indexed direct page (8 bit offset) → dp+X In this mode, a address is specified by the X register. This address value is the second byte (Operand) of command plus the data of -register. And it assigns the memory in Direct page. ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Example; X=15H, G=1, DPGR=03H E550: D4 LDA {X};ACC←RAM[X]. ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY, XMA, ASL, DEC, INC, LSR, ROL, ROR Example; G=0, X=0F5H E550: C645 315H data ~ ~ data → A ~ ~ 3AH data à D4 ~ ~ 26 45H+X À þ 0E550H LDA ~ ~ 0E550H C6 0E551H 45 PRELIMINARY À data → A þ 45H+0F5H=13AH Nov. 1999 Ver 1.0 PRELIMINARY Y indexed direct page (8 bit offset) → dp+Y GMS81C4040/87C4060 FA00: 3F35 JMP [35H] This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead of X. 35H 0A 36H E3 Y indexed absolute → !abs+Y ~ ~ Sets the value of 16-bit absolute address plus Y-register data as Memory. This addressing mode can specify memory in whole area. Example; Y=55H F100: D500FA LDA D5 0F101H 00 0F102H FA ~ ~ ~ ~ ~ ~ 35 þ X indexed indirect → [dp+X] 0FA00H+55H=0FA55H Processes memory data as Data, assigned by 16-bit pair m em ory w hich is deter mined by pair data [dp+X+1][dp+X] Operand plus X-register data in Direct page. À data → A data þ 3F !0FA00H+Y ~ ~ À jump to address 0E30AH NEXT 0FA00H 0F100H 0FA55H 0E30AH ~ ~ à ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, X=10H FA00: 1625 ADC [25H+X] (6) Indirect Addressing Direct page indirect → [dp] Assigns data address to use for accomplishing command which sets memory data(or pair memory) by Operand. Also index can be used with Index register X,Y. JMP, CALL 35H 05 36H E0 ~ ~ À ~ ~ 0E005H 0FA00H PRELIMINARY 25 + X(10) = 35H ~ ~ 16 25 Nov. 1999 Ver 1.0 þ data ~ ~ Example; G=0 0E005H à A + data + C → A 27 PRELIMINARY GMS81C4040/87C4060 Y indexed indirect → [dp]+Y Absolute indirect → [!abs] Processes momory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Direct page plus Y-register data. The program jumps to address specified by 16-bit absolute address. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0 Example; G=0, Y=10H FA00: 1725 JMP FA00: 1F25E0 ADC JMP [!0C025H] [25H]+Y PROGRAM MEMORY 25H 05 0E025H 25 26H E0 0E026H E7 ~ ~ 0E015H ~ ~ 0FA00H ~ ~ þ 0E725 H ~ ~ 0FA00H 17 À jump to address 0E30AH NEXT ~ ~ ~ ~ 25 28 0E005 H + Y(10) = 0E015H þ data ~ ~ À ~ ~ 1F 25 à A + data + C → A PRELIMINARY E0 Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 9. I/O PORTS The GMS81C4040/GMS87C4060 has digital ports (R0, R1, R2, R4, R5 and R6) and OSD ports (R,G,B). These ports pins may be multiplexed with an alternate function for the peripheral features on the device. In general, in a initial reset state, R ports are used as a general purpose digital port. 9.1 Registers for Port Port Data Registers The Port Data Registers in I/O buffer in each R ports are represented as a Type D flip-flop, which will clock in a value from the internal bus in response to a "write to data register" signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a "read data register" signal from the CPU. The level of the port pin itself is placed on the internal bus in response to "read data register" signal from the CPU. Some instructions that read a port activating the "read register" signal, and others activating the "read pin" signal ister) during initial setting as shown in Figure 9-1 . All the port direction registers in the GMS81C4040/ GMS87C4060 have 0 written to them by reset function. On the other hand, its initial status is input. WRITE "55H" TO PORT R0 DIRECTION REGISTER 0C0H R0 DATA 0C1H R0 DIRECTION Port Direction Registers ~ ~ All pins have data direction registers which can define these ports as output or input. A "1" in the port direction register configure the corresponding port pin as output. Conversely, write "0" to the corresponding bit to specify it as input pin. For example, to use the even numbered bit of R0 as output ports and the odd numbered bits as input ports, write "55H" to address 0C1H (R0 port direction reg- Nov. 1999 Ver 1.0 BIT ~ ~ 0C8H R4 DATA 0C9H R4 DIRECTION PRELIMINARY 0 1 0 1 0 1 0 1 7 6 5 4 3 2 1 0 I O I O I O I O PORT 7 6 5 4 3 2 1 0 I : INPUT PORT O : OUTPUT PORT Figure 9-1 Example of port I/O assignment 29 PRELIMINARY GMS81C4040/87C4060 9.2 I/O Ports Configuration R0 Ports The control registers for R1 are shown below. R0 is an 8-bit CMOS bidirectional I/O port (address 0C0H). Each I/O pin can independently used as an input or an output through the R0DD register (address 0C1H). ADDRESS : 00C2H RESET VALUE : Undefined R1 Data Register RW R1 R17 RW R16 RW R15 RW R14 RW RW RW RW R13 R12 R11 R10 The control registers for R0 are shown below. ADDRESS : 00C3H RESET VALUE : 0000 0000b R1 Direction Register ADDRESS : 00C0 H RESET VALUE : Undefined R0 Data Register R0 RW RW RW RW RW RW RW RW R07 R06 R05 R04 R03 R02 R01 R00 W W W W W W W W W W W RW A/D Enable 0: Disable 1: Enable AN0 (A/D input 0) AN1 (A/D input 1) AN2 (A/D input 2) AN3 (A/D input 3) AN4 (A/D input 4) AN5 (A/D input 5) VD (Vertical Sync. input) HD (Horizontal Sync. input) RW RW R A/D Status 0: Busy A/D Port select 1: Finish 000: AN0 001: AN1 A/D Start 010: AN2 0: Ignore 011: AN3 1: A/D start 100: AN4 101: AN5 110: AN6 111: No Analog port R1 Ports R1 is an 8-bit CMOS bidirectional I/O port (address 0C2H). Each I/O pin can independently used as an input or an output through the R1DD register (address 0C3H). R1 port have secondary functions as following table. RW RW ADEN ADS2 ADS1 ADS0 ADST ADSF ADCM In addition, Port R0 is only digital I/O. After reset, R0DD value is "0", R0 acts as normal digital input port. Alternate Function W ADDRESS : 00F0H RESET VALUE : --01 1101b A/D Convertor mode Register Port Direction 0: Input 1: Output R10 R11 R12 R13 R14 R15 R16 R17 W Port Direction 0: Input 1: Output R0DD Port Pin W ADDRESS : 00C1H RESET VALUE : 0000 0000b R0 Direction Register W W R1DD Analog input pin selector Register W W W ADDRESS : 00EFH RESET VALUE : --00 0000b W W W AIPS Port Property 0: Digital I/O 1: Analog Input ADDRESS : 00CFH RESET VALUE : ---0 0000b Port function select Register 2 FUNC2 W W W W W HDS VDS YMS YSS IS R16/VD select 0: R16 I/O 1: VD Input R17/HD select 0: R17 I/O 1: HD Input Port R1 is multiplexed with various special features.The control registers controls the selection of alternate function. After reset, R1 port acts as normal digital input port. The way to select alternate function such as A/D input or HD,VD will be shown in each peripheral section. 30 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 R2 Port R4 Port R2 is an 8-bit CMOS bidirectional I/O port (address 0C4H). Each I/O pin can independently used as an input or an output through the R2DD register (address 00C5H). R4 is consrutced with 4-bit Open drain Output port and 4bit CMOS bidirectional I/O port (address 0C8H). Each I/O pin can independently used as an input or an output through the R4DD register (address 0C9H). The control registers for R2 are shown below. The control registers for R4 are shown below. ADDRESS : 00C4 H RESET VALUE : Undefined R2 Data Register RW R27 R2 RW R26 RW R25 RW R24 RW R23 RW R22 RW R21 R4 W W W W W W RW RW RW RW RW RW RW RW R47 R46 R45 R44 R43 R42 R41 R40 R20 ADDRESS : 00C5H RESET VALUE : 0000 0000b R2 Direction Register ADDRESS : 00C8H RESET VALUE : Undefined R4 Data Register RW W W W R2DD ADDRESS : 00C9H RESET VALUE : 0000 ----b R4 Direction Register W W W W W W Port Direction 0: Input 1: Output RW IOSW SIOM Serial I/O 0: Serial In 1: Serial Out RW RW SM1 SM0 RW RW W W RW ICCR1 W R22 R22 Sout R22 R22 R21 R21 Sclk Sclk R21 W W W BSW1 BSW0 0 0 1 0 0 1 1 1 W W RW RW RW BC2 BC1 BC0 W R44 R44 SCL0 R44 SCL Bit count 000b (8bit) 001b~111b (1~7bit) R45 R45/PWM4 R45/PWM4 SCL1 SCL PWMCR1 W R46 R46 SDA0 R46 SDA R47 R47/PWM5 R47/PWM5 SDA1 SDA ADDRESS : 00EAH RESET VALUE : 0000 0000b PWM control Register 1 ADDRESS : 00F2H RESET VALUE : --00 0000b W RW ESO Slave address identification 0: Accept (Addressing format) 1: Decline (Free data format) R23 R23 R23 Sin R23 R20/INT2 R24/INT3 0: R20 1: INT2 R26/INT4 0: R24 1: INT3 0: R26 1: INT4 Ext. interrupt edge selection Register RW ALS Serial Start 0: Ignore 1: Serial start EC3S EC2S INT4S INT3S INT2S INT1S INT0S R27/EC3 0: R27 1: EC3 R25/EC2 0: R25 1: EC2 RW BSW1 BSW0 I2C enable 0: Disable 1: Enable ADDRESS : 00CEH RESET VALUE : -000 0000b W ADDRESS : 00DBH RESET VALUE : 00-0 0000b I2C Control Register 1 R Seriial Status 0: Busy 1: Finish Clock select 00: PS3 01: PS4 10: PS5 11: External Port function select Register 1 IEDS RW SCK1 SCK0 SIOST SIOSF SM1 SM0 Mode 0 0 Send 1 0 Receive 0 1 1 1 W Port Direction 0: Input 1: Output ADDRESS : 00DEH RESET VALUE : -000 0001b Serial I/O mode Register FUNC1 W R4DD RW RW RW RW RW RW RW RW EN5 EN4 EN3 EN2 EN1 EN0 EN8 CNT EN5,4,3,2,1 : R47,45,43,42,41,40 0: R4x acts normal digital port 1: R4x acts PWM output port 14/8bit PWM count 0: Count start 1: Count stop R51/PWM8 select 0: R51 1: PWM8 IED2H IED2L IED1H IED1L IED0H IED0L INT2 Nov. 1999 Ver 1.0 00: Ignore edge 01: Falling edge 10: Rising edge 11: Falling/Rising edge PRELIMINARY 31 PRELIMINARY GMS81C4040/87C4060 R5 Port R6 Port R5 is an 7-bit port (address 0CAH). Each I/O pin can independently used as an input or an output through the R5DD register (address 0CBH). R6 is an 1-bit CMOS bidirectional I/O port (address 0CCH). Each I/O pin can independently used as an input or an output through the R6DD register (address 0CDH). The control registers for R5 are shown below The control registers for R6 are shown below ADDRESS : 00CAH RESET VALUE : Undefined R5 Data Register RW R5 R56 RW R55 RW R54 RW R53 RW R52 RW R51 RW RW R6 R50 ADDRESS : 00CBH RESET VALUE : ---- 0000b R5 Direction Register W W W ADDRESS : 00CCH RESET VALUE : Undefined R6 Data Register R67 ADDRESS : 00CDH RESET VALUE : 0--- ----b R6 Direction Register W W R5DD R6DD Port Direction 0: Input 1: Output ADDRESS : 00CEH RESET VALUE : -000 0000b Port function select Register 1 W FUNC1 W W Port Direction 0: Input 1: Output W W W W EC3S EC2S INT4S INT3S INT2S INT1S INT0S ADDRESS : 00CEH RESET VALUE : -000 0000b Port function select Register 1 W FUNC1 W W W W W R52/INT0 0: R52 1: INT0 ADDRESS : 00CFH RESET VALUE : ---0 0000b Port function select Register 2 FUNC2 W W W W W HDS VDS YMS YSS IS R67/INT1 0: R67 1: INT1 Ext. interrupt edge selection Register W IEDS R54/YM R55/YS R56/I 0: R56 0: R55 0: R56 1: YM Output 1: YS Output 1: I Output ADDRESS : 00EBH RESET VALUE : --0- 0000b PWM control Register 2 RW PWMCR2 RW BUZS RW RW RW POL2 POL1 EN7 EN6 W EC3S EC2S INT4S INT3S INT2S INT1S INT0S W W ADDRESS : 00F2H RESET VALUE : --00 0000b W W W IED2H IED2L IED1H IED1L IED0H IED0L INT1 00: Ignore edge 01: Falling edge 10: Rising edge 11: Falling/Rising edge R50/BUZZ 0: R50 1: BUZZ Ext. interrupt edge selection Register W IEDS W W ADDRESS : 00F2H RESET VALUE : --00 0000b W W W IED2H IED2L IED1H IED1L IED0H IED0L 00: Ignore edge INT2 01: Falling edge 10: Rising edge 11: Falling/Rising edge 32 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 10. CLOCK GENERATOR As shown in Figure 10-1 , the clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and the peripheral hardware. It contains two oscillators: a main-frequency clock oscillator and a sub-frequency clock oscillator. The system clock can also be obtained from the external oscillator. The clock generator produces the system clocks forming clock pulse, which are supplied to the CPU and the peripheral hardware. 3.6MHz 1,111nS 4MHz 1,000nS 8MHz 500nS To the peripheral block, the clock among the not-divided original clocks, divided by 2, 4,..., up to 1024 can be provided. Peripheral clock is enabled or disabled by bit 4 of the peripheral clock enable register (ENPCK). fEX OSC Circuit Minimum instruction cycle time (ex:NOP ; fex 4clock is needed) Main clock Internal system clock Clock pulse Generator P R E SC A LE R ENPCK [0D6H] PS7 PS8 ÷64 ÷128 ÷256 ÷2048 PS6 ÷32 ÷1024 PS5 ÷16 PS11 PS4 ÷8 PS10 PS3 ÷4 ÷512 PS2 ÷2 PS9 PS1 Clock control register ÷1 WDT ENPCK BTCL BTS2 BTS1 BTS0 ON PS0 CKCTLR Peripheral clock Figure 10-1 Block Diagram of Clock Generator Note: On the initial reset, all peripherals are run because peripheral clock is supplied to each function block. If you want to see more details, see Clock Control Register (CKCTLR). ADDRESS : 00D6H RESET VALUE : --01 0111b Clock control register W CKCTLR Watch-dog timer select 0: Normal 6bit timer 1: Watch-dog timer Nov. 1999 Ver 1.0 PRELIMINARY W W W W W WDT ENPCK BTCL BTS2 BTS1 BTS0 ON Peri. Clock 0: Stop 1: Supply B.I.T Clock B.I.T set 0: Free run 1: B.I.T clear 33 PRELIMINARY GMS81C4040/87C4060 11. TIMER 11.1 Basic Interval Timer The GMS81C4040/GMS87C4060 has one 8-bit Basic Interval Timer that is free-run and can not be stopped. Block diagram is shown in Figure 11-1 . generated. The Basic Interval Timer is controlled by the clock control register (CKCTLR) shown in Figure 11-2 . Source clock can be selected by lower 3 bits of CKCTLR. The Basic Interval Timer generates the time base for watchdog timer counting, and etc. It also provides a Basic interval timer interrupt (BITIF). As the count overflow from FFH to 00H, this overflow causes the interrupt to be PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 fex÷24 fex÷25 fex÷26 fex÷27 fex÷28 fex÷29 MUX source clock 8-bit up-counter overflow BITIF BITR [0D6H] fex÷210 fex÷211 Basic Interval Timer Interrupt Watchdog timer clock (WDTCK) clear Select Input clock Clock control register [0D6H] CKCTLR BITR and CKCTLR are located at same address, and address 00D6H is read as a BITR and written to CKCTLR.. 3 BITCK BTCL WDT ENPCK BTCL BTS2 BTS1 BTS0 ON Internal bus line Figure 11-1 Block Diagram of Basic Interval Timer Source clock Interrupt (overflow) Period P re-S caler output At fex=8MHz BTS2~0 000 001 010 011 100 101 110 111 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 fex÷24 fex÷25 fex÷26 fex÷27 fex÷28 fex÷29 fex÷210 fex÷211 0.512 mS 1.024 2.048 4.096 8.192 16.384 32.768 65.536 Table 11-1 Basic Interval Timer Interrupt Time 34 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY W CKCTLR W W W W W ADDRESS : 00D6H RESET VALUE : --01 0111b WDT ENPCK BTCL BTS2 BTS1 BTS0 ON Watch-dog timer select 0: Normal 6bit timer 1: Watch-dog timer GMS81C4040/87C4060 B.I.T Clock B.I.T set 0: Free run 1: Clear 8-bit counter (BITR) to "0". This bit becomes 0 automatically after 1 machine cycle Peri. Clock 0: Stop 1: Supply Caution: Both register are in same address, when write, to be a CKCTLR, when read, to be a BITR. R R R R R R R R ADDRESS: 00D6H INITIAL VALUE: Undefined BITR 8-BIT BINARY COUNTER Figure 11-2 BITR: Basic Interval Timer Mode Register 11.2 Timer 0, 1 Timer 0, 1 consists of prescaler, multiplexer, 8-bit compare data register, 8-bit count register, Control register, and Comparator as shown in Figure 11-3 . These Timers can run separated 8bit timer or combined 16bit timer. These timers are operated by internal clock. The contents of TDR1 are compared with the contents of up-counter T1. If a match is found, a timer/counter 1 interrupt (T1IF) is generated, and the counter is cleared. Counting up is resumed after the counter is cleared. Note: You can read Timer 0, Timer 1 value from TDR0 or TDR1. But if you write data to TDR0 or TDR1, it changes Timer 0 or Timer 1 modulo data, not Timer value. The control registers for Timer 0,1 are shown below. RW TM0 T1ST RW RW RW T1SL1 T1SL0 T0ST RW RW RW T0CN T0SL1 T0SL0 Timer 0 input clock 00: PS2 (fex / 22) 01: PS4 (fex / 24) 10: PS6 (fex / 26) 11: PS8 (fex / 28) Timer 1 start 0: Count Hold 1: Count Clear and Start Timer 1 input clock 00: Timer 0 overflow (16bit mode) Timer 0 control 01: PS2 (fex / 22) 0: Count Hold 10: PS4 (fex / 24) 1: Count Continue Timer 0 start 11: PS6 (fex / 26) 0: Count Hold 1: Count Clear and Start ADDRESS : 00D2H RESET VALUE : Undefined Timer 0 data register RW The content of TDR0, TDR1 must be initialized (by software) with the value between 01H and FFH,not to 00H. Or not, Timer 0 or Timer 1 can not count up forever. ADDRESS : 00D0H RESET VALUE : -000 0000b Timer mode register 0 RW RW RW RW RW RW RW TDR0 ADDRESS : 00D3H RESET VALUE : Undefined Timer 1 data register RW RW RW RW RW RW RW RW TDR1 Nov. 1999 Ver 1.0 PRELIMINARY 35 PRELIMINARY GMS81C4040/87C4060 . Internal bus line TM0 TDR0 TDR1 T0CN PS2 PS4 PS6 PS8 8bit Comparator 8bit Comparator T0IF T1IF Timer 0 Timer 1 MUX Clock Clear Clock Clear T0ST NC PS2 PS4 PS6 MUX T1ST Figure 11-3 Simplified Block Diagram of 8bit Timer0, 1 TDR0 disable ou nt ~~ clear & start enable up -c stop ~~ TIME Timer 0 (T0IF) Interrupt Occur interrupt Occur interrupt T0ST Start & Stop T0CN Control count T0ST = 1 T0ST = 0 T0CN = 1 T0CN = 0 Figure 11-4 Count Example of Timer 36 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 Internal bus line TM0 TDR0 TDR1 0 0 T0CN 16bit Comparator T1IF PS2 PS4 PS6 PS8 Timer 0 Timer 1 MUX Clock Clear Clock Clear T0ST Figure 11-5 Simplified Block Diagram of 16bit Timer0, 1 11.3 Timer / Event Counter 2, 3 Timer 2, 3 consists of prescaler, multiplexer, 8-bit compare data register, 8-bit count register, Control register, and Comparator as shown in Figure 11-5 . The control registers for Timer 2,3 are shown below RW These Timers have two operating modes. One is the timer mode which is operated by internal clock, other is event counter mode which is operated by external clock from pin R25/EC2, R27/EC3. These Timers can run separated 8bit timer or combined 16bit timer. Note: You can read Timer 2, Timer 3 value from TDR2 or TDR3. But if you write data to TDR2 or TDR3, it changes Timer 2 or Timer 3 modulo data, not Timer value. TM2 T3ST RW RW RW T3SL1 T3SL0 T2ST RW RW RW T2CN T2SL1 T2SL0 Timer 2 input clock 00: PS2 (fex / 22) 01: PS4 (fex / 24) 10: PS6 (fex / 26) 11: PS8 (fex / 28) Timer 3 start 0: Count Hold 1: Count Clear and Start Timer 3 input clock 00: Timer 2 overflow (16bit mode) Timer 2 control 01: PS2 (fex / 22) 0: Count Hold 10: PS4 (fex / 24) 1: Count Continue Timer 2 start 11: PS6 (fex / 26) 0: Count Hold 1: Count Clear and Start ADDRESS : 00D4H RESET VALUE : Undefined Timer 2 data register RW The content of TDR2, TDR3 must be initialized (by software) with the value between 01H and FFH,not to 00H. Or not, Timer 2 or Timer 3 can not count up forever. ADDRESS : 00D1H RESET VALUE : -000 0000b Timer mode register 2 RW RW RW RW RW RW RW RW RW RW TDR2 ADDRESS : 00D5H RESET VALUE : Undefined Timer 3 data register RW RW RW RW RW TDR3 ADDRESS : 00CEH RESET VALUE : -000 0000b Port function select Register 1 W FUNC1 W W R27/EC3 0: R27 1: EC3 Nov. 1999 Ver 1.0 PRELIMINARY W W W W EC3S EC2S INT4S INT3S INT2S INT1S INT0S R25/EC2 0: R25 1: EC2 37 PRELIMINARY GMS81C4040/87C4060 . Internal bus line TM2 TDR2 TDR3 T2CN EC2 PS2 PS4 PS6 8bit Comparator 8bit Comparator T2IF T3IF Timer 2 Timer 3 MUX Clock Clear Clock Clear T2ST NC EC3 PS2 PS4 MUX T3ST Figure 11-6 Simplified Block Diagram of 8bit Timer/Event Counter 2,3 TDR2 disable ou nt ~~ clear & start enable up -c stop ~~ TIME Timer 2 (T2IF) Interrupt Occur interrupt Occur interrupt T2ST Start & Stop T2CN Control count T2ST = 1 T2ST = 0 T2CN = 1 T2CN = 0 Figure 11-7 Count Example of Timer / Event counter 38 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 Internal bus line TM2 TDR2 TDR3 0 0 T0CN 16bit Comparator T3IF EC2 PS4 PS6 PS8 Timer 2 Timer 3 MUX Clock Clear Clock Clear T0ST Figure 11-8 Simplified Block Diagram of 16bit Timer/Event Counter 2,3 Timer Mode n interrupt (TnIF) is generated and the up-counter is cleared to 0. Counting up is resumed after the up-counter is cleared. In the timer mode, the internal clock is used for counting up. Thus, you can think of it as counting internal clock input. The contents of TDRn (n=0~3) are compared with the contents of up-counter, Timer n. If match is found, a timer As the value of TDRn is changeable by software, time interval is set as you want Start count 0 TDRn (n=0~3) 1 2 3 N ~ ~ ~ ~ ~ ~ ~ ~ Up-counter ~ ~ Source clock N-2 N-1 N Match Detect TnIF (n=0~3) interrupt 0 1 2 3 4 Counter Clear ~ ~ Figure 11-9 Timer Mode Timing Chart Event counter Mode put. In event timer mode, counting up is started by an external trigger. This trigger means falling edge of the ECn (n=2~3) pin input. Source clock is used as an internal clock selected with TM2. The contents of TDRn are compared with the contents of the up-counter. If a match is found, an TnIF interrupt is generated, and the counter is cleared to 00 H. The counter is restarted by the falling edge of the ECn pin in- The maximum frequency applied to the ECn pin is fex/2 [Hz] in main clock mode. Nov. 1999 Ver 1.0 In order to use event counter function, the bit EC2S, EC3 of the Port Function Select Register1 FUNC1(address 0CEH) is required to be set to "1". After reset, the value of TDRn is undefined, it should be PRELIMINARY 39 PRELIMINARY GMS81C4040/87C4060 initialized to between 01H~FFH not to 00H Start count ~ ~ ECn (n=2~3) pin 1 0 2 N-1 N 0 1 2 ~ ~ ~ ~ TDRn (n=2~3) ~ ~ ~ ~ Up-counter N TnIF (n=2~3) interrupt ~ ~ Figure 11-10 Event Counter Mode Timing Chart The interval period of Timer is calculated as below equation. - × = ------ × TDR2 TDR2=n co un t ~~ up - PCP ~~ 8 ~~ n n-1 n-2 7 6 5 4 3 2 1 0 TIME Interrupt period = PCP x n Timer 2 (T2IF) Interrupt Occur interrupt Occur interrupt Occur interrupt Figure 11-11 Count Example of Timer / Event counter 40 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 TDR2 disable up -c ou nt ~~ clear & start enable stop ~~ TIME Timer 2 (T2IF) Interrupt Occur interrupt Occur interrupt T2ST Start & Stop T2CN Control count T2ST = 1 T2ST = 0 T2CN = 1 T2CN = 0 Figure 11-12 Count Operation of Timer / Event counter Nov. 1999 Ver 1.0 PRELIMINARY 41 PRELIMINARY GMS81C4040/87C4060 12. A/D Converter The A/D convertor circuit is shown in Figure 12-1 . The A/D convertor circuit consists of the comparator and c o n t r o l r eg i s te r A I P S ( 0 0 E F H ) , A D C M ( 0 0 F 0 H ) , ADR(00F1H). The AIPS register select normal port or an- alog input. The ADCM register control A/D converter’s activity. The ADR register stores A/D converted 8bit result. The more details are shown Figure 12-2 . ADEN ADS2 ADS1 ADS0 ADST ADSF ADCM [F0H] ADR [F1H] IFA Control circuit port select AN0 Comparator AN1 S/H AN2 AN3 MUX Vref AN4 + − Succesive Approximation Circuit AN5 Register ladder Figure 12-1 Block Diagram of A/D convertor circuit Control ; 1 : analog port LDM AIPS,#00??????b ; Set ADEN, xxx is analog port number LDM ADCM,#001xxx00b ; or “SET1 ADEN” ; Set ADST, xxx is analog port number LDM ADCM,#001xxx10b ; or “SET1 ADST” : : The GMS81C4040/GMS87C4060 contains a A/D converter module which has six analog inputs. 1. First of all, you have to select analog input pin by set the ADCM and AIPS. 2. Set ADEN (A/D enable bit : ADCM bit5). 3. Set ADST (A/D start bit : ADCM bit1). We recommend you do not set ADEN and ADST at once, it makes worse A/D converted result. 4. ADST bit will be cleared automatically 1cycle after you set this. Example: : ; Set AIPS, change ? to what you want ; 0 : digital port 42 5. After A/D conversion is completed, ADSF bit and interrupt flag IFA will be set. (A/D conversion takes 36 machine cycle : 9uS when fex=8MHz). Note: Make sure AIPS bits, if you using a port which is set digital input by AIPS, analog voltage will be flow into MCU internal logic not A/D converter. Sometimes device or port is damaged permanently. PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY ADDRESS : 00F0H RESET VALUE : --01 1101b A/D Convertor mode Register RW RW GMS81C4040/87C4060 RW RW RW R ADEN ADS2 ADS1 ADS0 ADST ADSF ADCM A/D Enable 0: Disable 1: Enable A/D Status 0: Busy A/D Port select 1: Finish 000: AN0 001: AN1 A/D Start 010: AN2 0: Ignore 011: AN3 1: A/D start 100: AN4 101: AN5 11x: No Analog port ADDRESS : 00F1H RESET VALUE : Undefined A/D Result Register R R R R R R R R ADR 8bit result is stored ADDRESS : 00EFH RESET VALUE : --00 0000b Analog input pin selector Register W W W W W W AIPS Port Property 0: Digital I/O 1: Analog Input Figure 12-2 A/D convertor Registers Nov. 1999 Ver 1.0 PRELIMINARY 43 PRELIMINARY GMS81C4040/87C4060 13. Serial I/O The Serial I/O circuit is shown in Figure 13-1 . The Serial I/O circuit consists of the octal counter, SIOR(DFH), SIOM(DEH). The SIOR register stores received IOSW SM1 SIOM [DEH] SM0 SCK1 SCK0 SIOST SIOSF data or data which will be transfered. The SIOM register controls serial communication mode, speed, start, etc. The more details about registers are shown Figure 13-2 . SIOR [DFH] D7 D6 D5 D4 D3 D2 D1 D0 PS3 PS4 PS5 Exclk MUX Control Circuit IFSIO Octal counter Sclk Sout 1 MUX Sin 0 Figure 13-1 Block Diagram of Serial I/O circuit Control The GMS81C4040/GMS87C4060 contains a Synchronous type Serial I/O module. 1. You have to select serial I/O pins by set the SM1~0. Port select SM1 SM0 Function R21 R22 R23 0 0 - R21 R22 R23 0 1 Send Sclk Sout R23 1 0 Receive Sclk R22 Sin 1 1 - R21 R22 R23 2. You have to select serial communication clock by set the SCK1~0. SCK1 SCK0 Selected Clock Ex: Frequency (fex=8MHz) 0 0 PS3 1uS 0 1 PS4 2uS 1 0 PS5 4uS 1 1 External clock User define 3. If you want to send data, write it to SIOR. Or not skip this. 4. Start serial communication by set SIOST(Serial I/O start, SIOM bit1). Note: Sout pin can handle serial data output or serial data input. You can input serial data to Sout pin when IOSW bit is 1. But Sin pin is dedicated serial data input pin. 44 5. After serial communication is completed, SIOSF bit and interrupt flag IFSIO will be set. PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY ADDRESS : 0DEH RESET VALUE : -000 0001b Serial I/O mode Register RW SIOM GMS81C4040/87C4060 RW RW IOSW SM1 SM0 RW RW RW Serial Status 0: Busy 1: Finish Clock Select Input select 0: Sin 1: Sout Serial I/O Interrupt Service routine R SCK1 SCK0 SIOST SIOSF Send / Receive No SIOSF=1? Serial COMM. Start 0: Ignore 1: COMM. start Yes Abnormal operation Serial I/O data Register SIOR SE=0 ADDRESS : 0DFH RESET VALUE : Undefined RW RW RW RW RW RW RW RW D7 D6 D5 D4 D3 D2 D1 D0 // SE : Interrupt enable bit Write SIOM // SR : Interrupt request flag No Figure 13-2 Serial I/O Registers SR=0? Yes Overrun error Normal operation Figure 13-3 Example for serial I/O check by S/W Input clock Sclk SIOST Sout D0 D1 D2 D3 D4 D5 D6 D7 Sin D0 D1 D2 D3 D4 D5 D6 D7 IFSIO Figure 13-4 Serial I/O Timing Chart Nov. 1999 Ver 1.0 PRELIMINARY 45 PRELIMINARY GMS81C4040/87C4060 14. Pulse Width Modulation (PWM) The PWM circuit is shown in Figure 14-1 , Figure . 14bit PWM 8bit PWM Resolution 0.5uS 4uS Input Clock 2MHz 250KHz Frame cycle 8,192uS 1,024uS The PWM control registers are PWMR7~0, PWMCR2~1, PWM8H, PWM8L. The more details about registers are shown Figure 14-2 . PWMCR1 [EAH] EN5 PWMCR2 [EBH] EN4 EN3 EN2 EN1 EN0 Example (fex =8MHz) The PWM circuit consists of the counter, comparator, Data register. CNTB PWM5 PWMR5 [E5H] PWM4 PWMR4 [E4 H] PWM3 PWMR3 [E3H] PWM2 PWMR2 [E2H] PWM1 PWMR1 [E1H] PWMR0 [E0 H] PWM0 8bit comparator PS5 IF1Frame 8bit counter Internal Control Figure 14-1 8bit register (PWM7~0) circuit PWMR8H 8bit [E8H] PWMCR1 [EAH] EN8 PWMCR2 [EBH] CNTB PWMR8L 6bit [E9H] PWM8 MSB 14bit comparator LSB PS2 14bit counter Figure 14-2 14bit register (PWM8) circuit 46 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY 8bit PWM Control The GMS81C4040/GMS87C4060 contains a one 14bit PWM and six 8bit PWM module. 1. 8bit PWM0~5 is wholy same internal circuit, but PWM0~5 output port is NMOS open drain. 2. Al l PWM polarity has the same by POL2’s value. 3. Calulate Frame cycle and Pulse width is as following. PWM Frame Cycle = 2 13/ fex (Sec) PWM Width = (PWMRn+1) * 2 5 / f ex (n=0~5) Pulse Duty (%) = (PWMRn +1) / 256 *100(%) (n=0~5) Positive Polarity (POL2=0) Negative Polarity (POL2=1) 1 1 2 2 5. CNTB controls all PWM counter enable. If CNTB=0, Counter is enabled. 14bit PWM Control 1. 14bit PWM’s operation concept is not the same as 8bit PWM. 1 PWM frame contains 64 sub PWMs. PWM8H : Set sub PWM’s basic Pulse Width. PWM8L : Number of sub PWM which is added 1 clock. 2. PWM polarity is selected by POL1’s value. If POL1=0, Positive Polarity. 3. Calulate Frame cycle and Pulse width is as following. Main PWM Frame Cycle = 216/ fex (Sec). Sub PWM Frame Cycle = Main Frame Cycle / 64. 4. Table 14-1, “PWM8L and Sub frame matching table,” on page 47 show PWM8L function. Bit value 1. Frame cycle 2. Pulse Width Figure 14-3 Wave form example for 8bit PWM 4. PWM output is enabled during ENn(n=0~5) bit (See PWMCR1~2) contains 1. ADDRESS : 0E0~E5H RESET VALUE : Undefined PWM Data Register PWMR0~5 W W W W W W W W D7 D6 D5 D4 D3 D2 D1 D0 ADDRESS : 0EAH RESET VALUE : 0000 0000 b PWM control Register 1 PWMCR1 RW RW RW RW RW RW RW RW EN5 EN4 EN3 EN2 EN1 EN0 EN8 CNTB EN5,4,3,2,1 : R47,45,43,42,41,40 0: R4x acts normal digital port 1: R4x acts PWM output port RW BUZS Pulse count if Bit0=1 32 1 if Bit1=1 16, 48 2 if Bit2=1 8, 24, 40, 56 4 if Bit3=1 4, 12, 20, 28, 36, 44, 52, 60 8 if Bit4=1 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54 16 if Bit5=1 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63 32 Table 14-1 PWM8L and Sub frame matching table Main PWM Frame 14bit Counter enable 0: Counter run 1: Counter stop 0 1 2 61 62 63 ..... RW RW Sub PWM Frame POL2 POL1 8bit PWM Polarity 0: Positive (PWM from Rising edge) 1: Negative (PWM from Rising edge) Figure 14-4 8bit PWM Registers Nov. 1999 Ver 1.0 Sub frame number which is added 1 clock ADDRESS : 0EBH RESET VALUE : --0- 00--b PWM control Register 2 PWMCR2 GMS81C4040/87C4060 Sub PWM Frame which is added 1 clock 1 clock width : PS2 Figure 14-5 Wave form example for 14bit PWM PRELIMINARY 47 PRELIMINARY GMS81C4040/87C4060 5. PWM output is enabled during EN8 bit contains 1. ADDRESS : 0E8H RESET VALUE : Undefined PWM Width Data Register PWM8H RW RW RW RW RW RW RW RW D7 D6 D5 D4 D3 D2 D1 D0 ADDRESS : 0E9H RESET VALUE : Undefined PWM Sub-pulse count Register PWM8L RW RW RW RW RW RW D5 D4 D3 D2 D1 D0 ADDRESS : 0EAH RESET VALUE : 0000 0000b PWM control Register 1 PWMCR1 RW RW RW RW RW RW RW RW EN5 EN4 EN3 EN2 EN1 EN0 EN8 CNTB 14bit PWM enable 0: R51 1: PWM8 PWMCR2 BUZS 14bit Counter enable 0: Counter run 1: Counter stop ADDRESS : 0EBH RESET VALUE : --0- 00--b PWM control Register 2 RW 6. CNTB controls PWM counter enable. If CNTB=0, Counter is enabled. RW RW POL2 POL1 14bit PWM Polarity 0: Positive (PWM from Rising edge) 1: Negative (PWM from Rising edge) Figure 14-6 14bit PWM Registers 48 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 15. Interrupt interval measurement circuit The Interrupt interval measurement circuit is shown in Figure 15-1 . tor, 8bit counter, measured result storing register, FIFO (9bit, 6level) interrupt, Control register, etc. The Interrupt interval measurement circuit consists of the input multiplexer, sampling clock multiplexer, Edge detec- The more details about registers are shown Figure 15-2 . IDCR [F9H] PS8 FCLR IMS I34H I34L ISEL IDCK IDST IDFS [FAH] INT3 FFUL FEMP 8bit counter Clear 0 Overflow 8 4 INTV 1 MUX INT4 FOE 1 MUX PS9 DPOL 0 Edge detector 0 MUX FCLR FIFO (9bit, 6level) 1 IDR [FBH] D7 D6 D5 D4 D3 D2 D1 D0 Figure 15-1 Block Diagram of Interrupt interval measurement circuit Control The GMS81C4040/GMS87C4060 contains a Interrupt interval measurement module. 1. Select interrupt input pin what you want to measure by set the FUNC1 [00CEH]. 2. Set IDCR [00F9H] : FIFO clear, interrupt mode, interrupt edge select, external interrupt select between INT3 and INT4, sampling clock select. edge is detected. After data was written, timer is cleard automatically and it counts continue. 5. You can select interrupt occuring point by set Interrupt Mode Select bit (IMS), every edge what you selected or FIFO 4 level is filled. 6. If input signal’s interval is larger than maximum counter value (0FFH), counter occurring an interrupt and count again from 00H. 7. See Figure 15-4 FIFO operating mechanism. 3. Set IDCR [00F9H] : set IDST to start measuring. 4. Counter value is stored to IDR [00FBH] when selected Nov. 1999 Ver 1.0 PRELIMINARY 49 PRELIMINARY GMS81C4040/87C4060 Interrupt interval determination control Register IDCR ADDRESS : 00F9H RESET VALUE : 0000 -000b RW RW RW RW RW RW RW FCLR IMS I34H I34L ISEL IDCK IDST Interrupt input Item Symbol I34H I34L Detecting edge 1 0 Rising edge 0 1 Falling edge 1 1 Both edge 1 1 Both edge Counter control See Figure 15-3 0: stop 1: Clear & count Int. occuring time 0: Every selected Sampling clock select edge by I34H/L 0: PS9 1: Every FIFO 4level 1: PS8 is filled FIFO clear is filled External Interrupt select 0: Ignored 0: INT3 1: Clear and return to 0 1: INT4 Interrupt interval determination FIFO status Register IDFS ADDRESS : 00FAH RESET VALUE : 1--- -001b R R DPOL FOE R R FIFO Empty flag 0: Data filled 1: Empty Data polarity 0: Data is stored every Falling edge 1: Data is stored every Rising edge FIFO Full flag 0: Not full 1: Full FIFO overrun error flag 0: No Error 1: Error detected Interrupt interval determination FIFO Data Register IDR R R R R R R R R D7 D6 D5 D4 D3 D2 D1 D0 W W W Pulse width ADDRESS : 00FBH RESET VALUE : Undefined Figure 15-3 Setting for measurement ADDRESS : 00CEH RESET VALUE : -000 0000b Port function select Register 1 FUNC1 Frame Cycle FFUL FEMP W W W W EC3S EC2S INT4S INT3S INT2S INT1S INT0S R26/INT4 0: R26 1: INT4 R24/INT3 0: R24 1: INT3 Figure 15-2 Int. interval measurement Registers 1) FIFO storing mechanism FEMP=1, FFUL=0 FEMP=0, FFUL=0 FEMP=0, FFUL=0 FEMP=0, FFUL=1 Data 1 Data 1 Data 1 Data 1 Data 2 Data 2 Data 2 Data 3 Data 3 Data 4 Data 4 Data 5 Data 5 Data 6 Data 7 Data in 2) FIFO reading mechanism Read out FEMP=0 Data 1 Read out Data in Data in FEMP=0, FFUL=1 Data in Data 6 will be erased. FOE=1 (Over run error) FEMP=0 FEMP=1 Data 2 Data 2 Figure 15-4 Example for FIFO operating mechanism 50 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 16. Buzzer driver The Buzzer driver circuit is shown in Figure 16-1 . register controls source clock and output frequency. The Buzzer driver circuit consists of the 6bit counter, 6bit comparator, Buzzer data register BUR(00EE H). The BUR The more details about registers are shown Figure 16-2 . BUCK BUCK -1 -0 BUR [EEH] BU5 BU4 BU3 BU2 BU1 BUR write BU0 6 6bit Comparator clear PS4 PS5 PS6 PS7 BUZZ Output Generator 6 00 6bit counter 01 clear 10 11 MUX PWMCR2 [EBH] BUZS POL2 POL1 EN7 EN6 Figure 16-1 Block Diagram of Buzzer driver circuit Control 3. Set BUZS bit for output enable. The GMS81C4040/GMS87C4060 contains a Buzzer driver module. 4. Output waveform is rectagle clock which has 50% duty. 5. You can use this clock for the other purposes. 1. Select an input clock am ong PS4~7 by set the BUCK1~0 of BUR. ADDRESS : 0EEH RESET VALUE : ???? ????b Buzzer data Register BUCK1 BUCK0 Clock source 0 0 PS4 0 1 PS5 1 0 PS6 1 1 PS7 W W BUCK BUCK -1 -0 BUR W W W W W W BU5 BU4 BU3 BU2 BU1 BU0 Input select Clock Select ADDRESS : 0EBH RESET VALUE : --0- 00--b PWM control Register 2 RW PWMCR2 BUZS RW RW POL2 POL1 R50/Buzz select 0: R50 1: Buzz output 2. Select output frequency by change the BU5~0. Output frequency = 1 / (PSx * BUy *2) Hz. x=4~7, y=5~0 See example Table 16-1 and Table 16-2. Figure 16-2 Buzzer driver Registers Note: Do not select 00H to BU5~0. It means counter stop. Nov. 1999 Ver 1.0 PRELIMINARY 51 PRELIMINARY GMS81C4040/87C4060 BUR5~0 Dec Hex 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Output frequency (KHz) BUR5~0 PS4 PS5 PS6 PS7 250 125 83.333 62.5 50 41.666 35.714 31.25 27.728 25 22.728 20.834 19.23 17.858 16.666 15.626 14.706 13.888 13.158 12.5 11.904 11.364 10.87 10.416 10 9.616 9.26 8.928 8.62 8.334 8.064 7.812 7.576 7.352 7.124 6.944 6.756 6.578 6.41 6.25 6.098 5.952 5.814 5.682 5.556 5.434 5.32 5.208 5.102 5 4.902 4.808 4.716 4.63 4.546 4.464 4.386 4.31 4.238 4.166 4.098 4.032 3.968 125 62.5 42.666 31.25 25 20.888 17.858 15.625 13.888 12.5 11.364 10.417 9.615 8.929 8.333 7.813 7.353 6.944 6.579 6.25 5.952 5.682 5.435 5.208 5 4.808 4.63 4.464 4.31 4.167 4.032 3.906 3.788 3.676 3.571 3.472 3.378 3.289 3.205 3.125 3.049 2.976 2.907 2.841 2.778 2.717 2.66 2.604 2.551 2.5 2.451 2.404 2.358 2.315 2.273 2.232 2.193 2.155 2.119 2.083 2.049 2.016 1.984 62.5 31.25 20.833 15.625 12.5 10.461 8.928 7.813 6.944 6.25 5.682 5.209 4.808 4.484 4.166 3.906 3.676 3.472 3.289 3.125 2.976 2.841 2.718 2.604 2.5 2.404 2.315 2.232 2.155 2.084 2.016 1.953 1.894 1.838 1.786 1.736 1.689 1.645 1.602 1.563 1.524 1.488 1.453 1.421 1.389 1.359 1.33 1.302 1.276 1.25 1.225 1.202 1.179 1.157 1.136 1.116 1.096 1.078 1.059 1.042 1.025 1.008 0.992 31.25 15.625 10.436 7.813 6.25 5.208 4.464 3.907 3.472 3.125 2.841 2.604 2.404 2.242 2.083 1.953 1.838 1.736 1.644 1.562 1.438 1.420 1.359 1.302 1.25 1.202 1.158 1.116 1.078 1.042 1.008 0.976 0.947 0.919 0.893 0.868 0.845 0.822 0.801 0.781 0.762 0.744 0.727 0.710 0.694 0.679 0.665 0.651 0.638 0.625 0.613 0.601 0.590 0.579 0.568 0.558 0.548 0.539 0.530 0.521 0.512 0.504 0.496 Dec Hex 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Table 16-1 . Example for fex=8MHz 52 Output frequency (KHz) PS4 PS5 PS6 PS7 375 187.5 125 93.75 75 62.5 53.572 46.875 41.666 37.5 34.09 31.25 28.846 26.786 25 23.436 22.058 20.833 19.736 18.75 17.858 17.045 16.304 15.625 15 14.424 13.888 13.393 12.932 12.5 12.096 11.718 11.364 11.03 10.714 10.416 10.136 9.868 9.616 9.375 9.146 8.929 8.72 8.523 8.334 8.152 7.978 7.813 7.654 7.5 7.352 7.212 7.076 6.944 6.818 6.696 6.578 6.466 6.356 6.25 6.148 6.048 5.952 187.5 93.75 62.5 46.875 37.5 31.25 26.786 23.436 20.833 18.75 17.045 15.625 14.423 13.393 12.5 11.719 11.029 10.417 9.868 9.375 8.929 8.523 8.152 7.813 7.5 7.212 6.944 6.696 6.466 6.25 6.048 5.859 5.682 5.515 5.357 5.208 5.068 4.934 4.808 4.688 4.573 4.464 4.36 4.261 4.167 4.076 3.989 3.906 3.827 3.75 3.676 3.606 3.538 3.472 3.409 3.348 3.289 3.233 3.178 3.125 3.074 3.024 2.976 93.75 46.875 31.35 23.436 18.75 15.625 13.393 11.719 10.417 9.375 8.523 7.813 7.211 6.696 6.25 5.859 5.515 5.208 4.934 4.688 4.464 4.261 4.076 3.906 3.75 3.606 3.472 3.348 3.233 3.125 3.024 2.930 2.841 2.757 2.679 2.604 2.534 2.467 2.404 2.344 2.287 2.232 2.18 2.131 2.083 2.038 1.995 1.953 1.913 1.875 1.838 1.802 1.769 1.736 1.705 1.674 1.645 1.616 1.589 1.563 1.537 1.512 1.488 46.875 23.438 15.625 11.719 9.375 7.813 6.696 5.895 5.208 4.688 4.261 3.906 3.606 3.348 3.125 2.930 2.757 2.604 2.467 2.344 2.232 2.131 2.038 1.953 1.875 1.803 1.736 1.674 1.616 1.563 1.512 1.465 1.420 1.379 1.339 1.302 1.267 1.234 1.202 1.172 1.143 1.116 1.09 1.065 1.042 1.019 0.997 0.977 0.957 0.938 0.919 0.901 0.884 0.868 0.852 0.837 0.822 0.808 0.795 0.781 0.768 0.756 0.744 Table 16-2 . Example for fex=12MHz PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 17. On Screen Display (OSD) The On Screen Display circuit is shown in Figure 17-1 . The GMS81C4040/GMS87C4060 can support 512 OSD chacters, but the last 6 characters (number 506 ~ 511, 1FAH ~ 1FF H) are reserved for IC test and its pattern is fixed by manufacturer. So you can use 506 characters for your own. Line 1,2 Attribute, Position register Line register L1ATTR [AF0H] OSDLN [AE5H] L1VPOS [AF1H] Full screen control register OSDCON1 [AE0H] Horizontal position register Sprite control register OSDCON2 [AE1H] Field detection register LHPOS [AE6 H] L2ATTR [AF3H] The OSD circuit consists of the Position attribute register, Line register, Full screen screen control register, sprite control register, sprite position reigster, I/O polarity register, sprite RAM, font ROM, VRAM, etc. The more details about registers are shown Figure 17-2. Sprite position register SPVPOS [AE8H] I/O polarity register OSDPOL [AE2H] SPHPOS [AE9H] FDWSET [AE3H] Color Mode Register L2VPOS [AF4H] Edge color register COLMOD [0AEFH] EDGECOL [AE4H] OSD Control Circuit Mesh Control Register MESHCON [0AEBH] Sprite Control Circuit VRAM Sprite RAM Font ROM OSD, Sprite Generation Circuit HSYNC VSYNC OSC1 OSC2 Sprite Control Circuit Output Control Circuit R G B I YS YM Synchronization Circuit Figure 17-1 Block Diagram of On Screen Display circuit Nov. 1999 Ver 1.0 PRELIMINARY 53 PRELIMINARY GMS81C4040/87C4060 Character(foreground) - 16 color with half intensity - Color selecting: VRAM n-character bit19~16(see VRAM) Background - 16 color with half intensity - Color selecting :VRAM n-character bit23-20(see VRAM) Characte(foreground) Outline - Controled by LnATTR register(see LnATTR) - 16 color with half intensity - Color selecting : EDGECOL register(see EDGECOL) Character Shadow - Controlled by LnATTR register(see LnATTR) and VRAM n-character bit11-10(see VRAM) - Color selecting : EDGECOL(see EDGECOL) - 16 color with half intensity Background Shadow - Controlled by VRAM n-character bit15-12 - Color selecting : EDGECOL register(see EDGECOL) - 16 color with half intensity (No Character Outline Case) Figure 17-2 OSD Character Font Example 54 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY ADDRESS : 0AE0H RESET VALUE : 0000 0000 b Full screen control Register RW OSDCON1 RW FULM FULI RW RW RW RW RW RW RW STOP OSD clock 0: Release 1: Stop Double dot clock mode 0: Normal 1: Double Double scan line mode 0: Normal 1: Double RW M I B G R Color 0 0 0 1 0 GREEN 0 0 0 1 1 RED+GREEN 0 0 1 0 0 BLUE 0 0 1 0 1 BLUE+RED 0 0 1 1 0 BLUE+GREEN 0 0 1 1 1 RED+GREEN+BLUE (WHITE) 0 1 0 0 0 BLACK 0 1 0 0 1 Half intensity RED 0 1 0 1 0 Half intensity GREEN 0 1 0 1 1 Half intencity RED+GREEN 0 1 1 0 0 Half intensity BLUE 0 1 1 0 1 Half intensity GREEN+BLUE 0 1 1 1 1 Half intensity WHITE 1 0 0 0 0 Half BLANK RW ADDRESS : 0AE1H RESET VALUE : 0000 0000 b Sprite OSD control Register RW RW FULB FULG FULR DLINE DDCLKSTOCK Full screen background FULLM : Half blank FULLI : Half intensity FULLB : Blue FULLG : Green FULLR : Red OSDCON2 RW GMS81C4040/87C4060 RW RW DUSP OBGW ONL2 ONL1 DUSP ENSP PRO CL SD OSD ON OSD, Sprite 0: All Off OSD line 2 1: All On 0: Off 1: On Priority 0: Sprite > OSD OSD line 1 1: OSD > Sprite 0: Off Sprite enable Background width 1: On 0: Disable per 1 character 1: Enable 0: 12dots Sprite size 1: 14dots 0: Normal 1: Double Double sprite dot clock (Sprite size) 0: x1, x2 1: x2, x4 Table 17-1 Full Screen Back ground color selection OSDCON2 bit 0: OSDON Figure 17-3 OSD Control Registers - 1 It controls OSD, Sprite, Full screen background at once. It does not affect anything to Vsync interrupt and OSD interrupt, etc. OSDCON1 bit 0: STOCK It controls OSD LC oscillation. If oscillation is stoped, IC’s power consumption is decreased. bit 1: DDCLK If you set this bit to 1, OSD input clock is doubled from LC oscillation. It makes OSD horisontal image size as doubled. bit 2: DLINE If you set this bit to 1, OSD vertical scan counter input clock is doubled from normal state. It makes OSD vertical image size as doubled. bit 1: PROSD It controls screen output priority between sprite and OSD. If its value is 1, OSD hide sprite pattern in overapped area. bit 2: ENSP It enables sprite display. bit 3: DUSP It doubles sprite’s horizontal & vertical size during this value is 1. bit 4: ONL1 bit 7~3: FULLM, I, B, G, R It enables OSD line 1 display. If it is enabled, OSD interrupt is activated. It controls back ground color as below. bit 5: ONL2 It enables OSD line 2 display. If it is enabled, OSD interrupt is activated. M I B G R Color 0 0 0 0 0 Transparent (Normal TV) 0 0 0 0 1 RED Table 17-1 Full Screen Back ground color selection Nov. 1999 Ver 1.0 bit 6: OBGW It controls character’s width. Default width is 12dots. If its value is set, 2 dots (background color) are added both left PRELIMINARY 55 PRELIMINARY GMS81C4040/87C4060 It controls HS, VS, I, YM, YS, B, G, R port’s polarity. If its value is 1, polarity is active high. and right side of character. bit 7: DUSPCL It controls sprite’s dot clock and scan line speed. It does not affect to OSD. Sprite size is controlled as below. DUSPCL DUSP 0 0 Normal 12x16 0 1 x2 24x32 1 0 Not used - 1 1 x4 48x64 FDWSET FDWSET (Field Detection Window Seting) register detects the begin of VSync(Vertical Sync.) signal and distinguishs its current field is Even field or Odd field. Size Ex1: VSync(Odd) Ex2: VSync(Even) Table 17-2 Sprite pattern size FMIN HSync OSDPOL W W W W W POL HS POL VS POLI POL YM POL YS POLHS : Hsync. input POLVS : Vsync. input : Half intensity output POLI POLYM : Half blank output : Blue output POLB : Green output POLG : Red output POLR 0: Active Low 1: Active High FDWSET W W W FMAX3 ~ 0 Field detection Maximum pointer W W W Figure 17-5 FDWSET detection region POLB POLG POLR OSD display enable, include the edge color. 0: Off 1: On W FPOL The region of FMIN[2:0] ~ FMAX[3:0] is field detection window. FMAX[3:0] can divide the region between HSync(Horizontal Sync.) by 16. You can assume there is 4 bit horizontal counter, for example HCOUNT[3:0] which count 0~15. ADDRESS : 0AE3H RESET VALUE : 0111 1010b Field detection Register W FMAX ADDRESS : 0AE2H RESET VALUE : Undefined I/O Polarity ( initial ) Register W W W F M IN 2 ~ 0 Field detection Minimum pointer Field detection polarity 0: Detect Odd field Masking range : Min.~Max. 1: Detect Even field Detecting range : Min.~Max. Figure 17-4 OSD Registers - 2 If the start of VSync is detected at the window, next field is even. Else if VSync is detected another region of the window, next field is odd. It means start of VSync is detected during FMIN[2:0] < HCOUNT[3:0] < FMAX[3:0] and FPOL value is 0, it distinguish odd field. And, start of VSync is detected during FMIN[2:0] < HCOUNT[3:0] < FMAX[3:0] and FPOL value is 1, it distinguish even field. FMIN[2:0], FMAX[3:0] are compared with the horizontal counter in OSD block. OSDPOL bit7~0 : POL HS, VS, I, YM, YS, B, G, R 56 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 Figure 17-7 OSD Registers - 4 Background shadow / edge color Register EDGECOL ADDRESS : 0AE4H RESET VALUE : Undefined W W W W W W W W EDG 2I EDG 2B EDG 2G EDG 2R EDG 1I EDG 1B EDG 1G EDG 1R Edge 2 color bit 0 : LIV8 It is equivalent with L1VPOS’s bit 8. See more details in L1VPOS. Edge 1 color : Half Intensity : Blue : Green : Red EDGnI EDGnB EDGnG EDGnR n:1~2 bit 1: FSC1 ADDRESS : 0AE5H RESET VALUE : ---0 0000b OSD line Register R OSDLN R R R V LR 4 R ~ 0 Current displayed OSD line number ( 00000 ~ 11111b : 0 ~ 63 ) OSD line horizontal position Register LHPOS L1ATTR ADDRESS : 0AE6H RESET VALUE : Undefined W W W W W W W W D7 D6 D5 D4 D3 D2 D1 D0 It selects character outline and shadow color. If it is 1, it select EDGE2 color in EDGECOL register. Or not, it select EDGE1 color. According to EDGECOL register and this bit character and shadow colors are selected simulteneously bit 3~2: CSZ11~CSZ10 It controls OSD character’s size ( x1, x2, x3). You can use this register and DDCLK, DLINE bit, horizontal / vertical size can be controlled (x2, x4, x6). OSD line’s horizontal position (00 ~ FFH) ADDRESS : 0AE8H RESET VALUE : Undefiend Sprite vertical position Register SPVPOS W W W W W W W W D7 D6 D5 D4 D3 D2 D1 D0 SPHPOS It enables line 1’s character(foreground) outline. ADDRESS : 0AE9H RESET VALUE : Undefined W W W W W W W W D7 D6 D5 D4 D3 D2 D1 D0 Figure 17-6 OSD Registers - 3 W ADDRESS : 0AF0 H RESET VALUE : Undefined W W W OBGH WDSL ENOL ENSH 1 1 1 1 L1ATTR W W CSZ 11 CSZ 10 W FSC1 L1V8 Character size 00: Normal Foreground shadow 01: 2 times out line color 10: 3 times 0: Edge 1’s color 11: Reserved 1: Edge 2’s color Shadow / Outline Character Shodow width 0: 1dot charcater outline control 0: Disable 1: Propotional control 1: Enable to character 0: Disable size 1: Enable W L1VPOS W L1V7 L1V6 ENOL ENSH outline, shadow 0 0 0 No outline, No shadow 0 0 1 Thin shadow 0 1 0 Thin outline 0 1 1 Thin outline Thick shadow 1 0 0 No outline, No shadow 1 0 1 Thick shadow 1 1 0 Thick outline 1 1 1 Thick outline Thick shadow Table 17-3 Character Outline, Shadow table bit 7: OBGH1 ADDRESS : 0AF1 H RESET VALUE : Undefined OSD line 1’s vertical position Register WDSL W Vertical position L1VPOS’s bit8 Character background height 0: 16dots 1: 18dots bit 6: WDSL1 It shows thickness of line 1’s shadow and outline. Sprite’s horisontal position (00 ~ FFH) OSD line 1’s attribute Register It enables line 1’s character(foreground) shadow. bit 5: ENOL1 Sprite’s vertical position (00 ~ FFH) Sprite horisontal position Register bit 4: ENSH1 W W W W W W L1V5 L1V4 L1V3 L1V2 L1V1 L1V0 It controls character’s height. Default height is 16dots. If its value is set, 2 dots (background color) are added both top and bottom side of character. OSD line 1’s vertical position (include L1V8 : 000 ~ 1FFH) Nov. 1999 Ver 1.0 PRELIMINARY 57 PRELIMINARY GMS81C4040/87C4060 L2VPOS It shows OSD line 2’s vertical position. Its function is the same as L1VPOS. L1VPOS It shows OSD line 1’s vertical position in 9bit format (LIV8 + L1VPOS, 000 ~ 1FFH). COLMOD It controls OSD output mode-RGB direct half intencity. OSD line 2’s attribute Register W ADDRESS : 0AF3 H RESET VALUE : Undefined W W W OBGH WDSL ENOL ENSH 2 2 2 2 L2ATTR W W CSZ 21 CSZ 20 OSD line 2’s vertical position Register L2VPOS FSC2 L2V8 W Character size 00: Normal Foreground shadow 01: 2 times out line color 10: 3 times 0: Edge 1’s color 11: Reserved 1: Edge 2’s color Shadow / Outline width 0: 1dot Out line control 1: Propotional 0: Disable to character 1: Enable size W L2V7 L2V6 ADDRESS : 0AEFH RESET VALUE : Undifined (see Note) W Vertical position L2VPOS’s bit8 Character background height 0: 16dots 1: 18dots W W Color Output Mode Register COLMOD C16EN Fill with ‘0’ RGB Half intensity enable 1: Enable 0: Enable Shodow control 0: Disable 1: Enable Figure 17-10 OSD Register - 7 ADDRESS : 0AF4 H RESET VALUE : Undefined W W W W W W L2V5 L2V4 L2V3 L2V2 L2V1 L2V0 OSD line 2’s vertical position (include L2V8 : 000 ~ 1FFH) bit 0: C16EN It enables RGB port half intencity output. When this bit is set, RGB port generates half intencity output. Half intencity output is 3.5V voltage level output of RGB port. When you use this bit, you must fill all the other bit with ‘0’. Figure 17-8 OSD Registers - 5 OSD line 2’s attribute Register W ADDRESS : 0AF3 H RESET VALUE : Undefined W W W OBGH WDSL ENOL ENSH 2 2 2 2 L2ATTR W W CSZ 21 CSZ 20 Shadow / Outline width 0: 1dot Out line control 1: Propotional 0: Disable to character 1: Enable size OSD line 2’s vertical position Register L2VPOS W FSC2 L2V8 Vertical position Character size L2VPOS’s bit8 00: Normal Foreground shadow 01: 2 times out line color 10: 3 times 0: Edge 1’s color 11: Reserved 1: Edge 2’s color Character background height 0: 16dots 1: 18dots W W W L2V7 L2V6 Note: When you do not use RGB direct half intncsity output , please initialize this register as 00h. Shodow control 0: Disable 1: Enable MESHCON It controls OSD mesh mode color. Mesh Mode Color Register ADDRESS : 0AEBH RESET VALUE : See Note MESHCON ADDRESS : 0AF4 H RESET VALUE : Undefined W W W W W W L2V5 L2V4 L2V3 L2V2 L2V1 L2V0 Figure 17-11 OSD Register - 8 OSD line 2’s vertical position (include L2V8 : 000 ~ 1FFH) Note: Please initialize this register as 00h. Though this register is for mesh mode color, it is not used currently. Figure 17-9 OSD Register - 6 L2ATTR VRAM It controls OSD line 2’s attributes. Its function is the same as L1ATTR. VRAM contains 1 OSD line, 24 character’s attributes. 58 Each character’s attribute is constructed with 3 bytes, it contains color data for background, shadow, outline, character and character number ( 000H ~ 1FFH, 512 characters PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY ), etc. Line No. 1 2 Character No. A40 A20 A00 2 A41 A21 A01 3 A42 A22 A02 : : : : 22 A55 A35 A15 15 23 A56 A36 A16 24 A57 A37 A17 1 AC0 AA0 A80 2 AC1 AA1 A81 3 AC2 AA2 A82 : : : : 22 AD5 AB5 A95 23 AD6 AB6 24 AD7 AB7 Name BSR Name Function 10 BSCUL Select color of left and top side shadow of the background 0: Edge1, 1: Edge2 color 9 ENRND Enable character’s rounding 8~0 CG8~0 Character font number ( among 000 ~ 1FFH ) Table 17-5 VRAM (bit15~0) function Note: if (BSL = 1) & (BSCUL = 0) & (LnATTR,ENSHn = 1), then the right bottom shadow of font character is shifted to 1 dot right side. This shadow effect will continue until that (BSR) of adjacent character attribution become (BSR = 1). Bit No. & Name Output ( Polarity : Through) Character color 19 18 17 16 A96 I B G R Y M Y S I B G R A97 0 0 0 0 0 0 0 0 0 0 Clear 0 0 0 1 0 1 0 0 0 1 Red 0 0 1 0 0 1 0 0 1 0 Green 0 0 1 1 0 1 0 0 1 1 Yellow 0 1 0 0 0 1 0 1 0 0 Blue 0 1 0 1 0 1 0 1 0 1 Magenta 0 1 1 0 0 1 0 1 1 0 Cyan 0 1 1 1 0 1 0 1 1 1 White 1 0 0 0 0 1 0 0 0 0 Black 1 0 0 1 0 1 0 0 0 1 Half-I,Red 1 0 1 0 0 1 0 0 1 0 Half-I,Green Table 17-4 VRAM memory map Bit No. Bit No. Address (bit 23~0) Hexa decimal 1 GMS81C4040/87C4060 Function Enable right side background shadow. cf. If BSL=1 and BSCUL=1 and LnATTR.ENSHn=1, character’s right bottom shadow is shifted to right side by 1dot unit. It acts continued until current character’s right side chacter’s BSR is set to 1. 14 BSL Enable left side background shadow. 1 0 1 1 0 1 0 0 1 1 Half-I, Yellow 13 BSD Enable bottom side background shadow. 1 1 0 0 0 1 0 1 0 0 Half-I,Blue 12 BSU Enable top side background shadow. 1 1 0 1 0 1 0 1 0 1 Half-I, Magenta 1 1 1 0 0 1 0 1 1 0 Half-I,Cyan 1 1 1 1 0 1 0 1 1 1 Half-I,White 11 BSCDR Select color of right and bottom side shadow of the background 0: Edge1, 1: Edge2 color Table 17-6 VRAM (bit19~16) function Table 17-5 VRAM (bit15~0) function Nov. 1999 Ver 1.0 PRELIMINARY 59 PRELIMINARY GMS81C4040/87C4060 this memory can not be accessed by user program. Bit No. & Name 23 22 Output ( Polarity : Through) Back ground color 21 20 Y S I B G R Address range Charact er code Upper 4bit Lower 8bit 000H 12000 H ~ 1200FH 10000H ~ 1000FH 001H 12010 H ~ 1201FH 10010H ~ 1001FH I B G R Y M 0 0 0 0 0 0 0 0 0 0 Clear 002H 12020 H ~ 1202FH 10020H ~ 1002FH 0 0 0 1 0 1 0 0 0 1 Red : : : 0 0 1 0 0 1 0 0 1 0 Green xyzH 0 0 1 1 0 1 0 0 1 1 Yellow (12000H + xyz0H) ~ (12000H + xyzFH) (10000H + xyz0H) ~ (10000H + xyzFH) 0 1 0 0 0 1 0 1 0 0 Blue : : : 0 1 0 1 0 1 0 1 0 1 Magenta 1FDH 13FD0 H ~ 13FDFH 11FD0H ~ 11FDFH 0 1 1 0 0 1 0 1 1 0 Cyan 1FEH 13FE0 H ~ 13FEFH 11FE0H ~ 11FEFH 0 1 1 1 0 1 0 1 1 1 White 1FFH 13FF0 H ~ 13FFFH 11FF0H ~ 11FFFH 1 0 0 0 1 0 0 0 0 0 Half blanking Table 17-8 Font ROM memory map 1 0 0 1 0 1 1 0 0 1 Half-I,Green 1 0 1 0 0 1 1 0 1 0 Half-I, Yellow 5. A character’s address and dot position in font ROM is described in Figure 17-12 . 1 0 1 1 0 1 1 0 1 1 Half-I,Blue 1 1 0 0 0 1 1 1 0 0 Half-I, Magenta 1 1 0 1 0 1 1 1 0 1 Half-I,Cyan 1 1 1 0 0 1 1 1 1 0 Half-I,White 1 1 1 1 0 1 0 1 1 1 Black Table 17-7 VRAM (bit 23 ~ 20) function Font ROM The GMS81C4040/GMS87C4060 OSD character size is fixed as 12dots (Horisontal) * 16dots (Vertical). Address Data 12530H 12531H 12532H 12533H 12534H 12535H 12536H 12537H 12538H 12539H 1253AH 1253BH 1253CH 1253DH 1253EH 1253FH MSB 00H 07H 08H 08H 08H 09H 0BH 08H 08H 08H 08H 08H 08H 08H 07H 00H LSB Address Data 10530H 10531H 10532H 10533H 10534H 10535H 10536H 10537H 10538H 10539H 1053AH 1053BH 1053CH 1053DH 1053EH 1053FH 00H FEH 01H 61H F1H F9H FDH 61H 61H 61H 61H 61H 61H 01H FEH 00H 1. Each horisontal data (12dots) needs 2byte ROM. 2. One character is constructed with 16 horisontal data to vertically. As a result, one character needs 32bytes (2 * 16 bytes). 3. GMS81C4040/GMS87C4060 contains 512 characters. Total Font ROM memory size is calulated as 16,384bytes ( 32bytes / character * 512 character ) 4. Font ROM memory is located from 10000H ~ 13FFFH, Figure 17-12 Example for a character (53H) Sprite RAM The GMS81C4040/GMS87C4060 contains a 32bytes (12dot * 16dot) sprite RAM. 1. In view point, sprite is similar to character font but it is not using font ROM. 2. You can selct color by dot unit. 3. Using above 1 and 2, you can make any of patterns what you want by software. For example, arrow cursor or some- 60 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 thing. 4. Sprite position is controlled by sprite position register SPVPOS[0AE8H] and SPHPOS[0AE9H]. 5. Sprite RAM is located 0C00~0CF5H. One sprite RAM byte contains 2 dot’s color data. See more details in Table 17-9 ~ Table 17-11. Row number B G R Color 0 0 0 Clear 0 0 1 Red 0 1 0 Green 0 1 1 Yellow Column number MSB ~ LSB 1 0 0 Blue 00H 0C05 H ~ 0C00 H 1 0 1 Black 01H 0C15 H ~ 0C10 H 1 1 0 Cyan 02H 0C25 H ~ 0C20 H 1 1 1 White : : ~ : 0nH (n=0~F) 0Cn5 H ~ 0Cn0 H : : ~ : 0EH 0C05 H ~ 0C00 H 0FH 0C05 H ~ 0C00 H Table 17-11 Sprite RAM Color Table Test Font GMS81C4040 use first OSD font as test purpose(see Fig17-13). When you design OSD characte font, you incert following font to Font ROM 00h. If you like to use this font originally, please contact us Table 17-9 Sprite RAM address map Odd dot color Even dot color bit No. 7 6 5 4 3 2 1 0 Function - B G R - B G R Table 17-10 A sprite RAM’s contents address data MSB 1200H 00H 1201H 00H 1202H 00H 1203H 01H 1204H 03H 1205H 07H 1206H 06H 1207H 06H 1208H 06H 1209H 06H 120AH 06H 120BH 06H 120CH 07H 120DH 03H 120EH 01H 120FH 00H LSB address 1000H 1001H 1002H 1003H 1004H 1005H 1006H 1007H 1008H 1009H 100AH 100BH 100CH 100DH 100EH 100FH data 00H 00H 00H F8H FCH 0EH 06H 06H 06H 06H 06H 06H 0EH FCH F8H 00H Figure 17-13 Test Font Pattern Nov. 1999 Ver 1.0 PRELIMINARY 61 PRELIMINARY GMS81C4040/87C4060 18. I2C Bus Interface The I2C Bus interface circuit is shown in Figure 18-1 . This multi-master I2C Bus interface circuit consists of the I2C address register, the I 2C data shift register, the I 2C clock control register, the I2C control register, the I2C status register and other control circuits. The multi-master I2C Bus interface is a serial communications circuit, conforming to the Phlips I2C Bus data transfer format. This interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. ICAR [D8H] ICDR [D9H] The more details about registers are shown Figure 18-2 ~ Figure 18-6 . SAD6 SDA5 SDA4 SDA3 SDA2 SDA1 SDA0 R/W D7 D6 D5 D4 D3 D2 D1 Address comparator Interrupt Generation Circuit IFI2CR D0 SDA Data Control Circuit Noise Elimination Circuit ICSR [00DAH] BB Circuit MST TRX BB PIN AL ALS ESO AAS AD0 LRB AL Circuit ICCR1 [00DBH] B S EL 1 ~ 0 B C 2~0 SCL Clock Control Circuit Bit counter ICCR2 [DCH] Noise Elimination Circuit ACLK ACK 1 CCR3~0 External clock Clock division Figure 18-1 Block Diagram of multi-master I2C circuit Control ITEM The GMS81C4040/GMS87C4060 contains two I2C Bus interface modules. It supports multi-master function, so it contains arbitration lost detection, synchronization function,etc. ITEM Format Communication mode 62 Function SCL clock frequency Function 66.6KHz ~ 500KHz (fex=12MHz) 44.4KHz ~ 333.3KHz (fex=8MHz) I2C address register It contains slave address (7bit) which is used during slave mode and Read/Write bit. Philips I2C standard 7bit addressing format Bit 7 ~ 0 : Slave address 6~0 Master transmitter Master receiver Slave transmitter Slave receiver Note: Bit 7~0 (SAD6~0) store slave address. The address data transmitted from the master is compared with the contents of these bits. PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 The more details about its bits are shown Table 18-1. ADDRESS : 00D8 H RESET VALUE : 0000 0000b RW ICAR RW RW RW RW RW RW R Bit No. Name Function MST TRX 00: Slave / Receiver mode 01: Slave / Transmitter mode 10: Master / Receiver mode 11: Master / Transmitter mode MST is cleared when - After reset. - After the arbitration lost is occured and 1 byte data transmission is finished. - After stop condition is detected. - When start condition is disabled by start condition duplication preventation function. TRX is cleared when - After reset. - When arbitration lost or stop condition is occured . - When MST is ‘0’, and start condition or ACK non-return mode is detected. BB BB(Bus busy)bit is 1 during bus is busy. This bit can be written by S/W. its value is ‘1’ by start condition, and cleared by stop condition. 4 PIN PIN(Pending Interrupt Not)bit is interrupt request bit. If I2C interrupt request is issued, its value is 0. PIN is cleared when - After 1 byte trasmission / receive is finished. PIN is set when - After reset. - After write instruction is excuted into I2C data shift register ICDR. - When PIN bit low, the output of SCL is pulled down, So if you want to release SCL, you must perform write instruction CDR. 3 AL Arbitration lost detection flag. If arbitration lost is detected, AL=1, or 0. AAS Slave address comparison flag. It shows compared result with received address data and I2C address register (ICAR). It is 1, when two of data is same. SAD6 SDA5 SDA4 SDA3 SDA2 SDA1 SDA0 R/W Slave address Figure 18-2 I2C address Register 7 6 I2C data shift register [ICDR] The I2C data shift register is an 8bit shift register to store received data and write transmit data. When transmit data is written into this register, it is transfered to the outside from bit7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When data is received, it is input to this register from bit0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. The I2C data shift register is in a write enable status only when the ESO bit of the I 2 C control register (address 00DCH) is “1”. The bit counter is reset by a write instruction to the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ESO bit value. 5 ADDRESS : 00D9 H RESET VALUE : 0000 0000b ICDR RW RW RW RW RW RW RW RW D7 D6 D5 D4 D3 D2 D1 D0 Shift le ft 1-bit e ach S C L Figure 18-3 Data shift register I2C status register The I2C status register controls the I2C Bus interface status. The low-order 4bits are read only bits and the high-order 4bits can be read out and written to. 2 Table 18-1 Bit function Nov. 1999 Ver 1.0 PRELIMINARY 63 PRELIMINARY GMS81C4040/87C4060 Bit No. Name Function AD0 General call detection flag. If general call is detected, AD0=1, or not 0. * General call : If received address is all ‘0’ . it is called general call. LRB Last received bit. it is used for receive confirmation. If ACK is returned, LRB=0, or not 1. 1 0 ADDRESS : 00DBH RESET VALUE : 00-0 0000b RW ICCR1 RW RW RW RW BSEL BSEL 1 0 ALS ESO BC2 RW BC1 RW BC0 Figure 18-5 I2C control Register 1 I2C control register 2 Table 18-1 Bit function It controls SCL mode, SCL frequency, etc. ADDRESS : 00DAH RESET VALUE : 0001 0000b ICSR RW RW RW RW R R R R MST TRX BB PIN AL AAS AD0 LRB Figure 18-4 I2C status Register It contains 8bit data to transmit to external device when trasmitter mode, or received 8bit data from external device when receive mode. Bit No. Name Function 7 ACLK Select acknowledge clock (ACK) mode. 0: No acknowledge clock mode. acknowledge clock is not generated after data was transmismitted. 1: acknowledge clock mode. acknowledge clock is generated after data was transmismitted. 6 ACK If acknowledge clock is returned, this bit is 0. Or not 1. 5 1 (fixed) I2C control register 1 It controls communication data format. Bit No. Name Function 7 6 I2C connection control. 00: No connection BSEL1 BSEL0 01: SCL1, SDA1 10: SCL2, SDA2 11: SCL1, SDA1, SCL2, SDA2 4 ALS Data format selection. 0: Addressing format 1: Free data format 3 ESO I2C Bus interface use enable flag 0: Disabled 1: Enabled 2 BC2 1 BC1 0 BC0 Not used. Table 18-3 Bit function Bit counter. 000 b: 8bit 001 b~111 b: 1~7bit Table 18-2 Bit function 64 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY Bit No. Figure 18-7 Interrupt request signal generation timing Name Function SCL Frequency selection SCL frequency = fex / (12 * CCR) Value 3 2 1 0 GMS81C4040/87C4060 CCR3 CCR2 CCR1 CCR0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 fex = 12MHz fex = 8MHz Not allowed Not allowed 333.3KHz 222.2KHz 166.6KHz 133.3KHz 111.1KHz 95.2KHz 83.3KHz 74.1KHz 66.6KHz 60.6KHz 55.5KHz 51.3KHz 47.6KHz 44.4KHz Not allowed Not allowed 500.0KHz 333.3KHz 250.0KHz 200.0KHz 166.6KHz 142.9KHz 125.0KHz 111.1KHz 100.0KHz 90.0KHz 83.3KHz 76.4KHz 71.4KHz 66.6KHz START condition generation When the ESO bit of the I2C control register (00DBH) is “1”, writing to the I2C status register will generate START condition. Refer to Figure 18-8 for the START condition generation timing diagram. ICSR write signal (I2C status reg.) SCL tBB BB (Bus busy) flag tSETUP : Setup time tHOLD : Hold time : Set time for BB tBB ADDRESS : 00DCH RESET VALUE : 000- 0000b ICCR2 RW ACLK ACK RW 1 RW CCR3 CCR2 RW tHOLD SDA Table 18-3 Bit function RW tSETUP Figure 18-8 START condition generation timing RW CCR1 CCR0 Figure 18-6 I2C control Register 2 RESTART condition generation RESTART condition’s setting sequence is as followings. 1. Write 020H to I2C status register (ICSR, 00DAH) SCL 2. Write slave address to I2C data shift register (ICDR, 00D9H) 3. Write 0F0H to I2C status register (ICSR, 00DA H) PIN I2C Request STOP condition generation Writing ‘C0h’ to ICSR will generate a stop condition, Nov. 1999 Ver 1.0 PRELIMINARY 65 PRELIMINARY GMS81C4040/87C4060 when ESO (ICCR bit3) is ‘1’ START / STOP condition detect ICSR write signal (I2C status reg.) SCL SDA START / STOP condition is detected when Table 18-4 is satisfied. tSETUP tHOLD tBB SCL release time BB (Bus busy) flag SCL tSETUP : Setup time tHOLD : Hold time : Set time for BB tBB tSETUP tHOLD SDA (START) SDA (STOP) Figure 18-9 STOP condition generating timing diagram tSETUP : Setup time tHOLD : Hold time START / STOP condition generation time is shown Table 18-4. Figure 18-10 START / STOP condition detection timing ITEM Timing SPEC. Setup time ( tSETUP ) 3.3uS (n=20cycles) Hold time ( tHOLD ) 3.3uS (n=20cycles) Set/Reset time for BB flag ( tBB ) 3.0uS (n=18cycles) START / STOP detection time is showed Table 18-5. ITEM Timing SPEC. SCL release time > 2.0uS (n=12cycles) Setup time > 1.0uS (n=6cycles) Hold time > 1.0uS (n=6cycles) Table 18-5 Example time ( fex=12MHz ) Table 18-4 Example time ( fex =12MHz ) 66 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY Address data communication The first transmitted data from master is compared with I2C address register (ICAR, 00D8 H). At this time R/W is GMS81C4040/87C4060 not compared but it determines next data operation. i.e, transmitting or receiving data Master -> Slave (with 7bit address) START Slave addr. ACK 7bit R/W (“0”) Data ACK Data ACK STOP /ACK Slave -> Master (with 7bit address) Data block from master to slave Data block from slave to master START Slave addr. ACK 7bit R/W (“1”) Data ACK Data ACK STOP Figure 18-11 Address data communication format Nov. 1999 Ver 1.0 PRELIMINARY 67 PRELIMINARY GMS81C4040/87C4060 19. INTERRUPTS The GMS81C4040/GMS87C4060 interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, Priority circuit and Master enable flag ("I" flag of PSW). 16 interrupt sources are provided. The configuration of interrupt circuit is shown in Figure 19-2 . Below table shows the Interrupt priority Reset/Interrupt Symbol Priority Hardware Reset External Interrupt 0 OSD Interrupt External Interrupt 1 External Interrupt 2 Timer/Counter 0 Timer/Counter 2 1 Frame Interrupt VSync Interrupt Timer/Counter 1 Timer/Counter 3 Interrupt interval measure Watchdog Timer Basic Interval Timer Serial I/O Interrupt I2C Interrupt RESET INT0 OSD INT1 INT2 Timer 0 Timer 2 1Frame VSync Timer 1 Timer 3 INTV(INT3/4) WDT BIT SIO I2C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Interrupt Mode Register It controls interrupt priority. It takes only one specified interrupt. Of course, interrupt’s priority is fixed by H/W, but sometimes user want to get specified interrupt even if higher priority interrupt was occured. Higher priority interrupt is processed the next time. It contains 2bit data to enable priority selection and 4bit data to select specified interrupt. Bit No. 5,4 3~0 The External Interrupts can each be transition-activated (1to-0 or 0-to-1 transition). When an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transitionactivated. Name IM1~0 IP3~0 Value 00 01 1X Function Mode 0: H/W priority Mode 1: S/W priority Interrupt is disabled, even if IE is set. INT0 OSD INT1 INT2 Timer 0 Timer 2 1Frame VSync Timer 1 Timer 3 INTV(INT3/4) WDT BIT SIO I2C Not used 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 19-1 Bit function T h e Ti me r /C o u nt er I n te r r up t s ar e ge n er at ed b y TnIF(n=0~3), which is set by a match in their respective timer/counter register. The Basic Interval Timer Interrupt is generated by BITIF which are set by a overflow in the timer register. ADDRESS : 00F3H RESET VALUE : Undefined RW IMOD The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW), the interrupt enable register (IENH, IENL) and the interrupt request flags (in IRQH,IRQL) except Power-on reset and software BRK interrupt. 68 PRELIMINARY IM1 RW IM0 RW RW RW RW IP3 IP2 IP1 IP0 Figure 19-1 Interrupt Mode Register Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 Internal bus line IENH [00F6H] Interrupt Enable Register (Higher byte) IMOD [00F3H] IRQH [0F7H] Bit5 INT0 INT0 IFOSD OSD INT1 INT1 INT2 INT2 RESET BRK T0 Timer 2 T2 1 Frame 1Frame IFVSync VSync Timer 1 T1 Timer 3 T3 Intr. interval INTV IFWDT WDT IFBIT BIT IFS SR IFI2C I2C To CPU Priority Control Timer 0 I Flag Interrupt Master Enable Flag I-flag is in PSW , it is cleared by "D I", set by "EI" instruction. W hen it goes interrupt service, I-flag is cleared by hardw are, thus any other interrupt are inhibited. W hen interrupt service is completed by "R ETI" instruction, I-flag is set to "1" by hardware. Interrupt Vector Address Generator IRQL [00F5H] IENL [00F4H] Interrupt Enable Register (Lower byte) Internal bus line Figure 19-2 Block Diagram of Interrupt Nov. 1999 Ver 1.0 PRELIMINARY 69 PRELIMINARY GMS81C4040/87C4060 Interrupt enable registers are shown in Figure 19-4 . These registers are composed of interrupt enable flags of each interrupt source, these flags determines whether an interrupt will be accepted or not. When enable flag is "0", a corre- R/W IRQH INT0 R/W R/W R/W OSD INT1 INT2 T0 R/W R/W sponding interrupt source is prohibited. Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once. R/W R/W T2 1Frame VSync MSB ADDRESS: 00F7H INITIAL VALUE: 0000 0000b LSB VSync interrupt request flag 1 Frame interrupt request flag Timer / Counter 2 interrupt request flag Timer / Counter 0 interrupt request flag External interrupt 2 interrupt request flag External interrupt 1 interrupt request flag On screen display interrupt request flag External interrupt 0 interrupt request flag IRQL R/W R/W R/W R/W R/W R/W R/W T1 T3 INTV WDT BIT SR I2C MSB ADDRESS: 00F5H INITIAL VALUE: 0000 000-b LSB I 2C interrupt request flag Serial I/O interrupt request flag Basic interval timer interrupt request flag Watch-dog timer interrupt request flag Interrupt interval measurement interrupt request flag (INT3/4) Timer / Counter 3 interrupt request flag Timer / Counter 1 interrupt request flag Figure 19-3 Interrupt Request Flags 70 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY R/W IENH INT0 R/W R/W R/W OSD INT1 INT2 T0 R/W R/W R/W R/W T2 1Frame VSync MSB GMS81C4040/87C4060 ADDRESS: 00F6H INITIAL VALUE: 0000 0000b LSB VSync interrupt enable flag 1Frame interrupt enable flag Timer / Counter 2 interrupt enable flag Timer / Counter 0 interrupt enable flag External interrupt 2 interrupt enable flag External interrupt 1 interrupt enable flag On screen display interrupt enable flag External interrupt 0 interrupt enable flag IENL R/W R/W R/W R/W R/W R/W R/W T1 T3 INTV WDT BIT SR I2C MSB ADDRESS: 00F4H INITIAL VALUE: 0000 000-b LSB I 2C interrupt enable flag Serial I/O interrupt enable flag Basic interval timer interrupt enable flag Watch-dog timer interrupt enable flag Interrupt interval measurement interrupt enable flag (INT3/4) Timer / Counter 3 interrupt enable flag Timer / Counter 1 interrupt enable flag Figure 19-4 Interrupt Enable Flags Nov. 1999 Ver 1.0 PRELIMINARY 71 PRELIMINARY GMS81C4040/87C4060 19.1 Interrupt Sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to "0" by a reset or an instruction. Interrupt acceptance sequence requires 8 fex (2 µs at fMAIN=4MHz) after the completion of the current instruction execution. The interrupt service task terminates upon execution of an interrupt return instruction [RETI]. Interrupt acceptance 2. Interrupt request flag for the interrupt source accepted is cleared to "0". 3. The contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. The stack pointer decrements 3 times. 4. The entry address of the interrupt service program is read from the vector table address, and the entry address is loaded to the program counter. 5. The instruction stored at the entry address of the interrupt service program is executed. 1. The interrupt master enable flag (I-flag) is cleared to "0" to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled. System clock Instruction Fetch Address Bus PC Data Bus Not used SP SP-1 PCH PCL SP-2 PSW V.L. V.L. ADL V.H. ADH New PC OP code Internal Read Internal Write Interrupt Processing Step Interrupt Service Task V.L. and V.H. are vector addresses. ADL and ADH are start addresses of interrupt service routine as vector contents. Figure 19-5 Interrupt Service routine Entering Timing 72 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY Basic Interval Timer Vector Table Address 0FFE6H 0FFE7H 012H 0E3H Entry Address 0E312H 0E313H GMS81C4040/87C4060 General-purpose register save/restore using push and pop instructions; 0EH 2EH main task acceptance of interrupt interrupt service task saving registers Correspondence between vector table address for BIT interrupt and the entry address of the interrupt service program. restoring registers A maskable interrupt is not accepted until the I-flag is set to "1" even if a maskable interrupt of higher priority than that of the current interrupt being serviced. When nested interrupt service is necessary, the I-flag is set to "1" in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. Saving/Restoring General-purpose Register During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but not the accumulator and other registers. These registers are saved by the program if necessary. Also, when nesting multiple interrupt services, it is necessary to avoid using the same data memory area for saving registers. interrupt return 19.2 BRK Interrupt Software interrupt can be invoked by BRK instruction, which is the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0. Each processing step is determined by B-flag as shown in Figure 19-6 . =0 The following method is used to save/restore the generalpurpose registers. Example: Register save using push and pop instructions INTxx: PUSH PUSH LDA A X DPGR PUSH A B-FLAG BRK or TCALL0 ;SAVE ACC. ;SAVE X REG. ;SAVE DPGR ; Direct page ; accessable reg. ; : interrupt processing : POP STA POP POP RETI A DPGR X A Nov. 1999 Ver 1.0 =1 BRK INTERRUPT ROUTINE TCALL0 ROUTINE RETI RET Figure 19-6 Execution of BRK/TCALL0 ;RESTORE DPGR ;RESTORE X REG. ;RESTORE ACC. ;RETURN PRELIMINARY 73 PRELIMINARY GMS81C4040/87C4060 19.3 Multi Interrupt If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines by hardware which request is serviced. Main Program service Example: Even though Timer1 interrupt is in progress, INT0 interrupt serviced without any suspend. TIMER 1 service enable INT0 disable other TIMER1: PUSH PUSH PUSH LDM LDM EI : : : INT0 service EI Occur TIMER1 interrupt However, multiple processing through software for special features is possible. Generally when an interrupt is accepted, the I-flag is cleared to disable any further interrupt. But as user set I-flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress. Occur INT0 : : : LDM LDM POP POP POP RETI enable INT0 enable other A X Y IENH,#80H IENL,#0 IENH,#FFH IENL,#FEH Y X A ;Enable INT0 only ;Disable other ;Enable Interrupt ;Enable all interrupts In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting the interrupt enable registers IENH,IENL and master enable "EI" in the TIMER1 routine. Figure 19-7 Execution of Multi Interrupt 74 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 19.4 External Interrupt The external interrupt on INT0, INT1... pins are edge triggered depending the edge selection register. Refer to “6. PORT STRUCTURES” on page 9. The edge detection of external interrupt has three transition activated mode: rising edge, falling edge, both edge. INT0 pin INT0IF INT0 INTERRUPT INT1IF edge selection INT1 pin INT1 INTERRUPT INT2 pin INT2IF INT0, INT1 and INT2 are multiplexed with general I/O ports. To use external interrupt pin, the bit of port function register FUNC1 should be set to "1" correspondingly. Response Time The INT0, INT1 and INT2 edge are latched into INT0IF, INT1IF and INT2IF at every machine cycle. The values are not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. For example, the DIV instruction takes twelve machine cycles. Thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine INT2 INTERRUPT IEDS [00F2H] Figure 19-8 External Interrupt Block Diagram System clock Instruction Fetch Last instruction execution (0~12cycle) Enter interrupt service routine (8cycle) Interrupt request sampling 1cycle Interrupt overhaed (9~21cycle) Figure 19-9 Interrupt Response Timing Diagram ( Interrupt overhead ) Nov. 1999 Ver 1.0 PRELIMINARY 75 PRELIMINARY GMS81C4040/87C4060 20. WATCHDOG TIMER The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and resumes the CPU to the normal state. The watchdog timer signal for detecting malfunction can be selected either a reset CPU or a interrupt request. When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals. 6-bit up-counter Clock source (BIT overflow : IFBIT) WDT clear comparator IFWDT Watchdog Timer interrupt 6-bit compare data enable 6 WDTCL[bit6] to reset CPU WDTR[bit5~0] WDTON[bit5] WDTR [00D7H] CKCTLR Watchdog Timer Register Clock control Register [00D6H] Figure 20-1 Block Diagram of Watchdog Timer Watchdog Timer Control Figure 20-2 shows the watchdog timer control register. The watchdog timer is automatically disabled after reset. The CPU malfunction is detected as setting the detection time, selecting output, and clearing the binary counter. Repeatedly clearing the binary counter within the setting detection time. If the malfunction occurs for any cause, the watchdog timer output will become active at the rising overflow from the binary counters unless the binary counter are cleared. At this time, when WDTON=1 a reset is generated, which drives the RESET pin low to reset the internal hardware. When WDTON=0, a watchdog timer interrupt (IFWDT) is generated. ADDRESS : 00D6 H RESET VALUE : 0000 0000b W WDT ON CKTCLR W W W W R ENP BTCL BTS2 BTS1 BTS0 CK Watchdog timer On/Off control 0: Normal 6bit timer, Watchdog off 1: Watchdog timer ADDRESS : 00D7H RESET VALUE : -011 1111b W WDTR WDT CL W W W W W D TR 5 W ~ W 0 Slave address Watchdog timer Clear 0: Watchdog timer free run 1: Watchdog timer clear and free run Automatically cleared this bit after 1cycle Figure 20-2 Watchdog timer register 76 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 Example: Sets the watchdog timer detection time Within WDT detection time Within WDT detection time LDM WDTR,#01??????b LDM CKCTLR,#00111???b ;Clear Counter and set value(??????b) ;You have to set WDTR first, for prevent unpredictable interrupt ;when you set WDTON bit. ;Select clock source(???b) and WDTON=1 LDM : : : : LDM : : : : LDM WDTR,#01??????b ;Clear counter WDTR,#01??????b ;Clear counter WDTR,#01??????b ;Clear counter Enable and Disable Watchdog Watchdog timer is enabled by setting WDTON (bit 5 in CKTCLR) to "1". WDTON is initialized to "0" during reset, WDTON should be set to "1" to operate after reset is released. Example: 6-bit timer interrupt setting up. LDX TXSP LDM LDM : : Example: Enables watchdog timer reset : LDM : : CKTCLR,#001?????b ;WDTON←1 The watchdog timer is disabled by clearing bit 5 (WDTON) of CKTCLR. Watchdog Timer Interrupt The watchdog timer can also be used as a simple 6-bit timer by clearing bit 5 (WDTON) of CKTCLR. The interval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is shown as below. = × The stack pointer (SP) should be initialized before using the watchdog timer output as an interrupt source. Nov. 1999 Ver 1.0 #03FH ;SP ← 3F CKTCLR,#000?????b ;WDTON←0 WDTR,#01??????b ;WDTCL←0 Refer table and see BIT timer (). CKCTLR BTS2~0 BIT input clock Watchdog timer input clock IFWDT cycle 000b PS4 (2uS) 512uS 32,256uS 001b PS5 (4uS) 1,024uS 64,512uS 010b PS6 (8uS) 2,048uS 129,024uS 011b PS7 (16uS) 4,096uS 258,048uS 100b PS8 (32uS) 8,192uS 516,096uS 101b PS9 (64uS) 16,384uS 1,032,192uS 110b PS10 (128uS) 32,768uS 2,064,384uS 111b PS11 (256uS) 65,536uS 4,128,768uS Table 20-1 Watchdog timer MAX. cycle (Ex:fex =8MHz) PRELIMINARY 77 PRELIMINARY GMS81C4040/87C4060 Source clock BIT overflow Binary-counter 2 1 3 0 1 2 3 0 Counter Clear WDTR 3 n Match Detect IFWDT interrupt WDTR ← "0100_0011b" WDT reset reset Figure 20-3 Watchdog timer Timing Minimizing Current Consumption It should be set properly that current flow through port doesn't exist. First conseider the setting to input mode. Be sure that there is no current flow after considering its relationship with external circuit. In input mode, the pin impedance viewing from external MCU is very high that the current doesn’t flow. But input voltage level should be VSS or VDD. Be careful 78 that if unspecified voltage, i.e. if unfirmed voltage level is applied to input pin, there can be little current (max. 1mA at around 2V) flow. If it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. Setting to High or Low is decided considering its relationship with external circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to High, and if there is external pull-down register, it is set to low. See Figure 20-4 . PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY INPUT PIN VDD GMS81C4040/87C4060 OUTPUT PIN VDD ON internal pull-up VDD OPEN OFF ON O O OFF i i VDD GND GND VDD ON X X OPEN Weak pull-up current flows OFF O O In the left case, much current flows from port to GND. VDD INPUT PIN OUTPUT PIN VDD O OPEN VDD L i=0 ON i OFF L OFF ON i GND GND Very weak current flows X i=0 GND O X i=0 O In the left case, Tr. base current flows from port to GND. To avoid power consumption, low output to the port . When port is configured as an input, input level should be closed to 0V or 5V to avoid power consumption. Figure 20-4 Application example of Port under Power Consumption Nov. 1999 Ver 1.0 PRELIMINARY 79 PRELIMINARY GMS81C4040/87C4060 21. OSCILLATOR CIRCUIT The GMS81C4040/GMS87C4060 has two oscillation circuits internally. XIN and X OUT are input and output for main frequency and OSC1 and OSC2 are input and output for OSD(On Screen display) frequency, respectively, of a inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 21-1 . Recommend C1 fc (MHz) XOUT C1 & C2 (pF) 10 C2 fc (MHz) 30 XIN 12 VSS 16 5 Crystal Oscillator Recommend C1 fc (MHz) C1 & C2 (pF) L (uH) 8 5 100 OSC1 12 20 15 VSS 16 10 15 20 5 15 OSC2 L1 C2 For selection L,C value, you have to tune the frequency to appropriate range which is dependent to your target set. LC Oscillator Open External Clock XOUT XIN External Oscillator Figure 21-1 Oscillation Circuit Oscillation components have their own characteristics, so user should consult the component manufacturers for appropriate values of external components. In addition, see Figure 21-2 for the layout of the crystal. Note: Minimize the wiring length. Do not allow wiring to intersect with other signal conductors. Do not allow wiring to come near changing high current. Set the potential of the grounding position of the oscillator capacitor to that of V SS. Do not ground to any ground pattern where high current is present. Do not fetch signals from the oscillator. XOUT XIN Figure 21-2 Layout example of Oscillator PCB circuit 80 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 22. RESET The GMS81C4040/GMS87C4060 have two types of reset generation procedures; one is an external reset input, other On-chip Hardware Program counter RAM page register Initial Value PC On-chip Hardware Initial Value (FFFFH) - (FFFEH) Peripheral clock Off 00H Watchdog timer Disable 0 Control registers Refer to Table 8-1 on page 22 DPGR G-flag of PSW is a watch-dog timer reset. Table 22-1 shows on-chip hardware initialization by reset action. G Table 22-1 Initializing Internal Status by Reset Action 22.1 External Reset Input The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. After reset, 64ms (at 4 MHz) add with 7 oscillator periods are required to start execution as shown in Figure 22-2 . A connecting for simple power-on-reset is shown in Figure 22-1 . VDD RESET Internal RAM is not affected by reset. When VDD is turned on, the RAM content is indeterminate. Therefore, this RAM should be initialized before reading or testing it. + − GND When the RESET pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH - FFFFH. Figure 22-1 Simple Power-on-Reset Circuit 1 3 ? ? 4 5 6 7 ~ ~ RESET ~ ~ Fetch ~ ~ ? ? FFFE FFFF Start ~ ~ ~ ~ ? ? ? ? FE ADL ADH OP ~ ~ DATA BUS 2 ~ ~ Oscillator (XIN pin) ADDRESS BUS MCU Stabilization Time tST = 62.5mS at 4.19MHz RESET Process Step tST = 1 fMAIN ÷1024 MAIN PROGRAM x 256 Figure 22-2 Timing Diagram after RESET Nov. 1999 Ver 1.0 PRELIMINARY 81 GMS81C4040/87C4060 PRELIMINARY 22.2 Watchdog Timer Reset Refer to “20. WATCHDOG TIMER” on page 76. 82 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 23. OTP Programming 23.1 GMS87C4060 OTP Programming You can burn out GMS87C4060 OTP through the general Gang programmer using Intel 27010/C010 mode. In Devleopment tool package auxiliary, GMS87C4060-to-27010/ C010 conversion socket is included. GMS87C4060 have two ROM memory areas. One is Program ROM memory and the other is Font ROM memory. Program ROM area is from 1000h to FFFFh Font ROM area is from 10000h to 13FFFh. When you acquire new OTP, actually, the OTP is not fully blank. The OPT have six test pattern in the OSD Font ROM memory(see figure23-1). The test pattern are written at 11FA0h ~ 11FFFh and 13FA0h ~ 13FFFh. Note: DO NOT write any data in this area(11FA0h ~ 11FFFh, 13FA0h ~ 13FFFh) file(***.OTP) and the other is font OTP file(***.FNT). You can make each file through ASMLINKER.exe and OSDFONT.exe respectively. All OTP file is Motolora Sformat. You can burn the program file and font file respectively or together. To burn program file and font file respectively, refer following procedure 1. Make program OTP file and font OTP file repectively. 2. Check whether six test pattern is included in font OTP file(see below Six Text Pattern) 3. Burn program OTP file(Set chip target address 1000h ~ FFFFh) 4. Burn font OTP file(Set chip target address 10000h ~13FFFh) Blank Check If you run blank check function of ROM writer, ROM writer inform blank error because of test pattern. To avoid this situation, you must run the blank check function seperetely. For example, check OTP address rage of 1000h ~ 11F9Fh at first. And then check OPT address range of 12000h ~ 13F9Fh. If you have ROM writer without partial blank check function, please do not run blank check function. Note: When you program the OTP file, DO NOT check the blank. Because there are already written data(Six test pattern / 11FA0h ~ 11FFFh, 13FA0h~13FFFh) It will occur blank error To burn program file and font file together, refer following procedure 1. Add program OTP file and font OTP file 1000H 2. Check whether six test pattern is included in font OTP file(see below Six Text Pattern) 3. Burn OTP file(Set chip target address 1000h ~ 13FFFh) Program Memory About other details, refer ROM wirter manual. Six Test Pattern FFFFH OSD Font Memory When you make font file through OSDFONT.exe, please confirm whether six test pattern is included or not in character address 1FAh ~ 1FFh, To include six test patern, refer following procedure. 13FFFH 1. Make Font file and save it to your PC Figure 23-1 GMS87C4060 OTP Memory Map Program Writing There are two kind of OTP file. One is program OTP Nov. 1999 Ver 1.0 2. Reopen the font file and save it to your HDD once again. 3. Then six test pattern will be included automatically. (Character address 1FAh ~ 1FFh) PRELIMINARY 83 PRELIMINARY GMS81C4040/87C4060 23.2 .Device configuration data A15 A13 A12 A11 A10 A9 A8 A7 A6 GND A5 A4 A3 A2 A1 A0 O7 O6 O5 O4 O3 A16 HYUNDAI GMS874060 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A14 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 CEB PGMB OEB VCC VPP O0 O1 O2 Figure 23-2 Figure Pin Configuration in OTP Programming Mode GMS87C4060 Intel 27010 Mode VPP CEB OEB PGMB VPP CEB OEB PGMB Program 12.75V Low High*2 Low*1 12.75V Low High Low Verify 12.75V Low Low High 12.75V Low Low High 5V Low Low X 5V Low Low X 12.75V Low High Low 12.75V Low High Low 12.75V, 5V Low Low X 12.75V Low Low X Optional Verify Gang Write *3 Gang Verify *4 Figure 23-3 Figure Mode Table 84 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY *1: Low = Input Low Voltage = VIL(<0.8V) GMS81C4040/87C4060 *4: In Gang Verify mode, the VPP pin can be sset to both normal high(5V), aand 12.75V and chip slecection is possible using the CEB pin *2: High = Input High Value = VIL(>2.0V) *3: In Gang Write Mode, All OTPs are programmed simulaneously. So all signals of OTPs are in the same condition SYMBOL tAS tOES tDS tAH tDH tDFP tVPS tCES tPW Parameter Address Setup Time OEB Setup Time Data Setup Time Address Hold Time Data Hold Time OEB High to Output Float Delay Vpp Setup Time CEB Setup Time PGMB initial program pulse width Min 2 2 2 0 2 0 2 2 95 Limits Typ Max 130 100 105 Conditions Unit µs µs µs µs µs ns µs µs µs tOE tACC tOH Data Valid from OEB 100 Address to output delay 150 output hold from addresses CEB or 0 0 OEB whichever occurrs first tCE CEB to output delay 100 tCS chip selection interval 100 (@Gang verify) *Note1: Output Float is defined as the point where data is no longer driven Note1 Quick pulse programming ns ns ns ns ns Figure 23-4 Figure AC Programming Characteristics Nov. 1999 Ver 1.0 PRELIMINARY 85 GMS81C4040/87C4060 PRELIMINARY Intel 27010 Pin Name VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND O3 O4 O5 O6 O7 CEB A10 OEB A11 A9 A8 A13 A14 N.C. PGMB VCC GMS87C4060 Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name TEST_N R67 R27 R24 R17 R16 R15 R14 R13 R12 R11 R10 R00 R01 R02 VSS R03 R04 R05 R06 R07 R41 R22 R53 R23 R21 R20 R25 R26 Pin Number 38 26 1 4 9 10 15 16 17 18 19 20 29 28 27 12, 40 25 24 23 22 21 51 6 41 5 7 8 3 2 R52 VDD 42 39 Figure 23-5 Pin Mapping Table between Intel 27010/C010 and GMS87C4060 86 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY Pin Name RESET_N Xout Xin R G B R56 R55 R54 OSC2 OSC1 R47 R46 R45 R44 R43 R42 R40 R50 R51 GMS81C4040/87C4060 Pin Number 11 13 14 30 31 32 33 34 35 36 37 45 46 47 48 49 50 52 44 43 Connect to GND Not Connect GND Not Connect Not Connect Not Connect Not Connect Not Connect Not Connect Not Connect GND GND GND GND GND Not Connect Not Connect GND VDD VDD Figure 23-6 Connection of Other Pins of GMS87C4060 in OTP Mode 23.3 Timing Chart Program Address Verify Optinal Verify VIH Address Stable VIL Address Valid tAS tAH VIH Data VIL Data in Stable tDS High Z Valid ouput Data out Valid tDFP tDH 12.5V VPP tVPS 5V VIH CEB PGMB VIL Don’t care VIH VIL OEB Don’t care tCES Don’t care tOES tPW tOE tOE VIH VIL Figure 23-7 Figure Programming Timing Chart Nov. 1999 Ver 1.0 PRELIMINARY 87 PRELIMINARY GMS81C4040/87C4060 Optinal Verify Address VIH Address Stable VIL ..... VIH Data VIL Data Data 0th OTP 1st OTP Data (n-1)th OTP VIH OEB CEB[0] VIL tACC VIH tCS VIL tACC CEB[1] VIH VIL tACC VIH CEB[n-1] VIL 1) When you verify the data in the same address of many OTPs. When you select OTPs using CEB, and can verify the data inthe same address. (PGMB : Don’t care , Vpp : VIH or 12.5V ) VIH OEB VIL CEB[0] tACC VIH tCS VIL tACC CEB[1] VIH VIL tACC CEB[n-1] VIH VIL VIH OEB CEB[0] VIL VIH tACC VIL VIH Address Addr0 VIL tACC Data Addr1 tACC Addr2 tACC Addr3 tACC VIH Data0 Data1 Data2 Data3 VIL 2) When you verify the data in s single OTP throughout the ROM address Figure 23-8 AC Wave Form in Gang Verify Mode 88 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY GMS81C4040/87C4060 24. Assemble mnemonics 24.1 Instruction Map 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 00 01 02 03 04 05 06 07 08 09 SET1 BBS BBS ADC ADC ADC ADC ASL ASL dp.bit A.bit,rel dp.bit,rel #imm dp dp+X !abs A dp // // SBC SBC SBC SBC ROL ROL #imm dp dp+X !abs A dp CMP CMP CMP CMP LSR LSR #imm dp dp+X !abs A dp 4 000 NOP 001 CLRC // 010 CLRG // 011 DI // 100 CLRV // 101 SETC // 110 SETG // 111 EI // // // // // // // // // // // // // 0A 0B TCALL SETA1 0 .bit 0C 0D 0E BIT POP PUSH dp A A TCALL CLRA1 COM 2 .bit TCALL NOT1 POP PUSH BRA X X rel TST POP M.bit dp Y PUSH PCALL Y OR OR OR OR ROR ROR TCALL OR1 CMPX POP PUSH dp dp+X !abs A dp 6 OR1B dp PSW PSW AND AND AND AND INC INC #imm dp dp+X !abs A dp EOR EOR EOR EOR DEC DEC #imm dp dp+X !abs A dp LDA LDA LDA LDA #imm dp dp+X !abs LDM STA STA STA dp,#imm dp dp+X !abs TAX BRK dp #imm TXA 0F TCALL AND1 CMPY CBNE 8 dp dp+X AND1B TXSP TCALL EOR1 DBNE 10 dp EOR1B XMA TSPX dp+X LDY TCALL LDC LDX LDX dp 12 LDCB dp dp+Y STY TCALL STC STX STX dp 14 M.bit dp dp+Y XCN Upage RET INC X DEC X DAS XAS 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 000 001 010 011 100 101 110 111 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F BPL CLR1 BBC BBC ADC ADC ADC ADC ASL ASL TCALL JMP BIT ADDW LDX JMP rel dp.bit A.bit,rel dp.bit,rel {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 1 !abs !abs dp SBC SBC SBC SBC ROL ROL {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 3 CMP CMP CMP CMP LSR LSR TCALL {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 5 BVC // // // rel BCC // // // rel BNE // // // rel BMI // // // rel BVS // // // rel BCS // // // rel BEQ // // rel Nov. 1999 Ver 1.0 // TCALL CALL OR OR OR OR ROR ROR {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 7 AND AND AND AND INC INC TCALL {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 9 EOR EOR EOR EOR DEC DEC TCALL {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 11 !abs MUL TEST SUBW !abs dp [!abs] JMP #imm [dp] TCLR1 CMPW CMPX !abs dp #imm TCALL DBNE CMPX LDYA CMPY Y DIV !abs dp CMPY INCW #imm INC !abs dp Y XMA XMA DECW DEC {X} dp dp Y LDA LDA LDA LDA LDY LDY TCALL LDA LDX STYA {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 13 {X}+ !abs dp STA STA STA STA STY STY TCALL STA STX CBNE {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 15 {X}+ !abs dp PRELIMINARY #imm LDY CALL [dp] RETI TAY TYA XAY DAA XYX NOP 89 PRELIMINARY GMS81C4040/87C4060 24.2 Alphabetic order table of instruction NO. MNENONIC OP CODE BYTE NO. CYCLE NO OPERATION 1 ADC #imm 04 2 2 Add with carry. 2 ADC dp 05 2 3 A ← A + (M) + C 3 ADC dp + X 06 2 4 4 ADC !abs 07 3 4 5 ADC !abs+Y 15 3 5 NV - - H - ZC 6 ADC [dp+X] 16 2 6 7 ADC [dp]+Y 17 2 6 8 ADC {X} 14 1 3 9 ADDW dp 1D 2 5 16-bits add without carry : YA ← YA + (dp+1)(dp) 10 AND #imm 84 2 2 Logical AND A ← A ^ (M) 11 AND dp 85 2 3 12 AND dp + X 86 2 4 13 AND !abs 87 3 4 14 AND !abs+Y 95 3 5 15 AND [dp+X] 96 2 6 16 AND [dp] + Y 97 2 6 17 AND {X} 94 1 3 FLAG NVGBHIZC NV - - H - ZC N-----Z- 18 AND1 M.bit 8B 3 4 Bit AND C-flag : C ← C ^ (M.bit) -------C 19 AND1B M.bit 8B 3 4 Bit AND C-flag and NOT : C ← C ^ ~(M.bit) -------C 20 ASL A 08 1 2 Arithmetic shift left 21 ASL dp 09 2 4 22 ASL dp + X 19 2 5 23 ASL !abs 18 3 5 24 BBC A.bit,rel y2 2 4/6 Branch if bit clear : 25 BBC dp.bit,rel y3 3 5/7 if(bit) = 0, then PC ← PC + rel 26 BBS A.bit,rel x2 2 4/6 Branch if bit clear : 27 BBS dp.bit,rel x3 3 5/7 if(bit) = 1, then PC ← PC + rel 28 BCC rel 50 2 2/4 Branch if carry bit clear : if(C) = 0, then PC ← PC + rel 29 BCS rel D0 2 2/4 Branch if carry bit set : If (C) =1, then PC ← PC + rel -------- 30 BEQ rel F0 2 2/4 Branch if equal : if (Z) = 1, then PC ← PC + rel -------- 31 BIT dp 0C 2 4 Bit test A with memory : 32 BIT !abs 1C 3 5 Z ← A ^ M, N ← (M7), V ← (M6) C 7 6 5 4 3 2 1 0 ← ← ← ← ← ← ← ← ← ← "0" N - - - - - ZC --------------MM - - - - Z - MM - - - - Z - 33 BMI rel 90 2 2/4 Branch if munus : if (N) = 1, then PC ← PC + rel -------- 34 BNE rel 70 2 2/4 Branch if not equal : if (Z) = 0, then PC ← PC + rel -------- 35 BPL rel 10 2 2/4 Branch if not minus : if (N) = 0, then PC ← PC + rel -------- 36 BRA rel 2F 2 4 Branch always : PC ← PC + rel -------- 37 BRK 0F 1 8 Software interrupt: B ← “1”, M(SP) ← (PCH), SP ← SP - 1, M(s) ← (PC L), SP ← S - 1, M(SP) ← PSW, ---1-0-- SP ← SP - 1, PC L ← (0FFDEH), PC H ← (0FFDFH) 38 BVC rel 30 2 2/4 Branch if overflow bit clear : If (V) = 0, then PC ← PC + rel 39 BVS rel B0 2 2/4 Branch if overflow bit set : If (V) = 1, then PC ← PC + rel 40 CALL !abs 3B 3 8 Subroutine call 41 CALL [dp] 5F 2 8 M(SP) ← (PCH), SP ← SP-1, M(SP) ← (PCL), SP←SP-1 --------------- -------- if !abs, PC ← abs ; if [dp], PCL ← (dp), PCH ← (dp+1) 42 CBNE dp,rel FD 3 5/7 Compare and branch if not equal ; 43 CBNE dp + X, rel 8D 3 6/8 If A ≠ (M), then PC ← PC + rel. 44 CLR1 dp.bit y1 2 4 Clear bit : (M.bit) ← “0” -------- 45 CLR1A A.bit 2B 2 2 Clear A.bit : (A.bit) ← “0” -------- -------- 46 CLRC 20 1 2 Clear C-flag : C ← “0” -------0 47 CLRG 40 1 2 Clear G-flag : G ← “0” --0----- 90 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY NO. MNENONIC OP CODE BYTE NO. CYCLE NO GMS81C4040/87C4060 OPERATION 48 CLRV 80 1 2 Clear V-flag : V ← “0” 49 CMP #imm 44 2 2 Compare accumulator contents with memory contents 50 CMP dp 45 2 3 A - (M) 51 CMP dp + X 46 2 4 52 CMP !abs 47 3 4 53 CMP !abs + Y 55 3 5 54 CMP [dp + X] 56 2 6 55 CMP [dp] + Y 57 2 6 56 CMP {X} 54 1 3 57 CMPW dp 5D 2 4 FLAG NVGBHIZC -0--0--- N - - - - - ZC Compare YA contents with memory pair contents : N - - - - - ZC YA - (dp+1)(dp) 58 CMPX #imm 5E 2 2 Compare X contents with memory contents 59 CMPX dp 6C 2 3 X - (M) 60 CMPX !abs 7C 3 4 61 CMPY #imm 7E 2 2 Compare Y contents with memory contents 62 CMPY dp 8C 2 3 Y - (M) 63 CMPY !abs 9C 3 4 64 COM dp 2C 2 4 1’s complement : (dp) ← ~(dp) N-----Z- 65 DAA DF 1 3 Decimal adjust for addition N - - - - - ZC 66 DAS CF 1 3 Decimal adjust for substraction N - - - - - ZC 67 DBNE dp,rel AC 3 5/7 Decrement and branch if not equal : 68 DBNE Y,rel 7B 2 4/6 if (M) ≠ 0, then PC ← PC + rel. 69 DEC A A8 1 2 Decrement 70 DEC dp A9 2 4 M←M-1 71 DEC dp + X B9 2 5 72 DEC !abs B8 3 5 73 DEC X AF 1 2 74 DEC Y BE 1 2 75 DECW dp BD 2 6 Decrement memory pair : (dp+1)(dp) ← {(dp+1)(dp)} - 1 76 DI 60 1 3 Disable interrupts : I ← “0” 77 DIV 9B 1 12 N - - - - - ZC N - - - - - ZC -------- N-----Z- N-----Z-----0-- Divide : YA/A ← Q:A, R:Y NV - - H - Z -----1-- 78 EI E0 1 3 Enable interrupts : I ← “1” 79 EOR #imm A4 2 2 Exclusive OR 80 EOR dp A5 2 3 A ← A ⊕ (M) 81 EOR dp + X A6 2 4 82 EOR !abs A7 3 4 83 EOR !abs + Y B5 3 5 84 EOR [ dp + X] 96 2 6 85 EOR [dp] + Y 97 2 6 86 EOR {X} 94 1 3 87 EOR1 M.bit AB 3 5 Bit exclusive-OR C-flag : C ← C ⊕ (M.bit) 88 EOR1B M.bit AB 3 5 Bit exclusive-OR C-flag and NOT : C ← C ⊕ ∼(M.bit) -------C 89 INC A 88 1 2 Increment N - - - - - ZC (M) ← (M) + 1 90 INC dp 89 2 4 91 INC dp + X 99 2 5 N-----Z- 92 INC !abs 98 3 5 93 INC X 8F 1 2 94 INC Y 9E 1 2 95 INCW dp 9D 2 6 Increment memory pair : (dp+1)(dp) ← {(dp+1)(dp)} + 1 96 JMP !abs 1B 3 3 Unconditional jump 97 JMP [!abs] 1F 3 5 PC ← jump address 98 JMP [dp] 3F 2 4 Nov. 1999 Ver 1.0 -------C N-----Z- PRELIMINARY N-----Z-------- 91 PRELIMINARY GMS81C4040/87C4060 NO. MNENONIC OP CODE BYTE NO. CYCLE NO OPERATION FLAG NVGBHIZC 99 LDA #imm C4 2 2 Load accumulator 100 LDA dp C5 2 3 A ← (M) 101 LDA dp + X C6 2 4 102 LDA !abs C7 3 4 103 LDA !abs + Y D5 3 5 104 LDA [dp + X] D6 2 6 105 LDA [dp]+Y D7 2 6 106 LDA {X} D4 1 3 107 LDA {X}+ DB 1 4 108 LDC M.bit CB 3 4 Load C-flag : C ← (M.bit) -------C 109 LDCB M.bit CB 3 4 Load C-flag with NOT : C ← ~(M.bit) -------C 110 LDM dp,#imm E4 3 5 Load memory with immediate data : (M) ← imm -------- 111 LDX #imm 1E 2 2 Load X-register 112 LDX dp CC 2 3 X ← (M) 113 LDX dp + Y CD 2 4 114 LDX !abs DC 3 4 115 LDY #imm 3E 2 2 Load X-register 116 LDY dp C9 2 3 Y ← (M) 117 LDY dp + Y D9 2 4 4 N-----Z- X-register auto-increment : A ← (M), X ← X + 1 N-----Z- N-----Z- 118 LDY !abs D8 3 119 LDYA dp 7D 2 5 Load YA : YA ← (dp+1)(dp) 120 LSR A 48 1 2 Logical shift right 121 LSR dp 49 2 4 122 LSR dp + X 59 2 5 7 6 5 4 3 2 1 0 C "0"→ → → → → → → → → → N-----Z- N - - - - - ZC 123 LSR !abs 58 3 5 124 MUL 5B 1 9 Multiply : YA ← Y x A 125 NOP 00,FF 1 2 No operation -------- 126 NOT1 M.bit 4B 3 5 Bit complement : (M.bit) ← ~(M.bit) -------- 127 OR #imm 64 2 2 Logical OR 128 OR dp 65 2 3 A ← A V (M) 129 OR dp + X 66 2 4 130 OR !abs 67 3 4 131 OR !abs + Y 75 3 5 132 OR [dp +X} 76 2 6 133 OR [dp] + Y 77 2 6 134 OR {X} 74 1 3 N-----Z- N-----Z- 135 OR1 M.bit 6B 3 5 Bit OR C-flag : C ← C V (M.bit) -------C 136 OR1B M.bit 6B 3 5 Bit OR C-flag and NOT : C ← C V ~(M.bit) -------C 137 PCALL 4F 2 6 U-page call : M(SP) ← (PCH), SP ← SP -1, M(SP) ← (PCL), SP ← SP -1, -------- PC L ← (upage), PCH ←"OFFH" 138 POP A 0D 1 4 Pop from stack 139 POP X 2D 1 4 SP ← SP + 1, Reg. ← M(SP) 140 POP Y 4D 1 4 141 POP PSW 6D 1 4 142 PUSH A 0E 1 4 Push to stack 143 PUSH X 2E 1 4 M(SP) ← Reg. 144 PUSH Y 4E 1 4 145 PUSH PSW 6E 1 4 146 RET 6F 1 5 (restored) SP ← SP - 1 Return from subroutine : SP ← SP+1, PCL ← M(SP), SP ← SP+1, PCH ← M(SP) 147 RETI 7F 1 6 -------- -------- -------- Return from interrupt : SP ← SP+1, PSW ← M(SP), SP ← SP+1,PCL ← M(SP), (restored) SP ← SP+1, PCH ← M(SP) 92 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY NO. MNENONIC OP CODE BYTE NO. CYCLE NO GMS81C4040/87C4060 OPERATION FLAG NVGBHIZC 148 ROL A 28 1 2 149 ROL dp 29 2 4 Rotate left through carry 150 ROL dp + X 39 2 5 151 ROL !abs 38 3 5 152 ROR A 68 1 2 153 ROR dp 69 2 4 154 ROR dp + X 79 2 5 155 ROR !abs 78 3 5 156 SBC #imm 24 2 2 Substract with carry 157 SBC dp 25 2 3 A ← A - (M) - ~(C) 158 SBC dp + X 26 2 4 159 SBC !abs 27 3 4 160 SBC !abs + Y 35 3 5 161 SBC [dp + X] 36 2 6 162 SBC [dp] + Y 37 2 6 163 SBC {X} 34 1 3 164 SET1 dp.bit x1 2 4 Set bit : (M.bit) ← “1” -------- 165 SETA1 A.bit 0B 2 2 Set A.bit : (A.bit) ← “1” -------- 166 SETC A0 1 2 Set C-flag : C ← “1” -------1 167 SETG C0 1 2 Set G-flag : G ← “1” --1----- 168 STA dp E5 2 3 Store accumulator contents in memory 169 STA dp + X E6 2 4 (M) ← A 170 STA !abs E7 3 4 171 STA !abs + Y F5 3 5 172 STA [dp + X] F6 2 6 173 STA [dp] + Y F7 2 6 174 STA {X} F4 1 3 175 STA {X}+ FB 1 4 X-register auto-increment : (M) ← A, X ← X + 1 176 STC M.bit EB 3 6 Store C-flag : (M.bit) ← C 177 STX dp EC 2 4 Store X-register contents in memory 178 STX dp + Y ED 2 5 (M) ← X 179 STX !abs FC 3 5 180 STY dp E9 2 4 Store Y-register contents in memory 181 STY dp + X F9 2 5 (M) ← Y 182 STY !abs F8 3 5 183 STYA dp DD 2 5 Store YA : (dp+1)(dp) ← YA 184 SUBW dp 3D 2 5 16-bits substract without carry : YA ← YA - (dp+1)(dp) 185 TAX E8 1 2 Transfer accumulator contents to X-register : X ← A N-----Z- 186 TAY 9F 1 2 Transfer accumulator contents to Y-register : Y ← A N-----Z- 187 TCALL n nA 1 8 C 7 6 5 4 3 2 1 0 ←←←←←←←←← N - - - - - ZC Rotate right through carry 7 6 5 4 3 2 1 0 C →→→→→→→→→ N - - - - - ZC NV - - HZC -------- --------------- --------------NV - - H - ZC Table call : M(SP) ← (PCH), SP ← SP -1, M(SP) ← (PCL), SP ← SP -1 -------- PC L ← (Table vector L), PCH ← (Table vector H) 188 TCLR1 !abs 5C 3 6 Test and clear bits with A : A - (M), (M) ← (M) ^ ~(A) 189 TSET1 !abs 3C 3 6 Test and set bits with A : A - (M), (M) ← (M) V (A) N-----ZN-----Z- 190 TSPX AE 1 2 Transfer stack-pointer contents to X-register : X ← SP N-----Z- 191 TST dp 4C 2 3 Test memory contents for negative or zero : (dp) - 00H N-----Z- 192 TXA C8 1 2 Transfer X-register contents to accumulator : A ← X N-----Z- 193 TXSP 8E 1 2 Transfer X-register contents to stack-pointer : SP ← X N-----ZN-----Z- 194 TYA BF 1 2 Transfer Y-register contents to accumulator : A ← Y 195 XAX EE 1 4 Exchange X-register contents with accumulator : X fA -------- 196 XAY DE 1 4 Exchange Y-register contents with accumulator : Y fA -------- Nov. 1999 Ver 1.0 PRELIMINARY 93 PRELIMINARY GMS81C4040/87C4060 NO. 197 MNENONIC XCN OP CODE BYTE NO. CYCLE NO CE 1 5 OPERATION Exchange nibbles within the accumulator: A7 ~ A4 f A3 ~ A0 198 XMA dp BC 2 5 Exchange memory contents with accumulator 199 XMA dp + X AD 2 6 (M) f A 200 XMA {X} BB 1 5 201 XYX FE 1 4 FLAG NVGBHIZC N-----Z- N-----Z- Exchange X-register contents with Y-register : X f Y -------- 24.3 Instruction Table by Function 1. Arithmetic/Logic Operation NO. MNENONIC OP CODE BYTE NO. CYCLE NO OPERATION 1 ADC #imm 04 2 2 Add with carry. 2 ADC dp 05 2 3 A ← A + (M) + C 3 ADC dp + X 06 2 4 4 ADC !abs 07 3 4 5 ADC !abs+Y 15 3 5 FLAG NVGBHIZC NV - - H - ZC 6 ADC [dp+X] 16 2 6 7 ADC [dp]+Y 17 2 6 8 ADC {X} 14 1 3 9 AND #imm 84 2 2 Logical AND 10 AND dp 85 2 3 A ← A ^ (M) 11 AND dp + X 86 2 4 12 AND !abs 87 3 4 13 AND !abs+Y 95 3 5 14 AND [dp+X] 96 2 6 15 AND [dp] + Y 97 2 6 16 AND {X} 94 1 3 17 ASL A 08 1 2 18 ASL dp 09 2 4 19 ASL dp + X 19 2 5 20 ASL !abs 18 3 5 21 CMP #imm 44 2 2 Compare accumulator contents with memory contents 22 CMP dp 45 2 3 A - (M) 23 CMP dp + X 46 2 4 24 CMP !abs 47 3 4 25 CMP !abs + Y 55 3 5 26 CMP [dp + X] 56 2 6 27 CMP [dp] + Y 57 2 6 28 CMP {X} 54 1 3 29 CMPX #imm 5E 2 2 Compare X contents with memory contents 30 CMPX dp 6C 2 3 X - (M) 31 CMPX !abs 7C 3 4 N-----Z- Arithmetic shift left C 7 6 5 4 3 2 1 0 ← ← ← ← ← ← ← ← ← ← "0" N - - - - - ZC N - - - - - ZC N - - - - - ZC 32 CMPY #imm 7E 2 2 Compare Y contents with memory contents 33 CMPY dp 8C 2 3 Y - (M) 34 CMPY !abs 9C 3 4 35 COM dp 2C 2 4 1’s complement : (dp) ← ~(dp) N-----Z- 36 DAA DF 1 3 Decimal adjust for addition N - - - - - ZC 37 DAS CF 1 3 Decimal adjust for substraction N - - - - - ZC 38 DEC A A8 1 2 Decrement 39 DEC dp A9 2 4 M←M-1 40 DEC dp + X B9 2 5 41 DEC !abs B8 3 5 42 DEC X AF 1 2 43 DEC Y BE 1 2 94 N - - - - - ZC N-----Z- PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY NO. MNENONIC OP CODE BYTE NO. CYCLE NO OPERATION Divide : YA/A ← Q:A, R:Y 44 DIV 9B 1 12 45 EOR #imm A4 2 2 Exclusive OR 46 EOR dp A5 2 3 A ← A ⊕ (M) 47 EOR dp + X A6 2 4 48 EOR !abs A7 3 4 49 EOR !abs + Y B5 3 5 50 EOR [ dp + X] 96 2 6 51 EOR [dp] + Y 97 2 6 52 EOR {X} 94 1 3 53 INC A 88 1 2 Increment 54 INC dp 89 2 4 (M) ← (M) + 1 55 INC dp + X 99 2 5 56 INC !abs 98 3 5 57 INC X 8F 1 2 58 INC Y 9E 1 2 59 LSR A 48 1 2 60 LSR dp 49 2 4 61 LSR dp + X 59 2 5 62 LSR !abs 58 3 5 63 MUL 5B 1 9 Multiply : YA ← Y x A 64 OR #imm 64 2 2 Logical OR 65 OR dp 65 2 3 A ← A V (M) 66 OR dp + X 66 2 4 67 OR !abs 67 3 4 68 OR !abs + Y 75 3 5 69 OR [dp +X} 76 2 6 70 OR [dp] + Y 77 2 6 71 OR {X} 74 1 3 GMS81C4040/87C4060 NV - - H - Z - N-----Z- N - - - - - ZC N-----Z- Logical shift right 7 6 5 4 3 2 1 0 C "0"→ → → → → → → → → → N - - - - - ZC N-----Z- N-----Z- 72 ROL A 28 1 2 73 ROL dp 29 2 4 74 ROL dp + X 39 2 5 75 ROL !abs 38 3 5 76 ROR A 68 1 2 77 ROR dp 69 2 4 78 ROR dp + X 79 2 5 79 ROR !abs 78 3 5 80 SBC #imm 24 2 2 Substract with carry 81 SBC dp 25 2 3 A ← A - (M) - ~(C) 82 SBC dp + X 26 2 4 83 SBC !abs 27 3 4 84 SBC !abs + Y 35 3 5 85 SBC [dp + X] 36 2 6 86 SBC [dp] + Y 37 2 6 87 SBC {X} 34 1 3 88 TST dp 4C 2 3 Test memory contents for negative or zero : (dp) - 00H 89 XCN CE 1 5 Exchange nibbles within the accumulator: Rotate left through carry C 7 6 5 4 3 2 1 0 ←←←←←←←←← N - - - - - ZC Rotate right through carry 7 6 5 4 3 2 1 0 C →→→→→→→→→ N - - - - - ZC NV - - HZC A7 ~ A4 f A3 ~ A0 Nov. 1999 Ver 1.0 FLAG NVGBHIZC PRELIMINARY N-----ZN-----Z- 95 PRELIMINARY GMS81C4040/87C4060 2. Register / Memory Operation NO. MNENONIC OP CODE BYTE NO. CYCLE NO OPERATION 1 LDA #imm C4 2 2 Load accumulator 2 LDA dp C5 2 3 A ← (M) 3 LDA dp + X C6 2 4 4 LDA !abs C7 3 4 5 LDA !abs + Y D5 3 5 6 LDA [dp + X] D6 2 6 7 LDA [dp]+Y D7 2 6 8 LDA {X} D4 1 3 9 LDA {X}+ DB 1 4 10 LDM dp,#imm E4 3 5 Load memory with immediate data : (M) ← imm 11 LDX #imm 1E 2 2 Load X-register 12 LDX dp CC 2 3 X ← (M) 13 LDX dp + Y CD 2 4 14 LDX !abs DC 3 4 15 LDY #imm 3E 2 2 Load X-register 16 LDY dp C9 2 3 Y ← (M) 17 LDY dp + Y D9 2 4 18 LDY !abs D8 3 4 19 STA dp E5 2 3 Store accumulator contents in memory 20 STA dp + X E6 2 4 (M) ← A 21 STA !abs E7 3 4 22 STA !abs + Y F5 3 5 23 STA [dp + X] F6 2 6 FLAG NVGBHIZC N-----Z- X-register auto-increment : A ← (M), X ← X + 1 -------- N-----Z- N-----Z- -------- 24 STA [dp] + Y F7 2 6 25 STA {X} F4 1 3 26 STA {X}+ FB 1 4 X-register auto-increment : (M) ← A, X ← X + 1 27 STX dp EC 2 4 Store X-register contents in memory 28 STX dp + Y ED 2 5 (M) ← X 29 STX !abs FC 3 5 30 STY dp E9 2 4 Store Y-register contents in memory 31 STY dp + X F9 2 5 (M) ← Y 32 STY !abs F8 3 5 33 TAX E8 1 2 Transfer accumulator contents to X-register : X ← A N-----Z- 34 TAY 9F 1 2 Transfer accumulator contents to Y-register : Y ← A N-----Z- -------- -------- 35 TSPX AE 1 2 Transfer stack-pointer contents to X-register : X ← SP N-----Z- 36 TXA C8 1 2 Transfer X-register contents to accumulator : A ← X N-----Z- 37 TXSP 8E 1 2 Transfer X-register contents to stack-pointer : SP ← X N-----Z- 38 TYA BF 1 2 Transfer Y-register contents to accumulator : A ← Y N-----Z- 39 XAX EE 1 4 Exchange X-register contents with accumulator : X fA -------- 40 XAY DE 1 4 Exchange Y-register contents with accumulator : Y fA -------- 41 XMA dp BC 2 5 Exchange memory contents with accumulator 42 XMA dp + X AD 2 6 (M) f A 43 XMA {X} BB 1 5 44 XYX FE 1 4 OP CODE BYTE NO. CYCLE NO N-----Z- Exchange X-register contents with Y-register : X f Y -------- 3. 16-Bit Operation NO. MNENONIC OPERATION FLAG NVGBHIZC 1 ADDW dp 1D 2 5 16-bits add without carry : YA ← YA + (dp+1)(dp) NV - - H - ZC 2 CMPW dp 5D 2 4 Compare YA contents with memory pair contents : N - - - - - ZC YA - (dp+1)(dp) 3 DECW dp BD 2 6 Decrement memory pair : (dp+1)(dp) ← {(dp+1)(dp)} - 1 N-----Z- 4 INCW dp 9D 2 6 Increment memory pair : (dp+1)(dp) ← {(dp+1)(dp)} + 1 N-----Z- 96 PRELIMINARY Nov. 1999 Ver 1.0 PRELIMINARY NO. MNENONIC OP CODE BYTE NO. CYCLE NO OPERATION 5 LDYA dp 7D 2 5 Load YA : YA ← (dp+1)(dp) 6 STYA dp DD 2 5 Store YA : (dp+1)(dp) ← YA 7 SUBW dp 3D 2 5 16-bits substract without carry : YA ← YA - (dp+1)(dp) OP CODE BYTE NO. CYCLE NO GMS81C4040/87C4060 FLAG NVGBHIZC N-----Z-------NV - - H - ZC 4. Bit Manipulation NO. MNENONIC OPERATION FLAG NVGBHIZC 1 AND1 M.bit 8B 3 4 Bit AND C-flag : C ← C ^ (M.bit) -------C 2 AND1B M.bit 8B 3 4 Bit AND C-flag and NOT : C ← C ^ ~(M.bit) -------C 3 BIT dp 0C 2 4 Bit test A with memory : 4 BIT !abs 1C 3 5 Z ← A ^ M, N ← (M7), V ← (M6) MM - - - - Z - 5 CLR1 dp.bit y1 2 4 Clear bit : (M.bit) ← “0” -------- 6 CLR1A A.bit 2B 2 2 Clear A.bit : (A.bit) ← “0” -------- 7 CLRC 20 1 2 Clear C-flag : C ← “0” -------0 8 CLRG 40 1 2 Clear G-flag : G ← “0” --0----- 9 CLRV 80 1 2 Clear V-flag : V ← “0” -0--0--- 10 EOR1 M.bit AB 3 5 Bit exclusive-OR C-flag : C ← C ⊕ (M.bit) -------C 11 EOR1B M.bit AB 3 5 Bit exclusive-OR C-flag and NOT : C ← C ⊕ ∼(M.bit) -------C 12 LDC M.bit CB 3 4 Load C-flag : C ← (M.bit) -------C 13 LDCB M.bit CB 3 4 Load C-flag with NOT : C ← ~(M.bit) -------C 14 NOT1 M.bit 4B 3 5 Bit complement : (M.bit) ← ~(M.bit) -------- 15 OR1 M.bit 6B 3 5 Bit OR C-flag : C ← C V (M.bit) -------C 16 OR1B M.bit 6B 3 5 Bit OR C-flag and NOT : C ← C V ~(M.bit) -------C 17 SET1 dp.bit x1 2 4 Set bit : (M.bit) ← “1” -------- 18 SETA1 A.bit 0B 2 2 Set A.bit : (A.bit) ← “1” -------- 19 SETC A0 1 2 Set C-flag : C ← “1” -------1 20 SETG C0 1 2 Set G-flag : G ← “1” --1----- 21 STC M.bit EB 3 6 Store C-flag : (M.bit) ← C -------- 22 TCLR1 !abs 5C 3 6 Test and clear bits with A : A - (M), (M) ← (M) ^ ~(A) 23 TSET1 !abs 3C 3 6 Test and set bits with A : A - (M), (M) ← (M) V (A) N-----ZN-----Z- 5. Branch / Jump Operation NO. MNENONIC OP CODE BYTE NO. CYCLE NO OPERATION 1 BBC A.bit,rel y2 2 4/6 Branch if bit clear : 2 BBC dp.bit,rel y3 3 5/7 if(bit) = 0, then PC ← PC + rel 3 BBS A.bit,rel x2 2 4/6 Branch if bit clear : 4 BBS dp.bit,rel x3 3 5/7 if(bit) = 1, then PC ← PC + rel 5 BCC rel 50 2 2/4 Branch if carry bit clear : if(C) = 0, then PC ← PC + rel FLAG NVGBHIZC --------------MM - - - - Z - 6 BCS rel D0 2 2/4 Branch if carry bit set : If (C) =1, then PC ← PC + rel -------- 7 BEQ rel F0 2 2/4 Branch if equal : if (Z) = 1, then PC ← PC + rel -------- 8 BMI rel 90 2 2/4 Branch if munus : if (N) = 1, then PC ← PC + rel -------- 9 BNE rel 70 2 2/4 Branch if not equal : if (Z) = 0, then PC ← PC + rel -------- 10 BPL rel 10 2 2/4 Branch if not minus : if (N) = 0, then PC ← PC + rel -------- 11 BRA rel 2F 2 4 Branch always : PC ← PC + rel -------- 12 BVC rel 30 2 2/4 Branch if overflow bit clear : If (V) = 0, then PC ← PC + rel 13 BVS rel B0 2 2/4 Branch if overflow bit set : If (V) = 1, then PC ← PC + rel Nov. 1999 Ver 1.0 PRELIMINARY --------------- 97 PRELIMINARY GMS81C4040/87C4060 NO. MNENONIC OP CODE BYTE NO. CYCLE NO OPERATION FLAG NVGBHIZC -------- 14 CALL !abs 3B 3 8 Subroutine call 15 CALL [dp] 5F 2 8 M(SP) ← (PCH), SP ← SP-1, M(SP) ← (PCL), SP←SP-1 if !abs, PC ← abs ; if [dp], PCL ← (dp), PCH ← (dp+1) 16 CBNE dp,rel FD 3 5/7 Compare and branch if not equal ; 17 CBNE dp + X, rel 8D 3 6/8 If A ≠ (M), then PC ← PC + rel. 18 DBNE dp,rel AC 3 5/7 Decrement and branch if not equal : 19 DBNE Y,rel 7B 2 4/6 if (M) ≠ 0, then PC ← PC + rel. 20 JMP !abs 1B 3 3 Unconditional jump 21 JMP [!abs] 1F 3 5 PC ← jump address 22 JMP [dp] 3F 2 4 23 PCALL 4F 2 6 --------------- -------- U-page call : M(SP) ← (PCH), SP ← SP -1, M(SP) ← (PCL), SP ← SP -1, -------- PC L ← (upage), PCH ←"OFFH" 24 TCALL n nA 1 8 Table call : M(SP) ← (PCH), SP ← SP -1, M(SP) ← (PCL), SP ← SP -1 -------- PC L ← (Table vector L), PCH ← (Table vector H) 6. Control Operation & etc. NO. 1 MNENONIC BRK OP CODE BYTE NO. CYCLE NO 0F 1 8 OPERATION FLAG NVGBHIZC Software interrupt: B ← “1”, M(SP) ← (PCH), SP ← SP - 1, M(s) ← (PC L), SP ← S - 1, M(SP) ← PSW, ---1-0-- SP ← SP - 1, PC L ← (0FFDEH), PC H ← (0FFDFH) 2 DI 60 1 3 Disable interrupts : I ← “0” -----0-- 3 EI E0 1 3 Enable interrupts : I ← “1” -----1-- 4 NOP FF 1 2 No operation -------- 5 POP A 0D 1 4 Pop from stack 6 POP X 2D 1 4 SP ← SP + 1, Reg. ← M(SP) 7 POP Y 4D 1 4 8 POP PSW 6D 1 4 9 PUSH A 0E 1 4 Push to stack 10 PUSH X 2E 1 4 M(SP) ← Reg. 11 PUSH Y 4E 1 4 12 PUSH PSW 6E 1 4 13 RET 6F 1 5 (restored) SP ← SP - 1 Return from subroutine : SP ← SP+1, PCL ← M(SP), SP ← SP+1, PCH ← M(SP) 14 RETI 7F 1 6 -------- -------- -------- Return from interrupt : SP ← SP+1, PSW ← M(SP), SP ← SP+1,PCL ← M(SP), (restored) SP ← SP+1, PCH ← M(SP) 98 PRELIMINARY Nov. 1999 Ver 1.0