12-BIT 500KSPS ADC AEGISADC GENERAL DESCRIPTION FEATURES The AEGISADC is a CMOS 2.5V 12-bit analog-todigital converter (ADC). It converts the analog input signal into 12-bit binary digital codes at a maximum conversion rate of 500KSPS with 2.5MHz clock. The device is a recycling type monolithic ADC with an on-chip sample-and-hold function. The ADC has power down mode. TYPICAL APPLICATIONS • Resolution : 12-bit • Maximum Conversion Rate : 500KSPS • Main Clock : 2.5MHz • Power Supply : 2.5V ±0.2V • Total Current : 20uA (Standby Mode) 2.2mA (Normal Operation) • Input Range : 0.0V ~ 2.5V (2.5VP-P) • Differential Linearity Error : ±1.0 LSB • Integral Linearity Error : ±2.0 LSB • Signal to Noise & Distortion Ratio : 62dB • Digital Output : CMOS Level • Operating Temperature Range : 0 °C ~ 70 °C MICOM Interface Portable Equipment Low-Voltage Low-Power Application FUNCTIONAL BLOCK DIAGRAM AINT MDAC1 STBY MAIN BIAS VREF AGND REF GEN MDAC2 FLASH1 FLASH2 CML GEN CKIN STC CLOCK GEN DIGITAL LOGIC Ver 1.2 (Apr. 2002) This datasheet is a preliminary version. No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this data sheet is subject to change without any notice. SAMSUNG ELECTRONICS Co. LTD DO[11:0] EOC AEGISADC 12bit 500KSPS ADC CORE PIN DESCRIPTION NAME I/O TYPE I/O PAD VREF AI pia_abb Reference Top (2.5V) AGND AI pia_abb Reference Bottom (0.0V) AVDD25A1 AP AVBB25A1 AG vbb_abb AVSS25A1 AG vss2t_abb Analog Ground (0.0V) AINT AI Analog Input piar50_abb (Input Range : 0.0V ~ 2.5V) STBY DI picc_abb VDD=power saving (standby), GND=normal CKIN DI picc_abb Sampling Clock Input D[11:0] DO poa_abb Digital Output EOC DO poa_abb End of Conversion Signal STC DI picc_abb Start of Conversion Signal AVSS25A2 DG vss2t_abb Digital GND (0.0V) AVDD25A2 DP vdd2t_abb Digital Power (2.5V) I/O TYPE ABBR. PIN DESCRIPTION vdd2t_abb Analog Power (2.5V) Analog Sub Bias (0.0V) • • • • AI : Analog Input DI : Digital Input AO : Analog Output DO : Analog Output • • • • AP AG DP DG : : : : Analog Power Analog Ground Digital Power Digital Ground • AB : Analog Bidirection • DB : Digital Bidirection avss25a1 avdd25a2 avdd25a1 avbb25a1 avss25a2 AINT [MSB:LSB] DO[11:0] aegisadc EOC VREF AGND STBY CKIN SEC ASIC 2/9 STC MIXED AEGISADC 12bit 500KSPS ADC ABSOLUTE MAXIMUM RATINGS Characteristics Value Symbol Unit Supply Voltage VDD 3.3 V Analog Input Voltage AINT VSS to VDD V Digital Input Voltage CKIN VSS to VDD V VREF / AGND VSS to VDD V Reference Voltage Storage Temperature Range Tstg -45 to 150 °C Operating Temperature Range Topr 0 to 70 °C NOTES 1. Absolute maximum rating specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5kΩ resistor (Human body model) RECOMMENDED OPERATING CONDITIONS Characteristics Symbol Min Typ Max Unit 2.3 2.5 2.7 V 2.0 2.5 2.7 AGND 0.0 0.0 0.0 Analog Input Voltage AINT 0.0 VREF - V Operating Temperature Toper 0 - 70 °C AVDD25A1 Supply Voltage Reference Input Voltage AVDD25A2 VREF V NOTES It is strongly recommended that all the supply pins (AVDD25A1, AVDD25A2) be powered from the same source to avoid power latch-up. DC ELECTRICAL CHARACTERISTICS Characteristics Differential Nonlinearity Integral Symbol Min Typ Max Unit DNL - ±0.8 ±1 LSB INL - ±1.0 ±3 LSB OFF - 10 16 LSB Nonlinearity Offset Voltage Test Condition VREF=2.5V AGND=0.0V VREF=2.5V AGND=0.0V VREF=2.5V AGND=0.0V (Converter Specifications : AVDD25A1=AVDD25A2=2.5V, AVSS25A1=AVSS25A2=0V, Toper=25 °C, VREF=2.5V, AGND=0.0V unless otherwise specified) SEC ASIC 3/9 MIXED AEGISADC 12bit 500KSPS ADC AC ELECTRICAL CHARACTERISTICS Characteristics Maximum Conversion Rate Standby Supply Symbol Min Typ Max Unit Test Condition fc - - 500 KSPS fCKIN = 2.5MHz - 20 40 uA STBY = VDD Current Dynamic Supply Current IVDD - 1.8 2.4 mA Reference Current IREF - 0.4 0.6 mA THD - -70 -66 dB SNDR 60 62 - dB Total Harmonic Distortion Signal-to-Noise & Distortion Ratio fCKIN=2.5MHz (without system load) VREF = 2.5V fCKIN = 2.5MHz AINT=100kHz fCKIN = 2.5MHz AINT=100kHz (Converter Specifications : AVDD25A1=AVDD25A2=2.5V, AVSS25A1=AVSS25A2=0V, Toper=25 °C, VREF=2.5V, AGND=0.0V unless otherwise specified) I/O CHART Index AINT Input (V) Digital Output 0 ~ 0.00061 0000 0000 0000 1 0.00061 ~ 0.00122 0000 0000 0001 2 0.00122 ~ 0.00183 0000 0000 0010 ~ ~ ~ 2047 1.64939 ~ 1.25000 0111 1111 1111 2048 1.25000 ~ 1.25061 1000 0000 0000 2049 1.25061 ~ 1.25122 1000 0000 0001 ~ ~ ~ 4093 2.49817 ~ 2.49872 1111 1111 1101 4094 2.49872 ~ 2.49939 1111 1111 1110 4095 2.49939 ~ 1111 1111 1111 SEC ASIC 4/9 1LSB=0.61mV VREF=2.5V AGND=0.0V MIXED AEGISADC 12bit 500KSPS ADC TIMING DIAGRAM 1. Main Waveform A2 A1 AINT Input Sampling Period CKIN 1 2 3 4 5 STBY STC EOC DO[11:0] 2. STC & CKIN Condition CKIN 10ns TSAFE 3ns STC The A/D Converter operates data conversion when STC (Start Conversion) signal is just "HIGH". Otherwise, output data (DO[11:0]) keep the current states. The STC signal should be changed during "TSAFE" with the "HIGH" level of the clock to operation as shown in the main waveform. • ADC External Interface Signal AINT : Analog Input Signal (Input) Input Range : VREF ~ AGND STBY : Stand-by Signal, Power Save Mode (Input) CKIN : ADC Main Clock, fCKIN = 2.5MHz, 1 Clock Period = 400ns (Input) STC : Start of Conversion Signal (Input) EOC : End of Conversion Signal (Output) DO[11:0] : Digital Output Signal (Output) SEC ASIC 5/9 MIXED AEGISADC 12bit 500KSPS ADC CORE EVALUATION GUIDE 1. ADC function is evaluated by external check on the bidirectional pads connected to input nodes of HOST DSP back-end circuit. 2. The reference voltages may be biased internally through resistor divider. avss25a1 avdd25a2 avdd25a1 avbb25a1 avss25a2 AINT [MSB:LSB] DO[11:0] aegisadc EOC VREF AGND STBY CKIN STC D[11:0] D[11:0] Digital Mux HOST DSP CORE D[11:0] Bidirectional PAD (ADC Function Test & externally forced Digital Input) SEC ASIC 6/9 MIXED AEGISADC 12bit 500KSPS ADC USER GUIDE 1. Input Range - The analog input is single-ended type and the range is from VREF to AGND. This AINT voltage follows reference voltage range fundamentally. So, if you want to alter into the another input range, you should change the voltage value of VREF. - You can use the AINT voltage whose minimum range is 2.0V. In this case, the VREF is 2.0V. SEC ASIC 7/9 MIXED AEGISADC 12bit 500KSPS ADC PHANTOM CELL INFORMATION STC EOC DO[6] DO[7] DO[11] DO[8] DO[9] DO[10] DO[5] DO[4] DO[3] DO[2] DO[1] DO[0] AVDD25A2 AVSS25A2 VREF AGND STBY aegisadc CKIN AVDD25A1AVSS25A1 AINT AVBB25A1 NAME I/O TYPE Pin Usage AINT AI Internal/External STBY DI Internal/External CKIN DI Internal/External D[11:0] DO Internal/External EOC DO Internal/External STC DI Internal/External VREF AI External AGND AI External AVDD25A1 AP External AVBB25A1 AG External AVSS25A1 AG External AVSS25A2 DG External AVDD25A2 DP External SEC ASIC PIN DESCRIPTION AINT signal should not be crossed by any signals and should not run next to digital signals to minimize capacitive coupling between the two signals. Voltage reference lines (VREF and AGND) must be wide metal to reduce voltage drop of metal lines. 1. It is recommended that you use thick analog power metal. When connected to PAD, the path should be kept as short as possible. 2. Digital power and analog power are separately used. 8/9 MIXED AEGISADC 12bit 500KSPS ADC FEEDBACK REQUEST ADC Specification Parameter Min Typ Max Unit Supply voltage V Reference Input voltage V Analog Input voltage Vpp Operating temperature °C Integral non-linearity error LSB Differential non-linearity error LSB Offset voltage error (Bottom) mV Offset voltage error (Top) mV Maximum conversion rate MSPS Dynamic supply current mA Power dissipation mW Signal-to-noise ratio dB Remarks Digital output format (Provide detailed description & timing diagram) • What do you want to choose as power supply voltages? For example, the analog VDD needs to be 5V. the digital VDD can be 2.5V/5V. • What resolution do you need for ADC? • How about conversion speed (data in → data out)? • How many cycles do exist during the latency of ADC (pipelined delay)? • What's the input range? And then what do you need between single input and differential input? • Can the bus interface be compatible with TTL? • Could you explain external/internal pin configurations as required? Specially requested function list : SEC ASIC 9/9 MIXED AEGISADC 12bit 500KSPS ADC HISTORY CARD Version Date ver 1.0 Modified Items Comments Original version published (preliminary) ver 1.1 2000.03 ver 1.2 02.04.29 Add the pin information to the phantom cell information SEC ASIC MIXED