ETC ADC1395X

10-BIT 500KSPS ADC
ADC1395X
GENERAL DESCRIPTION
FEATURES
The ADC1395X is a CMOS 3.3V 10-bit analog-todigital converter (ADC). It converts the analog input
signal into 10-bit binary digital codes at a maximum
conversion rate of 500KSPS with 2.5MHz clock.
The device is a recycling type monolithic ADC with
an on-chip sample-and-hold function.
The ADC has
power down mode.
TYPICAL APPLICATIONS
• Resolution : 10-bit
• Maximum Conversion Rate : 500KSPS
• Main Clock : 2.5MHz
• Power Supply : 3.3V ±0.3V
• Total Current : 10uA (Standby Mode)
2.7mA (Normal Operation)
• Input Range : 0.0V ~ 3.3V (3.3VP-P)
• Differential Linearity Error : ±1.0 LSB (Max)
• Integral Linearity Error : ±3.0 LSB (Max.)
• Signal to Noise & Distortion Ratio : 54dB
• Digital Output : CMOS Level
• Operating Temperature Range : -40 °C ~ 85 °C
MICOM Interface
Portable Equipment
Low-Voltage Low-Power Application
FUNCTIONAL BLOCK DIAGRAM
AINT
MDAC1
STBY
MAIN
BIAS
VREF
AGND
REF
GEN
MDAC2
FLASH1
FLASH2
CML
GEN
CKIN
STC
CLOCK
GEN
DIGITAL
LOGIC
Ver 1.0 (April. 2002)
No responsibility is assumed by SEC for its use nor for any infringements of patents
or other rights of third parties that may result from its use. The content of this data
sheet is subject to change without any notice.
SAMSUNG ELECTRONICS Co. LTD
DO[9:0]
EOC
10bit 500KSPS ADC
ADC1395X
CORE PIN DESCRIPTION
NAME
I/O TYPE
I/O PAD
PIN DESCRIPTION
VREF
AI
phia_abb
Reference Top (3.3V)
AGND
AI
phia_abb
Reference Bottom (0.0V)
AVDD33A
AP
AVBB33A
AG
vbbh_abb Analog Sub Bias (0.0V)
AVSS33A
AG
vssth_abb Analog Ground (0.0V)
AINT
AI
phiar50_abb
Analog Input
(Input Range : 0.0V ~ 3.3V)
STBY
DI
phicc_abb
VDD=power saving (standby),
GND=normal
CKIN
DI
phicc_abb Sampling Clock Input
D[9:0]
DO
phob4_abb Digital Output
EOC
DO
phob4_abb End of Conversion Signal
STC
DI
phicc_bb
AVSS33D
DG
vssth_abb Digital GND (0.0V)
AVDD33D
DP
vdd33th_abb Digital Power (3.3V)
vdd33th_abb Analog Power (3.3V)
I/O TYPE
•
•
•
•
AI : Analog Input
DI : Digital Input
AO : Analog Output
DO : Analog Output
•
•
•
•
AP
AG
DP
DG
:
:
:
:
Analog Power
Analog Ground
Digital Power
Digital Ground
• AB : Analog Bidirection
• DB : Digital Bidirection
Start of Conversion Signal
AVSS33A
AVDD33D
AVDD33A AVBB33A
AVSS33D
AINT
adc1395x
[MSB:LSB]
DO[9:0]
EOC
VREF
AGND
STBY CKIN
SEC ASIC
2/11
STC
Analog Core
10bit 500KSPS ADC
ADC1395X
ABSOLUTE MAXIMUM RATINGS
Characteristics
Value
Symbol
Unit
Supply Voltage
VDD
4.5
V
Analog Input Voltage
AINT
VSS to VDD
V
Digital Input Voltage
CKIN
VSS to VDD
V
VREF / AGND
VSS to VDD
V
-45 to 150
-40 to 85
°C
°C
Reference Voltage
Storage Temperature Range
Operating Temperature Range
Tstg
Topr
NOTES
1. Absolute maximum rating specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE
MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values
kept within the following operating conditions and function operation under any of these conditions is not implied.
2. All voltages are measured with respect to VSS unless otherwise specified.
3. 100pF capacitor is discharged through a 1.5kΩ resistor (Human body model)
RECOMMENDED OPERATING CONDITIONS
Characteristics
Symbol
Min
Typ
Max
Unit
3.0
3.3
3.6
V
VREF
2.0
3.3
3.6
AGND
0.0
0.0
0.0
Analog Input Voltage
AINT
0.0
VREF
-
V
Operating Temperature
Toper
-40
-
85
°C
AVDD33A
Supply Voltage
AVDD33D
Reference Input Voltage
V
NOTES
It is strongly recommended that all the supply pins (AVDD33A, AVDD33D) be powered from the same source to avoid power
latch-up.
DC ELECTRICAL CHARACTERISTICS
Characteristics
Differential
Nonlinearity
Integral
Nonlinearity
Offset
Voltage
Symbol
Min
Typ
Max
Unit
DNL
-
±0.8
±1
LSB
INL
-
±1.0
±3
LSB
OFF
-
3
8
LSB
Test Condition
VREF=3.3V
AGND=0.0V
VREF=3.3V
AGND=0.0V
VREF=3.3V
AGND=0.0V
(Converter Specifications : AVDD33A=AVDD33D=3.3V, AVSS33A=AVSS33D=0V,
Toper=25 °C, VREF=3.3V, AGND=0.0V unless otherwise specified)
SEC ASIC
3/11
Analog Core
10bit 500KSPS ADC
ADC1395X
AC ELECTRICAL CHARACTERISTICS
Characteristics
Maximum
Conversion Rate
Standby Supply
Symbol
Min
Typ
Max
Unit
Test Condition
fc
-
-
500
KSPS
fCKIN = 2.5MHz
-
10
40
uA
STBY = VDD
Current
Dynamic Supply Current
IVDD
-
2.7
3
mA
Reference Current
Total Harmonic
IREF
-
0.4
0.6
mA
THD
-
-58
-
dB
SNDR
48
54
-
dB
Distortion
Signal-to-Noise &
Distortion Ratio
fCKIN =2.5MHz
(without system load)
V REF = 3.3V
fCKIN = 2.5MHz
AINT=100kHz
fCKIN = 2.5MHz
AINT=100kHz
(Converter Specifications : AVDD33A=AVDD33D=3.3V, AVSS33A=AVSS33D=0V,
Toper=25 °C, VREF=3.3V, AGND=0.0V unless otherwise specified)
I/O CHART(12bit)
Index
AINT Input (V)
0
~ 0.00323
Digital Output
00 0000 0000
1
0.00323 ~ 0.0645
00 0000 0001
2
0.00645 ~ 0.00968
00 0000 0002
~
~
~
511
1.64677 ~ 1.65000
01 1111 1111
512
1.65000 ~ 1.65323
10 0000 0000
513
1.65323 ~ 1.65545
10 0000 0001
~
~
~
1021
3.29022 ~ 3.29355
11 1111 1101
1022
3.29355 ~ 3.29677
11 1111 1110
1023
3.29677 ~
11 1111 1111
SEC ASIC
4/11
1LSB=3.23mV
VREF=3.3V
AGND=0.0V
Analog Core
10bit 500KSPS ADC
ADC1395X
TIMING DIAGRAM
1. Main Waveform
A2
A1
AINT
Input Sampling Period
CKIN
1
2
3
4
5
STBY
STC
EOC
DO[9:0]
2. STC & CKIN Condition
CKIN
10ns
TSAFE
3ns
STC
The A/D Converter operates data conversion when STC (Start Conversion) signal is just "HIGH". Otherwise,
output data (DO[9:0]) keep the current states. The STC signal should be changed during "TSAFE" with the
"HIGH" level of the clock to operation as shown in the main waveform.
• ADC External Interface Signal
AINT : Analog Input Signal (Input)
Input Range : VREF ~ AGND
STBY : Stand-by Signal, Power Save Mode (Input)
CKIN : ADC Main Clock, fCKIN = 2.5MHz, 1 Clock Period = 400ns (Input)
STC
: Start of Conversion Signal (Input)
EOC : End of Conversion Signal (Output)
DO[9:0] : Digital Output Signal (Output)
SEC ASIC
5/11
Analog Core
10bit 500KSPS ADC
ADC1395X
CORE EVALUATION GUIDE
1. ADC function is evaluated by external check on the bidirectional pads connected to input nodes of HOST DSP
back-end circuit.
2. The reference voltages may be biased internally through resistor divider.
AVSS33A
AVDD33D
AVDD33A AVBB33A
AVSS33D
AINT
[MSB:LSB]
DO[9:0]
adc1395x
EOC
VREF
AGND
STBY CKIN
STC
D[9:0]
D[9:0]
Digital Mux
HOST
DSP
CORE
D[9:0]
Bidirectional
PAD
(ADC Function Test &
externally forced Digital Input)
SEC ASIC
6/11
Analog Core
10bit 500KSPS ADC
ADC1395X
PACKAGE CONFIGURATION
NOTES
1. NC denotes "No Connection".
Digital I
10u
0.1u
10u
0.1u
10u
0.1u
10u
0.1u
Analog
Digital II
10u
SEC ASIC
0.1u
1
VREF
AVDD33D
48
2
VREF
AVDD33D
47
3
AGND
AVSS33D
46
4
AGND
AVSS33D
45
5
NC
NC 44
6
AVDD33A
NC 43
7
AVDD33A
STC 42
8
AVBB33A
EOC 41
9
AVSS33A
NC 40
10
AVSS33A
11
AINT
NC 39
DO[9] 38
12
NC
13
NC
14
NC
15
NC
16
NC
17
STBY
DO[4] 33
DO[3] 32
18
VDDR
DO[2] 31
19
VSSR
20
CKIN
DO[1] 30
DO[0] 29
21
NC
TEST 28
22
NC
TEST 27
23
NC
NC 26
24
RP
RN 25
adc1395x
0.1u
10u
DO[8] 37
DO[7] 36
DO[6] 35
DO[5] 34
7/11
Analog Core
10bit 500KSPS ADC
ADC1395X
PACKAGE PIN DESCRIPTION
I/O
No.
NAME
1,2
VREF
AI
Reference Voltage (3.3V)
3,4
AGND
AI
Analog Ground (0.0V)
6, 7
VDDA
AP
8
VBBA
9, 10
VSSA
TYPE
PIN DESCRIPTION
CONFIGURATION
VREF
1
48
VDDD
Analog Power (3.3V)
VREF
2
47
VDDD
AG
Analog Sub Bias
AGND
3
46
VSSD
AG
Analog Ground
AGND
4
45
VSSD
NC
5
44
NC
VDDA
6
43
NC
VDDA
7
42
STC
VBBA
8
41
EOC
VSSA
9
40
NC
11
AINT
AI
17
STBY
DI
Analog Input
VDD=Power saving (Standby),
GND=Normal
18
VDDR
PP
PAD Power (3.3V)
VSSA
10
39
NC
19
VSSR
PG
PAD Ground
AINT
11
38
DO[9]
20
CKIN
DI
Clock Input (fCKIN = 2.5MHz)
NC
12
37
DO[8]
NC
13
36
DO[7]
24
RP
AO
Test Pin1
NC
14
35
DO[6]
25
RN
AO
Test Pin2
NC
15
34
DO[5]
27,28
TEST
DO
12bit TEST
NC
16
33
DO[4]
29
DO[0]
DO
Digital Output(LSB)
STBY
17
32
DO[3]
VDDR
18
31
DO[2]
30~37
DO[1:8]
DO
Digital Output
VSSR
19
30
DO[1]
38
DO[9]
DO
Digital Output(MSB)
CKIN
20
29
DO[0]
41
EOC
DO
End of Conversion Signal
NC
21
28
TEST
42
STC
DI
Start of Conversion Signal
NC
22
27
TEST
NC
23
26
NC
45, 46
VSSD
DG
Digital GND
RP
24
25
RN
47, 48
VSSD
DP
Digital Power (3.3V)
adc1395x
NOTES
1. I/O TYPE PP and PG denote PAD Power and PAD Ground respectively.
SEC ASIC
8/11
Analog Core
10bit 500KSPS ADC
ADC1395X
PHANTOM CELL INFORMATION
- Pins of the core can be assigned externally (Package pins) or internally (internal ports) depending
on design methods.
The term "External" implies that the pins should be assigned externally like power pins.
The term "External/internal" implies that the applications of these pins depend on the user.
ECO
AVBB33A
CKIN
STC
AVDD33A
AVSS33A
STBY
External
AVBB33A
AVDD33D
AVSS33D
AVBB33D
External
External
Pin Layout Guide
- Maintain the large width of lines as
far as the pads.
- place the port positions to minimize
the length of power lines.
- Do not merge the analog powers with
anoter power from other blocks.
- Use good power and ground source
on board.
- Do not overlap with digtal lines.
AINT
External/Internal
DO[8]
CKIN
External/Internal - Separate from all other analog signals
DO[9]
AGND
External/Internal - Maintain the larger width and the
VREF
External/Internal
STBY
External/Internal
DO[7]
AVSS33D
External
AVDD33
DO[6]
AINT
AVSS33A
DO[1]
DO[5]
10 bit 500K ADC
External
External
DO[4]
adc1395x
AVDD33A
AVBB33A
DO[3]
VREF
Pin Usage
DO[0]
DO[2]
AGND
Pin Name
STC
External/Internal
EOC
External/Internal
DO[9]
External/Internal
DO[8]
External/Internal
DO[7]
External/Internal
DO[6]
External/Internal
DO[5]
External/Internal
DO[4]
External/Internal
DO[3]
External/Internal
DO[2]
External/Internal
DO[1]
External/Internal
DO[0]
External/Internal
- Maintain the shotest path to pads.
shorter length as far as the pads.
- Separate from all other digital lines.
- Separated from the analog clean
signals if possible.
- Do not exceed the length by
1,000um.
9 / 11
SEC ASIC
Analog Core
10bit 500KSPS ADC
ADC1395X
USER GUIDE
1. Input Range
- The analog input is single-ended type and the range is from VREF to AGND. This AINT voltage follows
reference voltage range fundamentally. So, if you want to alter into the another input range, you should
change the voltage value of VREF.
- You can use the AINT voltage whose minimum range is 2.0V. In this case, the VREF is 2.0V.
SEC ASIC
10/11
Analog Core
10bit 500KSPS ADC
ADC1395X
FEEDBACK REQUEST
ADC Specification
Parameter
Min
Typ
Max
Unit
Supply voltage
V
Reference Input voltage
V
Analog Input voltage
Vpp
Operating temperature
°C
Integral non-linearity error
LSB
Differential non-linearity error
LSB
Offset voltage error (Bottom)
mV
Offset voltage error (Top)
mV
Maximum conversion rate
MSPS
Dynamic supply current
mA
Power dissipation
mW
Signal-to-noise ratio
dB
Remarks
Digital output format
(Provide detailed description
& timing diagram)
• What do you want to choose as power supply voltages? For example, the analog VDD needs to be 5V. the
digital VDD can be 3.3V/5V.
• What resolution do you need for ADC?
• How about conversion speed (data in → data out)?
• How many cycles do exist during the latency of ADC (pipelined delay)?
• What's the input range? And then what do you need between single input and differential input?
• Can the bus interface be compatible with TTL?
• Could you explain external/internal pin configurations as required?
Specially requested function list :
SEC ASIC
11/11
Analog Core