10BIT 30MSPS ADC ADC1280X GENERAL DESCRIPTION FEATURES The ADC1280X is a CMOS 10-bit low-voltage and high-speed A/D converter (ADC) for video and other applications. It has a four-step pipelined architecture, which consists of sample & hold amplifier, multiplying D/A converters (DACs), and subranging flash ADCs. The maximum conversion rate of ADC1280X is 30MSPS and supply voltage is 1.8V single. - Resolution : 10Bit Differential Linearity Error : ±1.0 LSB Integral Linearity Error : ±2.0 LSB Maximum Conversion Rate : 30MSPS Sample & Hold Function Implemented Low Power Consumption : 21.6mW(Typ) Power Supply : 1.8V Single Operating Temperature Range : -40~85ºC TYPICAL APPLICATIONS - CCD imaging processors Camcorders, scanners, and security cameras. - Read channel LSI HDD, DVD, and CD-ROM drives - IF and baseband signal digitizers - Portable equipments for low-power applications AVBB18D AVSS18D AVDD18D AVBB18A AVSS18A AVDD18A FUNCTIONAL BLOCK DIAGRAM AINT SHA MDAC1 MDAC2 MDAC3 Flash1 Flash2 Flash3 AINC REFTOP REFBOT STC ITEST STBY Flash4 EOC Digital Correction Logic (DCL) Bias Current Generator DO[9:0] Clock Generator CML Level Generator Ver 2.2 (May 2002) No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this datasheet is subject to change without any notice. SAMSUNG ELECTRONICS Co. LTD CML CKIN SPEEDUP ADC1280X 10BIT 30MSPS ADC CORE PIN DESCRIPTION NAME I/O TYPE I/O PAD PIN DESCRIPTION AINT AI piar50_abb Analog Input + (0.5V ~ 1.3V) AINC AI piar50_abb Analog Input - (1.3V ~ 0.5V) REFTOP AI pia_abb Reference Top (1.3V) REFBOT AI pia_abb Reference Bottom (0.5V) AVDD18A AP vdd1t_abb Analog Power (1.8V) AVSS18A AG vss1t_abb Analog Ground AVBB18A AG vbb1_abb Analog Sub Bias ITEST AB pia_abb Test pin (normally, open) STBY DI picc_abb Standby mode (normally, gnd) STC DI picc_abb Start of conversion signal (normally, high) SPEEDUP DI picc_abb Speed test pin (normally, gnd) CKIN DI picc_abb Sampling Clock Input CML AB pia_abb Test Pin (normally, open) DO[9:0] DO poa_abb Digital Output EOC DO poa_abb End of conversion signal AVBB18D DG vbb1_abb Digital Sub Bias AVSS18D DG vss1t_abb Digital Ground AVDD18D DP vdd1t_abb Digital Power I/O TYPE ABBR. - AI : Analog Input DI : Digital Input AO : Analog Output DO : Digital Output AB : Analog Bidirectional DB : Digital Bidirectional - AP DP AG DG : : : : Analog Power Digital Power Analog Ground Digital Ground AVBB18D AVSS18D AVDD18D AVBB18A AVSS18A AVDD18A CORE CONFIGURATION EOC AINT adc1280x DO[9:0] AINC 2 / 12 SPEEDUP STC STBY ITEST CML REFTOP SEC ASIC REFBOT CKIN MIXED ADC1280X 10BIT 30MSPS ADC ABSOLUTE MAXIMUM RATINGS Characteristic Value Symbol Unit Supply Voltage VDD 2.5 V Analog Input Voltage AIN VSS to VDD V Digital Input Voltage CLK VSS to VDD V VOH, VOL VSS to VDD V -45 to 125 ºC Digital Output Voltage Storage Temperature Range Tstg NOTES 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5KΩ resistor (Human body model). RECOMMENDED OPERATING CONDITIONS Symbol Min Typ Max Unit Supply Voltage AVDD18A - AVSS18A AVDD18D - AVSS18D 1.7 1.8 1.9 V Supply Voltage Difference AVDD18A - AVDD18D -0.1 0.0 0.1 V REFTOP REFBOT - 1.3 0.5 - V Analog Input Voltage (+) AINT 0.5 - 1.3 V Analog Input Voltage (-) AINC 1.3 - 0.5 V Operating Temperature Topr -40 - 85 ºC Characteristics Reference Input Voltage(Externally) NOTES 1. It is strongly recommended that all the supply pins (AVDD18A, AVDD18D) be powered from the same source to avoid power latch-up. SEC ASIC 3 / 12 MIXED ADC1280X 10BIT 30MSPS ADC DC ELECTRICAL CHARACTERISTICS Characteristics Symbol Min Typ Max Unit - - 10 - Bits Reference Current IREF - 2 3 mA Differential Linearity Error DLE - - ±1.0 LSB Integral Linearity Error ILE - - ±2.0 LSB Bottom Offset Voltage Error EOB - - 20 LSB Top Offset Voltage Error EOT - - 20 LSB Resolution Conditions NOTES 1. Converter Specifications (unless otherwise specified) AVDD18A=1.8V AVDD18D=1.8V AVSS18A=GND AVSS18D=GND Ta=25ºC 2. TBD : To Be Determined AC ELECTRICAL CHARACTERISTICS Characteristics Symbol Min Typ Max Unit Maximum Conversion Rate fc - - 30 MSPS Dynamic Supply Current Ivdd - - 12 mA fc=30MHz (without system load) Digital Output Data Delay td - 2.1 - ns See "TIMING DIAGRAM" Signal - to - Noise Ratio SNR 48 52 - dB AINT = 1MHz fc = 30MHz SEC ASIC 4 / 12 Conditions MIXED ADC1280X 10BIT 30MSPS ADC I/O CHART Index AINT Input (V) AINC Input (V) Digital Output 0 0.50000 ~ 0.50078 1.29922 ~ 1.30000 0000000000 1 0.50078 ~ 0.50156 1.29844 ~ 1.29922 0000000001 2 0.50156 ~ 0.50234 1.29766 ~ 1.29844 0000000010 ••• ••• ••• ••• 1LSB=1.5625mV 511 0.89922 ~ 0.90000 0.90078 ~ 0.90156 0111111111 for differential input 512 0.90000 ~ 0.90078 0.90000 ~ 0.90078 1000000000 513 0.90078 ~ 0.90156 0.89922 ~ 0.90000 1000000001 REFTOP=1.3V ••• ••• ••• ••• REFBOT=0.5V 1021 1.29766 ~ 1.29844 0.50156 ~ 0.50234 1111111101 1022 1.29844 ~ 1.29922 0.50078 ~ 0.50156 1111111110 1023 1.29922 ~ 1.30000 0.50000 ~ 0.50078 1111111111 SEC ASIC 5 / 12 MIXED ADC1280X 10BIT 30MSPS ADC TIMING DIAGRAM 1. Main Waveform A1 Analog Input A2 A6 A4 CKIN STC Pipeline Delay EOC td DO[9:0] D1 D2 D4 D6 Output code of DO[9:0] is generated during STC (Start of Conversion) signal is just "HIGH". Otherwise, it keeps the current states. After STC goes "HIGH", the A/D converter requires the pipeline delay of 3 clock period to generate EOC signal and DO[9:0]. 2. STC and CKIN 8ns Tsafe 4ns 8ns Tsafe 4ns CKIN STC The STC signal is rising-edge triggered, and it should be changed during "Tsafe" region on CKIN . SEC ASIC 6 / 12 MIXED ADC1280X 10BIT 30MSPS ADC CORE EVALUATION GUIDE 1. ADC function is evaluated by external check on the bidirectional pads connected to input nodes of HOST DSP back-end circuit. 2. The reference voltages may be biased internally through resistor devider. Analog Input Clock Input AINT AINC CKIN GND AVBB18A AVDD18D STBY AVSS18D AVBB18D GND SPEEDUP EOC DO[9:0] STC GND STC Input or 1.8V GND 1.8V ITEST AVSS18A GND CML 1.8V AVDD18A adc1280x REFBOT GND 1.3V 0.5V Reference Reference Top Bottom REFTOP : 0.1uF CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED : 10uF CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED MUX DIGITAL HOST DSP CORE 7 / 12 NOTES 10-bit Digital Output BIDIRECTIONAL PAD ADC Function Measuring & Digital Input Forcing SEC ASIC MIXED ADC1280X 10BIT 30MSPS ADC PACKAGE CONFIGURATION 1.3V 10u 0.1u 10u 0.1u 0.5V 0.1u 1.8V 10u 0.1u 0.1u Analog input 50 1K 0.1u 0.1u 1.8V 10u 0.1u Clock in 50 1 REFTOP AVDD18D 48 2 REFTOP AVDD18D 47 3 REFBOT AVSS18D 46 4 REFBOT AVSS18D 45 5 CML AVBB18D 44 6 AVDD18A STC 43 STC in 7 AVDD18A EOC 42 EOC out 8 AVBB18A NC 41 9 AVSS18A NC 40 10 AVSS18A NC 39 11 AINT NC 38 12 NC 13 AINC adc1280x_top NC 37 DO[9] 36 14 NC DO[8] 35 15 SPEEDUP DO[7] 34 16 ITEST DO[6] 33 17 STBY DO[5] 32 18 AVDD18R DO[4] 31 19 AVSS18R DO[3] 30 20 CKIN DO[2] 29 21 NC DO[1] 28 22 NC DO[0] 27 23 NC NC 26 24 NC NC 25 1.8V 0.1u 10u 10-b ADC output : Test Pin No bias forcing, Remain floating NOTES 1. This information is for testing the provided test-chips of ADC1280X. SEC ASIC 8 / 12 MIXED ADC1280X 10BIT 30MSPS ADC PACKAGE PIN DESCRIPTION NAME PIN NO. I/O TYPE PIN DESCRIPTION REFTOP 1,2 AI External Reference Top Bias (1.3V) REFBOT 3,4 AI External Reference Bottom Bias (0.5V) CML 5 AB Internal Bias Point (Test Pin) AVDD18A 6,7 AP Analog Power (1.8V) AVBB18A 8 AG Analog Sub Bias AVSS18A 9,10 AG Analog Ground AINT 11 AI Analog Input + (Input Range : 0.5~1.3V Differential) AINC 13 AI Analog Input. - (Input Range : 1.3~0.5V Differential) SPEEDUP 15 DI Speed test pin. Tie to analog gnd ITEST 16 AB open=use internal bias point STBY 17 DI Power saving standby mode (normally gnd) AVDD18R 18 PP Ouput Driver Power (1.8V) AVSS18R 19 PG Output Driver Ground CKIN 20 DI Sampling Clock Input DO[9:0] 27~36 DO 10bit Digitized Output EOC 42 DO End of conversion signal STC 43 DI Start of conversion signal AVBB18D 44 DG Digital Substrate Bias AVSS18D 45,46 DG Digital Ground AVDD18D 47,48 DP Digital Power (1.8V) NOTES 1. This information is for testing the provided test-chips of ADC1280X. 2.. I/O TYPE PP and PG denote PAD Power and PAD Ground respectively. SEC ASIC 9 / 12 MIXED ADC1280X 10BIT 30MSPS ADC USER GUIDE 1. Input signal range The ADC was designed to use both single and differential mode input, but the differential mode is recommended to guarantee the operating margin in the low voltage condition. - Differential mode input condition Pin Input range AINT 0.5V~1.3V AINC 1.3V~0.5V Conditions 180º phase shifted input with the same DC level with AINT - Single mode input condition Pin Input range AINT 0.2V~1.6V AINC 0.9V Conditions forced from the clean DC source or CML pin of adc1280x 2. Input signal speed Normal speed range of adc1280x is 1~6MHz input quantized by 30MHz clock, which is fixed by a normal video signal format. To use the input of adc1280x on near or over nyquist ranges such as the direct IF processing, consult about the additional performance issues with SEC. SEC ASIC 10 / 12 MIXED ADC1280X 10BIT 30MSPS ADC PHANTOM CELL INFORMATION - Pins of the core can be assigned externally (Package pins) or internally (internal ports) depending on design methods. The term "External" implies that the pins should be assigned externally like power pins. The term "External/internal" implies that the applications of these pins depend on the user. AVSS18A AVBB18A AVDD18A AVDD18A AVBB18A AVSS18A Pin Name Pin Usage AVDD18A External AVSS18A External AVBB18A External AVDD18A External Pin Layout Guide - Maintain the large width of lines as far as the pads. - place the port positions to minimize the length of power lines. - Do not merge the analog powers with AVSS18D AVBB18D External External anoter power from other blocks. - Use good power and ground source on board. AINT adc1280x AINC 10bit 30MSPS ADC REFBOT CML REFTOP STBY SPEEDUP ITEST AVBB18D AVDD18D AVSS18D EOC DO[9] DO[8] DO[7] DO[6] DO[5] DO[4] DO[3] DO[2] DO[1] STC DO[0] CKIN SEC ASIC AINT External/Internal - Do not overlap with digtal lines. AINC External/Internal - Maintain the shotest path to pads. CKIN External/Internal - Separate from all other analog signals REFTOP External/Internal - Maintain the larger width and the REFBOT External/Internal shorter length as far as the pads. CML External/Internal - Separate from all other digital lines. ITEST External/Internal STBY External/Internal STC External/Internal SPEEDUP External/Internal EOC External/Internal DO[9] External/Internal DO[8] External/Internal DO[7] External/Internal DO[6] External/Internal DO[5] External/Internal DO[4] External/Internal DO[3] External/Internal DO[2] External/Internal DO[1] External/Internal DO[0] External/Internal 11 / 12 - Separated from the analog clean signals if possible. - Do not exceed the length by 1,000um. MIXED ADC1280X 10BIT 30MSPS ADC FEEDBACK REQUEST It should be quite helpful to our ADC core development if you specify your system requirements on ADC in the following characteristic checking table and fill out the additional questions. We appreciate your interest in our products. Thank you very much. Characteristic Min Typ Max Unit Analog Power Supply Voltage V Digital Power Supply Voltage V Bit Resolution Bit Reference Input Voltage V Analog Input Voltage Vpp Operating Temperature ºC Integral Non-linearity Error LSB Differential Non-linearity Error LSB Bottom Offset Voltage Error mV Top Offset Voltage Error mV Maximum Conversion Rate Remarks MSPS Dynamic Supply Current mA Power Dissipation mW Signal-to-noise Ratio dB Pipeline Delay CLK Digital Output Format (Provide detailed description & timing diagram) 1. Between single input-output and differential input-output configurations, which one is suitable for your system and why? 2. Please comment on the internal/external pin configurations you want our ADC to have, if you have any reason to prefer some type of configuration. 3. Freely list those functions you want to be implemented in our ADC, if you have any. SEC ASIC 12 / 12 MIXED ADC1280X 10BIT 30MSPS ADC HISTORY CARD Version Date Modified Items ver 1.0 00.7.4 Original version published (preliminary) ver 1.1 01.3.10 Change the reference range from "0.6V~1.2V" to "0.5V~1.3V" ver 2.0 01.7.2 Release the formal datasheet ver 2.1 01.8.1 Add "td" spec ver 2.2 02.5.1 Change the Operating Temperature Range from 0~70ºC to -40~85ºC SEC ASIC Comments MIXED