a FEATURES Enhanced Replacement for LF441 and TL061 DC Performance: 200 mA max Quiescent Current 10 pA max Bias Current, Warmed Up (AD548C) 250 mV max Offset Voltage (AD548C) 2 mV/8C max Drift (AD548C) 2 mV p-p Noise, 0.1 Hz to 10 Hz AC Performance: 1.8 V/ms Slew Rate 1 MHz Unity Gain Bandwidth Available in Plastic, Hermetic Cerdip and Hermetic Metal Can Packages and in Chip Form Available in Tape and Reel in Accordance with EIA-481A Standard MIL-STD-883B Parts Available Dual Version Available: AD648 Surface Mount (SOIC) Package Available PRODUCT DESCRIPTION The AD548 is a low power, precision monolithic operational amplifier. It offers both low bias current (10 pA max, warmed up) and low quiescent current (200 µA max) and is fabricated with ion-implanted FET and laser wafer trimming technologies. Input bias current is guaranteed over the AD548’s entire common-mode voltage range. The economical J grade has a maximum guaranteed input offset voltage of less than 2 mV and an input offset voltage drift of less than 20 µV/°C. The C grade reduces input offset voltage to less than 0.25 mV and offset voltage drift to less than 2 µV/°C. This level of dc precision is achieved utilizing Analog’s laser wafer drift trimming process. The combination of low quiescent current and low offset voltage drift minimizes changes in input offset voltage due to self-heating effects. Four additional grades are offered over the commercial, industrial and military temperature ranges. The AD548 is recommended for any dual supply op amp application requiring low power and excellent dc and ac performance. In applications such as battery-powered, precision instrument front ends and CMOS DAC buffers, the AD548’s excellent combination of low input offset voltage and drift, low bias current and low 1/f noise reduces output errors. High common-mode rejection (86 dB, min on the “C” grade) and high open-loop gain ensures better than 12-bit linearity in high impedance, buffer applications. The AD548 is pinned out in a standard op amp configuration and is available in six performance grades. The AD548J and AD548K are rated over the commercial temperature range of 0°C to +70°C. The AD548A, AD548B and AD548C are rated Precision, Low Power BiFET Op Amp AD548 CONNECTION DIAGRAMS Plastic Mini-DIP (N) Package, Cerdip (Q) Package and SOIC (R)Package OFFSET NULL 1 8 NC INVERTING 2 INPUT NONINVERTING 3 INPUT V– 4 7 V+ 6 OUTPUT 5 OFFSET NULL AD548 TOP VIEW 10kΩ TO-99 (H) Package 4 NC OFFSET NULL AD548 V+ 6 3 TOP VIEW 7 INVERTING 2 INPUT NONINVERTING INPUT –15V VOS TRIM 8 1 5 1 5 4 OUTPUT OFFSET NULL V– NOTE : PIN 4 CONNECTED TO CASE NC = NO CONNECT over the industrial temperature range of –40°C to +85°C. The AD548S is rated over the military temperature range of –55°C to +125°C and is available processed to MIL-STD-883B, Rev. C. The AD548 is available in an 8-pin plastic mini-DIP, cerdip, TO-99 metal can, surface mount (SOIC), or in chip form. PRODUCT HIGHLIGHTS 1. A combination of low supply current, excellent dc and ac performance and low drift makes the AD548 the ideal op amp for high performance, low power applications. 2. The AD548 is pin compatible with industry standard op amps such as the LF441, TL061, and AD542, enabling designers to improve performance while achieving a reduction in power dissipation of up to 85%. 3. Guaranteed low input offset voltage (2 mV max) and drift (20 µV/°C max) for the AD548J are achieved utilizing Analog Devices’ laser drift trimming technology, eliminating the need for external trimming. 4. Analog Devices specifies each device in the warmed-up condition, insuring that the device will meet its published specifications in actual use. 5. A dual version, the AD648 is also available. 6. Enhanced replacement for LF441 and TL061. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD548–SPECIFICATIONS (@ +258C and V = 615 V dc unless otherwise noted) S Model Min INPUT OFFSET VOLTAGE 1 Initial Offset TMIN to TMAX vs. Temperature vs. Supply vs. Supply, TMIN to TMAX Long-Term Offset Stability AD548J/A/S Typ Max 0.75 2.0 3.0/3.0/3.0 20 80 76/76/76 Max 5 Min 0.5 0.7/0.8 5 86 80 5 INPUT IMPEDANCE Differential Common Mode AD548K/B Typ 0.3 15 INPUT BIAS CURRENT Either Input 2, VCM = 0 Either Input 2 at TMAX, VCM = 0 Max Input Bias Current Over Common-Mode Voltage Range Offset Current, VCM = 0 Offset Current at T MAX INPUT VOLTAGE RANGE Differential3 Common Mode Common-Mode Rejection VCM = ± 10 V TMIN to TMAX VCM = ± 11 V TMIN to TMAX Min 0.10 3 30 10 0.25/0.65/10 2 1 × 1012i3 3 × 1012i3 Max Units 0.25 0.4 2.0 mV mV µV/°C dB dB µV/Month 10 0.65 pA nA 15 5 0.35 pA pA nA 86 80 15 20 0.45/1.3/20 AD548C Typ 15 10 0.25/0.65 3 15 5 0.15/0.35 2 1 × 1012i3 3 × 1012i3 1 × 1012i3 3 × 1012i3 ΩipF ΩipF ± 11 ± 20 ± 12 ± 11 ± 20 ± 12 ± 11 ± 20 ± 12 V V 76 76/76/76 70 70/70/70 90 90 84 84 82 82 76 76 92 92 86 86 86 86 76 76 98 98 90 90 dB dB dB dB INPUT VOLTAGE NOISE Voltage 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz 2 80 40 30 30 2 80 40 30 30 2 80 40 30 30 INPUT CURRENT NOISE f = 1 kHz 1.8 1.8 1.8 fA/√Hz 1.0 30 1.8 8 MHz kHz V/µs µs FREQUENCY RESPONSE Unity Gain, Small Signal Full Power Response Slew Rate, Unity Gain Settling Time to ± 0.01% 1.0 30 1.8 8 0.8 300 300/300/300 150 150/150/150 1000 700 500 300 OUTPUT CHARACTERISTICS Voltage @ RL ≥ 10 kΩ, TMIN to TMAX Voltage @ RL ≥ 5 kΩ, TMIN to TMAX Short Circuit Current ± 12 ± 12/± 12/± 12 ± 11 ± 11/± 11/± 11 ± 13 POWER SUPPLY Rated Performance Operating Range Quiescent Current ± 4.5 OPEN LOOP GAIN VO = ± 10 V, RL ≥ 10 kΩ TMIN to TMAX, RL ≥ 10 kΩ VO = ± 10 V, RL ≥ 5 kΩ TMIN to TMAX, RL ≥ 5 kΩ TEMPERATURE RANGE Operating, Rated Performance Commercial (0°C to +70°C) Industrial (–40°C to +85°C) Military (–55°C to +125°C) PACKAGE OPTIONS SOIC (R-8) Plastic (N-8) Cerdip (Q-8) Metal Can (H-08A) Tape and Reel Chips Available 0.8 1.0 0.8 300 300 150 150 1000 700 500 300 300 300 150 150 1000 700 500 300 V/mV V/mV V/mV V/mV ± 12 ± 12 ± 11 ± 11 ± 13 ± 12 ± 12 ± 11 ± 11 ± 13 V ± 12.3 V 15 mA 15 ± 15 170 ± 4.5 ± 12.3 ± 15 170 AD548J AD548A AD548S AD548JR AD548JN AD548AQ AD548AH AD548JR-REEL AD548JCHIPS 1.0 15 ± 18 200 µV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz 1.0 30 1.8 8 1.0 ± 12.3 4.0 ± 18 200 AD548K AD548B ± 4.5 ± 15 170 ± 18 200 V V µA AD548C AD548KR, AD548BR AD548KN AD548CQ AD548BH AD548KR-REEL, AD548BR-REEL NOTES 1 Input Offset Voltage specifications are guaranteed after 5 minutes of operation at TA = +25°C. 2 Bias Current specifications are guaranteed maximum at either input after 5 minutes of operation at TA = +25°C. For higher temperature, the current doubles every 10°C. 3 Defined as voltages between inputs, such that neither exceeds ± 10 V from ground. Specifications subject to change without notice. –2– REV. C AD548 ABSOLUTE MAXIMUM RATINGS l METALIZATION PHOTOGRAPH Dimensions shown in inches and (mm). Contact factory for latest dimensions Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 18 V Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 500 mW Input Voltage3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 18 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and –VS Storage Temperature Range (Q, H) . . . . . . . . –65°C to +150°C (N, R) . . . . . . . . –65°C to +125°C Operating Temperature Range AD548J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C AD548A/B/C . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C AD548S . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C NOTES 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Thermal Characteristics: 8-Pin SOIC Package: θJA = 160°C/W, θJC = 42°C/W; 8-Pin Plastic Package: θJA = 90°C/W; 8-Pin Cerdip Package: θJC = 22°C/W, θJA = 110°C/W; 8-Pin Metal Can Package: θJC = 65°C/W, θJA = 150°C/W. 3 For supply voltages less than ± 18 V, the absolute maximum input voltage is equal to the supply voltage. Typical Characteristics 20 20 30 15 +VIN 10 –VIN 5 0 5 10 15 SUPPLY VOLTAGE – ±V –VOUT 10 25°C RL = 10k 5 0 20 5 10 15 SUPPLY VOLTAGE – ±V 20 INPUT BIAS CURRENT – pA 180 160 140 20 15 10 5 10 100 1k LOAD RESISTANCE – Ω 10k Figure 3. Output Voltage Swing vs. Load Resistance 10 200 25 0 0 Figure 2. Output Voltage Swing vs. Supply Voltage Figure 1. Input Voltage Range vs. Supply Voltage QUIESCENT CURRENT – µA 15 100nA 10nA 8 INPUT BIAS CURRENT 0 OUTPUT VOLTAGE SWING – Volts p-p OUTPUT VOLTAGE SWING – ±V INPUT VOLTAGE – ±V +VOUT 6 4 1nA 100pA 10pA 1pA 2 100fA 120 0 0 5 10 15 SUPPLY VOLTAGE – ±V 20 Figure 4. Quiescent Current vs. Supply Voltage 0 4 8 12 16 SUPPLY VOLTAGE – ±V 20 Figure 5. Input Bias Current vs. Supply Voltage CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD548 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. C –3– 10fA –55 –25 5 35 65 TEMPERATURE – °C 95 125 Figure 6. Input Bias Current vs. Temperature WARNING! ESD SENSITIVE DEVICE AD548–Typical Characteristics 30 1500 25 1250 OPEN LOOP GAIN – V/mV 10 INPUT BIAS CURRENT – pA 8 I∆VOSI – µV 20 6 4 15 10 2 750 500 250 0 –6 –2 2 6 10 0 10 100 60 GAIN 40 20 20 0 0 –20 –20 10k 100k 1M PHASE IN DEGREES 80 60 1k 50 60 0 –55 70 –25 5 –40 10M 100 90 80 70 125 Figure 9. Open Loop Gain vs. Temperature 2 4 6 8 10 12 14 SUPPLY VOLTAGE – ±V 16 +SUPPLY 100 80 60 40 –SUPPLY 20 0 100 18 1k 10k 100k FREQUENCY – Hz 1M Figure 12. PSRR vs. Frequency Figure 11. Open Loop Voltage Gain vs. Supply Voltage 22 90 95 –20 0 FREQUENCY – Hz Figure 10. Open Loop Frequency Response 65 120 110 60 35 TEMPERATURE – °C POWER SUPPLY REJECTION – dB PHASE –40 40 120 OPEN LOOP VOLTAGE GAIN – dB 100 40 30 Figure 8. Change in Offset Voltage vs. Warm-Up Time Figure 7. Input Bias Current vs. Common-Mode Voltage 80 20 WARM-UP TIME – Seconds COMMON-MODE VOLTAGE – V OPEN LOOP GAIN – dB 1000 5 0 –10 RL = 10k 10 10mV OUTPUT VOLTAGE – V p-p 80 CMRR – dB 70 60 50 40 OUTPUT VOLTAGE SWING – V 20 18 16 14 12 10 8 6 4 1mV 5 0 –5 1mV 30 2 0 20 1k 10k 100k FREQUENCY – Hz –10 10 1M 100 1k 10k 100k 0 1M 0.1 0.01 UNITY GAIN FOLLOWER 0.001 1k 10k FREQUENCY – Hz Figure 16. Total Harmonic Distortion vs. Frequency 100k 140 INPUT NOISE VOLTAGE – µV p-p INPUT NOISE VOLTAGE – nV/√Hz FOLLOWER WITH GAIN = 10 120 100 80 60 40 20 0 10 100 1k 10k 100k FREQUENCY – Hz Figure 17. Input Noise Voltage Spectral Density –4– 6 8 Figure 15. Output Swing and Error Voltage vs. Output Settling Time 160 1 4 SETTLING TIME – µs Figure 14. Large Signal Frequency Response 4 100 2 FREQUENCY – Hz Figure 13. CMRR vs. Frequency TOTAL HARMONIC DISTORTION – % 10mV WHENEVER JOHNSON NOISE IS GREATER THAN AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE CONSIDERED NEGLIGIBLE FOR APPLICATION 10,000 1,000 1kHz BANDWIDTH RESISTOR JOHNSON NOISE 100 10 10Hz BANDWIDTH 1 AMPLIFIER GENERATED NOISE 0 100k 1M 10M 100M 1G 10G 100G SOURCE IMPEDANCE – Ω Figure 18. Total Noise vs. Source Impedance REV. C Typical Characteristics–AD548 Figure 19a. Unity Gain Follower Figure 20a. Utility Gain Inverter Figure 19b. Unity Gain Follower Pulse Response (Large Signal) Figure 20b. Utility Gain Inverter Pulse Response (Large Signal) APPLICATION NOTES The AD548 is a JFET-input op amp with a guaranteed maximum IB of less than 10 pA, and offset and drift laser-trimmed to 0.25 mV and 2 µV/°C respectively (AD548C). AC specs include 1 MHz bandwidth, 1.8 V/µs typical slew rate and 8 µs settling time for a 20 V step to ± 0.01%—all at a supply current less than 200 µA. To capitalize on the device’s performance, a number of error sources should be considered. The minimal power drain and low offset drift of the AD548 reduce self-heating or “warm-up” effects on input offset voltage, making the AD548 ideal for on/off battery powered applications. The power dissipation due to the AD548’s 200 µA supply current has a negligible effect on input current, but heavy output loading will raise the chip temperature. Since a JFET’s input current doubles for every 10°C rise in chip temperature, this can be a noticeable effect. Figure 19c. Unity Gain Follower Pulse Response (Small Signal) Figure 20c. Unity Gain Inverter Pulse Response (Small Signal) Applying the AD548 Figure 21. Offset Null Configuration LAYOUT OFFSET NULLING To take full advantage of the AD548’s 10 pA max input current, parasitic leakages must be kept below an acceptable level. The practical limit of the resistance of epoxy or phenolic circuit board material is between 1 × 1012 Ω and 3 × 1012 Ω. This can result in an additional leakage of 5 pA between an input of 0 V and a –15 V supply line. Teflon or a similar low leakage material (with a resistance exceeding 1017 Ω) should be used to isolate high impedance input lines from adjacent lines carrying high voltages. The insulator should be kept clean, since contaminants will degrade the surface resistance. Unlike bipolar input amplifiers, zeroing the input offset voltage of a BiFET op amp will not minimize offset drift. Using balance Pins 1 and 5 to adjust the input offset voltage as shown in Figure 21 will induce an added drift of 0.24 µV/°C per 100 µV of nulled offset. The low initial offset (0.25 mV) of the AD548C results in only 0.6 µV/°C of additional drift. A metal guard completely surrounding the high impedance nodes and driven by a voltage near the common-mode input potential can also be used to reduce some parasitic leakages. The guarding pattern in Figure 22 will reduce parasitic leakage due to finite board surface resistance; but it will not compensate for a low volume resistivity board. The amplifier is designed to be functional with power supply voltages as low as ± 4.5 V. It will exhibit a higher input offset voltage than at the rated supply voltage of ± 15 V, due to power supply rejection effects. The common-mode range of the AD548 extends from 3 V more positive than the negative supply to 1 V more negative than the positive supply. Designed to cleanly drive up to 10 kΩ and 100 pF loads, the AD548 will drive a 2 kΩ load with reduced open loop gain. REV. C –5– AD548 Figure 22. Board Layout for Guarding Inputs Figure 24. AD548 Used as DAC Output Amplifier That is: INPUT PROTECTION The AD548 is guaranteed to withstand input voltages equal to the power supply potential. Exceeding the negative supply voltage on either input will forward bias the substrate junction of the chip. The induced current may destroy the amplifier due to excess heat. R VOS Output =VOS Input 1+ FB RO RFB is the feedback resistor for the op amp, which is internal to the DAC. RO is the DAC’s R-2R ladder output resistance. The value of RO is code dependent. This has the effect of changing the offset error voltage at the amplifier’s output. An output amplifier with a sub millivolt input offset voltage is needed to preserve the linearity of the DAC’s transfer function. Input protection is required in applications such as a flame detector in a gas chromatograph, where a very high potential may be applied to the input terminals during a sensor fault condition. Figure 23 shows a simple current limiting scheme that can be used. RPROTECT should be chosen such that the maximum overload current is 1.0 mA (l00 kΩ for a 100 V overload, for example). The AD548 in this configuration provides a 700 kHz small signal bandwidth and 1.8 V/µs typical slew rate. The 33 pF capacitor across the feedback resistor optimizes the circuit’s response. The oscilloscope photos in Figures 25 and 26 show small and large signal outputs of the circuit in Figure 24. Upper traces show the input signal VIN. Lower traces are the resulting output voltage with the DAC’s digital input set to all 1s. The AD548 settles to ± 0.01% for a 20 V input step in 14 µs. Exceeding the negative common-mode range on either input terminal causes a phase reversal at the output, forcing the amplifier output to the corresponding high or low state. Exceeding the negative common-mode on both inputs simultaneously forces the output high. Exceeding the positive common-mode range on a single input doesn’t cause a phase reversal, but if both inputs exceed the limit the output will be forced high. In all cases, normal amplifier operation is resumed when input voltages are brought back within the common-mode range. 5V 20V 5µS 100 90 10 0% Figure 25. Response to ± 20 V p-p Reference Square Wave 50mV Figure 23. Input Protection of IV Converter 200mV 2µS 100 90 D/A CONVERTER OUTPUT BUFFER The circuit in Figure 24 shows the AD548 and AD7545 12-bit CMOS D/A converter in a unipolar binary configuration. VOUT will be equal to VREF attenuated by a factor depending on the digital word. VREF sets the full scale. Overall gain is trimmed by adjusting RIN. The AD548’s low input offset voltage, low drift and clean dynamics make it an attractive low power output buffer. 10 0% Figure 26. Response to ± 100 mV p-p Reference Square Wave The input offset voltage of the AD548 output amplifier results in an output error voltage. This error voltage equals the input offset voltage of the op amp times the noise gain of the amplifier. –6– REV. C Application Hints–AD548 PHOTODIODE PREAMP The performance of the photodiode preamp shown in Figure 27 is enhanced by the AD548’s low input current, input voltage offset and offset voltage drift. The photodiode sources a current proportional to the incident light power on its surface. RF converts the photodiode current to an output voltage equal to RF × IS. Figure 27. An error budget illustrating the importance of low amplifier input current, voltage offset and offset voltage drift to minimize output voltage errors can be developed by considering the equivalent circuit for the small (0.2 mm2 area) photodiode shown in Figure 27. The input current results in an error proportional to the feedback resistance used. The amplifier’s offset will produce an error proportional to the preamp’s noise gain (I + RF/RSH), where RSH is the photodiode shunt resistance. The amplifier’s input current will double with every 10°C rise in temperature, and the photodiode’s shunt resistance halves with every 10°C rise. The error budget in Figure 28 assumes a room temperature photodiode RSH of 500 MΩ, and the maximum input current and input offset voltage specs of an AD548C. TEMP 8C RSH (MV) VOS (mV) (1+ RF/RSH) VOS –25 0 +25 +50 +75 +85 15,970 2,830 500 88.5 15.6 7.8 150 200 250 300 350 370 151 µV 207 µV 300 µV 640 µV 2.6 mV 5.1 mV IB (pA) IBRF TOTAL 0.30 2.26 10.00 56.6 320 640 30 µV 262 µV 1.0 mV 5.6 mV 32 mV 64 mV 181 µV 469 µV 1.30 mV 6.24 mV 34.6 mV 69.1 mV Figure 28. Photo Diode Pre-Amp Errors Over Temperature The capacitance at the amplifier’s negative input (the sum of the photodiode’s shunt capacitance, the op amp’s differential input capacitance, stray capacitance due to wiring, etc.) will cause a rise in the preamp’s noise gain over frequency. This can result in excess noise over the bandwidth of interest. CF reduces the noise gain “peaking” at the expense of bandwidth. INSTRUMENTATION AMPLIFIER The AD548C’s maximum input current of 10 pA makes it an excellent building block for the high input impedance instrumentation amplifier shown in Figure 29. Total current drain for this circuit is under 600 µA. This configuration is optimal for conditioning differential voltages from high impedance sources. The overall gain of the circuit is controlled by RG, resulting in the following transfer function: VOUT VIN REV. C =1+ (R1 + R2 ) RG Figure 29. Low Power Instrumentation Amplifier Gains of 1 to 100 can be accommodated with gain nonlinearities of less than 0.01%. Referred to input errors, which contribute an output error proportional to in amp gain, include a maximum untrimmed input offset voltage of 0.5 mV and an input offset voltage drift over temperature of 4 µV/°C. Output errors, which are independent of gain, will contribute an additional 0.5 mV offset and 4 µV/°C drift. The maximum input current is 15 pA over the common-mode range, with a common-mode impedance of over 1 × 1012 Ω. Resistor pairs R3/R5 and R4/R6 should be ratio matched to 0.01% to take full advantage of the AD548’s high common-mode rejection. Capacitors C1 and C1′ compensate for peaking in the gain over frequency caused by input capacitance when gains of 1 to 3 are used. The –3 dB small signal bandwidth for this low power instrumentation amplifier is 700 kHz for a gain of 1 and 10 kHz for a gain of 100. The typical output slew rate is 1.8 V/µs. LOG RATIO AMPLIFIER Log ratio amplifiers are useful for a variety of signal conditioning applications, such as linearizing exponential transducer outputs and compressing analog signals having a wide dynamic range. The AD548’s picoamp level input current and low input offset voltage make it a good choice for the front-end amplifier of the log ratio circuit shown in Figure 30. This circuit produces an output voltage equal to the log base 10 of the ratio of the input currents I1 and I2. Resistive inputs R1 and R2 are provided for voltage inputs. Input currents I1 and I2 set the collector currents of Q1 and Q2, a matched pair of logging transistors. Voltages at points A and B are developed according to the following familiar diode equation: V BE = (kT/q) ln (I C /I ES ) In this equation, k is Boltzmann’s constant, T is absolute temperature, q is an electron charge, and IES is the reverse saturation current of the logging transistors. The difference of these two voltages is taken by the subtractor section and scaled by a factor of approximately 16 by resistors R9, R10, and R8. Temperature –7– AD548 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C999a–19–12/86 TO-99 (H) Package Plastic Mini-DIP (N) Package Figure 30. Log Ratio Amplifier compensation is provided by resistors R8 and R15, which have a positive 3500 ppm/°C temperature coefficient. The transfer function for the output voltage is: Cerdip (Q) Package VOUT = 1V log 10 (I 2 / I 1 ) Frequency compensation is provided by R11, R12, C1, and C2. Small signal bandwidth is approximately 300 kHz at input currents above 100 µA and will proportionally decrease with lower signal levels. D1, D2, R13, and R14 compensate for the effects of the two logging transistors’ ohmic emitter resistance. This circuit ensures a 1% log conformance error over an input current range of 300 pA to 1 mA, with low level accuracy limited by the AD548’s input current. The low level input voltage accuracy of this circuit is limited by the input offset voltage and drift of the AD548. PRINTED IN U.S.A. To trim this circuit, set the two input currents to 10 µA and adjust VOUT to zero by adjusting the potentiometer on A3. Then set I2 to 1 µA and adjust the scale factor such that the output voltage is 1 V by trimming potentiometer R10. Offset adjustment for A1 and A2 is provided to increase the accuracy of the voltage inputs. SOIC (R) Package –8– REV. C