ETC AD822ARM

a
Single-Supply, Rail-to-Rail
Low Power FET-Input Op Amp
AD822
FEATURES
True Single-Supply Operation
Output Swings Rail-to-Rail
Input Voltage Range Extends Below Ground
Single-Supply Capability from 3 V to 36 V
Dual-Supply Capability from 1.5 V to 18 V
High Load Drive
Capacitive Load Drive of 350 pF, G = +1
Minimum Output Current of 15 mA
Excellent AC Performance for Low Power
800 A Max Quiescent Current per Amplifier
Unity Gain Bandwidth: 1.8 MHz
Slew Rate of 3.0 V/ms
Good DC Performance
800 V Max Input Offset Voltage
2 V/C Typ Offset Voltage Drift
25 pA Max Input Bias Current
Low Noise
13 nV/÷Hz @ 10 kHz
No Phase Inversion
CONNECTION DIAGRAM
8-Lead Plastic DIP, MSOP, and SOIC
8 V+
OUT1 1
–IN1 2
7 OUT2
+IN1 3
6 –IN2
V–
4
AD822
5 +IN2
with an input voltage range extending below the negative rail,
allowing the AD822 to accommodate input signals below ground
in the Single-Supply Mode. Output voltage swing extends to within
10 mV of each rail providing the maximum output dynamic range.
Offset voltage of 800 mV max, offset voltage drift of 2 mV/∞C,
input bias currents below 25 pA, and low input voltage noise
provide dc precision with source impedances up to a Gigaohm.
1.8 MHz unity gain bandwidth, –93 dB THD at 10 kHz,
and 3 V/ms slew rate are provided with a low supply current of
800 mA per amplifier. The AD822 drives up to 350 pF of direct
capacitive load as a follower and provides a minimum output
current of 15 mA. This allows the amplifier to handle a wide
range of load conditions. Its combination of ac and dc performance, plus the outstanding load drive capability, results in an
exceptionally versatile amplifier for the single-supply user.
APPLICATIONS
Battery-Powered Precision Instrumentation
Photodiode Preamps
Active Filters
12- to 14-Bit Data Acquisition Systems
Medical Instrumentation
Low Power References and Regulators
PRODUCT DESCRIPTION
The AD822 is a dual precision, low power FET input op amp
that can operate from a single supply of 3.0 V to 36 V or dual
supplies of ± 1.5 V to ± 18 V. It has true single-supply capability
The AD822 is available in two performance grades. The A and
B grades are rated over the industrial temperature range of
–40∞C to +85∞C.
The AD822 is offered in three varieties of 8-lead packages:
Plastic DIP, MSOP, and SOIC.
100
INPUT VOLTAGE NOISE – nV/ HZ
1V
100
5V
1V
20µs
.... .... .... .... .... .... .... .... .... ....
90
.
10
VOUT
10
0%
0V
(GND)
1
10
100
1k
FREQUENCY – Hz
.... .... .... .... .... .... .... .... .... ....
1V
10k
Figure 1. Input Voltage Noise vs. Frequency
Figure 2. Gain-of-2 Amplifier; VS = 5, 0, VIN = 2.5 V
Sine Centered at 1.25 V, RL = 100 kW
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
AD822–SPECIFICATIONS (V = 0, 5 V @ T = 25C, V
S
Parameter
DC PERFORMANCE
Initial Offset
Max Offset over Temperature
Offset Drift
Input Bias Current
at TMAX
Input Offset Current
at TMAX
Open-Loop Gain
Conditions
VO = 0.2 V to 4 V
RL = 100 kW
RL = 10 kW
TMIN to TMAX
RL = 1 kW
TMIN to TMAX
DYNAMIC PERFORMANCE
Unity Gain Frequency
Full Power Response
Slew Rate
Settling Time
to 0.1%
to 0.01%
MATCHING CHARACTERISTICS
Initial Offset
Max Offset over Temperature
Offset Drift
Input Bias Current
Crosstalk @ f = 1 kHz
f = 100 kHz
INPUT CHARACTERISTICS
Common-Mode Voltage Range1
TMIN to TMAX
CMRR
TMIN to TMAX
Input Impedance
Differential
Common Mode
OUTPUT CHARACTERISTICS
Output Saturation Voltage2
VOL–VEE
TMIN to TMAX
VCC–VOH
TMIN to TMAX
VOL–VEE
TMIN to TMAX
VCC–VOH
TMIN to TMAX
VOL–VEE
TMIN to TMAX
VCC–VOH
TMIN to TMAX
Operating Output Current
TMIN to TMAX
Capacitive Load Drive
POWER SUPPLY
Quiescent Current TMIN to TMAX
Power Supply Rejection
TMIN to TMAX
Min
CM
= 0 V, VOUT = 0.2 V, unless otherwise noted.)
AD822A
Typ
0.1
0.5
2
2
0.5
2
0.5
VCM = 0 V to 4 V
TMIN to TMAX
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
Input Current Noise
0.1 Hz to 10 Hz
f = 1 kHz
Harmonic Distortion
f = 10 kHz
A
500
400
80
80
15
10
RL = 10 kW to 2.5 V
VO = 0.25 V to 4.75 V
VO p-p = 4.5 V
VO = 0.2 V to 4.5 V
Max
Min
0.8
1.2
25
5
20
1000
500
400
80
80
15
10
150
30
AD822B
Typ
Max
Unit
0.1
0.5
2
2
0.5
2
0.5
mV
mV
mV/∞C
pA
nA
pA
nA
150
30
2
25
21
16
13
mV p-p
nV/÷Hz
nV/÷Hz
nV/÷Hz
nV/÷Hz
18
0.8
18
0.8
fA p-p
fA/÷Hz
–93
–93
dB
1.8
210
3
1.8
210
3
MHz
kHz
V/ms
1.4
1.8
1.4
1.8
ms
ms
0.5
1.3
3
20
VCM = 0 V to 2 V
10
–130
–93
–130
–93
+4
+4
80
–0.2
–0.2
69
66
1013储0.5
1013储2.8
ISINK = 20 mA
5
ISOURCE = 20 mA
10
ISINK = 2 mA
40
ISOURCE = 2 mA
80
ISINK = 15 mA
300
ISOURCE = 15 mA
800
7
10
14
20
55
80
110
160
500
1000
1500
1900
–2–
80
5
10
40
80
300
800
1.24
80
70
70
1.24
80
V
V
dB
dB
7
10
14
20
55
80
110
160
500
1000
1500
1900
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
pF
1.6
mA
dB
dB
350
1.6
mV
mV
mV/∞C
pA
dB
dB
W储pF
W储pF
15
12
350
66
66
+4
+4
1013储0.5
1013储2.8
15
12
VS+ = 5 V to 15 V
V/mV
V/mV
V/mV
V/mV
V/mV
V/mV
2
25
21
16
13
3
–0.2
–0.2
66
66
10
2.5
10
1000
1.0
1.6
RL = 5 kW
0.4
0.9
REV. D
SPECIFICATIONS
Parameter
DC PERFORMANCE
Initial Offset
Max Offset over Temperature
Offset Drift
Input Bias Current
at TMAX
Input Offset Current
at TMAX
Open-Loop Gain
Conditions
VO = –4 V to +4 V
RL = 100 kW
RL = 10 kW
TMIN to TMAX
RL = 1 kW
TMIN to TMAX
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
Input Current Noise
0.1 Hz to 10 Hz
f = 1 kHz
Harmonic Distortion
f = 10 kHz
DYNAMIC PERFORMANCE
Unity Gain Frequency
Full Power Response
Slew Rate
Settling Time
to 0.1%
to 0.01%
MATCHING CHARACTERISTICS
Initial Offset
Max Offset over Temperature
Offset Drift
Input Bias Current
Crosstalk @ f = 1 kHz
f = 100 kHz
INPUT CHARACTERISTICS
Common-Mode Voltage Range1
TMIN to TMAX
CMRR
TMIN to TMAX
Input Impedance
Differential
Common Mode
OUTPUT CHARACTERISTICS
Output Saturation Voltage2
VOL–VEE
TMIN to TMAX
VCC–VOH
TMIN to TMAX
VOL–VEE
TMIN to TMAX
VCC–VOH
TMIN to TMAX
VOL–VEE
TMIN to TMAX
VCC–VOH
TMIN to TMAX
Operating Output Current
TMIN to TMAX
Capacitive Load Drive
POWER SUPPLY
Quiescent Current TMIN to TMAX
Power Supply Rejection
TMIN to TMAX
Min
AD822A
Typ
0.1
0.5
2
2
0.5
2
0.5
VCM = –5 V to +4 V
TMIN to TMAX
REV. D
AD822
(VS = 5 V @ TA = 25C, VCM = 0 V, VOUT = 0 V, unless otherwise noted.)
400
400
80
80
20
10
Max
Min
0.8
1.5
25
5
20
1000
400
400
80
80
20
10
150
30
AD822B
Typ
Max
Unit
0.1
0.5
2
2
0.5
2
0.5
mV
mV
mV/∞C
pA
nA
pA
nA
0.4
1
10
2.5
10
1000
V/mV
V/mV
V/mV
V/mV
V/mV
V/mV
150
30
2
25
21
16
13
2
25
21
16
13
mV p-p
nV/÷Hz
nV/÷Hz
nV/÷Hz
nV/÷Hz
18
0.8
18
0.8
fA p-p
fA/÷Hz
RL = 10 kW
VO = ± 4.5 V
–93
–93
dB
VO p-p = 9 V
1.9
105
3
1.9
105
3
MHz
kHz
V/ms
1.4
1.8
1.4
1.8
ms
ms
VO = 0 V to ± 4.5 V
1.0
3
0.5
2
3
3
25
RL = 5 kW
VCM = –5 V to +2 V
10
–130
–93
–5.2
–5.2
66
66
–130
–93
+4
+4
80
–5.2
–5.2
69
66
1013储0.5
1013储2.8
ISINK = 20 mA
5
ISOURCE = 20 mA
10
ISINK = 2 mA
40
ISOURCE = 2 mA
80
ISINK = 15 mA
300
ISOURCE = 15 mA
800
7
10
14
20
55
80
110
160
500
1000
1500
1900
5
10
40
80
300
800
–3–
1.3
80
7
10
14
20
55
80
110
160
500
1000
1500
1900
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
pF
1.6
mA
dB
dB
350
1.6
70
70
1.3
80
V
V
dB
dB
W储pF
W储pF
15
12
350
66
66
80
1013储0.5
1013储2.8
15
12
VS+ = 5 V to 15 V
+4
+4
mV
mV
mV/∞C
pA
dB
dB
AD822–SPECIFICATIONS (V = 15 V @ T = 25C, V
S
Parameter
DC PERFORMANCE
Initial Offset
Max Offset over Temperature
Offset Drift
Input Bias Current
at TMAX
Input Offset Current
at TMAX
Open-Loop Gain
A
Conditions
= 0 V, VOUT = 0 V, unless otherwise noted.)
Min
VO = +10 V to –10 V
RL = 100 kW
RL = 10 kW
TMIN to TMAX
RL = 1 kW
AD822A
Typ
0.4
0.5
2
2
40
0.5
2
0.5
VCM = 0 V
VCM = –10 V
VCM = 0 V
TMIN to TMAX
TMIN to TMAX
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
Input Current Noise
0.1 Hz to 10 Hz
f = 1 kHz
Harmonic Distortion
f = 10 kHz
DYNAMIC PERFORMANCE
Unity Gain Frequency
Full Power Response
Slew Rate
Settling Time
to 0.1%
to 0.01%
MATCHING CHARACTERISTICS
Initial Offset
Max Offset over Temperature
Offset Drift
Input Bias Current
Crosstalk @ f = 1 kHz
f = 100 kHz
INPUT CHARACTERISTICS
Common-Mode Voltage Range1
TMIN to TMAX
CMRR
TMIN to TMAX
Input Impedance
Differential
Common Mode
OUTPUT CHARACTERISTICS
Output Saturation Voltage2
VOL–VEE
TMIN to TMAX
VCC–VOH
TMIN to TMAX
VOL–VEE
TMIN to TMAX
VCC–VOH
TMIN to TMAX
VOL–VEE
TMIN to TMAX
VCC–VOH
TMIN to TMAX
Operating Output Current
TMIN to TMAX
Capacitive Load Drive
POWER SUPPLY
Quiescent Current TMIN to TMAX
Power Supply Rejection
TMIN to TMAX
CM
500
500
100
100
30
20
Max
Min
2
3
0.3
0.5
2
2
40
0.5
2
0.5
25
5
20
2000
500
500
100
100
30
20
500
45
AD822B
Typ
Max
Unit
1.5
2.5
mV
mV
mV/∞C
pA
pA
nA
pA
nA
12
2.5
12
2000
V/mV
V/mV
V/mV
V/mV
V/mV
V/mV
500
45
2
25
21
16
13
2
25
21
16
13
mV p-p
nV/÷Hz
nV/÷Hz
nV/÷Hz
nV/÷Hz
18
0.8
18
0.8
fA p-p
fA/÷Hz
RL = 10 kW
VO = ± 10 V
–85
–85
dB
VO p-p = 20 V
1.9
45
3
1.9
45
3
MHz
kHz
V/ms
4.1
4.5
4.1
4.5
ms
ms
VO = 0 V to ± 10 V
3
4
2
2.5
3
3
25
RL = 5 kW
VCM = –15 V to +12 V
12
–130
–93
–15.2
–15.2
70
70
–130
–93
+14
+14
80
–15.2
–15.2
74
74
1013储0.5
1013储2.8
ISINK = 20 mA
5
ISOURCE = 20 mA
10
ISINK = 2 mA
40
ISOURCE = 2 mA
80
ISINK = 15 mA
300
ISOURCE = 15 mA
800
7
10
14
20
55
80
110
160
500
1000
1500
1900
5
10
40
80
300
800
–4–
1.4
80
7
10
14
20
55
80
110
160
500
1000
1500
1900
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
pF
1.8
mA
dB
dB
350
1.8
70
70
1.4
80
V
V
dB
dB
W储pF
W储pF
20
15
350
70
70
90
1013储0.5
1013储2.8
20
15
VS+ = 5 V to 15 V
+14
+14
mV
mV
mV/∞C
pA
dB
dB
REV. D
SPECIFICATIONS (V = 0, 3 V @ T = 25ⴗC, V
S
Parameter
DC PERFORMANCE
Initial Offset
Max Offset over Temperature
Offset Drift
Input Bias Current
at TMAX
Input Offset Current
at TMAX
Open-Loop Gain
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
Input Current Noise
0.1 Hz to 10 Hz
f = 1 kHz
Harmonic Distortion
f = 10 kHz
DYNAMIC PERFORMANCE
Unity Gain Frequency
Full Power Response
Slew Rate
Settling Time
to 0.1%
to 0.01%
MATCHING CHARACTERISTICS
Offset Drift
Crosstalk @ f = 1 kHz
f = 100 kHz
INPUT CHARACTERISTICS
CMRR
Input Impedance
Differential
Common Mode
OUTPUT CHARACTERISTICS
Output Saturation Voltage2
VOL–VEE
VCC–VOH
VOL–VEE
VCC–VOH
VOL–VEE
VCC–VOH
Capacitive Load Drive
POWER SUPPLY
Quiescent Current
Power Supply Rejection
A
CM
= 0 V, VOUT = 0.2 V, unless otherwise noted.)
AD822
Conditions
Typ
Unit
VCM = 0 V to 2 V
0.2
0.5
1
2
0.5
2
0.5
mV
mV
mV/∞C
pA
nA
pA
nA
1000
150
30
V/mV
V/mV
V/mV
2
25
21
16
13
mV p-p
nV/÷Hz
nV/÷Hz
nV/÷Hz
nV/÷Hz
18
0.8
fA p-p
fA/÷Hz
RL = 10 kW to 1.5 V
VO = ± 1.25 V
–92
dB
VO p-p = 2.5 V
1.5
240
3
MHz
kHz
V/ms
1
1.4
ms
ms
2
–130
–93
mV/∞C
dB
dB
VO = 0.2 V to 2 V
RL = 100 kW
RL = 10 kW
RL = 1 kW
VO = 0.2 V to 2.5 V
RL = 5 kW
VCM = 0 V to 1 V
74
1013储0.5
1013储2.8
ISINK = 20 mA
ISOURCE = 20 mA
ISINK = 2 mA
ISOURCE = 2 mA
ISINK = 10 mA
ISOURCE = 10 mA
VS+ = 3 V to 15 V
dB
W储pF
W储pF
5
10
40
80
200
500
350
mV
mV
mV
mV
mV
mV
pF
1.24
80
mA
dB
NOTES
1
This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (+V S – 1 V) to +VS. Common-mode error
voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply.
2
VOL–VEE is defined as the difference between the lowest possible output voltage (V OL) and the minus voltage supply rail (V EE).
VCC–VOH is defined as the difference between the highest possible output voltage (V OH) and the positive supply voltage (V CC).
Specifications subject to change without notice.
REV. D
–5–
AD822
AD822
ABSOLUTE MAXIMUM RATINGS1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation2
Plastic DIP (N) . . . . . . . . . . . . . . Observe Derating Curves
SOIC (R) . . . . . . . . . . . . . . . . . . . Observe Derating Curves
Input Voltage . . . . . . . . . . . . . . (+VS + 0.2 V) to –(20 V + VS)
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . ± 30 V
Storage Temperature Range (N) . . . . . . . . . –65∞C to +125∞C
Storage Temperature Range (R, RM) . . . . . –65∞C to +150∞C
Operating Temperature Range
AD822A/AD822B . . . . . . . . . . . . . . . . . . –40∞C to +85∞C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . 260∞C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
8-Lead Plastic DIP Package: qJA = 90∞C/W
8-Lead SOIC Package: qJA = 160∞C/W
8-Lead MSOP Package: qJA = 190∞C/W
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD822
is limited by the associated rise in junction temperature. For plastic
packages, the maximum safe junction temperature is 145∞C. If
these maximums are exceeded momentarily, proper circuit operation will be restored as soon as the die temperature is reduced.
Leaving the device in the “overheated” condition for an extended
period can result in device burnout. To ensure proper operation,
it is important to observe the derating curves shown in TPC 24.
While the AD822 is internally short circuit protected, this may
not be sufficient to guarantee that the maximum junction temperature is not exceeded under all conditions. With power supplies
± 12 V (or less) at an ambient temperature of 25∞C or less, if the
output node is shorted to a supply rail, then the amplifier will not
be destroyed, even if this condition persists for an extended period.
ORDERING GUIDE
Package
Branding
Model*
Temperature Range
Package Description
Option
Information
AD822AN
AD822AR
AD822ARM
AD822BR
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
8-Lead PDIP
8-Lead SOIC
8-Lead MSOP
8-Lead SOIC
N-8
RN-8
RM-8
RN-8
B4A
*SPICE model is available at www.analog.com.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD822 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–6–
WARNING!
ESD SENSITIVE DEVICE
REV. D
Typical Performance Characteristics–AD822
70
5
VS = 0V, 5V
50
INPUT BIAS CURRENT – pA
NUMBER OF UNITS
60
40
30
20
10
0
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
OFFSET VOLTAGE – mV
0.3
0.4
VS = 0V, +5V, AND 5V
VS = 5V
–5
–5
0.5
–4
–3
–2
–1
0
1
2
COMMON-MODE VOLTAGE – V
3
4
5
TPC 4. Input Bias Current vs. Common-Mode Voltage;
VS = 5 V, 0 V, and VS = ± 5 V
TPC 1. Typical Distribution of Offset Voltage (390 Units)
1k
16
VS = 5V
14
INPUT BIAS CURRENT – pA
VS = 15V
12
10
% IN BIN
0
8
6
4
100
10
1
2
0
–12
–10
–8
–6
–4
–2
0
2
4
OFFSET VOLTAGE DRIFT – V/C
6
8
0.1
–16
10
–12
–8
–4
0
4
8
COMMON-MODE VOLTAGE – V
12
16
TPC 5. Input Bias Current vs. Common-Mode Voltage;
VS = ± 15 V
TPC 2. Typical Distribution of Offset Voltage Drift
(100 Units)
100k
50
45
10k
INPUT BIAS CURRENT – pA
40
NUMBER OF UNITS
35
30
25
20
15
10
1k
100
10
1
5
0.1
20
0
0
1
2
3
4
5
6
7
INPUT BIAS CURRENT – pA
8
9
10
60
80
100
TEMPERATURE – C
120
140
TPC 6. Input Bias Current vs. Temperature; VS = 5 V,
VCM = 0
TPC 3. Typical Distribution of Input Bias Current
(213 Units)
REV. D
40
–7–
AD822
10M
40
1M
VS = 0V, 5V
VS = 0V, 3V
100k
RL = 20k
20
INPUT VOLTAGE – V
0PEN-LOOP GAIN – V/V
VS = 15V
POS RAIL
RL = 2k
NEG RAIL
POS RAIL
0
POS
RAIL
–20
NEG RAIL
RL = 100k
10k
100
1k
10k
LOAD RESISTANCE – –40
100k
60
120
180
240
OUTPUT VOLTAGE FROM SUPPLY RAILS – mV
300
TPC 10. Input Error Voltage with Output Voltage within
300 mV of Either Supply Rail for Various Resistive Loads;
VS = ± 5 V
TPC 7. Open-Loop Gain vs. Load Resistance
1k
RL = 100k
INPUT VOLTAGE NOISE – nV/ HZ
10M
OPEN-LOOP GAIN – V/V
NEG RAIL
0
VS = 15V
1M
VS = 0V, 5V
VS = 15V
RL = 10k
VS = 0V, 5V
100k
VS = 15V
RL = 600
100
10
VS = 0V, 5V
10k
–60
–40
–20
0
20
40
60
80
TEMPERATURE – C
100
120
1
1
140
10
100
FREQUENCY – Hz
1k
10k
TPC 11. Input Voltage Noise vs. Frequency
TPC 8. Open-Loop Gain vs. Temperature
–40
300
–50
200
RL = 10k
ACL = –1
RL = 10k
RL = 100k
THD – dB
INPUT VOLTAGE – V
–60
100
0
–100
–70
–80
–90
RL = 600
VS = 0V, 3V; VOUT = 2.5V p-p
VS = 15V; VOUT = 20V p-p
VS = 5V; VOUT = 9V p-p
–200
–100
–300
–16
VS = 0V, 5V; VOUT = 4.5V p-p
–110
100
1k
10k
FREQUENCY – Hz
–12
–8
–4
0
4
OUTPUT VOLTAGE – V
8
12
16
100k
TPC 12. Total Harmonic Distortion vs. Frequency
TPC 9. Input Error Voltage vs. Output Voltage for
Resistive Loads
–8–
REV. D
AD822
100
100
80
80
90
60
60
GAIN
40
40
20
20
RL = 2k
CL = 100pF
0
–20
10
0
10k
100k
FREQUENCY – Hz
1M
–20
10M
50
VS = 0V, 5V
VS = 0V, 3V
40
30
20
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
TPC 16. Common-Mode Rejection vs. Frequency
5
1k
COMMON-MODE ERROR VOLTAGE – mV
ACL = +1
VS = 15V
100
OUTPUT IMPEDANCE – 60
0
10
TPC 13. Open-Loop Gain and Phase Margin vs.
Frequency
10
1
0.1
0.01
100
VS = 15V
70
10
1k
100
PHASE MARGIN IN DEGREES
OPEN-LOOP GAIN – dB
PHASE
COMMON-MODE REJECTION – dB
80
10k
100k
FREQUENCY – Hz
1k
1M
NEGATIVE
RAIL
4
3
+25C
2
+125C
–55C
1
–55C
+125C
0
–1
10M
POSITIVE
RAIL
0
1
2
COMMON-MODE VOLTAGE FROM SUPPLY RAILS – V
3
TPC 17. Absolute Common-Mode Error vs. CommonMode Voltage from Supply Rails (VS – VCM)
TPC 14. Output Impedance vs. Frequency
16
1000
8
OUTPUT SATURATION VOLTAGE – mV
OUTPUT SWING FROM 0 TO VOLTS
12
1%
4
0.01%
ERROR
0.1%
0
0.01%
–4
–8
1%
–12
–16
0.0
1.0
2.0
3.0
SETTLING TIME – s
4.0
VS – VOH
VOL – VS
10
0
5.0
0.001
0.01
0.1
1
LOAD CURRENT – mA
10
100
TPC 18. Output Saturation Voltage vs. Load Current
TPC 15. Output Swing and Error vs. Settling Time
REV. D
100
–9–
AD822
100
1000
90
POWER SUPPLY REJECTION – dB
OUTPUT SATURATION VOLTAGE – mV
ISOURCE = 10mA
ISINK = 10mA
100
ISOURCE = 1mA
ISINK = 1mA
ISOURCE = 10A
10
ISINK = 10A
1
–60
–40
–20
0
60
20
40
80
TEMPERATURE – C
100
120
+PSRR
60
50
40
–PSRR
30
20
10
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
TPC 22. Power Supply Rejection vs. Frequency
30
80
70
VS = 15V
RL = 2k
25
VS = 15V
60
50
OUTPUT VOLTAGE – V
SHORT CIRCUIT CURRENT LIMIT – mA
70
0
10
140
TPC 19. Output Saturation Voltage vs. Temperature
–OUT
VS = 15V
40
VS = 0V, 5V
30
+
VS = 0V, 3V
–
–
20
VS = 0V, 5V
10
+
+
VS = 0V, 3V
20
15
10
5
VS = 0V, 5V
VS = 0V, 3V
0
–60
–40
–20
0
20
40
60
80
TEMPERATURE – C
100
120
0
10k
140
10M
2.4
1600
2.2
T = +125C
TOTAL POWER DISSIPATION – W
1400
T = +25C
1200
T = –55C
1000
800
600
400
200
0
1M
100k
FREQUENCY – Hz
TPC 23. Large Signal Frequency Response
TPC 20. Short Circuit Current Limit vs. Temperature
QUIESCENT CURRENT – A
80
2.0
1.8
8-LEAD MINI-DIP
8-LEAD SOIC
1.6
1.4
1.2
1.0
0.8
0.6
8-LEAD MSOP
0.4
0.2
0
4
8
12
16
20
24
28
TOTAL SUPPLY VOLTAGE – V
32
0.0
–60
36
TPC 21. Quiescent Current vs. Supply Voltage vs.
Temperature
–40
–20
0
20
40
AMBIENT TEMPERATURE – C
60
80
TPC 24. Maximum Power Dissipation vs. Temperature for
Plastic Packages
–10–
REV. D
AD822
–70
VOUT
+VS
–80
20k
0.1F
CROSSTALK – dB
–90
2
20V p-p
–100
1
1/2
AD822
6
7
3
5k
1/2
AD822
–110
1F
8
2.2k
5
5k
VIN
–120
CROSSTALK = 20LOG
VOUT
10VIN
0.1F
1F
–VS
–130
–140
300
3k
1k
10k
30k
FREQUENCY – Hz
100k
300k
1M
TPC 25. Crosstalk vs. Frequency
TPC 28. Crosstalk Test Circuit
5V
5µs
100
1/2
AD822
+VS
90
0.01F
8
VIN
0.01F
4
100pF
RL
VOUT
10
0%
TPC 26. Unity Gain Follower
5V
TPC 29. Large Signal Response Unity Gain Follower;
VS = ± 15 V, RL = 10 kW
10mV
10µs
100
100
90
90
10
10
0%
0%
TPC 30. Small Signal Response Unity Gain Follower;
VS = ± 15 V, RL = 10 kW
TPC 27. 20 V p-p, 25 kHz Sine Wave Input; Unity
Gain Follower; RL = 600 W, VS = ± 15 V
REV. D
500ns
–11–
AD822
1V
2µs
1V
100
100
90
90
10
GND
2µs
10
0%
GND
0%
TPC 34. VS = 5 V, 0 V; Unity Gain Follower Response
to 0 V to 5 V Step
TPC 31. VS = 5 V, 0 V; Unity Gain Follower Response
to 0 V to 4 V Step
10mV
2µs
100
90
+VS
0.01F
8
VIN
4
1/2
AD822
100pF
RL
VOUT
10
GND
TPC 32. Unity Gain Follower
0%
TPC 35. VS = 5 V, 0 V; Unity Gain Follower Response, to
40 mV Step Centered 40 mV Above Ground, RL = 10 kW
10mV
VIN
10k
2µs
100
20k
+VS
90
VOUT
0.01F
8
4
1/2
AD822
RL
100pF
10
GND
TPC 33. Gain-of-Two Inverter
0%
TPC 36. VS = 5 V, 0 V; Gain-of-Two Inverter Response to
20 mV Step, Centered 20 mV Below Ground, RL = 10 kW
–12–
REV. D
AD822
1V
1V
2µs
100
100
10µs
.... .... .... .... .... .... .... .... .... ....
90
90
10
10
GND
GND
0%
.... .... .... .... .... .... .... .... .... ....
0%
1V
(a)
TPC 37. VS = 5 V, 0 V; Gain-of-Two Inverter Response to
2.5 V Step Centered –1.25 V Below Ground, RL = 10 kW
+VS
500mV
100
10µs
1V
1V
.... .... .... .... .... .... .... .... .... ....
90
10µs
100
90
10
GND
0%
.... .... .... .... .... .... .... .... .... ....
1V
10
GND
(b)
0%
5V
RP
TPC 38. VS = 3 V, 0 V; Gain-of-Two Inverter, VIN = 1.25 V,
25 kHz, Sine Wave Centered at –0.75 V, RL = 600 W
VIN
VOUT
TPC 39. (a) Response with RP = 0; VIN from 0 to +VS
(b) VIN = 0 to +VS + 200 mV
VOUT = 0 to +VS
RP = 49.9 kW
APPLICATION NOTES
INPUT CHARACTERISTICS
In the AD822, n-channel JFETs are used to provide a low offset,
low noise, high impedance input stage. Minimum input commonmode voltage extends from 0.2 V below –VS to 1 V less than +VS.
Driving the input voltage closer to the positive rail will cause a
loss of amplifier bandwidth (as can be seen by comparing the
large signal responses shown in TPCs 31 and 34) and increased
common-mode voltage error as illustrated in TPC 17.
The AD822 does not exhibit phase reversal for input voltages up
to and including +VS. TPC 39a shows the response of an AD822
voltage follower to a 0 V to 5 V (+VS) square wave input. The
input and output are superimposed. The output tracks the input
up to +VS without phase reversal. The reduced bandwidth above
a 4 V input causes the rounding of the output wave form. For
REV. D
input voltages greater than +VS, a resistor in series with the AD822’s
noninverting input will prevent phase reversal, at the expense of
greater input voltage noise. This is illustrated in TPC 39b.
Since the input stage uses n-channel JFETs, input current during normal operation is negative; the current flows out from the
input terminals. If the input voltage is driven more positive than
+VS – 0.4 V, the input current will reverse direction as internal device
junctions become forward biased. This is illustrated in TPC 4.
A current limiting resistor should be used in series with the input of
the AD822 if there is a possibility of the input voltage exceeding the
positive supply by more than 300 mV, or if an input voltage will
be applied to the AD822 when ±VS = 0. The amplifier will be damaged if left in that condition for more than 10 seconds. A 1 kW resistor
allows the amplifier to withstand up to 10 V of continuous overvoltage and increases the input voltage noise by a negligible amount.
–13–
AD822
Input voltages less than –VS are a completely different story.
The amplifier can safely withstand input voltages 20 V below
the minus supply voltage as long as the total voltage from the
positive supply to the input terminal is less than 36 V. In addition, the input stage typically maintains picoamp level input
currents across that input voltage range.
20mV
100
2µs
.... .... .... .... .... .... .... .... .... ....
90
The AD822 is designed for 13 nV/÷Hz wideband input voltage
noise and maintains low noise performance to low frequencies
(refer to TPC 11). This noise performance, along with the
AD822’s low input current and current noise, means that the
AD822 contributes negligible noise for applications with source
resistances greater than 10 kW and signal bandwidths greater
than 1 kHz. This is illustrated in Figure 3.
10
0%
.... .... .... .... .... .... .... .... .... ....
100k
10k
Figure 4. Small Signal Response of AD822 as
Unity Gain Follower Driving 350 pF
WHENEVER JOHNSON NOISE IS GREATER THAN
AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE
CONSIDERED NEGLIGIBLE FOR APPLICATION.
INPUT VOLTAGE NOISE – V
1kHz
Figure 5 is a plot of capacitive load that will result in a 20 degree
phase margin versus noise gain for the AD822. Noise gain is the
inverse of the feedback attenuation factor provided by the feedback network in use.
1k
RESISTOR JOHNSON
NOISE
100
5
10
10Hz
1
0.1
10k
100k
10M
100M
1M
SOURCE IMPEDANCE – 1G
RF
NOISE GAIN – 1+ ––––
R1
AMPLIFIER-GENERATED
NOISE
10G
Figure 3. Total Noise vs. Source Impedance
OUTPUT CHARACTERISTICS
4
3
2
The AD822’s unique bipolar rail-to-rail output stage swings within
5 mV of the minus supply and 10 mV of the positive supply with
no external resistive load. The AD822’s approximate output saturation resistance is 40 W sourcing and 20 W sinking. This can be
used to estimate output saturation voltage when driving heavier
current loads. For instance, when sourcing 5 mA, the saturation
voltage to the positive supply rail will be 200 mV; when sinking
5 mA, the saturation voltage to the minus rail will be 100 mV.
1
300
1k
3k
10k
CAPACITIVE LOAD FOR 20 O PHASE MARGIN – pF
RF
30k
CL
The amplifier’s open-loop gain characteristic will change as a
function of resistive load, as shown in TPCs 7 through 10. For
load resistances over 20 kW, the AD822’s input error voltage is
virtually unchanged until the output voltage is driven to 180 mV
of either supply.
Figure 5. Capacitive Load Tolerance vs. Noise Gain
If the AD822’s output is overdriven so as to saturate either of the
output devices, the amplifier will recover within 2 ms of its input
returning to the amplifier’s linear operating region.
Figure 6 shows a method for extending capacitance load drive
capability for a unity gain follower. With these component values,
the circuit will drive 5,000 pF with a 10% overshoot.
R1
Direct capacitive loads will interact with the amplifier’s effective
output impedance to form an additional pole in the amplifier’s
feedback loop which can cause excessive peaking on the pulse
response or loss of stability. Worst case is when the amplifier is
used as a unity gain follower. Figure 4 shows the AD822’s pulse
response as a unity gain follower driving 350 pF. This amount
of overshoot indicates approximately 20 degrees of phase margin—
the system is stable but is nearing the edge. Configurations with
less loop gain, and as a result less loop bandwidth, will be much
less sensitive to capacitance load effects.
+VS
0.01F
8
VIN
100
1/2
AD822
0.01F
4
VOUT
CL
–VS
20pF
20k
Figure 6. Extending Unity Gain Follower
Capacitive Load Capability Beyond 350 pF
–14–
REV. D
AD822
APPLICATIONS
Single-Supply Voltage-to-Frequency Converter
Table I. In Amp Performance
The circuit shown in Figure 7 uses the AD822 to drive a low power
timer that produces a stable pulse of width t1. The positive going
output pulse is integrated by R1–C1 and used as one input to the
AD822 that is connected as a differential integrator. The other
input (nonloading) is the unknown voltage, VIN. The AD822 output
drives the timer trigger input, closing the overall feedback loop.
+10V
C5
0.1F
2
6
U4
REF02
VREF = 5V
5
3
4
CMOS
74HCO4
RSCALE**
10k
4
R2
499k 1%
U3B
VIN
OUT1
0.01F, 2%
U1
C1
R3*
116k
6
2
AD822B
7
499k 1%
C2
0.01F, 2%
0V TO 2.5V
FULL SCALE
1
OUT2
VS = 3 V, 0 V
VS = 5 V
CMRR
Common-Mode
Voltage Range
3 dB BW, G = 10
G = 100
tSETTLING
2 V Step (VS = 0 V, 3 V)
5 V (VS = ± 5 V)
Noise @ f = 1 kHz, G = 10
G = 100
ISUPPLY (Total)
74 dB
80 dB
–0.2 V to +2 V –5.2 V to +4 V
180 kHz
180 kHz
18 kHz
18 kHz
2 ms
5 ms
270 nV/÷Hz
2.2 mV/÷Hz
1.15 mA
270 nV/÷Hz
2.2 mV/÷Hz
1.10 mA
U2
CMOS 555
1/2
R1
C3
0.1F
U3A
3 2
Parameters
4
R
THR
8
V+
OUT
TR
DIS
GND
1
CV
5µs
3
100
.... .... .... .... .... .... .... .... .... ....
90
5
.
C4
0.01F
NOTES
fOUT = VIN/(VREFt1 ), t1 = 1.1R3C6
=
* =
** =
t1 =
10
25kHz FS AS SHOWN
1% METAL FILM, <50ppm/C TC
10% 20T FILM, <100ppm/C TC
33s FOR fOUT = 20kHz @ VIN = 2.0V
0%
.... .... .... .... .... .... .... .... .... ....
1V
Figure 7. Single-Supply Voltage-to-Frequency Converter
Figure 8a. Pulse Response of In Amp to a 500 mV p-p
Input Signal; VS = 5 V, 0 V; Gain = 10
Typical AD822 bias currents of 2 pA allow Megohm-range source
impedances with negligible dc errors. Linearity errors on the
order of 0.01% full scale can be achieved with this circuit. This
performance is obtained with a 5 V single supply which delivers
less than 1 mA to the entire circuit.
R1
90k
Single-Supply Programmable Gain Instrumentation Amplifier
R2
9k
R3
1k
R4
1k
R5
9k
R6
90k
VREF
The AD822 can be configured as a single-supply instrumentation
amplifier that is able to operate from single supplies down to 3 V
or dual supplies up to ±15 V. Using only one AD822 rather than
three separate op amps, this circuit is cost and power efficient.
AD822 FET inputs’ 2 pA bias currents minimize offset errors
caused by high unbalanced source impedances.
G = 10
G = 100
G = 100
G = 10
+VS
0.1F
6
2
An array of precision thin-film resistors sets the in amp gain to be
either 10 or 100. These resistors are laser trimmed to ratio match
to 0.01% and have a maximum differential TC of 5 ppm/∞C.
VIN1
VIN2
RP
1k
3
1/2
AD822
RP
1k
1
5
1/2
AD822
7
4
(G = 10)
R6
VOUT = (VIN1 – VIN2) 1+ –––––––– +VREF
R4 + R5
(G = 100)
R5 + R6
VOUT = (VIN1 – VIN2) 1+ –––––––– +VREF
R4
Figure 8b. A Single-Supply Programmable
Instrumentation Amplifier
REV. D
OHMTEK
PART # 1043
–15–
VOUT
AD822
3 V, Single-Supply Stereo Headphone Driver
Low Dropout Bipolar Bridge Driver
The AD822 exhibits good current drive and THD + N performance,
even at 3 V single supplies. At 1 kHz, total harmonic distortion
plus noise (THD + N) equals –62 dB (0.079%) for a 300 mV p-p
output signal. This is comparable to other single- supply op amps
that consume more power and cannot run on 3 V power supplies.
3V
1F
MYLAR
0.1F
95.3k
+
0.1F
CHANNEL 1
47.5k
1/2
AD822
The AD822 can be used for driving a 350 W Wheatstone bridge.
Figure 10 shows one half of the AD822 being used to buffer the
AD589—a 1.235 V low power reference. The output of 4.5 V
can be used to drive an A/D converter front end. The other half
of the AD822 is configured as a unity gain inverter and generates
the other bridge input of –4.5 V. Resistors R1 and R2 provide
a constant current for bridge excitation. The AD620 low power
instrumentation amplifier is used to condition the differential
output voltage of the bridge. The gain of the AD620 is programmed
using an external resistor RG and determined by:
500F
G=
4.99k
95.3k
L
10k
+Vs
HEADPHONES
32 IMPEDANCE
10k
49.9k
4.99k
R
1F
MYLAR
47.5k
R1
20
+1.235V
AD589
CHANNEL 2
49.4 kW
+1
RG
1/2
AD822
1/2
AD822
TO A/D CONVERTER
REFERENCE INPUT
25.4k 1%
500F
10k 1%
Figure 9. 3 V Single-Supply Stereo Headphone Driver
350
350
In Figure 9, each channel’s input signal is coupled via a 1 mF
Mylar capacitor. Resistor dividers set the dc voltage at the noninverting inputs so that the output voltage is midway between the
power supplies (1.5 V). The gain is 1.5. Each half of the AD822
can then be used to drive a headphone channel. A 5 Hz high-pass
filter is realized by the 500 mF capacitors and the headphones
that can be modeled as 32 W load resistors to ground. This ensures
that all signals in the audio frequency range (20 Hz–20 kHz) are
delivered to the headphones.
+VS
350
350
10k 1%
10k 1%
1/2
AD822
RG
AD620
VREF
–VS
–4.5V
R2
20
+Vs
+Vs
+
0.1F
GND
+
0.1F
–Vs
+
+
+5V
1F
1F
–5V
Figure 10. Low Dropout Bipolar Bridge Driver
–16–
REV. D
AD822
OUTLINE DIMENSIONS
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(RN-8)
8-Lead Plastic Dual-in-Line Package [PDIP]
(N-8)
Dimensions shown in inches and (millimeters)
Dimensions shown in millimeters and (inches)
0.375 (9.53)
0.365 (9.27)
0.355 (9.02)
8
1
5
4
5.00 (0.1968)
4.80 (0.1890)
0.295 (7.49)
0.285 (7.24)
0.275 (6.98)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.180
(4.57)
MAX
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
4.00 (0.1574)
3.80 (0.1497)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015
(0.38)
MIN
8
5
1
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
SEATING
PLANE
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
COPLANARITY
SEATING
0.10
PLANE
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.33 (0.0130)
0.50 (0.0196)
ⴛ 45ⴗ
0.25 (0.0099)
8ⴗ
0.25 (0.0098) 0ⴗ 1.27 (0.0500)
0.41 (0.0160)
0.19 (0.0075)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES)
8-Lead MSOP Package [MSOP]
(RM-8)
Dimensions shown in millimeters
3.00
BSC
8
5
4.90
BSC
3.00
BSC
1
4
PIN 1
0.65 BSC
1.10 MAX
0.15
0.00
0.38
0.22
COPLANARITY
0.10
0.23
0.08
8ⴗ
0ⴗ
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
REV. D
6.20 (0.2440)
5.80 (0.2284)
–17–
0.80
0.40
AD822
Revision History
Location
Page
10/02—Data sheet changed from REV. C to REV. D
Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Updated SOIC PACKAGE OUTLINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8/02—Data sheet changed from REV. B to REV. C
All figures updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global
Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Updated all PACKAGE OUTLINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7/01—Data sheet changed from REV. A to REV. B
All figures updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global
Cerdip references removed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 6, and 18
Additions to Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
8-Lead SOIC and 8-Lead MSOP Diagrams added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Deletion of AD822S column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Edits to Absolute Maximum Ratings and Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Removed Metalization Photograph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
–18–
REV. D
–19–
–20–
PRINTED IN U.S.A.
C00874–0–10/02(D)