3.3V 16M x 64/72-Bit 1 BANK SDRAM Module 3.3V 32M x 64/72-Bit 2 BANK SDRAM Module HYS64/72V16300GU HYS64/72V32220GU 168 pin unbuffered DIMM Modules • 168 Pin unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main memory applications • PC100 & PC133 versions • 1 bank 16M x 64, 16M x 72 and 2 bank 132M x 64, 32M x 72 organisation • Optimized for byte-write non-parity (x64) or ECC (x72) applications • JEDEC standard Synchronous DRAMs (SDRAM) • Fully PC board layout compatible to INTEL’s Rev. 1.0 module specification • SDRAM Performance: • -7.5 -8 PC133 PC100 Units fCK Clock frequency (max.) 133 100 MHz tAC Clock access time 5.4 6 ns Programmed Latencies : Product Speed CL tRCD tRP -7.5 PC133 3 3 3 -8 PC100 2 2 2 • Single +3.3V(± 0.3V ) power supply • Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave) • Auto Refresh (CBR) and Self Refresh • Decoupling capacitors mounted on substrate • All inputs, outputs are LVTTL compatible • Serial Presence Detect with E2PROM • Utilizes 16M x 8 SDRAMs in TSOPII-54 packages with 4096 refresh cycles every 64 ms • 133,35 mm x 31.75 mm x 4,00 mm card size with gold contact pads INFINEON Technologies 1 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 8.99 HYS64(72)V16300/32220GU SDRAM-Modules The HYS64(72)16300GU and HYS64(72)32220 are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs) which are organised as 16M x 64, 16M x 72 in one bank and 32M x 64 and 32M x 72 in two banks high speed memory arrays designed with 128M Synchronous DRAMs (SDRAMs) for non-parity and ECC applications. The DIMMs use -7.5 speed sorted 16M x 8 SDRAM devices in TSOP54 packages to meet the PC133-333 requirements and -8 & -8A components for the standard PC100 applications. Decoupling capacitors are mounted on the PC board. The PC board design is according to INTEL’s PC SDRAM Rev. 1.0 module specification.The DIMMs have a serial presence detect, implemented with a serial E2PROM using the two pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All INFINEON 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133,35 mm long footprint, with 1,25“ ( 31,75 mm) height. Ordering Information Type Code Package Descriptions Module Height HYS 64V16300GU-7.5-... PC133-333-520 L-DIM-168-33 133 Mhz 16M x 64 1 bank SDRAM module 1,25“ HYS 72V16300GU-7.5-... PC133-333-520 L-DIM-168-33 133 Mhz 16M x 72 1 bank SDRAM module 1,25“ HYS 64V16300GU-8-... PC100-222-620 L-DIM-168-33 100 MHz 16M x 64 1 bank SDRAM module 1,25“ HYS 72V16300GU-8-... PC100-222-620 L-DIM-168-33 100 MHz 16M x 72 1 bank SDRAM module 1,25“ HYS 64V32220GU-7.5-... PC133-333-520 L-DIM-168-30 133 MHz 32M x 64 2 bank SDRAM module 1,25“ HYS 64V32220GU-7.5-... PC133-333-520 L-DIM-168-30 133 Mhz 32M x 72 2 bank SDRAM module 1,25“ HYS 64V32220GU-8-... PC100-222-620 L-DIM-168-30 100 MHz 32M x 64 2 bank SDRAM module 1,25“ HYS 72V32220GU-8-... PC100-222-620 L-DIM-168-30 100 Mhz 32M x 72 2 bank SDRAM module 1,25“ 64MByte DIMMs: 128 MByte DIMMs: Note: All partnumbers end with a place code (not shown), designating the die revision. Consult factory for current revision. Example: HYS64V16300GU-8-C, indicating Rev.C dies are used for SDRAM components. Pin Names A0-A11 BA0, BA1 DQ0 - DQ63 Address Inputs Read / Write Input Vss Ground CKE0, CKE1 Clock Enable SCL Clock for SPD WE Bank Selects CLK0 - CLK3 Clock Input SDA Serial Data Out CB0-CB7 Check Bits (x72 only) Data Input/Output DQMB0 - DQMB7 Data Mask N.C. No Connection RAS Row Address Strobe CS0 - CS3 Chip Select CAS Column Address Strobe Vcc Power (+3.3 Volt) Address Format: Part Number Rows Columns Bank Select Refresh Period Interval 16M x 64 HYS 64V16300GU 12 10 2 4k 64 ms 15,6 µs 16M x 72 HYS 72V16300GU 12 10 2 4k 64 ms 15,6 µs 32M x 64 HYS 64V32220GU 12 10 2 4k 64 ms 15,6 µs 32M x 72 HYS 72V32220GU 12 10 2 4k 64 ms 15,6 µs INFINEON Technologies 2 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS64(72)V16300/32220GU SDRAM-Modules Pin Configuration PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Symbol VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 NC (CB0) NC (CB1) VSS NC NC VCC WE DQMB0 DQMB1 CS0 DU VSS A0 A2 A4 A6 A8 A10 BA1 VCC VCC CLK0 PIN # 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Symbol PIN # VSS DU CS2 DQMB2 DQMB3 DU VCC NC NC NC (CB2) NC (CB3) VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC DU CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC WP SDA SCL VCC 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Symbol VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 NC (CB4) NC (CB5) VSS NC NC VCC CAS DQMB4 DQMB5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VCC CLK1 NC PIN # 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Symbol VSS CKE0 CS3 DQMB6 DQMB7 NC VCC NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC DU NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC SA0 SA1 SA2 VCC Note : Pinnames in brackets are for the x72 ECC versions INFINEON Technologies 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS64(72)V16300/32220GU SDRAM-Modules WE CS0 DQMB0 DQ(7:0) CS WE DQM DQ0-DQ7 D0 DQMB4 DQ(39:32) CS WE DQM DQ0-DQ7 D4 DQMB1 DQ(15:8) CS WE DQM DQ0-DQ7 D1 DQMB5 DQ(47:40) CS WE DQM DQ0-DQ7 D5 CS WE DQM DQ0-DQ7 D8 CB(7:0) CS2 DQMB2 DQ(23:16) CS WE DQM DQ0-DQ7 D2 DQMB6 DQ(55:48) CS WE DQM DQ0-DQ7 D6 DQMB3 DQ(31:24) CS WE DQM DQ0-DQ7 D3 DQMB7 DQ(63:56) CS WE DQM DQ0-DQ7 D7 A0-A11, BA0, BA1 D0-D7, (D8) VCC D0-D7, (D8) E 2 PROM (256 word x 8 Bit) SA0 SA1 SA2 SCL C0-C15, (C16, C17) VSS D0-D7, (D8) RAS D0-D7, (D8) CAS D0-D7, (D8) CKE0 D0-D7, (D8) SA0 SA1 SA2 SCL SDA WP 47 k Ω Clock Wiring CLK0 CLK1 CLK2 CLK3 Note: D8 is only used in the x72 ECC version. 8 M x 64 8 M x 72 4 SDRAM + 3.3 pF Termination 4 SDRAM + 3.3 pF Termination 5 SDRAM Termination 4 SDRAM + 3.3 pF Termination SPB03958 Block Diagram for 8M x 64/72 SDRAM DIMM modules (HYS64/72V82(3)00GU) INFINEON Technologies 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS64(72)V16300/32220GU SDRAM-Modules CS1 CS0 CS DQM DQ0-DQ7 DQMB0 DQ(7:0) CS DQM DQ0-DQ7 CS DQM DQ0-DQ7 CS DQM DQ0-DQ7 D1 CS DQM DQ0-DQ7 CB(7:0) CS DQM DQ0-DQ7 D4 D8 D0 DQMB1 DQ(15:8) CS DQM DQ0-DQ7 DQMB4 DQ(39:32) CS DQM DQ0-DQ7 DQMB5 DQ(47:40) D9 D12 CS DQM DQ0-DQ7 D5 D13 CS D16 DQM DQ0-DQ7 D17 CS3 CS2 CS DQM DQ0-DQ7 DQMB2 DQ(23:16) CS DQM DQ0-DQ7 D2 CS DQM DQ0-DQ7 DQMB3 DQ(31:24) CS DQM DQ0-DQ7 A0-A11, BA0, BA1 D0-D15, (D16, D17) VDD D0-D15, (D16, D17) D0-D7, (D8) RAS, CAS, WE D0-D15, (D16, D17) CKE0 D0-D7, (D16) CS DQM DQ0-DQ7 DQMB7 DQ(63:56) D14 CS DQM DQ0-DQ7 D7 D11 D15 E 2 PROM (256 Word x 8 Bit) SA0 SA1 SA2 SCL C0-C31, (C32...C35) VSS CS DQM DQ0-DQ7 D6 D10 D3 SA0 SA1 SA2 SCL SDA WP 47 k Ω Clock Wiring VDD 10 k Ω CKE1 CS DQM DQ0-DQ7 DQMB6 DQ(55:48) CLK0 CLK1 CLK2 CLK3 D9-D15, (D17) 16 M x 64 16 M x 72 4 SDRAM + 3.3 pF 4 SDRAM + 3.3 pF 4 SDRAM + 3.3 pF 4 SDRAM + 3.3 pF 5 SDRAM 5 SDRAM 4 SDRAM + 3.3 pF 4 SDRAM + 3.3 pF Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10 Ω except otherwise noted. SPB03769 Block Diagram for 16M x 64/72 SDRAM DIMM modules (HYS64/72V1620GU) INFINEON Technologies 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS64(72)V16300/32220GU SDRAM-Modules DC Characteristics TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V Parameter Symbol Limit Values Unit min. max. Input high voltage VIH 2.0 Vcc+0.3 V Input low voltage VIL – 0.5 0.8 V Output high voltage (IOUT = – 4.0 mA) VOH 2.4 – V Output low voltage (IOUT = 4.0 mA) VOL – 0.4 V Input leakage current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) II(L) – 40 40 µA Output leakage current (DQ is disabled, 0 V < VOUT < VCC) IO(L) – 40 40 µA Capacitance TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Limit Values Unit max. max. max. max. 16Mx64 16Mx72 32Mx64 32Mx72 CI1 65 72 105 144 pF Input capacitance (CS0 -CS3, ) CI2 32 40 32 40 pF Input capacitance (CLK0 - CLK3) CICL 35 38 35 38 pF Input capacitance (CKE0, CKE1) CI3 65 72 65 72 pF Input capacitance (DQMB0 - DQMB7) CI4 13 13 20 20 pF Input / Output capacitance CIO 10 10 15 15 pF Input Capacitance (SCL,SA0-2) Csc 8 8 8 8 pF Input/Output Capacitance Csd 10 10 10 10 pF Input capacitance (A0 to A11, BA0, BA1, RAS, CAS, WE) (DQ0-DQ63, CB0-CB7) INFINEON Technologies 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS64(72)V16300/32220GU SDRAM-Modules Operating Currents per SDRAM component (TA = 0 to 70oC, Vdd = 3.3V ± 0.3V 1) (Recommended Operating Conditions unless otherwise noted)) Parameter & Test Condition Symb. -7.5 -8 Note max. OPERATING CURRENT trc=trcmin., tck=tckmin. Ouputs open, Burst Length = 4, CL=3 All banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access ICC1 130 120 1.5 mA 1 mA 1 PRECHARGE STANDBY CURRENT in Power Down Mode CS =VIH (min.), CKE<=Vil(max) tck = min. ICC2P PRECHARGE STANDBY CURRENT in Non-Power Down Mode CS = VIH (min.), CKE>=Vih(min) tck = min. ICC2N 40 35 mA 1 NO OPERATING CURRENT CKE>=VIH(min.) ICC3N 50 45 mA 1 tck = min., CS = VIH(min), active state ( max. 4 banks) CKE<=VIL(max.) ICC3P mA 1 BURST OPERATING CURRENT tck = min., Read command cycling AUTO REFRESH CURRENT tck = min., Auto Refresh command cycling SELF REFRESH CURRENT Self Refresh Mode, CKE=0.2V INFINEON Technologies standard version 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 10 ICC4 130 120 mA 1,2 ICC5 180 170 mA 1 mA 1 ICC6 1.5 12.99 HYS64(72)V16300/32220GU SDRAM-Modules AC Characteristics 3)4) TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns Parameter Limit Values Symbol -7.5 PC133-333 Unit Note -8 PC100-222 min. max. min. max. Clock Cycle Time tCK CAS Latency = 3 CAS Latency = 2 7.5 10 – – 10 10 – – fCK System Frequency CAS Latency = 3 CAS Latency = 2 – – 133 100 – – 100 100 Clock Access Time tAC CAS Latency = 3 CAS Latency = 2 – – 5.4 6 – – 6 6 ns ns 4,5) Clock and Access Time ns ns MHz MHz Clock High Pulse Width tCH 2.5 – 3 – ns 6) Clock Low Pulse Width tCL 2.5 – 3 – ns 6) Input Setup time tIS 1.5 – 2 – ns 7) Input Hold Time tIH 0.8 – 1 – ns 7) Power Down Mode Entry Time tSB – 1 – 1 CLK 8) Power Down Mode Exit Setup Time tPDE 1 – 1 – CLK 9) Mode Register Setup Time tRCS 2 – 2 – CLK Transition time (rise and fall) tT 1 – 1 – ns RAS to CAS delay tRCD 20 – 20 – ns Precharge Time tRP 20 – 20 – ns Active Command Period tRAS 45 100k 50 Cycle Time tRC 67.5 – 70 – ns Bank to Bank Delay Time tRRD 15 – 16 – ns CAS to CAS delay time (same bank) tCCD 1 – 1 – CLK Set and Hold Parameters Common Parameters INFINEON Technologies 8 Powered by ICminer.com Electronic-Library Service CopyRight 2003 100k ns 12.99 HYS64(72)V16300/32220GU SDRAM-Modules Parameter Limit Values Symbol -7.5 PC133-333 Unit Note -8 PC100-222 min. max. min. max. Refresh Cycle Refresh Period (4096 cycles) tREF – 64 – 64 ms Self Refresh Exit Time tSREX 1 – 1 – CLK 10) Data Out Hold Time tOH 3 – 3 – ns 4) Data Out to Low Impedance tLZ 0 – 0 – ns Data Out to High Impedance tHZ 3 7 3 8 ns DQM Data Out Disable Latency tDQZ – 2 – 2 CLK tWR 2 – 2 – CLK tDQW 0 – 0 – CLK Read Cycle 11) Write Cycle Data input to Precharge (write recovery) DQM Write Mask Latency INFINEON Technologies 9 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS64(72)V16300/32220GU SDRAM-Modules Notes: 1. These parameters depend on the cycle rate. These values are measured at 133 MHz for -7.5 and at 100 Mhz for -8 modules. Input signals are changed once during tck, excepts for ICC6 and for standby currents when tck=infinity. All values are shown per memory component. 2. These parameters are measured with continous data stream during read access and all DQ toggling. CL=3 and BL=4 assumed and the VDDQ current is excluded. 3. All AC characteristics are shown on SDRAM component level. An initial pause of 100µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have Vil = 0.4 V and Vih = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between Vih and Vil. All AC measurements assume tT=1ns with the AC output load circuit show. Specified tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V. t CH 2.4 V 0.4 V CLOCK t CL t SETUP tT t HOLD INPUT 1.4 V t AC t LZ t AC t OH I/O OUTPUT 1.4 V t HZ 50 pF Measurement conditions for tac and toh SPT03404 5. 6. 7. 8. If clock rising time is longer than 1ns, a time (tT/2 -0.5) ns has to be added to this parameter. Rated at 1.5 V If tT is longen than 1 ns, a time (tT -1) ns has to be added to this parameter. Anytime the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up“ the device. 9. Timing is asynchronous. if setup time is not met by rising edge of the clock then the CKE signal is assumed latched on the next cycle. 10.Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 11.Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. INFINEON Technologies 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS64(72)V16300/32220GU SDRAM-Modules SPD-Table for PC133 Modules: Byte# Description SPD Entry Value 0 1 2 3 Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses(for 8Mx8 SDRAMs) Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access time from Clock at CL=3 Dimm Config Refresh Rate/Type 128 256 SDRAM 12 Hex 16Mx64 16Mx72 32Mx64 32Mx72 -7.5 -7.5 -7.5 -7.5 80 08 04 0C 10 0A 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SDRAM width, Primary Error Checking SDRAM data width Minimum clock delay for back-to-back random column address Burst Length supported Number of SDRAM banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM module attributes SDRAM Device Attributes :General Min. Clock Cycle Time at CAS Latency = 2 Max. data access time from Clock for CL=2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL=1 Minimum Row Precharge Time Minimum Row Active to Row Active delay tRRD INFINEON Technologies 1/2 64 / 72 0 LVTTL 7.5 ns 5.4 ns none / ECC Self-Refresh, 15.6µs x8 n/a / x8 01 40 02 48 00 02 00 02 00 08 80 08 00 08 01 1, 2, 4 & 8 4 CAS latency = 2 & 3 CS latency = 0 Write latency = 0 non buffered/non reg. Vcc tol +/- 10% 0F 04 06 0E 10.0 ns A0 6.0 ns 60 not supported FF not supported FF 20 ns 14 15 ns 0F Powered by ICminer.com Electronic-Library Service CopyRight 2003 48 00 01 75 54 tccd = 1 CLK 11 40 01 01 00 12.99 HYS64(72)V16300/32220GU SDRAM-Modules Byte# Description 29 Minimum RAS to CAS delay tRCD 30 Minimum RAS pulse width tRAS 31 Module Bank Density (per bank) 32 SDRAM input setup time 33 SDRAM input hold time 34 SDRAM data input hold time 35 SDRAM data input setup time 62-61 Superset information (may be used in future) 62 SPD Revision 63 Checksum for bytes 0 - 62 64- Manufacturers information 125 (optional) (FFh if not used) 126 Frequency Specification 127 133 MHz support details 128+ Unused storage locations INFINEON Technologies SPD Entry Value 20 ns Hex 16Mx64 16Mx72 32Mx64 32Mx72 -7.5 -7.5 -7.5 -7.5 14 45 ns 2D 128 MByte 20 1.5 ns 0.8 ns 1.5 ns 0.8 ns 15 08 15 08 FF Revision 1.2 12 13 XX 25 XX 14 XX 26 XX 64 AF FF FF 12 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS64(72)V16300/32220GU SDRAM-Modules SPD-Table for PC100 Modules: Byte# Description SPD Entry Value 0 1 2 3 Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses(for 8Mx8 SDRAMs) Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access time from Clock at CL=3 Dimm Config Refresh Rate/Type 128 256 SDRAM 12 Hex 16Mx64 16Mx72 32Mx64 32Mx72 -8 -8 -8 -8 80 08 04 0C 10 0A 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SDRAM width, Primary Error Checking SDRAM data width Minimum clock delay for back-to-back random column address Burst Length supported Number of SDRAM banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM module attributes SDRAM Device Attributes :General Min. Clock Cycle Time at CAS Latency = 2 Max. data access time from Clock for CL=2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL=1 Minimum Row Precharge Time Minimum Row Active to Row Active delay tRRD INFINEON Technologies 1/2 64 / 72 0 LVTTL 10.0 ns 6.0 ns none / ECC Self-Refresh, 15.6µs x8 n/a / x8 01 40 02 48 00 02 00 02 00 08 80 08 00 08 01 1, 2, 4 & 8 4 CAS latency = 2 & 3 CS latency = 0 Write latency = 0 non buffered/non reg. Vcc tol +/- 10% 0F 04 06 0E 10.0 ns A0 6.0 ns 60 not supported FF not supported FF 20 ns 14 16 ns 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 48 00 01 A0 60 tccd = 1 CLK 13 40 01 01 00 12.99 HYS64(72)V16300/32220GU SDRAM-Modules Byte# Description 29 Minimum RAS to CAS delay tRCD 30 Minimum RAS pulse width tRAS 31 Module Bank Density (per bank) 32 SDRAM input setup time 33 SDRAM input hold time 34 SDRAM data input hold time 35 SDRAM data input setup time 62-61 Superset information (may be used in future) 62 SPD Revision 63 Checksum for bytes 0 - 62 64- Manufacturers information 125 (optional) (FFh if not used) 126 Frequency Specification 127 100 MHz support details 128+ Unused storage locations INFINEON Technologies SPD Entry Value 20 ns Hex 16Mx64 16Mx72 32Mx64 32Mx72 -8 -8 -8 -8 14 45 ns 2D 128 MByte 20 2 ns 1 ns 2 ns 1 ns 20 10 20 10 FF Revision 1.2 12 71 XX 83 XX 100 MHz 72 XX 84 XX 64 AF FF FF 14 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS64(72)V16300/32220GU SDRAM-Modules L-DIM-168-30 SDRAM DIMM Module package HYS64/72V32220GU 133.35 127.35 31.75 4 ± 0.1 4 3 *) 1 10 3 11 6.35 1.27 40 41 6.35 84 1.27± 0.1 42.18 85 94 2 95 124 125 168 4.45 8.25 17.78 3.125 91 x 1.27 = 115.57 *) R1.27 +0.1 3 min. 2.26 *) on ECC modules only 2.54 min. 0.2 ± 0.15 Detail of Contacts 1 ± 0.05 1.27 INFINEON Technologies GLD09159 15 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS64(72)V16300/32220GU SDRAM-Modules L-DIM-168-33 SDRAM DIMM Module package HYS64/72V16300GU 133,35 127,35 3,0 1 10 11 40 84 41 17,78 x) 42,18 1,27+- 0.1 66,68 A 85 C B 94 95 124 6,35 125 168 6,35 1,0 + - 0.5 2,54 min. 3,125 3,125 1,27 2,0 Detail A 31.75 4,0 max. 2,0 0,2 +- 0,15 Detail C Detail B DM168-33.WMF x) on ECC modules only INFINEON Technologies 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS64(72)V16300/32220GU SDRAM-Modules Update Releases: June 1, 1999 June 17, 1999 August 3, 1999 August 5, 1999 August 23, 1999 Sept.30, 1999 Dec. 2, 1999 INFINEON Technologies Explanation for factory specific code in part numbers added Byte 22 for PC100 modules changed from 06 to 0E PC133 spec incorpoated SPD tables added Byte 126 changed to 64h for PC133 modules Some errors corrected, checksums added Some timing parameters adjusted according to INTELs PC133 specification -8A speedsort removed 17 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS64(72)V16300/32220GU SDRAM-Modules INFINEON Technologies 18 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99