HYS 64/72V128220GU SDRAM-Modules 3.3 V 128M x 64/72-Bit, 1024 MByte SDRAM Modules 168-pin Unbuffered DIMM Modules Target Datasheet 11.01 • Single + 3.3 V (± 0.3 V) power supply • 168-pin unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main memory applications using 256Mbit technology. • Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) • PC100-222, PC133-333 & PC133-222 versions • Auto Refresh (CBR) and Self Refresh • Two bank 128M × 64 and 128M × 72 organization • Decoupling capacitors mounted on substrate • All inputs and outputs are LVTTL compatible • Optimized for byte-write non-parity and ECC applications • Serial Presence Detect with E2PROM • JEDEC standard Synchronous DRAMs (SDRAM) • Uses Infineon 512 Mbit SDRAM components in 64M × 8 organization and TSOPII-54 packages • Programmed Latencies: Product Speed CL tRCD tRP -7 PC133 2 2 2 -7.5 PC133 3 3 3 -8 PC100 2 2 2 • Fully PC board layout compatible to INTEL’s Rev. 1.0 module specification • Gold contact pad, card size: 133.35 mm × 31.75 mm × 4.00 mm (JEDEC MO-161-BA) • SDRAM Performance: -7 -7.5 -8 PC133 PC133 PC100 Unit fCK Clock Frequency (max.) 133 133 100 MHz tAC Clock Access time 5.4 5.4 6 ns Description The HYS 64V128220GU and HYS 72128220GU are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs) which are organized as 128M × 64 and 128M × 72 in two banks high speed memory arrays designed with 512M Synchronous DRAMs (SDRAMs) for non-parity and ECC applications. The DIMMs use “-7” speed sorted 512 Mbit Synchronous DRAMs (SDRAMs) to meet the PC133-222 requirements, “-7.5” for PC133-333 and “-8” components for PC100-222 applications. Decoupling capacitors are mounted on the PC board. The PC board design is according to INTEL’s module specification. The DIMMs have a serial presence detect, implemented with a serial E2PROM using the 2-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint, with 1.25“ (31.75 mm) height. INFINEON Technologies 1 11.01 HYS 64/72V128220GU SDRAM-Modules Ordering Information Type Code Package Descriptions Module Height HYS 64128220GU-7-A PC133-222-520 L-DIM-168-30 PC133 128M × 64 2 bank 1.25“ SDRAM module HYS 72V128220GU-7-A PC133-222-520 L-DIM-168-30 PC133 128M × 72 2 bank 1.25“ SDRAM module HYS 64V128220GU-7.5-A PC133-333-520 L-DIM-168-30 PC133 128M × 64 2 bank 1.25“ SDRAM module HYS 72V128220GU-7.5-A PC133-333-520 L-DIM-168-30 PC133 128M × 72 2 bank 1.25“ SDRAM module HYS 64V128220GU-8-A PC100-222-620 L-DIM-168-30 PC100 128M × 64 2 bank 1.25“ SDRAM module HYS 72V128220GU-8-A PC100-222-620 L-DIM-168-30 PC100 128M × 72 2 bank 1.25“ SDRAM module Note: All part numbers end with a place code, designating the die revision. Consult factory for current revision. Example: HYS 64V128220GU-8-A, indicating Rev.A dies are used for SDRAM components. ames in paranthese are for the x72 ECC versions; example: Pin 106 = (CB5) Pin Definitions and Functions A0 - A12 Address Inputs CLK0 - CLK3 BA0, BA1 Bank Selects DQMB0 - DQMB7 Data Mask DQ0 - DQ63 Data Input/Output CS0 - CS3 Clock Input Chip Select CB0 - CB7 Check Bits (x72 organization only) VDD RAS Row Address Strobe VSS Ground CAS Column Address Strobe SCL Clock for Presence Detect WE Read/Write Input SDA Serial Data Out for Presence Detect N.C./DU No Connection CKE0, CKE1 Clock Enable Power (+ 3.3 V) Address Format 128M × 64 128M × 72 Part Number Rows Columns Bank Select Refresh Period Interval HYS64V128220GU HYS72V128220GU 13 2 8k INFINEON Technologies 11 2 64 ms 7.8 µ s 11.01 HYS 64/72V128220GU SDRAM-Modules Pin Configuration PIN# Symbol PIN# Symbol PIN# 1 VSS 43 VSS 85 2 DQ0 44 DU 86 87 3 DQ1 45 CS2 4 DQ2 46 DQMB2 88 5 DQ3 47 DQMB3 89 48 DU 90 6 VDD 91 7 DQ4 49 VDD 8 DQ5 50 N.C. 92 9 DQ6 51 N.C. 93 10 DQ7 52 N.C. (CB2) 94 11 DQ8 53 N.C. (CB3) 95 54 VSS 96 12 VSS 13 DQ9 55 DQ16 97 14 DQ10 56 DQ17 98 15 DQ11 57 DQ18 99 16 DQ12 58 DQ19 100 101 17 DQ13 59 VDD 18 VDD 60 DQ20 102 19 DQ14 61 N.C. 103 20 DQ15 62 DU 104 21 N.C. (CB0) 63 CKE1 105 106 22 N.C. (CB1) 64 VSS 23 VSS 65 DQ21 107 24 N.C. 66 DQ22 108 25 N.C. 67 DQ23 109 68 VSS 110 26 VDD 27 WE 69 DQ24 111 28 DQMB0 70 DQ25 112 29 DQMB1 71 DQ26 113 72 DQ27 114 30 CS0 115 31 DU 73 VDD 32 VSS 74 DQ28 116 33 A0 75 DQ29 117 34 A2 76 DQ30 118 35 A4 77 DQ31 119 120 36 A6 78 VSS 37 A8 79 CLK2 121 38 A10 80 N.C. 122 39 BA1 81 WP 123 82 SDA 124 40 VDD 83 SCL 125 41 VDD 126 42 CLK0 84 VDD Note: Pin names in parenthses are for the x72 ECC versions INFINEON Technologies 3 Symbol PIN# Symbol VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 N.C. (CB4) N.C. (CB5) VSS N.C. N.C. VDD CAS DQMB4 DQMB5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD CLK1 A12 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 VSS CKE0 CS3 DQMB6 DQMB7 N.C. VDD N.C. N.C. CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VDD DQ52 N.C. DU N.C. VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CLK3 N.C. SA0 SA1 SA2 VDD 11.01 HYS 64/72V128220GU SDRAM-Modules CS1 CS0 DQMB0 DQ(7:0) DQMB1 DQ(15:8) CS DQM DQ0-DQ7 D0 CS DQM DQ0-DQ7 D8 DQMB4 DQ(39:32) CS DQM DQ0-DQ7 D4 CS DQM DQ0-DQ7 D12 CS DQM DQ0-DQ7 CS DQM DQ0-DQ7 D9 DQMB5 DQ(47:40) CS DQM DQ0-DQ7 D5 CS DQM DQ0-DQ7 D13 D1 CS DQM DQ0-DQ7 D16 DQM DQ0-DQ7 D17 DQMB2 DQ(23:16) CS DQM DQ0-DQ7 D2 CS DQM DQ0-DQ7 D10 DQMB6 DQ(55:48) CS DQM DQ0-DQ7 D6 CS DQM DQ0-DQ7 D14 DQMB3 DQ(31:24) CS DQM DQ0-DQ7 D3 CS DQM DQ0-DQ7 D11 DQMB7 DQ(63:56) CS DQM DQ0-DQ7 D7 CS DQM DQ0-DQ7 D15 CB(7:0) CS CS3 CS2 A0-A12, BA0, BA1 D0-D15, (D16, D17) VDD D0-D15, (D16, D17) 2 E PROM (256 Word x 8 Bit) SA0 SA1 SA2 SCL C VSS D0-D15, (D16, D17) RAS, CAS, WE D0-D15, (D16, D17) CKE0 SA0 SA1 SA2 SCL 47 kΩ Clock Wiring D0-D7, (D16) VDD 32 M x 64 10 kΩ CKE1 SDA WP CLK0 CLK1 CLK2 CLK3 D9-D15, (D17) 4 SDRAM + 4 SDRAM + 4 SDRAM + 4 SDRAM + 3.3 pF 3.3 pF 3.3 pF 3.3 pF 32 M x 72 5 SDRAM 5 SDRAM 4 SDRAM + 3.3 pF 4 SDRAM + 3.3 pF Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10Ω except otherwise noted. BL012 Block Diagram: 64M x 64/72 Two Bank SDRAM DIMM Modules INFINEON Technologies 4 11.01 HYS 64/72V128220GU SDRAM-Modules Absolute Maximum Ratings Parameter Symbol Limit Values min. max. Unit Input / Output voltage relative to VSS VIN, VOUT – 1.0 4.6 Power supply voltage on VDD VDD – 1.0 4.6 V V Storage temperature range T STG -55 +150 o Power dissipation per SDRAM component PD – 1 W Data out current (short circuit) IOS – 50 mA C Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. Functional operation should be restricted to recommended operation conditions. Exposure to higher than recommended voltage for extended periods of time affect device reliability DC Characteristics TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V Parameter Symbol Limit Values Unit min. max. Input High Voltage VIH 2.0 VDD + 0.3 Input Low Voltage VIL – 0.5 0.8 V Output High Voltage (I OUT = – 4.0 mA) VOH 2.4 – V Output Low Voltage (IOUT = 4.0 mA) VOL – 0.4 V Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) II(L) – 40 40 µA Output Leakage Current (DQ is disabled, 0 V < V OUT < V DD) IO(L) – 40 40 µA V Capacitance TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Limit Values Unit max. 64M × 64 max. 64M × 72 CI1 105 144 pF Input Capacitance (CS0 - CS3) CI2 32 40 pF Input Capacitance (CLK0 - CLK3) CICL 40 43 pF Input Capacitance (CKE0, CKE1) CI3 65 72 pF Input Capacitance (DQMB0 - DQMB7) CI4 20 25 pF Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7) CIO 17 17 pF Input Capacitance (SCL, SA0-2) CSC 8 8 pF Input/Output Capacitance CSD 8 8 pF Input Capacitance (A0 to A11, BA0, BA1, RAS, CAS, WE) INFINEON Technologies 5 11.01 HYS 64/72V128220GU SDRAM-Modules Operating Currents per SDRAM Component TA = 0 to 70 oC; VSS = 0 V; VDD , VDDQ = 3.3 V ± 0.3 V Parameter & Test Condition Symb. -7 -7.5 -8 Note max. Operating Current One bank active, Burst length = 1 t RC = tRC(min), Io = 0 mA IDD1 tbd. tbd. tbd. mA 3, 4 Precharge Standby Current in Power Down Mode CS =VIH (min.), CKE<=Vil(max) IDD2P 4 4 4 mA 3 Precharge Standby Current in Non-Power Down Mode CS = VIH (min.), CKE>=Vih(min) IDD2N 36 36 30 mA 3 No Operating Current CS = VIH(min), CKE>=VIH(min.) IDD3N 35 35 30 mA 3 CS = VIH(min), CKE<=VIL(max.) IDD3P 11 11 11 mA 3 IDD4 255 255 150 mA 3, 4 440 440 360 mA tbd. tbd. tbd. mA active state ( max. 4 banks) Burst Operating Current Read command cycling Auto Refresh Current t RFC= tRFC(min) Auto Refresh command cycling tRFC= 7.8 µs IDD5 Self Refresh Current (standard components) Self Refresh Mode CKE=0.2V. tck=infinity IDD6 4 4 4 mA Self Refresh Current (low power components) Self Refresh Mode CKE=0.2V. tck=infinity IDD6 tbd. tbd. tbd. mA 5 Notes: 3. These parameters depend on the cycle rate. All values are measured at 133 MHz for “-7” and “-7.5” and at 100 MHz for “-8” components with the outputs open. Input signals are changed once during tck. 4. These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and the VDDQ current is excluded. 5. tRFC= tRFC(min) “burst refresh”, t RFC= 7.8 µs “distributed refresh”. INFINEON Technologies 6 11.01 HYS 64/72V128220GU SDRAM-Modules AC Characteristics 1), 2) TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symbol Limit Values -7 -7.5 PC133-222 PC133-333 Unit Note -8 PC100-222 min. max min. max. min. max. Clock Clock Cycle Time CAS Latency = 3 CAS Latency = 2 tCK System Frequency CAS Latency = 3 CAS Latency = 2 fCK Clock Access Time CAS Latency = 3 CAS Latency = 2 tAC Clock High Pulse Width Clock Low Pulse Width – 7.5 7.5 – – 7.5 10 – – 10 10 – – ns ns – – 133 133 – – 133 100 – – 100 100 MHz MHz – – 5.4 5.4 – – 5.4 6 – – 6 6 ns ns tCH 2.5 – 2.5 – 3 – ns 4) tCL 2.5 – 2.5 – 3 – ns 4) Input Setup Time tCS 1.5 – 1.5 – 2 – ns 5) Input Hold Time tCH 0.8 – 0.8 – 1 – ns 5) Power Down Mode Entry Time tSB – 1 – 1 – 1 CLK 6) Power Down Mode Exit Setup Time tPDE 1 – 1 – 1 – CLK 7) Mode Register Setup Time tRSC 2 – 2 – 2 – CLK Transition Time (rise and fall) tT 1 – 1 – 1 – ns – RAS to CAS Delay tRCD 15 – 20 – 20 – ns – Precharge Time tRP 15 – 20 – 20 – ns – Active Command Period tRAS 42 – 45 100k 50 100k ns – Cycle Time tRC 60 – 67.5 – 70 – ns – Bank to Bank Delay Time tRRD 14 – 15 – 16 – ns – 1 – 1 – 1 – CLK – – 3), 4) Setup and Hold Times Common Parameters CAS to CAS Delay Time (same bank) tCCD INFINEON Technologies 7 11.01 HYS 64/72V128220GU SDRAM-Modules AC Characteristics (cont’d) 1), 2) TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symbol Limit Values -7 -7.5 PC133-222 PC133-333 Unit Note -8 PC100-222 min. max min. max. min. max. Refresh Cycle Refresh Period (8192 cycles) tREF 64 – – 64 – 64 ms 6) Self Refresh Exit Time tSREX – 1 1 – 1 – CLK 8) Data Out Hold Time tOH 3 – 3 – 3 – ns 2) Data Out to Low Impedance tLZ 0 – 0 – 0 – ns – Data Out to High Impedance tHZ 3 7 3 7 3 8 ns 9) DQM Data Out Disable Latency tDQZ – 2 – 2 – 2 CLK – Data Input to Precharge (write recovery) tWR 2 – 2 – 2 – CLK – DQM Write Mask Latency tDQW 0 – 0 – 0 – CLK – Read Cycle Write Cycle Notes 1. All AC characteristics are shown on SDRAM component level. An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed by eight Auto-Refresh (CBR) cycles before the Mode Register Set Operation can begin. 2. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between V IH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit show. Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate between 0.8 V and 2.0 V. 3. If clock rising time is longer than 1 ns, a time (tT/2 – 0.5) ns must be added to this parameter. 4. Rated at 1.4 V 5. If tT is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter. 6. Anytime the Refresh Period has been exceeded, a minimum of two Auto-Refresh (CBR) commands must be given to “wake-up” the device. 7. Timing is asynchronous. If setup time is not met by rising edge of the clock then the CKE signal is assumed latched on the next cycle. INFINEON Technologies 8 11.01 HYS 64/72V128220GU SDRAM-Modules 8. Self-Refresh Exit is a synchronous operation and begins on the second positive clock edge after CKE returns high. Self-Refresh Exit is not complete until a time period equal to tRC is satisfied after the Self Refresh Exit command is registered. 9. This is referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. t CH 2.4 V 0.4 V 1.4 V CLOCK t CL t IS tT t IH 1.4 V INPUT tAC t LZ tAC t OH I/O OUTPUT 1.4 V t HZ 50 pF Measurement conditions for tAC and tOH IO.vsd Serial Presence Detect A serial presence detect storage device - E 2PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E2PROM device during module production using a serial presence detect protocol (I2C synchronous 2-wire bus). INFINEON Technologies 9 11.01 HYS 64/72V128220GU SDRAM-Modules SPD-Table for 128M x 64 (1024 MByte non-ECC) Modules HYS64V128220GU Byte Description # SPD Entry Value -7 0 1 2 3 4 5 6 7 8 9 10 11 12 Number of SPD Bytes Total Bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels SDRAM Cycle Time at CL = 3 Access Time from Clock at CL = 3 DIMM Config Refresh Rate/Type 13 14 15 SDRAM Width, Primary Error Checking SDRAM Data Width Minimum Clock Delay for Back-toBack Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General SDRAM Cycle Time at CL = 2 Access Time from Clock for CL = 2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL = 1 Minimum Row Precharge Time Minimum Row Active to Row Active Delay tRRD Minimum RAS to CAS Delay t RCD Minimum RAS Pulse Width tRAS Module Bank Density (per bank) SDRAM Input Setup Time SDRAM Input Hold Time 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 INFINEON Technologies 128 256 SDRAM 13 11 2 64 0 LVTTL 7.5 / 10 ns 5.4 / 6 ns non-ECC Self-Refresh, 7.8 µs x8 na tCCD = 1 CLK 1, 2, 4 & 8 4 CL = 2 & 3 CS latency = 0 Write latency = 0 unbuffered VDD tol +/– 10% 7.5 / 10.0 ns 5.4 / 6.0 ns not supported not supported 75 54 Hex 128M x 64 -7.5 80 08 04 0D 0B 02 40 00 01 75 54 00 82 -8 A0 60 08 00 01 75 54 00 00 0F 04 06 01 01 00 0E A0 60 00 00 A0 60 00 00 15 / 20 ns 14 / 15 / 16 ns 0F 0E 14 0F 14 10 15 / 20 ns 42 / 45 / 50 ns 256 MByte 1.5 / 2.0 ns 0.8 / 1.0 ns 0F 2A 14 2D 80 15 08 14 32 10 15 08 20 10 11.01 HYS 64/72V128220GU SDRAM-Modules SPD-Table for 128M x 64 (1024 MByte non-ECC) Modules HYS64V128220GU Byte Description # 34 35 36-61 62 63 64 65-71 72 73-90 91-92 93-94 95-98 99125 126 127 128+ SPD Entry Value SDRAM Data Input Hold Time SDRAM Data Input Setup Time Superset Information SPD Revision Checksum for Bytes 0 - 62 Manufacturers JEDEC ID Code Manufacturer Module Assembly Locaction Module Part Number Module Revision Code Module Manufacturing Code Module Serial Number Superset Information 1.5 / 2.0 ns 0.8 / 1.0 ns – Revision 1.2 – – Frequency Specification 100 MHz Support Details Unused Storage Locations INFINEON Technologies – – 11 -7 15 08 FF 12 35 Hex 128M x 64 -7.5 15 08 FF 12 7A C1 INFINEO(N) -8 20 10 FF 12 DD 64 FF FF 64 FF FF 64 FF FF 11.01 HYS 64/72V128220GU SDRAM-Modules SPD-Table for 128M x 72 (1024 MByte ECC) Modules HYS72V128220GU Byte# Description SPD Entry Value -7 0 1 2 3 4 5 6 7 8 9 10 11 12 Number of SPD Bytes Total Bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels SDRAM Cycle Time at CL = 3 Access Time from Clock at CL = 3 DIMM Config Refresh Rate/Type 13 14 15 SDRAM Width, Primary Error Checking SDRAM Data Width Minimum Clock Delay for Back-toBack Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General SDRAM Cycle Time at CL = 2 Access Time from Clock for CL = 2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL = 1 Minimum Row Precharge Time Minimum Row Active to Row Active Delay tRRD Minimum RAS to CAS Delay tRCD Minimum RAS Pulse Width tRAS Module Bank Density (per bank) SDRAM Input Setup Time SDRAM Input Hold Time 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 INFINEON Technologies 128 256 SDRAM 13 11 2 72 0 LVTTL 7.5 / 10 ns 5.4 / 6 ns ECC Self-Refresh, 7.8 µ s x8 x8 tCCD = 1 CLK 1, 2, 4 & 8 4 CL = 2 & 3 CS latency = 0 Write latency = 0 unbuffered VDD tol +/– 10% 7.5 / 10.0 ns 5.4 / 6.0 ns not supported not supported 12 75 54 Hex 128M x 72 -7.5 80 08 04 0D 0B 02 48 00 01 75 54 02 82 -8 A0 60 08 08 01 75 54 00 00 0F 04 06 01 01 00 0E A0 60 00 00 A0 60 00 00 15 / 20 ns 14 / 15 / 16 ns 0F 0E 14 0F 14 10 15 / 20 ns 42 / 45 / 50 ns 256 MByte 1.5 / 2.0 ns 0.8 / 1.0 ns 0F 2A 14 2D 80 15 08 14 32 15 08 20 10 11.01 HYS 64/72V128220GU SDRAM-Modules SPD-Table for 128M x 72 (1024 MByte ECC) Modules HYS72V128220GU Byte# Description 34 35 36-61 62 63 64 65-71 72 73-90 91-92 93-94 95-98 99-125 126 127 128+ SPD Entry Value SDRAM Data Input Hold Time SDRAM Data Input Setup Time Superset Information SPD Revision Checksum for Bytes 0 - 62 Manufacturers JEDEC ID Code Manufacturer Module Assembly Locaction Module Part Number Module Revision Code Module Manufacturing Code Module Serial Number Superset Information Frequency Specification 100 MHz Support Details Unused Storage Locations INFINEON Technologies 1.5 / 2.0 ns 0.8 / 1.0 ns – Revision 1.2 – – – – 13 -7 15 08 FF 12 47 Hex 128M x 72 -7.5 15 08 FF 12 8C C1 INFINEO(N) -8 20 10 FF 12 EF 64 FF FF 64 FF FF 64 FF FF 11.01 HYS 64/72V128220GU SDRAM-Modules Package Outlines L-DIM-168-30 (JEDEC MO-161-BA) SDRAM DIMM Module Package HYS 64/72V128220GU 133.35 +- 0.15 4 max. 4 31.75 +- 0.13 127.35 *) 3 1 10 3 11 6.35 1.27 40 41 6.35 84 1.27 +- 0.1 42.18 85 94 2 95 124 125 168 17.78 3.125 91 x 1.27 = 115.57 *) 3 min. 3 *) on ECC modules only 2.55 0.25 Detail of Contacts 1 1.27 L-DIM-168-30 Note: All tolerances according to JEDEC standard INFINEON Technologies 14 11.01 HYS 64/72V128220GU SDRAM-Modules Change List: 4.11.2001 INFINEON Technologies First Revision 15 11.01