ETC HYS64V16302GU-7.5-D

HYS 64V16302GU
SDRAM-Modules
3.3 V 16M × 64-Bit, 128MByte SDRAM Module
168-pin Unbuffered DIMM Modules
• 168 Pin unbuffered 8 Byte Dual-In-Line
SDRAM Modules for PC main memory
applications using 256Mbit technology
• Programmed Latencies:
Product Speed
CL
tRCD
tRP
2
• PC100-222, PC133-333 and PC133-222
versions
-7
PC133 2
2
-7.5
PC133 3
3
3
• One bank 16M × 64 organization
-8
PC100 2
2
2
• Optimized for byte-write non-parity
• Programmable CAS Latency, Burst Length,
and Wrap Sequence
(Sequential & Interleave)
• JEDEC standard Synchronous DRAMs
(SDRAM)
• Auto Refresh (CBR) and Self Refresh
• Single 3.3 V (± 0.3 V) power supply
• Decoupling capacitors mounted on substrate
• SDRAM Performance:
• All inputs and outputs are LVTTL compatible
-7/ -7.5 -8
fCK Clock
Unit
PC133
PC100
133
100
MHz
6
ns
• Serial Presence Detect with E2PROM
• Utilizes 16M × 16 (256Mbit SDRAMs in
TSOPII-54 packages with
8096 refresh cycles every 64 ms
Frequency
(max.)
tAC Clock Access 5.4
• 133.35 mm × 29.21 mm × 3.00 mm card size
with gold contact pads
(JEDEC MO-161)
Time
Description
The HYS 64V16302 is an industry standard 168-pin 8-byte Dual in-line Memory Module (DIMM)
which is organized as 16M × 64 in an one bank high speed memory arrays designed with 256 Mbit
Synchronous DRAMs for non-parity applications. The DIMMs use -7 speed sorted 16M × 16
organised 256Mbit SDRAM devices in TSOP54 packages to meet the PC133-222 requirements, 7.5 for PC133-333 and -8 parts for the standard PC100 applications. Decoupling capacitors are
mounted on the PC board. The PC board design is according to INTEL’s module specification.
The DIMMs have a serial presence detect, implemented with a serial E2PROM using the 2-pin I2C
protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are
available to the end user.
All Infineon 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm
long footprint.
Important Notice:
This module, which is based on 256MBit device technology can only be used in applications, where
the 256Mbit addressing is supported.
INFINEON Technologies
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9.01
HYS 64V16302GU
SDRAM-Modules
Ordering Information
Type
Code
Package
Description
Module
Height
HYS 64V16302GU-7-D
PC133-222-520 L-DIM-168-32 133 MHz CL=2 16M × 64
one bank SDRAM module
HYS 64V16302GU-7.5-C2 PC133-333-520 L-DIM-168-32 133 MHz CL=3 16M × 64
one bank SDRAM module
HYS 64V16302GU-7.5-D
1.15”
PC100-222-620 L-DIM-168-32 100 MHz CL=2 16M × 64
one bank SDRAM module
1.15”
HYS 64V16302GU-8-C2
Note: All part numbers end with a place code (not shown), designating the die revision. Consult
factory for current revision. Example: HYS64V16302GU-8-C2, indicating Rev.C2 dies are
used for SDRAM components.
Pin Definitions and Functions
A0 - A12
Address Inputs
CLK0 - CLK3
Clock Input
BA0, BA1
Bank Select
DQMB0 - DQMB7 Data Mask
DQ0 - DQ63
Data Input/Output
CS0, CS2
Chip Select
CB0 - CB7
Check Bits (x72
organization only)
VDD
Power (+ 3.3 V)
RAS
Row Address Strobe
VSS
Ground
Clock for Presence Detect
CAS
Column Address Strobe
SCL
WE
Read/Write Input
SDA
Serial Data Out for Pres. Detect
CKE0
Clock Enable
N.C./DU
No Connection
Address Format
Part Number
16M×64
Rows Columns Bank Select
HYS64V16302GU 13
INFINEON Technologies
9
2
2
Refresh
Period
Interval
8k
64 ms
7,8 µs
9.01
HYS 64V16302GU
SDRAM-Modules
Pin Configuration
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
PIN#
1
VSS
43
VSS
85
VSS
127
VSS
2
3
4
5
6
DQ0
DQ1
DQ2
DQ3
DU
CS2
DQMB2
DQMB3
DU
86
87
88
89
90
DQ32
DQ33
DQ34
DQ35
VDD
44
45
46
47
48
VDD
128
129
130
131
132
CKE0
N.C.
DQMB6
DQMB7
N.C.
7
DQ4
49
VDD
91
DQ36
133
VDD
8
9
10
11
12
DQ5
DQ6
DQ7
DQ8
N.C.
N.C.
N.C.
N.C.
92
93
94
95
96
DQ37
DQ38
DQ39
DQ40
VSS
134
135
136
137
138
N.C.
N.C.
CB6
CB7
VSS
50
51
52
53
54
13
14
15
16
17
DQ9
DQ10
DQ11
DQ12
DQ13
55
56
57
58
59
DQ16
DQ17
DQ18
DQ19
DQ41
DQ42
DQ43
DQ44
DQ45
139
140
141
142
143
DQ48
DQ49
DQ50
DQ51
VDD
97
98
99
100
101
18
VDD
60
DQ20
102
VDD
144
DQ52
19
20
21
22
DQ14
DQ15
N.C.
N.C.
61
62
63
64
N.C.
DU
N.C.
DQ46
DQ47
N.C.
N.C.
145
146
147
148
N.C.
DU
N.C.
VSS
103
104
105
106
23
VSS
65
DQ21
107
VSS
149
DQ53
24
25
26
N.C.
N.C.
DQ22
DQ23
108
109
110
N.C.
N.C.
VDD
150
151
152
DQ54
DQ55
VDD
66
67
68
27
28
29
30
31
WE
DQMB0
DQMB1
CS0
DU
69
70
71
72
73
DQ24
DQ25
DQ26
DQ27
CAS
DQMB4
DQMB5
N.C.
RAS
153
154
155
156
157
DQ56
DQ57
DQ58
DQ59
VDD
111
112
113
114
115
32
VSS
74
DQ28
116
VSS
158
DQ60
33
34
35
36
A0
A2
A4
A6
75
76
77
78
DQ29
DQ30
DQ31
A1
A3
A5
A7
159
160
161
162
DQ61
DQ62
DQ63
VSS
117
118
119
120
37
38
39
40
A8
A10
BA1
CLK2
N.C.
WP
SDA
121
122
123
124
A9
BA0
A11
VDD
79
80
81
82
VDD
163
164
165
166
CLK3
N.C.
SA0
SA1
41
VDD
83
SCL
125
CLK1
167
SA2
42
CLK0
84
VDD
126
A12
168
VDD
INFINEON Technologies
VSS
VSS
3
Symbol
VSS
VDD
VSS
VSS
VDD
VSS
9.01
HYS 64V16302GU
SDRAM-Modules
Functional Block Diagrams
CS0, CLK0
DQMB4
DQ32-DQ39
DQMB0
DQ0-DQ7
CS, CLK
LDQM
DQ0-DQ7
UDQM
DQ8-DQ15
D0
DQMB5
DQ40-DQ47
DQMB1
DQ8-DQ15
CS, CLK
LDQM
DQ0-DQ7
UDQM
DQ8-DQ15
D1
CS, CLK
LDQM
DQ0-DQ7
UDQM
DQ8-DQ15
D2
DQMB7
DQ56-DQ63
DQMB3
DQ24-DQ31
CS, CLK
LDQM
DQ0-DQ7
UDQM
DQ8-DQ15
D3
CS2, CLK2
DQMB6
DQ48-DQ55
DQMB2
DQ16-DQ23
A0-A12, BA0, BA1
D0-D3
VCC
D0-D3
2
E PROM (256 word x 8 Bit)
SA0
SA1
SA2
SCL
C
VSS
D0-D3
RAS, CAS, WE
D0-D3
CKE0
D0-D3
SA0
SA1
SA2
SCL
SDA
WP
47 k Ω
Clock Wiring
8 M x 64
CLK1, CLK3
CLK0
CLK1
CLK2
CLK3
10 pF
Notes:
2 SDRAM + 3.3 pF
Termination
2 SDRAM + 3.3 pF
Termination
1) All resistors are 10 Ohm except otherwise noted
BL03 7.8.00
Block Diagram: 16M x 64 One Bank SDRAM DIMM Modules (HYS 64V16302GU)
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HYS 64V16302GU
SDRAM-Modules
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
min.
max.
Unit
Input / Output voltage relative to VSS
VIN, VOUT
– 1.0
4.6
Power supply voltage on VDD
VDD,
– 1.0
4.6
V
V
Storage temperature range
T STG
-55
+150
o
Power dissipation
PD
–
4
W
Data out current (short circuit)
IOS
–
50
mA
C
Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended operation conditions.
Exposure to higher than recommended voltage for extended periods of time affect device reliability
DC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V
Parameter
Symbol
Limit Values
min.
max.
Input High Voltage
VIH
2.0
VDD + 0.3
Unit
V
Input Low Voltage
VIL
– 0.5
0.8
V
Output High Voltage (I OUT = – 4.0 mA)
VOH
2.4
–
V
Output Low Voltage (IOUT = 4.0 mA)
VOL
–
0.4
V
Input Leakage Current, any input
(0 V < VIN < 3.6 V, all other inputs = 0 V)
II(L)
– 10
10
µA
Output Leakage Current
(DQ is disabled, 0 V < V OUT < V DD)
IO(L)
– 10
10
µA
Capacitance
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
Limit Values
Unit
Input Capacitance (A0 - A12, RAS, CAS, WE)
CI1
35
pF
Input Capacitance (CS0 ,CS2)
CI2
25
pF
Input Capacitance (CLK0 - CLK3)
CICL
35
pF
Input Capacitance (CKE0)
CI3
30
pF
Input Capacitance (DQMB0 - DQMB7)
CI4
13
pF
Input /Output Capacitance (DQ0 - DQ63, CB0 - CB7)
CIO
10
pF
Input Capacitance (SCL, SA0-2)
CSC
8
pF
Input /Output Capacitance
CSD
10
pF
max.
INFINEON Technologies
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HYS 64V16302GU
SDRAM-Modules
Operating Currents per SDRAM component
TA = 0 to 70 °C, VDD = 3.3 V ± 0.3 V
Parameter
Test Condition Symbol -7.5
-8
Unit Note
max.
Operating current
tRC = tRC(MIN.), tCK = tCK(MIN.)
Outputs open, Burst Length = 4, CL=3
All banks operated in random access,
all banks operated in ping-pong
manner to maximize gapless data
access
–
ICC1
230
170
mA
1)
Precharge standby current
in Power Down Mode
CS = V IH (MIN.), CKE ≤ V IL(MAX.)
tCK = min
ICC2P
2
2
mA
1)
Precharge stand-by current
in Non Power Down Mode
CS = V IH (MIN.), CKE ≥ V IH(MIN.)
tCK = min
ICC2N
40
30
mA
1)
No operating current
tCK = min., CS = VIH (MIN.),
active state (max. 4 banks)
CKE ≥ VIH(MIN.)
ICC3N
50
45
mA
1)
CKE ≤ VIL(MAX.)
ICC3P
10
10
mA
1)
Burst Operating Current
tCK = min
Read command cycling
–
ICC4
170
120
mA
1, 2)
Auto Refresh Current
tCK = min
Auto Refresh command cycling
–
ICC5
150
100
mA
1)
ICC6
3
3
mA
1)
Self Refresh Current
Self Refresh Mode
CKE = 0.2 V
1. All values are shown per one SDRAM component.
2. These parameters depend on the cycle rate. These values are measured at 133 MHz operation
frequency for-7 & -7.5 and at 100 MHz for -8 modules.
Input signals are changed once during t CK, excepts for ICC6 and for stand-by currents when
tCK = infinity.
3. These parameters are measured with continuous data stream during read access and all DQ
toggling. CL = 3 and BL = 4 are assumed and th data-out current is excluded.
INFINEON Technologies
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HYS 64V16302GU
SDRAM-Modules
AC Characteristics 1), 2)
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values
-7
-7.5
PC133-222 PC133-333
Unit Note
-8
PC100-222
min. max min. max. min. max.
Clock
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
tCK
System Frequency
CAS Latency = 3
CAS Latency = 2
fCK
Clock Access Time
CAS Latency = 3
CAS Latency = 2
tAC
Clock High Pulse Width
Clock Low Pulse Width
–
7.5
7.5
–
–
7.5
10
–
–
10
10
–
–
ns
ns
–
–
133
133
–
–
133
100
–
–
100
100
MHz
MHz
–
–
5.4
5.4
–
–
5.4
6
–
–
6
6
ns
ns
tCH
2.5
–
2.5
–
3
–
ns
4)
tCL
2.5
–
2.5
–
3
–
ns
4)
Input Setup Time
tCS
1.5
–
1.5
–
2
–
ns
5)
Input Hold Time
tCH
0.8
–
0.8
–
1
–
ns
5)
Power Down Mode Entry Time
tSB
–
1
–
1
–
1
CLK
6)
Power Down Mode Exit Setup Time
tPDE
1
–
1
–
1
–
CLK
7)
Mode Register Setup Time
tRSC
2
–
2
–
2
–
CLK
Transition Time (rise and fall)
tT
1
–
1
–
1
–
ns
–
RAS to CAS Delay
tRCD
15
–
20
–
20
–
ns
–
Precharge Time
tRP
15
–
20
–
20
–
ns
–
Active Command Period
tRAS
42
–
45
100k 50
100k ns
–
Cycle Time
tRC
60
–
67.5
–
70
–
ns
–
Bank to Bank Delay Time
tRRD
14
–
15
–
16
–
ns
–
1
–
1
–
1
–
CLK –
–
3), 4)
Setup and Hold Times
Common Parameters
CAS to CAS Delay Time (same bank) tCCD
INFINEON Technologies
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HYS 64V16302GU
SDRAM-Modules
AC Characteristics (cont’d) 1), 2)
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values
-7
-7.5
PC133-222 PC133-333
Unit Note
-8
PC100-222
min. max min. max. min. max.
Refresh Cycle
Refresh Period (8192 cycles)
tREF
64
–
–
64
–
64
ms
6)
Self Refresh Exit Time
tSREX
–
1
1
–
1
–
CLK
8)
Data Out Hold Time
tOH
3
–
3
–
3
–
ns
2)
Data Out to Low Impedance
tLZ
0
–
0
–
0
–
ns
–
Data Out to High Impedance
tHZ
3
7
3
7
3
8
ns
9)
DQM Data Out Disable Latency
tDQZ
–
2
–
2
–
2
CLK –
Data Input to Precharge
(write recovery)
tWR
2
–
2
–
2
–
CLK –
DQM Write Mask Latency
tDQW
0
–
0
–
0
–
CLK –
Read Cycle
Write Cycle
INFINEON Technologies
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HYS 64V16302GU
SDRAM-Modules
Notes
1. All AC characteristics are shown for the SDRAM components.
An initial pause of 100 µ s is required after power-up. Then a Precharge All Banks command must
be given followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation
can begin.
2. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between V IH and VIL. All AC measurements assume
tT = 1 ns with the AC output load circuit shown in Figure below. Specified tAC and tOH parameters
are measured with a 50 pF only, without any resistive termination and with a input signal of 1V/
ns edge rate between 0.8 V and 2.0 V.
3. If clock rising time is longer than 1 ns, a time (tT/2 − 0.5) ns must be added to this parameter.
4. Rated at 1.4 V.
5. If tT is longer than 1 ns, a time (tT − 1) ns must be added to this parameter.
6. Whenever the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
commands must be given to “wake-up” the device.
7. Timing is a asynchronous. If setup time is not met by rising edge of the clock then the CKE signal
is assumed latched on the next cycle.
8. Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied
after the Self Refresh Exit command is registered.
9. This is referenced to the time at which the output achieved the open circuit condition, not to
output voltage levels.
t CH
2.4 V
0.4 V
CLOCK
t CL
t SETUP
tT
t HOLD
1.4 V
INPUT
t AC
t LZ
t AC
I/O
t OH
50 pF
OUTPUT
1.4 V
Measurement conditions for
tAC and tOH
t HZ
SPT03404
Serial Presence Detect
A serial presence detect storage device - E 2PROM - is assembled onto the module. Information
about the module configuration, speed, etc. is written into the E2PROM device during module
production using a serial presence detect protocol (I2C synchronous 2-wire bus).
INFINEON Technologies
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HYS 64V16302GU
SDRAM-Modules
SPD-Table for 16M x 64 (128 MByte non-ECC) Modules HYS64V16302GU
Byte# Description
SPD Entry Value
-7
0
1
2
3
4
5
6
7
8
9
10
11
12
Number of SPD Bytes
Total Bytes in Serial PD
Memory Type
Number of Row Addresses
Number of Column Addresses
Number of DIMM Banks
Module Data Width
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL = 3
SDRAM Access Time at CL = 3
DIMM Config
Refresh Rate/Type
13
14
15
SDRAM Width, Primary
Error Checking SDRAM Data Width
Minimum Clock Delay for Back-toBack Random Column Address
Burst Length Supported
Number of SDRAM Banks
Supported CAS Latencies
CS Latencies
WE Latencies
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
SDRAM Cycle Time at CL = 2
SDRAM Access Time at CL = 2
SDRAM Cycle Time at CL = 1
SDRAM Access Time at CL = 1
Minimum Row Precharge Time
Min. Row to Row Active Delay tRRD
Minimum RAS to CAS Delay tRCD
Minimum RAS Pulse Width tRAS
Module Bank Density (per bank)
SDRAM Input Setup Time
SDRAM Input Hold Time
SDRAM Data Input Hold Time
SDRAM Data Input Setup Time
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
INFINEON Technologies
128
256
SDRAM
13
10
1
64
0
LVTTL
7.5 / 10 ns
5.4 / 6 ns
non-ECC
Self-Refresh,
7.8 µ s
x16
na
tCCD = 1 CLK
1, 2, 4 & 8
4
CL = 2 & 3
CS latency = 0
Write latency = 0
unbuffered
VDD tol +/– 10%
7.5 / 10.0 ns
5.4 / 6.0 ns
not supported
not supported
15 / 20 ns
14 / 15 / 16 ns
15 / 20 ns
42 / 45 / 50 ns
256 MByte
1.5 / 2.0 ns
0.8 / 1.0 ns
1.5 / 2.0 ns
0.8 / 1.0 ns
10
75
54
Hex
16M x 64
-7.5
80
08
04
0D
09
01
40
00
01
75
54
00
82
-8
A0
60
10
00
01
75
54
00
00
0F
0E
0F
2A
15
08
15
08
0F
04
06
01
01
00
0E
A0
60
FF
FF
14
0F
14
2D
20
15
08
15
08
A0
60
FF
FF
14
10
14
2D
20
10
20
10
9.01
HYS 64V16302GU
SDRAM-Modules
Byte# Description
36-61
62
63
64
65-71
72
73-90
91-92
93-94
95-98
99-125
126
127
128+
SPD Entry Value
Superset Information
SPD Revision
Checksum for Bytes 0 - 62
Manufacturers JEDEC ID Code
Manufacturer
Module Assembly Locaction
Module Part Number
Module Revision Code
Module Manufacturing Code
Module Serial Number
Superset Information
Frequency Specification
100 MHz Support Details
Unused Storage Locations
INFINEON Technologies
–
Revision 1.2
–
–
–
–
11
Hex
16M x 64
-7
-7.5
-8
FF
FF
FF
12
12
12
DA
1D
7B
C1
INFINEO(N)
64
AF
FF
64
AF
FF
64
AF
FF
9.01
HYS 64V16302GU
SDRAM-Modules
Package Outlines
L-DIM-168-32 (JEDEC MO-161-BA)
SDRAM DIMM Module Package
133.35 -+ 0.15
3 max.
4
29.21 +- 0.13
127.35
3
1
10
3
11
6.35
1.27
40
41
6.35
84
+ 0.1
1.27 -
42.18
85
94
2
95
124
125
168
17.78
3.125
91 x 1.27 = 115.57
66.68
3 min.
L-DIM-168-32
2.55
0.25
Detail of Contacts
1
1.27
Note: All tolerances according to JEDEC standard
Dimensions in mm
INFINEON Technologies
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9.01