HYS 64V8301GU SDRAM-Modules 3.3 V 8M × 64-Bit 1 Bank SDRAM Module 168-pin Unbuffered DIMM Modules • Programmed Latencies: • 168 Pin unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main memory applications Product Speed CL tRCD tRP • PC100 and PC133 versions -7.5 PC133 3 3 3 • One bank 8M × 64 organization -8 PC100 2 2 2 • Single 3.3 V (± 0.3 V) power supply • Optimized for byte-write non-parity applications • Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) • JEDEC standard Synchronous DRAMs (SDRAM) • Fully PC board layout compatible to INTEL’s latest module specification • Auto Refresh (CBR) and Self Refresh • SDRAM Performance: • All inputs and outputs are LVTTL compatible fCK Clock -7.5 -8 PC133 PC100 133 100 • Decoupling capacitors mounted on substrate • Serial Presence Detect with E2PROM Unit • Utilizes four 8M × 16 SDRAMs in TSOPII-54 packages with 4096 refresh cycles every 64 ms MHz Frequency (max.) tAC Clock Access 5.4 6 • 133.35 mm × 29.31 mm × 4.00 mm card size with gold contact pads ns Time The HYS 64V8301 is an industry standard 168-pin 8-byte Dual in-line Memory Module (DIMM) which is organized as 8M × 64 in an one bank high speed memory arrays designed with 128 Mbit Synchronous DRAMs for non-parity applications. The DIMMs use -7.5 speed sorted 4M × 16 SDRAM devices in TSOP54 packages to meet the PC133-333 requirements and -8 parts for the standard PC100 applications. Decoupling capacitors are mounted on the PC board. The PC board design is according to INTEL’s module specification. The DIMMs have a serial presence detect, implemented with a serial E2PROM using the 2-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint., Data Book 1 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS 64V8301GU SDRAM-Modules Ordering Information Type Code Package Description Module Height HYS 64V8301GU-7.5-C PC133-333-520 L-DIM-168-32 133 MHz 4M × 64 1 bank SDRAM module 1.15” HYS 64V8301GU-8-C PC100-222-620 L-DIM-168-32 100 MHz 4M × 64 1 bank SDRAM module 1.15” Note: All part numbers end with a place code (not shown), designating the die revision. Consult factory for current revision. Example: HYS64V4300GU-8-C, indicating Rev.C dies are used for SDRAM components. Pin Definitions and Functions A0 - A11 Address Inputs (RA0 ~ RA11 / CA0 ~ CA7, CA10) CLK0 - CLK3 BA0, BA1 Bank Select DQMB0 - DQMB7 Data Mask DQ0 - DQ63 Data Input/Output CS0 - CS3 Chip Select CB0 - CB7 Check Bits (x72 organization only) VDD Power (+ 3.3 V) RAS Row Address Strobe VSS Ground CAS Column Address Strobe SCL Clock for Presence Detect WE Read/Write Input SDA Serial Data Out for Pres. Detect N.C./DU No Connection CKE0, CKE1 Clock Enable Clock Input Address Format 8M × 64 Data Book Part Number Rows Columns Bank Select Refresh Period Interval HYS 64V8301GU 12 4k 64 ms 15.6 µs 9 2 2 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS 64V8301GU SDRAM-Modules Pin Configuration PIN# Symbol PIN# Symbol PIN# Symbol PIN# Symbol 1 VSS 43 VSS 85 VSS 127 VSS 2 3 4 5 6 DQ0 DQ1 DQ2 DQ3 DU CS2 DQMB2 DQMB3 DU 86 87 88 89 90 DQ32 DQ33 DQ34 DQ35 VDD 44 45 46 47 48 VDD 128 129 130 131 132 CKE0 CS3 DQMB6 DQMB7 N.C. 7 DQ4 49 VDD 91 DQ36 133 VDD 8 9 10 11 12 DQ5 DQ6 DQ7 DQ8 N.C. N.C. N.C. N.C. 92 93 94 95 96 DQ37 DQ38 DQ39 DQ40 VSS 134 135 136 137 138 N.C. N.C. CB6 CB7 VSS 50 51 52 53 54 13 14 15 16 17 DQ9 DQ10 DQ11 DQ12 DQ13 55 56 57 58 59 DQ16 DQ17 DQ18 DQ19 DQ41 DQ42 DQ43 DQ44 DQ45 139 140 141 142 143 DQ48 DQ49 DQ50 DQ51 VDD 97 98 99 100 101 VDD 18 VDD 60 DQ20 102 VDD 144 DQ52 19 20 21 22 DQ14 DQ15 N.C. N.C. 61 62 63 64 N.C. DU CKE1 DQ46 DQ47 N.C. N.C. 145 146 147 148 N.C. DU N.C. VSS 103 104 105 106 23 VSS 65 DQ21 107 VSS 149 DQ53 24 25 26 N.C. N.C. DQ22 DQ23 108 109 110 N.C. N.C. VDD 150 151 152 DQ54 DQ55 VDD 66 67 68 27 28 29 30 31 WE DQMB0 DQMB1 CS0 DU 69 70 71 72 73 VDD 111 112 113 114 115 CAS DQMB4 DQMB5 CS1 RAS 153 154 155 156 157 VDD 32 VSS 74 DQ28 116 VSS 158 DQ60 33 34 35 36 A0 A2 A4 A6 75 76 77 78 DQ29 DQ30 DQ31 A1 A3 A5 A7 159 160 161 162 DQ61 DQ62 DQ63 VSS 117 118 119 120 VSS 37 38 39 40 A8 A10 BA1 CLK2 N.C. WP SDA 121 122 123 124 A9 BA0 A11 VDD 79 80 81 82 VDD 163 164 165 166 CLK3 N.C. SA0 SA1 41 VDD 83 SCL 125 CLK1 167 SA2 42 CLK0 84 VDD 126 N.C. 168 VDD Data Book VSS VSS DQ24 DQ25 DQ26 DQ27 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 VSS VSS VSS DQ56 DQ57 DQ58 DQ59 12.99 HYS 64V8301GU SDRAM-Modules Functional Block Diagrams CS0 CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 DQMB0 DQ0-DQ7 DQMB1 DQ8-DQ15 CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 DQMB4 DQ32-DQ39 DQMB5 DQ40-DQ47 D2 D0 CS2 CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 DQMB2 DQ16-DQ23 DQMB3 DQ24-DQ31 CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 DQMB6 DQ48-DQ55 DQMB7 DQ56-DQ63 D1 A0-A11, BA0, BA1 D0-D3, (D4) VCC D0-D3, (D4) D3 E 2 PROM (256 word x 8 Bit) SA0 SA1 SA2 SCL C VSS D0-D3, (D4) RAS, CAS, WE D0-D3, (D4) CKE0 D0-D3 SA0 SA1 SA2 SCL SDA WP 47 k Ω Clock Wiring 4 M x 64 CLK1, CLK3 CLK0 CLK1 CLK2 CLK3 10 pF Notes: 2 SDRAM + 15 pF Termination 2 SDRAM + 15 pF Termination 1) All resistors are 10 Ω 2) DIMM may combine bytes 0 with 4, 1 with 5, 2 with 6 and 3 with 7 to obtain most advantagous board layout to obtain minimum DQ trance length SPB04204 Block Diagram: 4M × 64 One Bank SDRAM DIMM Modules (HYS 64V4300GU) Data Book 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS 64V8301GU SDRAM-Modules DC Characteristics TA = 0 to 70 °C; VSS = 0 V; VDD; VDDQ = 3.3 V ± 0.3 V Parameter Symbol Limit Values min. max. Unit Input High Voltage VIH 2.0 VDD + 0.3 V Input Low Voltage VIL – 0.5 0.8 V Output High Voltage (IOUT = – 4.0 mA) VOH 2.4 – V Output Low Voltage (IOUT = 4.0 mA) VOL – 0.4 V Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) II(L) – 10 10 µA Output Leakage Current (DQ is disabled, 0 V < VOUT < VDD) IO(L) – 10 10 µA Capacitance TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Limit Values Unit max. Input Capacitance (A0 - A11, RAS, CAS, WE) CI1 35 pF Input Capacitance (CS0 , CS2) CI2 25 pF Input Capacitance (CLK0 - CLK3) CICL 35 pF Input Capacitance (CKE0) CI3 30 pF Input Capacitance (DQMB0 - DQMB7) CI4 13 pF Input /Output Capacitance (DQ0 - DQ63, CB0 - CB7) CIO 10 pF Input Capacitance (SCL, SA0-2) CSC 8 pF Input /Output Capacitance CSD 8 pF Data Book 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS 64V8301GU SDRAM-Modules Operating Currents 1 TA = 0 to 70 °C, VDD = 3.3 V ± 0.3 V (Recommended Operating Conditions unless otherwise noted) Parameter Test Condition Symbol -7.5 -8 Unit Note max. Operating current tRC = tRC(MIN.), tCK = tCK(MIN.) Outputs open, Burst Length = 4, CL=3 All banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access – ICC1 150 140 mA 1) Precharge standby current in Power Down Mode CS = VIH (MIN.), CKE ≤ VIL(MAX.) tCK = min ICC2P 2 2 mA 1) tCK = infinity ICC2PS 1 1 mA 1) Precharge stand-by current in Non Power Down Mode CS = VIH (MIN.), CKE ≥ VIH(MIN.) tCK = min ICC2N 40 35 mA 1) tCK = infinity ICC2NS 5 5 mA 1) No operating current tCK = min., CS = VIH (MIN.), active state (max. 4 banks) CKE ≥ VIH(MIN.) ICC3N 50 45 mA 1) CKE ≤ VIL(MAX.) ICC3P 10 10 mA 1) Burst Operating Current tCK = min Read command cycling – ICC4 150 140 mA 1, 2) Auto Refresh Current tCK = min Auto Refresh command cycling – ICC5 180 170 mA 1) ICC6 1.5 1.5 mA 1) Self Refresh Current Self Refresh Mode CKE = 0.2 V Data Book 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS 64V8301GU SDRAM-Modules AC Characteristics 3,4 TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symbol Limit Values -7.5 PC133-333 min. max. Unit Note -8 PC100-222 min. max. Clock and Access Time Clock Cycle Time CAS Latency = 3 CAS Latency = 2 tCK System Frequency CAS Latency = 3 CAS Latency = 2 fCK Access Time from Clock CAS Latency = 3 CAS Latency = 2 tAC Clock High Pulse Width Clock Low Pulse Width – 7.5 10 – – 10 10 – – ns ns – – 133 100 – – 100 100 MHz MHz – – 5.4 6 – – 6 6 ns ns 4), 5) tCH 2.5 – 3 – ns 6) tCL 2.5 – 3 – ns 6) Input Setup Time tCS 1.5 – 2 – ns 7) Input Hold Time tCH 0.8 – 1 – ns 7) Power Down mode Entry Time tSB – 1 – 1 CLK 8) Power Down Mode Exit Setup Time tPDE 1 – 1 – CLK 9) Mode Register Setup Time tESC 2 – 2 – CLK Transition Time tT 1 – 1 – ns – RAS to CAS Delay tRCD 20 – 20 – ns – Precharge Time tRP 20 – 20 – ns – Active Command Period tRAS 45 100k 50 100k ns – Cycle Time tRC 67.5 – 70 – ns – Bank to Bank Delay Time tRRD 15 – 16 – ns – CAS to CAS Delay Time (same bank) tCCD 1 – 1 – CLK – – Setup and Hold Parameters Common Parameters Data Book 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS 64V8301GU SDRAM-Modules AC Characteristics (cont’d)3,4 TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symbol Limit Values -7.5 PC133-333 Unit Note -8 PC100-222 min. max. min. max. Refresh Cycle Refresh Period (4096 cycles) tREF – 64 – 64 ms 8) Self Refresh Exit Time tSREX 1 – 1 – CLK 10) Data Out Hold Time tOH 3 – 3 – ns 4) Data Out to Low Impedance Time tLZ 0 – 0 – ns – Data Out to High Impedance Time tHZ 3 7 3 8 ns 11) DQM Data Out Disable Latency tDQZ – 2 – 2 CLK – Data Input to Precharge (write recovery) tWR 2 – 2 – CLK – DQM Write Mask Latency tDQW 0 – 0 – CLK – Read Cycle Write Cycle Notes 1. These parameters depend on the cycle rate. These values are measured at 133 MHz for -7.5 and at 100 MHz for -8 modules. Input signals are changed once during tCK, excepts for ICC6 and for stand-by currents when tCK = infinity. All values are shown per memory component. 2. These parameters are measured with continuous data stream during read access and all DQ toggling. CL = 3 and BL = 4 are assumed and the VDDQ current is excluded. 3. All AC characteristics are shown for device level. An initial pause of 100 µs is required after power-up. Then a Precharge All Banks command must be given followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown in Figure below. Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V/ ns edge rate between 0.8 V and 2.0 V. 5. If clock rising time is longer than 1 ns, a time (tT/2 − 0.5) ns must be added to this parameter. 6. Rated at 1.4 V. 7. If tT is longer than 1 ns, a time (tT − 1) ns must be added to this parameter. Data Book 8 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS 64V8301GU SDRAM-Modules 8. Whenever the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up” the device. 9. Timing is a asynchronous. If setup time is not met by rising edge of the clock then the CKE signal is assumed latched on the next cycle. 10.Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied after the Self Refresh Exit command is registered. 11.This is referenced to the time at which the output achieved the open circuit condition, not to output voltage levels. t CH 2.4 V 0.4 V CLOCK t CL t SETUP tT t HOLD INPUT 1.4 V t AC t LZ t AC I/O t OH 50 pF OUTPUT 1.4 V Measurement conditions for tAC and tOH t HZ SPT03404 A serial presence detect storage device - E2PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E2PROM device during module production using a serial presence detect protocol (I2C synchronous 2-wire bus). Data Book 9 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS 64V8301GU SDRAM-Modules SPD-Table Byte# Description SPD Entry Value Hex 8M × 64 8M × 64 -7.5 -8 0 Number of SPD bytes 128 80 80 1 Total Bytes in Serial PD 256 08 08 2 Memory Type SDRAM 04 04 3 Number of Row Addresses (without BS bits) 12 0C 0C 4 Number of Column Addresses (for 16 SDRAM) 9 09 09 5 Number of DIMM Banks 1 01 01 6 Module Data Width 64 40 40 7 Module Data Width (cont’d) 0 00 00 8 Module Interface Levels LVTTL 01 01 9 SDRAM Cycle Time at CL = 3 7.5/10.0 ns 75 A0 10 SDRAM Access Time from Clock at CL = 3 5.4/6.0 ns 54 60 11 DIMM Config (Error Det/Corr.) none 00 00 12 Refresh Rate/Type Self-Refresh, 15.6 µs 80 80 13 SDRAM Width, Primary x16 10 10 14 Error Checking SDRAM Data Width n/a 00 00 15 Minimum Clock Delay for Back-to-Back Random Column Address tCCD = 1 CLK 01 01 16 Burst Length Supported 1, 2, 4, & 8 0F 0F 17 Number of SDRAM Banks 4 04 04 18 Supported CAS Latencies CL = 2 & 3 06 06 19 CS Latencies CS latency = 0 01 01 20 WE Latencies WL = 0 01 01 21 SDRAM DIMM Module Attributes non buffered/non reg. 00 00 22 SDRAM Device Attributes: General VDD tol. ± 10% 0E Data Book 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 0E 12.99 HYS 64V8301GU SDRAM-Modules SPD-Table (cont’d) Byte# Description SPD Entry Value Hex 4M × 64 4M × 64 -7.5 -8 23 Minimum Clock Cycle Time at CAS Latency = 2 10.0 ns A0 A0 24 Maximum Data Access Time from Clock for CL = 2 6.0 ns 60 60 25 Minimum Clock Cycle Time at CL = 1 not supported FF FF 26 Maximum Data Access Time from Clock at CL = 1 not supported FF FF 27 Minimum Row Precharge Time 20 ns 14 14 28 Minimum Row Active to Row Active Delay 15/16 ns 0F 10 tRRD 29 Minimum RAS to CAS Delay tRCD 20 ns 14 14 30 Minimum RAS Pulse Width tRAS 45 ns 2D 2D 31 Module Bank Density (per bank) 64 MByte 10 10 32 SDRAM Input Setup Time 1.5/2 ns 15 20 33 SDRAM Input Hold Time 0.8/1 ns 08 10 34 SDRAM Data Input Setup Time 1.5/2 ns 15 20 35 SDRAM Data Input Hold Time 0.8/1 ns 08 10 36-61 Superset Information (may be used in future) – FF FF 62 SPD Revision Revision 1.2 12 12 63 Checksum for bytes 0 - 62 – TBD TBD 64-125 Manufacturers Information (optional) (FFH if not used) – – XX 64 64 126 Max. Frequency Specification 127 Details – AF AF 128+ Unused Storage Locations – FF FF Data Book 11 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS 64V8301GU SDRAM-Modules Package Outlines L-DIM-168-32 SDRAM DIMM Module Package 133.35 127.35 3 29.31 4 ± 0.1 4 max. 1 10 3 11 6.35 1.27 40 41 6.35 84 1.27± 0.1 42.18 3.125 91 x 1.27 = 115.57 94 124 125 168 17.78 85 66.68 2 95 3 min. 2.54 min. 0.2 ± 0.15 Detail of Contacts 1 ± 0.05 1.27 Data Book GLD09263 12 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99