ETC HYS64V32300GU-7.5-C2

HYS 64/72V32300GU
SDRAM-Modules
3.3 V 32M × 64/72-Bit, 256MByte SDRAM Modules
168-pin Unbuffered DIMM Modules
• Single + 3.3 V (± 0.3 V) power supply
• 168 Pin unbuffered 8 Byte Dual-In-Line
SDRAM Modules for PC main memory
applications using 256Mbit technology.
• Programmable CAS Latency, Burst Length,
and Wrap Sequence (Sequential &
Interleave)
• PC100-222, PC133-333 and PC133-222
versions
• Auto Refresh (CBR) and Self Refresh
• One bank 32M × 64 and 32M × 72
organisation
• Decoupling capacitors mounted on substrate
• All inputs, outputs are LVTTL compatible
• Optimized for byte-write non-parity or ECC
applications
• Serial Presence Detect with E2PROM
• Fully PC board layout compatible to INTEL’s
Rev. 1.0 module specification
• Uses Infineon 256 Mbit SDRAM components
in 32M × 8 organization and TSOPII-54
packages
• Programmed Latencies:
Product Speed
CL
tRCD
• Gold contact pads, card size:
133.35 mm × 31.75 mm × 3.00 mm
(JEDEC MO-161-BA)
tRP
-7
PC133
2
2
2
-7.5
PC133
3
3
3
-8
PC100
2
2
2
• SDRAM Performance:
-7 / -7.5
-8
PC133
PC100
Unit
fCK
Clock Frequency (max.)
133
100
MHz
tAC
Clock Access Time
5.4
6
ns
Description
The HYS 64V32300GU and HYS 72V32300GU are industry standard 168-pin 8-byte Dual in-line
Memory Modules (DIMMs) which are organized as 32M × 64 and 32M × 72 in 1 memory bank high
speed memory arrays designed with 256M Synchronous DRAMs (SDRAMs) for non-parity and
ECC applications. The DIMMs use -7 speed sorted 32M × 8 SDRAM devices in TSOP54 packages
to meet the PC133-222 requirement, -7.5 components for PC133-333 and -8 components for the
standard PC100 applications. Decoupling capacitors are mounted on the PC board. The PC board
design is according to INTEL’s module specification. The DIMMs have a serial presence detect,
implemented with a serial E2PROM using the 2-pin I2C protocol. The first 128 bytes are utilized by
the DIMM manufacturer and the second 128 bytes are available to the end user. All Infineon 168pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint, with
1.25“ (31.75 mm) height.
INFINEON Technologies
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HYS 64/72V32300GU
SDRAM-Modules
Ordering Information
Type
Code
Package
Descriptions
Module
Height
HYS 64V32300GU-7-D
PC133-222-520 L-DIM-168-33 PC133 32M × 64 1 bank
SDRAM module
1.25“
HYS 72V32300GU-7-D
PC133-222-520 L-DIM-168-33 PC133 32M × 72 1 bank
ECC-SDRAM module
1.25“
HYS 64V32300GU-7.5-C2 PC133-333-520 L-DIM-168-33 PC133 32M × 64 1 bank
SDRAM module
HYS 64V32300GU-7.5-D
1.25“
HYS 72V32300GU-7.5-C2 PC133-333-520 L-DIM-168-33 PC133 32M × 72 1 bank
ECC-SDRAM module
HYS 72V32300GU-7.5-D
1.25“
HYS 64V32300GU-8-C2
PC100-222-620 L-DIM-168-33 PC100 32M × 64 1 bank
SDRAM module
1.25“
HYS 72V32300GU-8-C2
PC100-222-620 L-DIM-168-33 PC100 32M × 72 1 bank
ECC-SDRAM module
1.25“
Note: All part numbers end with a place code designating the die revision. Consult factory for
current revision. Example: HYS 64V32300GU-8-C2, indicating Rev. C2 dies are used for
SDRAM components.
Pin Definitions and Functions
A0 - A12
Address Inputs
CLK0 - CLK3
BA0, BA1
Bank Selects
DQMB0 - DQMB7 Data Mask
CS0, CS2
DQ0 - DQ63 Data Input/Output
Clock Input
Chip Select
CB0 - CB7
Check Bits (x72 organisation only) VDD
RAS
Row Address Strobe
VSS
Ground
Power (+ 3.3 V)
CAS
Column Address Strobe
SCL
Clock for Presence Detect
WE
Read/Write Input
SDA
Serial Data Out for
Presence Detect
CKE0
Clock Enable
N.C./DU
No Connection
Address Format
Part Number
Rows Columns
32M × 64/72 HYS64/72V32300GU 13
INFINEON Technologies
10
2
Bank Select
Refresh Period Interval
2
8k
64 ms
7.8 µ s
9.01
HYS 64/72V32300GU
SDRAM-Modules
Pin Configuration
PIN# Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
N.C. (CB0)
N.C. (CB1)
VSS
N.C.
N.C.
VDD
WE
DQMB0
DQMB1
CS0
DU
VSS
A0
A2
A4
A6
A8
A10
BA1
VDD
VDD
CLK0
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
VSS
DU
CS2
DQMB2
DQMB3
DU
VDD
N.C.
N.C.
N.C. (CB2)
N.C. (CB3)
VSS
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
N.C.
DU
N.C.
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
CLK2
N.C.
WP
SDA
SCL
VDD
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
N.C. (CB4)
N.C. (CB5)
VSS
N.C.
N.C.
VDD
CAS
DQMB4
DQMB5
N.C.
RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VDD
CLK1
A12
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
VSS
CKE0
N.C.
DQMB6
DQMB7
N.C.
VDD
N.C.
N.C.
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
VDD
DQ52
N.C.
DU
N.C.
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
CLK3
N.C.
SA0
SA1
SA2
VDD
Note: Pin names in parantheses are for the x72 ECC versions; example: Pin 106 = (CB5)
INFINEON Technologies
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HYS 64/72V32300GU
SDRAM-Modules
WE
CS0
DQMB0
DQ(7:0)
CS
WE
DQM
DQ0-DQ7
D0
DQMB4
DQ(39:32)
CS
WE
DQM
DQ0-DQ7
D4
DQMB1
DQ(15:8)
CS
WE
DQM
DQ0-DQ7
D1
DQMB5
DQ(47:40)
CS
WE
DQM
DQ0-DQ7
D5
CS
WE
DQM
DQ0-DQ7
D8
CB(7:0)
CS2
DQMB2
DQ(23:16)
CS
WE
DQM
DQ0-DQ7
D2
DQMB6
DQ(55:48)
CS
WE
DQM
DQ0-DQ7
D6
DQMB3
DQ(31:24)
CS
WE
DQM
DQ0-DQ7
D3
DQMB7
DQ(63:56)
CS
WE
DQM
DQ0-DQ7
D7
A0-A12, BA0, BA1
VCC
VSS
2
E PROM (256 word x 8 Bit)
D0-D7, (D8)
RAS
D0-D7, (D8)
CAS
D0-D7, (D8)
SA0
SA1
SA2
SCL
SA0
SA1
SA2
SCL
D0-D7, (D8)
C0-C15, (C16, C17)
D0-D7, (D8)
47 k Ω
Clock Wiring
16 M x 64
CKE0
SDA
WP
D0-D7, (D8)
CLK0
CLK1
CLK2
CLK3
Note: D8 is only used in the x72 ECC version and
all resistor values are 10 Ohm except
otherwise noted.
4 SDRAM + 3.3 pF
Termination
4 SDRAM + 3.3 pF
Termination
16 M x 72
5 SDRAM
Termination
4 SDRAM + 3.3 pF
Termination
BL013
Block Diagram: 32M x 64/72 One Bank SDRAM DIMM Modules
INFINEON Technologies
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HYS 64/72V32300GU
SDRAM-Modules
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
min.
max.
4.6
Unit
Input / Output voltage relative to VSS
VIN, VOUT
– 1.0
V
Power supply voltage on VDD
VDD
– 1.0
4.6
V
Storage temperature range
T STG
-55
+150
o
Power dissipation per SDRAM component
PD
–
1
W
Data out current (short circuit)
IOS
–
50
mA
C
Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended operation conditions.
Exposure to higher than recommended voltage for extended periods of time affect device reliability
DC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V
Parameter
Symbol
Limit Values
min.
Unit
max.
Input High Voltage
VIH
2.0
VDD + 0.3
V
Input Low Voltage
VIL
– 0.5
0.8
V
Output High Voltage (I OUT = – 4.0 mA)
VOH
2.4
–
V
Output Low Voltage (IOUT = 4.0 mA)
VOL
–
0.4
V
Input Leakage Current, any input
(0 V < VIN < 3.6 V, all other inputs = 0 V)
II(L)
– 40
40
µA
Output Leakage Current
(DQ is disabled, 0 V < V OUT < V DD)
IO(L)
– 40
40
µA
Limit Values
Unit
Capacitance
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
max.
32M x 64
max.
32M x 72
CI1
65
72
pF
Input Capacitance (CS0 - CS3)
CI2
32
40
pF
Input Capacitance (CLK0 - CLK3)
CICL
38
40
pF
Input Capacitance (CKE0)
CI3
65
72
pF
Input Capacitance (DQMB0 - DQMB7)
CI4
13
16
pF
Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7) C IO
10
10
pF
Input Capacitance
(A0 to A11, BA0, BA1, RAS, CAS, WE)
Input Capacitance (SCL, SA0-2)
CSC
8
8
pF
Input/Output Capacitance
CSD
8
8
pF
INFINEON Technologies
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HYS 64/72V32300GU
SDRAM-Modules
Operating Currents per SDRAM Component
TA = 0 to 70 oC, VDD = 3.3 V ± 0.3 V
Parameter
Operating current
1)
Test
Condition
Symbol
-7.5
-8
Unit Note
–
ICC1
230
170
mA
2)
tCK = min.
ICC2P
2
2
mA
2)
tCK = min.
ICC2N
40
30
mA
2)
CKE ≥ VIH(MIN.) ICC3N
50
45
mA
2)
CKE ≤ VIL(MAX.) ICC3P
10
10
mA
2)
max.
tRC = tRCMIN., tCK = tCKMIN.
Outputs open, Burst Length = 4, CL = 3
All banks operated in random access,
all banks operated in ping-pong manner
to maximize gapless data access
Precharge stand-by current
in Power Down Mode
CS = V IH(MIN.), CKE ≤ VIL(MAX.)
Precharge Stand-by Current
in Non-Power Down Mode
CS = V IH (MIN.), CKE ≥ V IH(MIN.)
No operating current
tCK = min., CS = VIH(MIN.),
active state (max. 4 banks)
Burst operating current
tCK = min.,
Read command cycling
–
ICC4
150
100
mA
2), 3)
Auto refresh current
tCK = min.,
Auto Refresh command cycling
–
ICC5
240
220
mA
2)
ICC6
3
3
mA
2)
Self refresh current
Self Refresh Mode, CKE = 0.2 V
1. All values are shown per one SDRAM component.
2. These parameters depend on the cycle rate. These values are measured at 133 MHz operation frequency
for -7 & -7.5 and at 100 MHz for -8 modules.
Input signals are changed once during tCK , excepts for ICC6 and for stand-by currents when tCK = infinity.
3. These parameters are measured with continuous data stream during read access and all DQ toggling.
CL = 3 and BL = 4 are assumed and the data-out current is excluded.
INFINEON Technologies
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HYS 64/72V32300GU
SDRAM-Modules
AC Characteristics 1), 2)
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values
-7
-7.5
PC133-222 PC133-333
Unit Note
-8
PC100-222
min. max min. max. min. max.
Clock
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
tCK
System Frequency
CAS Latency = 3
CAS Latency = 2
fCK
Clock Access Time
CAS Latency = 3
CAS Latency = 2
tAC
Clock High Pulse Width
Clock Low Pulse Width
–
7.5
7.5
–
–
7.5
10
–
–
10
10
–
–
ns
ns
–
–
133
133
–
–
133
100
–
–
100
100
MHz
MHz
–
–
5.4
5.4
–
–
5.4
6
–
–
6
6
ns
ns
tCH
2.5
–
2.5
–
3
–
ns
4)
tCL
2.5
–
2.5
–
3
–
ns
4)
Input Setup Time
tCS
1.5
–
1.5
–
2
–
ns
5)
Input Hold Time
tCH
0.8
–
0.8
–
1
–
ns
5)
Power Down Mode Entry Time
tSB
–
1
–
1
–
1
CLK
6)
Power Down Mode Exit Setup Time
tPDE
1
–
1
–
1
–
CLK
7)
Mode Register Setup Time
tRSC
2
–
2
–
2
–
CLK
Transition Time (rise and fall)
tT
1
–
1
–
1
–
ns
–
RAS to CAS Delay
tRCD
15
–
20
–
20
–
ns
–
Precharge Time
tRP
15
–
20
–
20
–
ns
–
Active Command Period
tRAS
42
–
45
100k 50
100k ns
–
Cycle Time
tRC
60
–
67.5
–
70
–
ns
–
Bank to Bank Delay Time
tRRD
14
–
15
–
16
–
ns
–
1
–
1
–
1
–
CLK –
–
3), 4)
Setup and Hold Times
Common Parameters
CAS to CAS Delay Time (same bank) tCCD
INFINEON Technologies
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9.01
HYS 64/72V32300GU
SDRAM-Modules
AC Characteristics (cont’d) 1), 2)
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values
-7
-7.5
PC133-222 PC133-333
Unit Note
-8
PC100-222
min. max min. max. min. max.
Refresh Cycle
Refresh Period (8192 cycles)
tREF
64
–
–
64
–
64
ms
6)
Self Refresh Exit Time
tSREX
–
1
1
–
1
–
CLK
8)
Data Out Hold Time
tOH
3
–
3
–
3
–
ns
2)
Data Out to Low Impedance
tLZ
0
–
0
–
0
–
ns
–
Data Out to High Impedance
tHZ
3
7
3
7
3
8
ns
9)
DQM Data Out Disable Latency
tDQZ
–
2
–
2
–
2
CLK –
Data Input to Precharge
(write recovery)
tWR
2
–
2
–
2
–
CLK –
DQM Write Mask Latency
tDQW
0
–
0
–
0
–
CLK –
Read Cycle
Write Cycle
INFINEON Technologies
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9.01
HYS 64/72V32300GU
SDRAM-Modules
Notes
1. All AC characteristics are shown for the SDRAM components.
An initial pause of 100 µ s is required after power-up. Then a Precharge All Banks command must
be given followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation
can begin.
2. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between V IH and VIL. All AC measurements assume
tT = 1 ns with the AC output load circuit shown in Figure below. Specified tAC and tOH parameters
are measured with a 50 pF only, without any resistive termination and with a input signal of 1V/
ns edge rate between 0.8 V and 2.0 V.
3. If clock rising time is longer than 1 ns, a time (tT/2 − 0.5) ns must be added to this parameter.
4. Rated at 1.4 V.
5. If tT is longer than 1 ns, a time (tT − 1) ns must be added to this parameter.
6. Whenever the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
commands must be given to “wake-up” the device.
7. Timing is a asynchronous. If setup time is not met by rising edge of the clock then the CKE signal
is assumed latched on the next cycle.
8. Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied
after the Self Refresh Exit command is registered.
9. This is referenced to the time at which the output achieved the open circuit condition, not to
output voltage levels.
t CH
2.4 V
0.4 V
CLOCK
t CL
t SETUP
tT
t HOLD
1.4 V
INPUT
t AC
t LZ
t AC
I/O
t OH
50 pF
OUTPUT
1.4 V
Measurement conditions for
tAC and tOH
t HZ
SPT03404
Serial Presence Detect
A serial presence detect storage device - E 2PROM - is assembled onto the module. Information
about the module configuration, speed, etc. is written into the E2PROM device during module
production using a serial presence detect protocol (I2C synchronous 2-wire bus).
INFINEON Technologies
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HYS 64/72V32300GU
SDRAM-Modules
SPD-Table for 32M x 64 (256MByte non-ECC) Modules HYS64V32300GU
Byte# Description
SPD Entry Value
-7
0
1
2
3
4
5
6
7
8
9
10
11
12
Number of SPD Bytes
Total Bytes in Serial PD
Memory Type
Number of Row Addresses
Number of Column Addresses
Number of DIMM Banks
Module Data Width
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL = 3
SDRAM Access Time at CL = 3
DIMM Config
Refresh Rate/Type
13
14
15
SDRAM Width, Primary
Error Checking SDRAM Data Width
Minimum Clock Delay for Back-toBack Random Column Address
Burst Length Supported
Number of SDRAM Banks
Supported CAS Latencies
CS Latencies
WE Latencies
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
SDRAM Cycle Time at CL = 2
SDRAM Access Time at CL = 2
SDRAM Cycle Time at CL = 1
SDRAM Access Time at CL = 1
Minimum Row Precharge Time
Min. Row to Row Active Delay tRRD
Minimum RAS to CAS Delay tRCD
Minimum RAS Pulse Width tRAS
Module Bank Density (per bank)
SDRAM Input Setup Time
SDRAM Input Hold Time
SDRAM Data Input Hold Time
SDRAM Data Input Setup Time
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
INFINEON Technologies
128
256
SDRAM
13
10
1
64
0
LVTTL
7.5 / 10 ns
5.4 / 6 ns
non-ECC
Self-Refresh,
7.8 µ s
x8
na
tCCD = 1 CLK
1, 2, 4 & 8
4
CL = 2 & 3
CS latency = 0
Write latency = 0
unbuffered
VDD tol +/– 10%
7.5 / 10.0 ns
5.4 / 6.0 ns
not supported
not supported
15 / 20 ns
14 / 15 / 16 ns
15 / 20 ns
42 / 45 / 50 ns
256 MByte
1.5 / 2.0 ns
0.8 / 1.0 ns
1.5 / 2.0 ns
0.8 / 1.0 ns
10
75
54
Hex
32M x 64
-7.5
80
08
04
0D
0A
01
40
00
01
75
54
00
82
-8
A0
60
08
00
01
75
54
00
00
0F
0E
0F
2A
15
08
15
08
0F
04
06
01
01
00
0E
A0
60
FF
FF
14
0F
14
2D
40
15
08
15
08
A0
60
FF
FF
14
10
14
32
20
10
20
10
9.01
HYS 64/72V32300GU
SDRAM-Modules
Byte# Description
36-61
62
63
64
65-71
72
73-90
91-92
93-94
95-98
99-125
126
127
128+
SPD Entry Value
Superset Information
SPD Revision
Checksum for Bytes 0 - 62
Manufacturers JEDEC ID Code
Manufacturer
Module Assembly Locaction
Module Part Number
Module Revision Code
Module Manufacturing Code
Module Serial Number
Superset Information
Frequency Specification
100 MHz Support Details
Unused Storage Locations
INFINEON Technologies
–
Revision 1.2
–
–
–
–
11
Hex
32M x 64
-7
-7.5
-8
FF
FF
FF
12
12
12
F3
36
99
C1
INFINEO(N)
64
AF
64
AF
FF
64
AF
9.01
HYS 64/72V32300GU
SDRAM-Modules
SPD-Table for 32M x 72 (256MByte ECC) Modules HYS72V32300GU
Byte# Description
SPD Entry Value
-7
0
1
2
3
4
5
6
7
8
9
10
11
12
Number of SPD Bytes
Total Bytes in Serial PD
Memory Type
Number of Row Addresses
Number of Column Addresses
Number of DIMM Banks
Module Data Width
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL = 3
SDRAM Access Time at CL = 3
DIMM Config
Refresh Rate/Type
13
14
15
SDRAM Width, Primary
Error Checking SDRAM Data Width
Minimum Clock Delay for Back-toBack Random Column Address
Burst Length Supported
Number of SDRAM Banks
Supported CAS Latencies
CS Latencies
WE Latencies
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
SDRAM Cycle Time at CL = 2
SDRAM Access Time at CL = 2
SDRAM Cycle Time at CL = 1
SDRAM Access Time at CL = 1
Minimum Row Precharge Time
Min. Row to Row Active Delay tRRD
Minimum RAS to CAS Delay tRCD
Minimum RAS Pulse Width tRAS
Module Bank Density (per bank)
SDRAM Input Setup Time
SDRAM Input Hold Time
SDRAM Data Input Hold Time
SDRAM Data Input Setup Time
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
INFINEON Technologies
128
256
SDRAM
13
10
1
72
0
LVTTL
7.5 / 10 ns
5.4 / 6 ns
ECC
Self-Refresh,
7.8 µ s
x8
x8
tCCD = 1 CLK
1, 2, 4 & 8
4
CL = 2 & 3
CS latency = 0
Write latency = 0
unbuffered
VDD tol +/– 10%
7.5 / 10.0 ns
5.4 / 6.0 ns
not supported
not supported
15 / 20 ns
14 / 15 / 16 ns
15 / 20 ns
42 / 45 / 50 ns
256 MByte
1.5 / 2.0 ns
0.8 / 1.0 ns
1.5 / 2.0 ns
0.8 / 1.0 ns
12
75
54
Hex
32M x 72
-7.5
80
08
04
0D
0A
01
48
00
01
75
54
02
82
-8
A0
60
08
08
01
75
54
00
00
0F
0E
0F
2A
15
08
15
08
0F
04
06
01
01
00
0E
A0
60
FF
FF
14
0F
14
2D
40
15
08
15
08
A0
60
FF
FF
14
10
14
32
20
10
20
10
9.01
HYS 64/72V32300GU
SDRAM-Modules
Byte# Description
36-61
62
63
64
65-71
72
73-90
91-92
93-94
95-98
99-125
126
127
128+
SPD Entry Value
Superset Information
SPD Revision
Checksum for Bytes 0 - 62
Manufacturers JEDEC ID Code
Manufacturer
Module Assembly Locaction
Module Part Number
Module Revision Code
Module Manufacturing Code
Module Serial Number
Superset Information
Frequency Specification
100 MHz Support Details
Unused Storage Locations
INFINEON Technologies
–
Revision 1.2
–
–
–
–
13
Hex
32M x 72
-7
-7.5
-8
FF
FF
FF
12
12
12
05
48
AB
C1
INFINEO(N)
64
AF
64
AF
FF
64
AF
9.01
HYS 64/72V32300GU
SDRAM-Modules
Package Outlines
L-DIM-168-33 (JEDEC MO-161-BA)
SDRAM DIMM Module Package
133.35 +- 0.15
3 max.
4
+
- 0.13
127.35
31.75
*)
3
1
10
3
11
6.35
1.27
40
41
6.35
84
1.27 +- 0.1
42.18
85
94
2
95
124
125
168
17.78
3.125
91 x 1.27 = 115.57
3 min.
3
*) on ECC modules only
2.55
0.25
Detail of Contacts
1
1.27
L-DIM-168-33
Note: All tolerances according to JEDEC standard
Dimensions in mm
INFINEON Technologies
14
9.01