ETC HYS72V128320GR-8

HYS 72Vx3xxGR-8
PC100 Registered SDRAM-Modules
3.3 V 168-pin Registered SDRAM Modules
256 MB, 512 MB & 1 GB Densities
• Programmable CAS Latency, Burst Length,
and Wrap Sequence (Sequential &
Interleave)
• 168-pin JEDEC Standard, Registered 8 Byte
Dual-In-Line SDRAM Modules for Server
main memory applications using memory
frequencies up to 100MHz
• Auto Refresh (CBR) and Self Refresh
• One bank 32M × 72 and 64M × 72
organization, two bank 128M × 72
organization
• All inputs and outputs are LVTTL compatible
• Serial Presence Detect with E2PROM
• Optimized for ECC applications with very low
input capacitances
• Utilizes SDRAMs in TSOPII-54 packages
with registers and PLL.The two bank module
uses stacked TSOP54 packages.
• Programmed Latencies:
CL
tRCD
tRP
2
2
2
• Card Size: 133.35 mm × 43.18 mm with
Gold contact pads (JEDEC MO-161)
• These Registered DIMM modules support
operation in “registered” and “buffered” mode
• Single + 3.3 V (± 0.3 V) power supply
• Performance:
-8
Unit
Operation mode
registered
buffered
fCK
Clock Frequency (max.)
100
66
MHz
tCK
Clock Cycle Time (min.)
10
15
ns
tAC
Clock Access Time (max.)
6
6
ns
The HYS 72Vx3xxGR-8 family are industry standard 168-pin 8-byte Dual in-line Memory Modules
(DIMMs) which are organized as 32M × 72, 64M × 72 & 128M × 72 high speed memory arrays
designed with Synchronous DRAMs (SDRAMs) for ECC applications. All control and address
signals are registered on-DIMM and the design incorporates a PLL circuit for the Clock inputs. Use
of an on-board register reduces capacitive loading on the input signals but are delayed by one cycle
in arriving at the SDRAM devices. Decoupling capacitors are mounted on the PC board. The DIMMs
use a serial presence detects scheme implemented via a serial E2PROM using the 2-pin I2C
protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are
available to the end user. All Infineon 168-pin DIMMs provide a high performance, flexible 8-byte
interface in a 133.35 mm long footprint. The PCB layout is based on latest industry PC133/PC100
standard gerber files. Besides standard PC100 applications, this module family is intended for
applications where Registered DIMM modules are used in “buffered mode” at a 67 MHz memory
bus speed.
INFINEON Technologies
1
9.01
HYS 72Vx3xxGR-8
PC100 Registered SDRAM-Modules
Ordering Information
Type
Compliance
Code
Description
SDRAM Components
HYS 72V32301GR-8
PC100-222-622R one bank 256 MB
Reg. DIMM
128 MBit (x4)
HYB39S128400CT-7.5
with trp<= 15ns
HYS 72V64300GR-8
PC100-222-622R one bank 512 MB
Reg. DIMM
256 MBit (x4)
HYB39S256400CT-7.5
with trp<= 15ns
HYS 72V128320GR-8
PC100-222-622R two bank 1 GByte
Reg. DIMM
256 MBit (x4 stacked)
HYB39S256400CT-7.5
with trp<= 15ns
Note: All part numbers end with a place code (not shown), designating the die revision. Consult
factory for current revisions. Example: HYS 72V64300GR-8-C2, indicating Rev. C2 dies are
used for SDRAM components.
INFINEON Technologies
2
9.01
HYS 72Vx3xxGR-8
PC100 Registered SDRAM-Modules
Pin Definitions and Functions
A0 - A11, A12 Address Inputs
DQMB0 - DQMB7 Data Mask
BA0, BA1
Bank Selects
CS0 - CS3
Chip Select
DQ0 - DQ63
Data Input/Output
REGE *)
Register Enable
“H” or N.C = registered mode
“L” = buffered mode
CB0 - CB7
Check Bits (x72 organization only) V DD
RAS
Row Address Strobe
VSS
Ground
CAS
Column Address Strobe
SCL
Clock for Presence Detect
WE
Read/Write Input
SDA
Serial Data Out
CKE0
Clock Enable
N.C.
No Connection
–
–
CLK0 - CLK3 Clock Input
Power (+ 3.3 V)
*) note : both operation modes are supported by this module family
Address Format
Density Organization Memory SDRAMs
Banks
# of
# of row/bank/ Refresh Period Interval
SDRAMs columns bits
256 MB 32M × 72
1
32M × 4
18
12/2/11
4k
64 ms 15.6 µs
512 MB 64M × 72
1
64M × 4
18
13/2/11
8k
64 ms 7.8 µs
2
64M × 4
36
13/2/11
8k
64 ms 7.8 µs
1 GB
128M × 72
Pin Configuration
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
1
PIN# Symbol
VSS
43
VSS
85
VSS
127
VSS
2
DQ0
44
DU
86
DQ32
128
CKE0
3
DQ1
45
CS2
87
DQ33
129
CS3
4
DQ2
46
DQMB2
88
DQ34
130
DQMB6
5
DQ3
47
DQMB3
89
DQ35
131
DQMB7
6
VDD
48
DU
90
VDD
132
N.C.
7
DQ4
49
VDD
91
DQ36
133
VDD
8
DQ5
50
N.C.
92
DQ37
134
N.C.
9
DQ6
51
N.C.
93
DQ38
135
N.C.
10
DQ7
52
CB2
94
DQ39
136
CB6
11
DQ8
53
CB3
95
DQ40
137
CB7
12
VSS
54
VSS
96
VSS
138
VSS
13
DQ9
55
DQ16
97
DQ41
139
DQ48
INFINEON Technologies
3
9.01
HYS 72Vx3xxGR-8
PC100 Registered SDRAM-Modules
Pin Configuration (cont’d)
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
14
PIN# Symbol
DQ10
56
DQ17
98
DQ42
140
DQ49
15
DQ11
57
DQ18
99
DQ43
141
DQ50
16
DQ12
58
DQ19
100
DQ44
142
DQ51
17
DQ13
59
VDD
101
DQ45
143
VDD
18
VDD
60
DQ20
102
VDD
144
DQ52
19
DQ14
61
N.C.
103
DQ46
145
N.C.
20
DQ15
62
DU
104
DQ47
146
DU
21
CB0
63
N.C.
105
CB4
147
REGE
22
CB1
64
VSS
106
CB5
148
VSS
23
VSS
65
DQ21
107
VSS
149
DQ53
24
N.C.
66
DQ22
108
N.C.
150
DQ54
25
N.C.
67
DQ23
109
N.C.
151
DQ55
26
VDD
68
VSS
110
VDD
152
VSS
27
WE
69
DQ24
111
CAS
153
DQ56
28
DQMB0
70
DQ25
112
DQMB4
154
DQ57
29
DQMB1
71
DQ26
113
DQMB5
155
DQ58
30
CS0
72
DQ27
114
CS1
156
DQ59
31
DU
73
VDD
115
RAS
157
VDD
32
VSS
74
DQ28
116
VSS
158
DQ60
33
A0
75
DQ29
117
A1
159
DQ61
34
A2
76
DQ30
118
A3
160
DQ62
35
A4
77
DQ31
119
A5
161
DQ63
36
A6
78
VSS
120
A7
162
VSS
37
A8
79
CLK2
121
A9
163
CLK3
38
A10 (AP)
80
N.C.
122
BA0
164
N.C.
39
BA1
81
WP
123
A11
165
SA0
40
VDD
82
SDA
124
VDD
166
SA1
41
VDD
83
SCL
125
CLK1
167
SA2
42
CLK0
84
VDD
126
A12
168
VDD
INFINEON Technologies
4
9.01
HYS 72Vx3xxGR-8
PC100 Registered SDRAM-Modules
RCS0
RDQMB0
RDQMB4
DQ0-DQ3
DQM
CS
DQ0-DQ3
D0
DQ32-DQ35
DQM
CS
DQ0-DQ3
D8
DQ4-DQ7
DQM
CS
DQ0-DQ3
D1
DQ36-DQ39
DQM
CS
DQ0-DQ3
D9
RDQMB1
RDQMB5
DQ8-DQ11
DQM
CS
DQ0-DQ3
D2
DQ40-DQ43
DQM
CS
DQ0-DQ3
D10
DQ12-DQ15
DQM
CS
DQ0-DQ3
D3
DQ44-DQ47
DQM
CS
DQ0-DQ3
D11
CB0-CB3
DQM
CS
DQ0-DQ3
D16
CB4-CB7
DQM
CS
DQ0-DQ3
D17
RCS2
RDQMB2
RDQMB6
DQ16-DQ19
CS
DQM
DQ0-DQ3
D4
DQ48-DQ51
CS
DQM
DQ0-DQ3
D12
DQ20-DQ23
DQM
CS
DQ0-DQ3
D5
DQ52-DQ55
DQM
CS
DQ0-DQ3
D13
RDQMB3
RDQMB7
DQ24-DQ27
DQM
CS
DQ0-DQ3
D6
DQ56-DQ59
DQM
CS
DQ0-DQ3
D14
DQ28-DQ31
CS
DQM
DQ0-DQ3
D7
DQ60-DQ63
CS
DQM
DQ0-DQ3
D15
CLK0
PLL
CS0/CS2
DQMB0-7
BA0, BA1
A0-A11, A12* )
RAS
CAS
CKE0
WE
REGE
10 k Ω
V CC
Register
12 pF
SDRAMs D0-D17
CLK1, CLK2, CLK3
RCS0/RCS2
RDQMB0-7
RBA0, RBA1
RA0-RA11
RRAS
RCAS
RCKE0
RWE
12 pF
SDRAMs D0-D17
SDRAMs D0-D17
SDRAMs D0-D17
SDRAMs D0-D17
SDRAMs D0-D17
SDRAMs D0-D17
*) A12 is only used for
128 M x 72 organisation
SA0
SA1
SA2
SCL
E 2PROM
(256 word x 8 Bit)
SA0
SA1 SDA
WP
SA2
SCL
V CC
47 k Ω
D0-D17, Reg., DLL
C
V SS
D0-D17, Reg., DLL
1)
DQ wirding may differ from that decribed
in this drawing; however DQ/DQB relationship
must be maintained as shown
2) All resistors are 10 Ω unless otherwise noted
SPB04131
Block Diagram: One Bank 32M x 72 & 64M x 72 SDRAM DIMM Modules
HYS72V32301 and HYS 72V64300GR Using x4 Organized SDRAMs
INFINEON Technologies
5
9.01
HYS 72Vx3xxGR-8
PC100 Registered SDRAM-Modules
RCS0
RCS1
RDQMB0
RDQMB4
DQ0-DQ3
DQM
CS
DQ0-DQ3
D0
DQM
CS
DQ0-DQ3
D0
DQ32-DQ35
DQM
CS
DQ0-DQ3
D8
DQM
CS
DQ0-DQ3
D8
DQ4-DQ7
CS
DQM
DQ0-DQ3
D1
CS
DQM
DQ0-DQ3
D1
DQ36-DQ39
CS
DQM
DQ0-DQ3
D9
CS
DQM
DQ0-DQ3
D9
DQ8-DQ11
CS
DQM
DQ0-DQ3
D2
CS
DQM
DQ0-DQ3
D2
DQ40-DQ43
CS
DQM
DQ0-DQ3
D10
CS
DQM
DQ0-DQ3
D10
DQ12-DQ15
DQM
CS
DQ0-DQ3
D3
DQM
CS
DQ0-DQ3
D3
DQ44-DQ47
DQM
CS
DQ0-DQ3
D11
DQM
CS
DQ0-DQ3
D11
CB0-CB3
CS
DQM
DQ0-DQ3
D16
CS
DQM
DQ0-DQ3
D16
CB4-CB7
CS
DQM
DQ0-DQ3
D17
CS
DQM
DQ0-DQ3
D17
DQ16-DQ19
DQM
CS
DQ0-DQ3
D4
DQM
CS
DQ0-DQ3
D4
DQ48-DQ51
DQM
CS
DQ0-DQ3
D12
DQM
CS
DQ0-DQ3
D12
DQ20-DQ23
DQM
CS
DQ0-DQ3
D5
DQM
CS
DQ0-DQ3
D5
DQ52-DQ55
DQM
CS
DQ0-DQ3
D13
DQM
CS
DQ0-DQ3
D13
DQ24-DQ27
DQM
CS
DQ0-DQ3
D6
DQM
CS
DQ0-DQ3
D6
DQ56-DQ59
DQM
CS
DQ0-DQ3
D14
DQM
CS
DQ0-DQ3
D14
DQ28-DQ31
DQM
CS
DQ0-DQ3
D7
DQM
CS
DQ0-DQ3
D7
DQ61-DQ63
DQM
CS
DQ0-DQ3
D15
DQM
CS
DQ0-DQ3
D15
RDQMB1
RDQMB5
RCS2
RCS3
RDQMB2
RDQMB6
RDQMB3
CLK0
RDQMB7
PLL
Stacked SDRAMs D0-D17
CLK1, CLK2, CLK3
CS0-CS3
DQMB0-7
BA0, BA1
A0-A11, A12* )
RAS
CAS
CKE0
WE
REGE
10 k Ω
V CC
Register
12 pF
RCS0-RCS3
RDQMB0-7
RBA0, RBA1
RA0-RA11
RRAS
RCAS
RCKE0
RWE
*)
12 pF
Stacked SDRAMs D0-D17
Stacked SDRAMs D0-D17
Stacked SDRAMs D0-D17
Stacked SDRAMs D0-D17
Stacked SDRAMs D0-D17
Stacked SDRAMs D0-D17
E 2PROM
(256 word x 8 Bit)
SA0
SA0
SA1
SA1 SDA
SA2
SA2
WP
SCL
SCL
V CC
47 k Ω
D0-D17, Reg. DLL
C
V SS
D0-D17, Reg. DLL
1.)
DQ wirding may differ from that decribed
in this drawing; however DQ/DQB relationship
must be maintained as shown
2.) All resistors are 10 Ω unless otherwise noted
A12 is only used for
128 M x 72 organisation
SPB04132
Block Diagram: Two Bank 128M x 72 SDRAM DIMM Modules
HYS 72V128320GR Using Stacked x4 Organized SDRAMs
INFINEON Technologies
6
9.01
HYS 72Vx3xxGR-8
PC100 Registered SDRAM-Modules
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
min.
max.
4.6
V
Input / Output voltage relative to VSS
VIN, VOUT
– 1.0
Power supply voltage on V DD to VSS
VDD
– 1.0
4.6
V
Storage temperature range
TSTG
-55
+150
o
Power dissipation (per SDRAM component)
PD
–
1
W
Data out current (short circuit)
IOS
–
50
mA
C
Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended operation conditions.
Exposure to higher than recommended voltage for extended periods of time affect device reliability
DC Characteristics
TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V
Parameter
Symbol
Limit Values
min.
Unit
max.
Input High Voltage
VIH
2.0
VDD + 0.3
V
Input Low Voltage
VIL
– 0.5
0.8
V
Output High Voltage (I OUT = – 4.0 mA)
VOH
2.4
–
V
Output Low Voltage (IOUT = 4.0 mA)
VOL
–
0.4
V
Input Leakage Current, any input
(0 V < VIN < 3.6 V, all other inputs = 0 V)
II(L)
– 10
10
µA
Output Leakage Current
IO(L)
– 10
10
µA
(DQ is disabled, 0 V < VOUT < VDD)
Capacitance
TA = 0 to 70 °C 1); VDD = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
Limit Values
Unit
One Bank Two Bank
Modules Modules
Input Capacitance
(all inputs except CLK and CKE)
CIN
10
20
pF
Input Capacitance (CLK)
CCLK
30
30
pF
Input Capacitance (CKE)
CCKE
17
30
pF
Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7)
CIO
10
17
pF
Input Capacitance (SCL, SA0 - 2)
CSC
8
8
pF
Input/Output Capacitance (SDA)
CSD
8
8
pF
INFINEON Technologies
7
9.01
HYS 72Vx3xxGR-8
PC100 Registered SDRAM-Modules
Operating Currents per SDRAM component
TA = 0 to 70 °C 1), VDD = 3.3 V ± 0.3 V
(Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
Test
Condition
Symbol
–
ICC1
128Mb
256Mb
max.
max.
150
210
Unit
Note
2)
tRC = tRC(MIN.), tCK = tCK(MIN.)
mA
Outputs open, Burst
Length = 4, CL = 3. All banks
operated in random access,
all banks operated in pingpong manner to maximize
gapless data access
Precharge stand-by current
in Power Down Mode
CS = V IH(MIN.), CKE ≤ VIL(MAX.)
tCK = min. ICC2P
2
2
mA
2)
No operating current
CKE ≥
ICC3N
45
45
mA
2)
ICC3P
10
10
mA
2)
–
ICC4
90
120
mA
2), 3)
–
Auto refresh current
tCK = min.,
Auto Refresh command cycling
ICC5
210
240
mA
2)
Self refresh current
Self Refresh Mode,
CKE = 0.2 V
ICC6
1.5
2.5
mA
2)
VIH(MIN.)
tCK = min., CS = VIH(MIN.),
active state (max. 4 banks)
Burst operating current
tCK = min.,
Read command cycling
INFINEON Technologies
CKE ≤
VIL(MAX.)
–
8
9.01
HYS 72Vx3xxGR-8
PC100 Registered SDRAM-Modules
AC Characteristics (SDRAM Device Specification) 4), 5)
TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values Unit
Note
min.
max.
10
10
–
–
ns
ns
–
–
100
100
MHz
MHz
8)
–
–
6
6
ns
ns
–
Clock and Access Times
8)
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
tCK
Clock Frequency
CAS Latency = 3
CAS Latency = 2
fCK
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
tAC
Clock High Pulse Width
tCH
3
–
ns
–
Clock Low Pulse Width
tCL
3
–
ns
–
Transition Time
tT
0.5
10
ns
–
Input Setup Time
tIS
2
–
ns
–
Input Hold Time
tIH
1
–
ns
–
Power Down Mode Entry Time
tSB
–
1
CLK
–
Power Down Mode Exit Setup Time
tPDE
1
–
CLK
–
Mode Register Set-up Time
tRSC
2
–
CLK
–
Transition Time
tT
0.5
10
ns
–
Row to Column Delay Time
tRCD
20
–
ns
–
Row Precharge Time
tRP
15
–
ns
8)
Row Active Time
tRAS
50
100k
ns
–
Row Cycle Time
tRC
70
–
ns
–
Activate (a) to Activate (b) Command Period
tRRD
2
–
CLK
–
CAS(a) to CAS(b) Command Period
tCCD
1
–
CLK
–
Setup and Hold Parameters
Common Parameters
INFINEON Technologies
9
9.01
HYS 72Vx3xxGR-8
PC100 Registered SDRAM-Modules
AC Characteristics (SDRAM Device Specification) (cont’d)
4), 5)
TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values Unit
min.
max.
Note
Refresh Cycle
µs
–
7.8
µs
–
–
CLK
6)
3
–
ns
–
0
–
ns
7)
tHZ
3
8
ns
7)
tDQZ
–
2
CLK
–
Data Input to Precharge
(write recovery)
tWR
2
–
CLK
8)
DQM Write Mask Latency
tDQW
0
–
CLK
–
Refresh Period (128 Mb components)
tREF
–
15.6
Refresh Period (256 Mb components)
tREF
–
Self Refresh Exit Time
tSREX
1
Data Out Hold Time
tOH
Data Out to Low Impedance
tLZ
Data Out to High Impedance
DQM Data Out Disable Latency
Read Cycle
Write Cycle
INFINEON Technologies
10
9.01
HYS 72Vx3xxGR-8
PC100 Registered SDRAM-Modules
Notes
1. The registered DIMM modules are designed to operate under system operating conditions between 0-55 deg
C ambient, 500 MB/sec sustained bandwidth and 0 LFM airflow. Operating at higher ambient temperatures
needs sufficient air flow to limit the case temperature of the SDRAM components do not exceed 85oC.
Maximum operation frequency of this module family is 100MHz when operating in “registered mode” and 67
MHz when in “buffered mode”
2. These parameters depend on the cycle rate. All values are measured at 100MHz operation frequency. Input
signals are changed once during tck excepts for Icc6 and for standby currents when tck = infinity.
3. These parameters are measured with continous data stream during read access and all DQ toggling. CL=3 and
BL=4 is assumed and the data-out current is excluded.
4. An initial pause of 100 µs is required after power-up. Then a Precharge All Banks command must be given
followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. Also the onDIMM PLL must be given enough clock cycles to stabilize before any operation can be guaranteed.
5. AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.4 V crossover point. The
transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output
load circuit shown. Specified t AC and tOH parameters are measured with a 50 pF only, without any resistive
termination and with a input signal of 1 V/ns edge rate between 0.8 V and 2.0 V.
6. Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after CKE returns
high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied after the Self Refresh Exit
command is registered.
7. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
8. This module family uses SDRAM components with a write recovery time twr (sometimes also named tdpl) of
two clocks and a trp (“precharge time”) of <=15 ns to achieve proper operation in “buffered mode” at a
operation frequency of 67 MHz.
t CH
2.4 V
0.4 V
1.4 V
CLOCK
t CL
t IS
tT
t IH
1.4 V
INPUT
tAC
t LZ
tAC
t OH
I/O
50 pF
OUTPUT
1.4 V
Measurement conditions for
tAC and tOH
t HZ
IO.vsd
Serial Presence Detect
A serial presence detect storage device - E 2PROM 34C02 - is assembled onto the module.
Information about the module configuration, speed, etc. is written into the E2PROM device during
module production using a serial presence detect protocol (I2C synchronous 2-wire bus)
INFINEON Technologies
11
9.01
HYS 72Vx3xxGR-8
PC100 Registered SDRAM-Modules
SPD-Table for Registered DIMM Modules
128
256
SDRAM
12/13
1 GB
2 Banks
Number of SPD Bytes
Total Bytes in Serial PD
Memory Type
Number of Row Addresses
Hex
512 MB
1 Bank
0
1
2
3
SPD Entry Value
256 MB
1 Bank-
Byte# Description
0C
80
08
04
0D
0D
(without BS bits)
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Number of Column Addresses
Number of DIMM Banks
Module Data Width
Module Data Width (cont’d)
Module Interface Levels
Cycle Time at CL = 3
Access Time from Clock at CL = 3
DIMM Config (Error Det/Corr.)
Refresh Rate/Type
11
1
72
0
LVTTL
10.0 ns
6.0 ns
ECC
Self-Refresh,
15.6 / 7.8 µs
SDRAM Width, Primary
x4
Error Checking SDRAM Data Width
x4
Minimum tCCD
1 CLK
Burst Length Supported
1, 2, 4, 8
Number of SDRAM Banks
4
SDRAM Supported CAS Latencies
2&3
SDRAM CS Latencies
0
SDRAM WE Latencies
0
SDRAM DIMM Module Attributes
registered/buffered
SDRAM Device Attributes
VDD tol +/– 10%
Min. Clock Cycle Time at CL = 2
10 ns
Max. Data Access Time from Clock for 6 ns
CL = 2
Min. Clock Cycle Time at CL = 1
not supp.
Max. Data Access Time from Clock at not supp.
CL = 1
SDRAM Minimum tRP
15 ns
SDRAM Minimum tRRD
20 ns
SDRAM Minimum tRCD
20 ns
SDRAM Minimum tRAS
50 ns
Module Bank Density (per bank)
256/ 512 MByte
SDRAM Input Setup Time
2 ns
SDRAM Input Hold Time
1 ns
INFINEON Technologies
12
0B
01
80
0B
01
48
00
01
A0
60
02
82
0B
02
82
04
04
01
0F
04
06
01
01
1F
0E
A0
60
00
00
40
0F
14
14
32
80
20
10
80
9.01
HYS 72Vx3xxGR-8
PC100 Registered SDRAM-Modules
SPD-Table for Registered DIMM Modules (cont’d)
34
35
36-61
SDRAM Data Input Setup Time
SDRAM Data Input Hold Time
Superset Information (may be used in
future)
62
SPD Revision
63
Checksum for Bytes
0 - 62
64-125 Manufacturer’s Information
126
Frequency Specification
127
Details of Clocks
128+
Unused Storage Locations
INFINEON Technologies
2 ns
1 ns
–
1.2
–
–
100MHz
–
–
13
1 GB
2 Banks
Hex
512 MB
1 Bank
SPD Entry Value
256 MB
1 Bank-
Byte# Description
20
10
00
DB
12
1E
1F
XX
64
8F
FF
9.01
HYS 72Vx3xxGR-8
PC100 Registered SDRAM-Modules
Package Outlines
Module Package
JEDEC MO-161
256 & 512 MByte Registered Module based
on x4 organised SDRAMs
133.35
4 max.
43.18
127.35
Register
Register
PLL
3
1
10
11
6.35
3
1.27
40
41
6.35
84
1.27± 0.1
42.18
2
85
94
95
124
17.78
3.125
66.68
125
168
4 ± 0.1
Register
2.55
0.25
Detail of Contacts
+0.5
1
L-DIM-168-37
1.27
note: all tolerances are in accordance with the JEDEC standard
INFINEON Technologies
14
9.01
HYS 72Vx3xxGR-8
PC100 Registered SDRAM-Modules
Module Package
JEDEC MO-161
1 GByte Registered DIMM Module with Stacked x4 SDRAMs
133.35
6.8 max.
43.18
127.35
Register
PLL
3
Register
1
10
11
6.35
3
1.27
40
41
6.35
84
1.27± 0.1
42.18
2
85
94
95
124
17.78
3.125
66.68
125
168
4 ± 0.1
Register
2.55
0.25
Detail of Contacts
+0.5
1
L-DIM-168-37-S
1.27
note: all tolerances are in accordance with the JEDEC standard
INFINEON Technologies
15
9.01
HYS 72Vx3xxGR-8
PC100 Registered SDRAM-Modules
Functional Description
These Registered DIMMs achieve high speed data transfer rate up to 100 MHz, when in “registered
mode” and up to 67 MHz when in “buffered mode”. The “registered mode” is achieved when the
REGE input signal is in “high” state or the pin is not connected. Operation in “buffered mode” (REGE
= “low”) needs careful system design to compensate all input signals for the extra delay time of the
register components when in “buffered mode”. “Buffered mode” is limited to 67 Mhz operation.
Registered Mode:
All control and address signals are synchronized with the positive edge of externally supplied clocks
and are registered on-DIMM and hence delayed by one clock cycle in arriving at the SDRAM
devices. The use of the on-board register reduces the capacitive loading of the DIMM on input
control and address signals. The SDRAM device data lines (DQ) are connected directly to the DIMM
tabs through 10 Ohm series resistors. All the following timing diagrams and explanations show
DIMM operation at the tabs, not SDRAM operation.
The picture below depicts an overview of the effect of the Registered Mode on the data outputs
(DQs) for a Read operation. Without the registers, the data is delayed according to the device CAS
latency, in the case two clocks. With the register, the data is delayed according to the device CAS
latency plus an additional clock cycle. This is known as the DIMM CAS latency, and in this example
is four three. The data path can be thought of as a pipeline in which the register effectively lengthens
the pipe by one clock cycle.
Registered DIMM Burst Read Operation (BL = 4)
T0
T1
T2
T3
T4
T5
T6
Read A
NOP
NOP
NOP
NOP
NOP
NOP
CLK
Command
Device
CAS latency = 2
t CK2 , DQ’s
DIMM
CAS latency = 3
t CK3 , DQ’s
DOUT A0 DOUT A1 DOUT A2 DOUT A3
DOUT A0 DOUT A1 DOUT A2 DOUT A3
Added for on-DIMM pipeline register
One Clock Reg-DIMM Latency = 1
SPT03968
In case of a Burst Write Command the data-in is delayed one clock due the op-DIMM pipeline
register also. Therefore, data for the first Burst Write cycle must be applied on the DQ pins on the
next clock cycle after the Write command is issued. the remaining data inputs must be supplied on
each subsequent rising clock edge until the burst length is completed. When the burst has finished,
any additional data supplied to the DQ pins will be ignored.
INFINEON Technologies
16
9.01
HYS 72Vx3xxGR-8
PC100 Registered SDRAM-Modules
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
Write A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DIN A0
DIN A1
DIN A2
DIN A3
don’t care
CLK
Command
DQ’s
The first data element and the Write
are registered on the next clock edge
Reg-DIMM Latency = 1 CLK
Extra data is ignored after
termination of a Burst.
SPT03969
Registered DIMM Burst Write Operation (BL = 4)
Buffered Mode:
Operating margins when Registered DIMM modules are used in “buffered mode” are derived from
the post register timing only. For a complete system level timing the system designer must add/
subtract to/from this margin other parameters such as, system to DIMM flight time, clow skew, clock
jitter, external register clock to output delay etc.
The table below shows an example for the post register timing for DIMM modules in “buffered
mode”:
Property
Time [ns]
Set-up
Property
TIme [ns]
Hold
Tpd.BUF.max
1.96
Tpd.BUF.min
0.91
Tflight.max
3.43
Tflight.min
2.66
Tsso.brd.max
0.30
Tsso.brd.min
0.0
Tsu.SDRAM
2.00
TholdSDRAM
-1.00
Period
15.00
tpd.BUF.max: The maximum time for the signal to exit the register with REGE in a low stgate. This
is measured into 0 pf load.
Tflight.max: The maximum time for the signal to propagate from the register to the SDRAM
INFINEON Technologies
17
9.01
HYS 72Vx3xxGR-8
PC100 Registered SDRAM-Modules
Tsso.brd.max: The time the flight tine is extended due to simultaneous switching outputs and
crosstalk from other signals.
Tsu.SDRAM: The set-up required for the SDRAM inputs.
Tpd.BUF.min. : The minimum time for the signal to exit the register with REGE in a low state. This
is measured into a 0 pf load.
Tflight.min: The minimum time for the signal to propagate from the register to the SDRAM
Thold.DRAM: The hold time required for the SDRAM inputs
Period: Minimum cycle time expressing in ns allowed for operating these Registered DIMM
modules in “buffered mode”
Module Label Example:
IFX partnumber
IFX coding for:
- design step
- PCB rev.
- date code
- lot code
INFINEON Technologies
HYS72V64300GR-8-C2
64Mx72 SDRAM
C1W106112256
PC100-222-622R
Assembled in USA
512MB, SYNC, 100MHz, CL2,ECC,REG
18
9.01
HYS 72Vx3xxGR-8
PC100 Registered SDRAM-Modules
Rev. Changes
13.2.2001
Target Specification for operation up to 100 MHz in “registered mode” and
67 Mhz when used in “buffered mode”
Special module family for applications based on INTEL’s 460GX chipset,
where PC100 modules are used in “buffered mode” at 67 MHz maximum operation frequency.
Uses components with twr = tdpl = 2Clock which support trp <= 15ns to guarantee operation at 67MHz when these modules are used in “buffered mode”
21.6.2001
29.06.01
06.09.2001
Outline Drawings updated and changed to L-DIM-168-37 & 37S
Absolute maximum rating section added
SCR: Thickness of modules with stacked components changed
from 6.4 to 6.8 max.
Datasheet changed from “Preliminary” to “Final”
INFINEON Technologies
19
9.01