HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules 3.3 V 168-pin Registered SDRAM Modules PC133 128 MByte Module PC133 256 MByte module PC133 512 MByte Module PC133 1 GByte Module PC133 2 GByte Module • 168-pin Registered 8 Byte Dual-In-Line SDRAM Module for PC and Server main memory applications • Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) • One bank 16M × 72, 32M x 72, 64M × 72and 128M x 72, two bank 128M × 72 and 256M x 72 organization • All inputs and outputs are LVTTL compatible • Serial Presence Detect with E2PROM • Utilizes SDRAMs in TSOPII-54 packages with registers and PLL. • Optimized for ECC applications with very low input capacitances • Card Size: 133.35 mm × 38.10 / 43.18 mm with Gold contact pads and max. 4.00 / 6.80 mm thickness (JEDEC MO-161) • JEDEC standard Synchronous DRAMs (SDRAM) Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave) • These modules all fully compatible with the current industry standard PC133 and PC100 specifications • Single + 3.3 V (± 0.3 V) power supply • Auto Refresh (CBR) and Self Refresh • Performance: speed grade -7 -7.5 Unit MHz fCK Clock Frequency (max.) @ CL = 3 133 133 tCK Clock Cycle Time (min.) @ CL = 3 7.5 7.5 ns tAC Clock Access Time (min.) @ CL= 3 5.4 5.4 ns fCK Clock Frequency (max.) @ CL = 2 133 100 MHz tCK Clock Cycle Time (min.) @ CL = 2 7.5 10 ns tAC Clock Access Time (min.) @ CL= 2 5.4 6 ns Description The HYS 72Vxx3xxGR-7 and -7.5 are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs) organized as 16M × 72, 32M x 72, 64M × 72, 128M × 72 and 256M x 72 high speed memory arrays designed with Synchronous DRAMs (SDRAMs) for ECC applications. All control and address signals are registered on-DIMM and the design incorporates a PLL circuit for the Clock inputs. Use of an on-board register reduces capacitive loading on the input signals but are delayed by one cycle in arriving at the SDRAM devices. Decoupling capacitors are mounted on the PC board. The DIMMs use a serial presence detects scheme implemented via a serial E2PROM using the 2-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint. INFINEON Technologies 1 1.02 HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules Ordering Information Partnumber 1) Compliance Code 2) Description SDRAM Technology PC133-333: HYS 72V16300GR-7.5-C HYS 72V16300GR-7.5-E PC133R-333-542-B2 one bank 128 MB Reg. DIMM 64 MBit (x4) HYS 72V16301GR-7.5-C2 PC133R-333-542-B2 one bank 128 MB Reg. DIMM 128 MBit (x8) HYS 72V32301GR-7.5-C2 PC133R-333-542-B2 one bank 256 MB Reg. DIMM 128 Mbit (x4) HYS 72V32300GR-7.5-C2 HYS 72V32300GR-7.5-D PC133R-333-542-AA one bank 256 MB Reg. DIMM 256 Mbit (x8) HYS 72V64300GR-7.5-C2 HYS 72V64300GR-7.5-D PC133R-333-542-B2 one bank 512 MB Reg. DIMM 256 MBit (x4) HYS 72V128320/1GR-7.5-C2 PC133R-333-542-B2 two banks 1 GByte Reg. DIMM HYS 72V128320/1GR-7.5-D 256 MBit (x4, stacked) 3) HYS 72V128300GR-7.5-A PC133R-333-542-B2 one bank 1 GByte Reg. DIMM 512 MBit (x4) HYS 72V256320/1GR-7.5-A PC133R-333-542-B2 two banks 2 GByte Reg. DIMM 512 MBit (x4, stacked) 3) PC133-222: HYS 72V16300GR-7-E PC133R-222-542-B2 one bank 128 MB Reg. DIMM 64 MBit (x4) HYS 72V16301GR-7-C2 PC133R-222-542-B2 one bank 128 MB Reg. DIMM 128 MBit (x8) HYS 72V32301GR-7-C2 PC133R-222-542-B2 one bank 256 MB Reg. DIMM 128 Mbit (x4) HYS 72V32300GR-7-D PC133R-222-542-AA one bank 256 MB Reg. DIMM 256 Mbit (x8) HYS 72V64300GR-7-D PC133R-222-542-B2 one bank 512 MB Reg. DIMM 256 MBit (x4) HYS 72V128320/1GR-7-D PC133R-222-542-B2 two banks 1 GByte Reg. DIMM 256 MBit (x4, stacked) 3) HYS 72V128300GR-7-A PC133R-222-542-B2 one bank 1 GByte Reg. DIMM 512 MBit (x4) HYS 72V256320/1GR-7-A PC133R-222-542-B2 two banks 2 GByte Reg. DIMM 512 MBit (x4, stacked) 3) Notes: 1.) All part numbers end with a place code, designating the die revision of the components used on the Registered DIMM module. Consult factory for current revision. Example: HYS 64V32300GR-7.5-D, indicating Rev.D dies are used for 256Mbit SDRAM components. 2.) The Compliance Code is printed on the modules labels and describes speed sort of the modules, latencies, access time from clock,SPD revision and Raw Card version acording to the actual JEDEC standard. 3.) Modules with stacked components are available in two version, with components stacked using a soldering stacking technique (f.e. HYS72V128320GR-7.5 ) and an welding technique developed by INFINEON Technologies (f.e. HYS72V128321GR-7.5) . INFINEON Technologies 2 1.02 HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules Pin Definitions and Functions A0 - A11, A12 Address Inputs (A12 is used for 256Mbit based modules only) DQMB0 - DQMB7 Data Mask BA0, BA1 Bank Selects CS0 - CS3 Chip Select DQ0 - DQ63 Data Input/Output REGE*) Register Enable “H” or N.C = registered mode “L” = buffered mode CB0 - CB7 Check Bits VDD Power (+ 3.3 V) RAS Row Address Strobe VSS Ground CAS Column Address Strobe SCL Clock for Presence Detect WE Read/Write Input SDA Serial Data Out CKE0 Clock Enable N.C. No Connection CLK0 - CLK3 Clock Input – – Note : *) To confirm to this specification, motherboards must pull this pin to high state or no connect. Address Format Density Organization Memory SDRAMs Banks # of # of row/bank/ Refresh Period Interval SDRAMs columns bits 128 MB 16M × 72 1 16M × 4 18 12/2/10 4k 64 ms 15.6 µs 128 MB 16M × 72 1 16M x 8 9 12/2/10 4k 64 ms 15.6 µs 256 MB 32M x 72 1 32M x 4 18 12/2/11 4k 64 ms 15.6 µs 256 MB 32M x 72 1 32M x 8 9 13/2/10 8k 64 ms 7.8 µs 512 MB 64M × 72 64 ms 7.8 µs 1 64M × 4 18 13/2/11 8k 1 GB 128M × 72 2 64M × 4 36 13/2/11 8k 64 ms 7.8 µs 1 GB 128M × 72 1 128M × 4 18 13/2/12 8k 64ms 7.8 µs 2 GB 256M × 72 2 128M × 4 36 13/2/12 8k 64ms 7.8 µs INFINEON Technologies 3 1.02 HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules Pin Configuration PIN# Symbol 1 VSS 2 DQ0 3 DQ1 4 DQ2 5 DQ3 VDD 6 7 DQ4 8 DQ5 9 DQ6 10 DQ7 11 DQ8 VSS 12 13 DQ9 14 DQ10 15 DQ11 16 DQ12 17 DQ13 18 VDD 19 DQ14 20 DQ15 21 CB0 22 CB1 23 VSS 24 N.C. 25 N.C. 26 VDD 27 WE 28 DQMB0 29 DQMB1 30 CS0 31 DU 32 VSS 33 A0 34 A2 35 A4 36 A6 37 A8 38 A10 (AP) 39 BA1 40 VDD VDD 41 42 CLK0 INFINEON Technologies PIN# 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Symbol PIN# 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 VSS DU CS2 DQMB2 DQMB3 DU VDD N.C. N.C. CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 N.C. DU N.C. VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CLK2 N.C. WP SDA SCL VDD 4 Symbol VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS N.C. N.C. VDD CAS DQMB4 DQMB5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD CLK1 A12 PIN# 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Symbol VSS CKE0 CS3 DQMB6 DQMB7 N.C. VDD N.C. N.C. CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VDD DQ52 N.C. DU REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CLK3 N.C. SA0 SA1 SA2 VDD 1.02 HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules RCS0 RDQMB0 RDQMB4 DQ0-DQ3 DQM CS DQ0-DQ3 D0 DQ32-DQ35 DQM CS DQ0-DQ3 D8 DQ4-DQ7 DQM CS DQ0-DQ3 D1 DQ36-DQ39 DQM CS DQ0-DQ3 D9 RDQMB1 RDQMB5 DQM DQ0-DQ3 DQ40-DQ43 DQM CS DQ0-DQ3 D10 DQ12-DQ15 CS DQM DQ0-DQ3 D3 DQ44-DQ47 CS DQM DQ0-DQ3 D11 CB0-CB3 DQM CS DQ0-DQ3 D16 CB4-CB7 DQM CS DQ0-DQ3 D17 DQ8-DQ11 D2 RCS2 RDQMB2 RDQMB6 DQ16-DQ19 DQM CS DQ0-DQ3 D4 DQ48-DQ51 DQM CS DQ0-DQ3 D12 DQ20-DQ23 CS DQM DQ0-DQ3 D5 DQ52-DQ55 CS DQM DQ0-DQ3 D13 RDQMB3 RDQMB7 DQ24-DQ27 CS DQM DQ0-DQ3 D6 DQ56-DQ59 CS DQM DQ0-DQ3 D14 DQ28-DQ31 CS DQM DQ0-DQ3 D7 DQ60-DQ63 CS DQM DQ0-DQ3 D15 CLK0 PLL CS0/CS2 DQMB0-7 BA0, BA1 A0-A11, A12 RAS CAS CKE0 WE Register 12 pF SDRAMs D0-D17 CLK1, CLK2, CLK3 RCS0/RCS2 RDQMB0-7 RBA0, RBA1 RA0-RA11, RA12 RRAS RCAS RCKE0 RWE 12 pF SDRAMs D0-D17 SDRAMs D0-D17 SDRAMs D0-D17 SDRAMs D0-D17 SDRAMs D0-D17 SDRAMs D0-D17 REGE 10 k Ω SA0 SA1 SA2 SCL E 2PROM (256 word x 8 Bit) SA0 SA1 SDA WP SA2 SCL V CC 47 k Ω D0-D17, Reg., DLL C V SS D0-D17, Reg., DLL 1) DQ wirding may differ from that decribed in this drawing; however DQ/DQB relationship must be maintained as shown 2) All resistors are 10 Ω unless otherwise noted V CC SPB04135 Block Diagram: One Bank 16M x 72, 32M x 72, 64M x 72 and 128M x 72 SDRAM DIMM Modules HYS72V16300GR, HYS72V32301GR, HYS72V64300GR and HYS72V128320GR using x4 organized SDRAMs INFINEON Technologies 5 1.02 HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules RCS0 RDQMB0 DQ0-DQ7 CS DQM DQ0-DQ7 D0 RDQMB4 DQ32-DQ39 CS DQM DQ0-DQ7 D4 RDQMB1 DQ8-DQ15 CS DQM DQ0-DQ7 D1 RDQMB5 DQ40-DQ47 CS DQM DQ0-DQ7 D5 CS WE DQM DQ0-DQ7 D8 CB0- CB7 RCS2 RDQMB2 DQ16-DQ23 CS DQM DQ0-DQ7 D2 RDQMB4 DQ48-DQ55 CS DQM DQ0-DQ7 D6 RDQMB3 DQ24-DQ31 CS DQM DQ0-DQ7 D3 RDQMB7 DQ56-DQ63 CS DQM DQ0-DQ7 D7 VC C D0-D8, Reg., DLL C VSS D0-D8, Reg., DLL CLK0 PLL Register 47 k Ω SDRAMs D0-D8 12 pF CS0/CS2 DQMB0-7 BA0, BA1 A0-A11,12* ) RAS CAS CKE0 WE E 2 PROM (256 word x 8 Bit) SA0 SA0 SA1 SA1 SDA SA2 SA2 WP SCL SCL RCS0/RCS2 RDQMB0-7 RBA0, RBA1 RA0-11,12 RRAS RCAS RCKE0 RWE SDRAMs SDRAMs SDRAMs SDRAMs SDRAMs SDRAMs D0-D8 D0-D8 D0-D8 D0-D8 D0-D8 D0-D8 Notes: 1) DQ wirding may differ from that decribed in this drawing; however DQ/DQB relationship must be maintained as shown 2) All resistors are 10 Ω unless otherwise noted * ) A12 is only for 32 M x 72 organisation CLK1, CLK2, CLK3 REGE 10 k Ω VC C 12 pF SPB04130-2 Block Diagram: One Bank 16M x72 and 32M x 72 Modules HYS72V16301 & HYS72V32300GR using x8 organized SDRAMs INFINEON Technologies 6 1.02 HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules RCS0 RCS1 RDQMB0 RDQMB4 DQ0-DQ3 CS DQM DQ0-DQ3 D0 CS DQM DQ0-DQ3 D0 DQ32-DQ35 DQM CS DQ0-DQ3 D8 CS DQM DQ0-DQ3 D8 DQ4-DQ7 DQM CS DQ0-DQ3 D1 DQM CS DQ0-DQ3 D1 DQ36-DQ39 DQM CS DQ0-DQ3 D9 DQM CS DQ0-DQ3 D9 DQ8-DQ11 DQM CS DQ0-DQ3 D2 DQM CS DQ0-DQ3 D2 DQ40-DQ43 DQM CS DQ0-DQ3 D10 DQM CS DQ0-DQ3 D10 DQ12-DQ15 CS DQM DQ0-DQ3 D3 CS DQM DQ0-DQ3 D3 DQ44-DQ47 DQM CS DQ0-DQ3 D11 CS DQM DQ0-DQ3 D11 CB0-CB3 CS DQM DQ0-DQ3 D16 CS DQM DQ0-DQ3 D16 CB4-CB7 DQM CS DQ0-DQ3 D17 DQM CS DQ0-DQ3 D17 DQ16-DQ19 DQM CS DQ0-DQ3 D4 DQM CS DQ0-DQ3 D4 DQ48-DQ51 DQM CS DQ0-DQ3 D12 DQM CS DQ0-DQ3 D12 DQ20-DQ23 DQM CS DQ0-DQ3 D5 DQM CS DQ0-DQ3 D5 DQ52-DQ55 DQM CS DQ0-DQ3 D13 CS DQM DQ0-DQ3 D13 DQ24-DQ27 DQM CS DQ0-DQ3 D6 DQM CS DQ0-DQ3 D6 DQ56-DQ59 DQM CS DQ0-DQ3 D14 CS DQM DQ0-DQ3 D14 DQ28-DQ31 DQM CS DQ0-DQ3 D7 DQM CS DQ0-DQ3 D7 DQ61-DQ63 DQM CS DQ0-DQ3 D15 DQM CS DQ0-DQ3 D15 RDQMB1 RDQMB5 RCS2 RCS3 RDQMB2 RDQMB6 RDQMB3 CLK0 RDQMB7 PLL CS0-CS3 DQMB0-7 BA0, BA1 A0-A11, A12* ) RAS CAS CKE0 WE REGE 10 k Ω V CC Register 12 pF Stacked SDRAMs D0-D17 CLK1, CLK2, CLK3 RCS0-RCS3 RDQMB0-7 RBA0, RBA1 RA0-RA11 RRAS RCAS RCKE0 RWE 12 pF Stacked SDRAMs D0-D17 Stacked SDRAMs D0-D17 Stacked SDRAMs D0-D17 Stacked SDRAMs D0-D17 Stacked SDRAMs D0-D17 Stacked SDRAMs D0-D17 E 2PROM (256 word x 8 Bit) SA0 SA0 SA1 SA1 SDA SA2 SA2 WP SCL SCL V CC 47 k Ω D0-D17, Reg. DLL C V SS D0-D17, Reg. DLL 1.) *) A12 is only used for 128 M x 72 organisation DQ wirding may differ from that decribed in this drawing; however DQ/DQB relationship must be maintained as shown 2.) All resistors are 10 Ω unless otherwise noted SPB04136 Block Diagram: Two Bank 128M x 72 and 256M x 72 SDRAM DIMM Modules HYS 72V128320GR and HYS72V256320GR Using Stacked x4 Organized SDRAMs INFINEON Technologies 7 1.02 HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules Absolute Maximum Ratings Parameter Symbol Limit Values Unit min. max. Input / Output voltage relative to VSS VIN, VOUT – 1.0 4.6 V Power supply voltage on V DD VDD – 1.0 4.6 V Storage temperature range TSTG -55 +150 o Power dissipation (per SDRAM component) PD – 1 W Data out current (short circuit) IOS – 50 mA C Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. Functional operation should be restricted to recommended operation conditions. Exposure to higher than recommended voltage for extended periods of time affect device reliability DC Characteristics TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V Parameter Symbol Limit Values min. Unit max. Input High Voltage VIH 2.0 VDD + 0.3 V Input Low Voltage VIL – 0.5 0.8 V Output High Voltage (I OUT = – 4.0 mA) VOH 2.4 – V Output Low Voltage (IOUT = 4.0 mA) VOL – 0.4 V Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) II(L) – 10 10 µA Output Leakage Current IO(L) – 10 10 µA (DQ is disabled, 0 V < VOUT < VDD) Capacitance TA = 0 to 70 °C 1); VDD = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Limit Values Unit One Bank Two Bank Modules Modules Input Capacitance (all inputs except CLK and CKE) CIN 10 20 pF Input Capacitance (CLK) CCLK 30 30 pF Input Capacitance (CKE) CCKE 17 30 pF Input/Output Capacitance(DQ0 - DQ63, CB0 - CB7) CIO 10 17 pF Input Capacitance (SCL, SA0 - 2) CSC 8 8 pF Input/Output Capacitance (SDA) CSD 8 8 pF INFINEON Technologies 8 1.02 HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules Operating Currents per SDRAM Component TA = 0 to 70 °C 1), VDD = 3.3 V ± 0.3 V Parameter Test Condition Symbol 64 Mb 128 Mb 256 Mb 512 Mb Unit Note max. Operating current 2) – tRC = tRC(MIN.), tCK = tCK(MIN.) ICC1 110 160 270 tbd. mA tCK = min. ICC2P 2 1.5 2 tbd. mA 2) tCK = min. ICC2N 40 40 25 tbd. mA 2) CKE ≥ V IH(MIN.) ICC3N 50 50 50 tbd. mA 2) CKE ≤ V IL(MAX.) ICC3P 8 10 10 tbd. mA 2) – ICC4 70 100 170 tbd. mA Outputs open, Burst Length = 4, CL = 3. All banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access Precharge stand-by current in Power Down Mode CS = V IH(MIN.), CKE ≤ VIL(MAX.) Precharge Stand-by Current in Non-Power Down Mode CS = V IH (MIN.), CKE ≥ V IH(MIN.) No operating current tCK = min., CS = VIH(MIN.), active state (max. 4 banks) Burst operating current tCK = min., Read command cycling 2), 3) – Auto refresh current tCK = min., Auto Refresh command cycling ICC5 140 230 240 tbd. mA 2) Self refresh current – Self Refresh Mode,CKE = 0.2 V ICC6 1 1.5 2.5 tbd. mA 2) INFINEON Technologies 9 1.02 HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules AC Characteristics (SDRAM Device Specification) 4), 5) TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symbol Limit Values -7 PC133-222 Unit Note -7.5 PC133-333 min. max. min. max. 7.5 7.5 – – 7.5 10 – – ns ns – – 133 133 – – 133 100 MHz MHz – – 5.4 5.4 – – 5.4 6 ns ns Clock and Access Time tCK Clock Cycle Time CAS Latency = 3 CAS Latency = 2 – fCK Clock Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock tAC CAS Latency = 3 CAS Latency = 2 – – Clock High Pulse Width tCH 2.5 – 2.5 – ns – Clock Low Pulse Width tCL 2.5 – 2.5 – ns – Transition Time tT 0.5 7.5 0.5 10 ns – Input Setup Time tIS 1.5 – 1.5 – ns – Input Hold Time tIH 0.8 – 0.8 – ns – Power Down Mode Entry Time tSB – 1 – 1 CLK – Power Down Mode Exit Setup Time tPDE 1 – 1 – CLK – Mode Register Setup Time tRCS 2 – 2 – CLK – Row to Column Delay Time tRCD 15 – 20 – ns – Row Precharge Time tRP 15 – 20 – ns – Row Active Time tRAS 37 – 45 100k ns – Row Cycle Time tRC 60 – 67.5 – ns – Activate (a) to Activate (b) Command Period tRRD 2 – 2 – CLK – CAS(a) to CAS(b) Command Period tCCD 1 – 1 – CLK – Setup and Hold Parameters Common Parameters INFINEON Technologies 10 1.02 HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules AC Characteristics (SDRAM Device Specification) (cont’d) 4), 5) TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symbol Limit Values -7 PC133-222 Unit Note -7.5 PC133-333 min. max. min. max. – – 15.6 7.8 – – 15.6 7.8 µs µs tSREX 1 – 1 – CLK tOH 3 – 3 – ns – Refresh Cycle tREF Refresh Period 64&128MBit SDRAM Based Modules 256&512MBit SDRAM Based Modules Self Refresh Exit Time – 6) Read Cycle Data Out Hold Time Data Out to Low Impedance Time tLZ 0 – 0 – ns 7) Data Out to High Impedance Time tHZ 3 7 3 7 ns 7) DQM Data Out Disable Latency tDQZ – 2 – 2 CLK – Data Input to Precharge (write recovery) tWR 2 – 2 – CLK – DQM Write Mask Latency tDQW 0 – 0 – CLK – Write Cycle INFINEON Technologies 11 1.02 HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules Notes 1. The registered DIMM modules are designed to operate under system operating conditions between 0-55 deg C ambient, maximum sustained bandwidth and 0 LFM airflow. Operating at higher ambient temperatures needs sufficient air flow to limit the case temperature of the SDRAM components do not exceed 85oC. 2. These parameters depend on the cycle rate. All values are measured at 133 MHz operation frequency. Input signals are changed once during tck excepts for Icc6 and for standby currents when tck = infinity. 3. These parameters are measured with continous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and the data-out current is excluded. 4. An initial pause of 100 µ s is required after power-up. Then a Precharge All Banks command must be given followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. Also the on-DIMM PLL must be given enough clock cycles to stabilize (tSTAB ) before any operation can be guaranteed. 5. AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between V IH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown. Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate between 0.8 V and 2.0 V. 6. Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied after the Self Refresh Exit command is registered. 7. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. t CH 2.4 V 0.4 V 1.4 V CLOCK t CL t IS tT t IH INPUT 1.4 V tAC t LZ tAC t OH I/O OUTPUT 1.4 V t HZ 50 pF Measurement conditions for tAC and tOH IO.vsd Serial Presence Detect A serial presence detect storage device - E 2PROM 34C02 - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E2PROM device during module production using a serial presence detect protocol (I2C synchronous 2-wire bus).The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. INFINEON Technologies 12 1.02 HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules SPD-Table for -7.5 Registered DIMM Modules 15 16 1 GB 1 Bank 2 GB 2 Banks 08 Memory Type SDRAM Number of Row Addresses 12/13 0C 0C 0C 0D 0D 0D 0D 0D Number of Column Addresses 10/11/12 0A 0A 0B 0A 0B 0B 0C 0C Number of DIMM Banks 1/2 01 01 01 01 01 02 01 02 Module Data Width 72 512 MB 1 Bank 80 256 04 48 Module Data Width (cont’d) 0 00 Module Interface Levels LVTTL 01 Cycle Time at CL = 3 7.5 ns 75 Access Time from Clock at CL = 3 5.4 ns 54 DIMM Config (Error Det/Corr.) ECC 02 Refresh Rate/Type 15.6/7.8 µs 80 80 80 82 82 82 82 82 SDRAM Width, Primary x4 / x8 04 08 04 08 04 04 04 04 Error Checking SDRAM Data Width Minimum tCCD x4 / x8 04 08 04 08 04 04 04 04 Burst Length Supported 1, 2, 4, 8 & (full page) 4 23 24 Min. Clock Cycle Time at CL = 2 27 28 29 30 256 MB 1 Bank 4) 128 Total Bytes in Serial PD Number of SDRAM Banks 26 256 MB 1 Bank 3) Number of SPD Bytes 17 18 19 20 21 22 25 128 MB 1 Bank 2) 1 GB 2 Banks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Hex SPD Entry Value 128 MB 1 Bank 1) Byte# Description 1 CLK 01 8F 0F 0F 0F 0F 06 SDRAM CS Latencies 0 01 SDRAM WE Latencies 0 01 SDRAM DIMM Module Attributes with PLL 1F SDRAM Device Attributes VDD tol +/– 10% 10 ns 0E Max. Data Access Time from Clock 6.0 ns for CL = 2 Min. Clock Cycle Time at CL = 1 not supported Max. Data Access Time from Clock not supp. at CL = 1 SDRAM Minimum tRP 20 ns 60 SDRAM Minimum tRRD 15 ns 0F SDRAM Minimum tRCD 20 ns 14 SDRAM Minimum tRAS 45 ns 2D 13 0F 0F 04 SDRAM Supported CAS Latencies 2 & 3 INFINEON Technologies 0F A0 00 00 14 1.02 HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules SPD-Table for -7.5 Registered DIMM Modules (cont’d) 128 MB 1 Bank 2) 256 MB 1 Bank 3) 256 MB 1 Bank 4) 512 MB 1 Bank 1 GB 2 Banks 1 GB 1 Bank 2 GB 2 Banks Hex SPD Entry Value 128 MB 1 Bank 1) Byte# Description 20 20 40 40 80 80 01 01 31 Module Bank Density (per bank) 32 33 34 35 36-61 SDRAM Input Setup Time 128 MByte 256 Mbyte 512 MByte 1 GByte 1.5 ns SDRAM Input Hold Time 0.8 ns SDRAM Data Input Setup Time 1.5 ns 15 SDRAM Data Input Hold Time 0.8 ns 08 Superset Information (may be used in future) SPD Revision – 00 Checksum for Bytes 0 - 62 – Manufacturer’s Information – Frequency Specification – 64 Details of Clocks – 8F Unused Storage Locations – FF 62 63 64-125 126 127 128+ 15 08 JEDEC 2 12 D8 60 79 83 BC BD 3E 3F 1) HYS72V16300GR-7.5 2) HYS72V16301GR-7.5 3) HYS72V32301GR-7.5 4) HYS72V32300GR-7.5 INFINEON Technologies 14 1.02 HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules SPD-Table for -7 Registered DIMM Modules 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 GB 2 Banks 1 GB 1 Bank 1 GB 2 Banks 512 MB 1 Bank 256 MB 1 Bank 4) 80 256 08 Memory Type SDRAM Number of Row Addresses 12/13 0C 0C 0C 0D 0D 0D 0D 0D Number of Column Addresses 10/11/12 0A 0A 0B 0A 0B 0B 0C 0C Number of DIMM Banks 1/2 01 01 01 01 01 02 01 02 Module Data Width 72 04 48 Module Data Width (cont’d) 0 00 Module Interface Levels LVTTL 01 Cycle Time at CL = 3 7.5 ns 75 Access Time from Clock at CL = 3 5.4 ns 54 DIMM Config (Error Det/Corr.) ECC 02 Refresh Rate/Type 15.6/7.8 µs 80 80 80 82 82 82 82 82 SDRAM Width, Primary x4 / x8 04 08 04 08 04 04 04 04 Error Checking SDRAM Data Width Minimum tCCD x4 / x8 04 08 04 08 04 04 04 04 Burst Length Supported 1, 2, 4, 8 & (full page) 4 8F 0F 0F 0F 0F 0F 0F 0F 23 24 Min. Clock Cycle Time at CL = 2 27 28 29 30 256 MB 1 Bank 3) 128 Total Bytes in Serial PD Number of SDRAM Banks 26 128 MB 1 Bank 2) Number of SPD Bytes 17 18 19 20 21 22 25 Hex SPD Entry Value 128 MB 1 Bank 1) Byte# Description 1 CLK 01 04 SDRAM Supported CAS Latencies 2 & 3 06 SDRAM CS Latencies 0 01 SDRAM WE Latencies 0 01 SDRAM DIMM Module Attributes with PLL 1F SDRAM Device Attributes VDD tol +/– 10% 7.5 ns 0E Max. Data Access Time from Clock 5.6 ns for CL = 2 Min. Clock Cycle Time at CL = 1 not supported Max. Data Access Time from Clock not supp. at CL = 1 SDRAM Minimum tRP 15 ns 54 0F SDRAM Minimum tRRD 14 ns 0E SDRAM Minimum tRCD 15 ns 0F SDRAM Minimum tRAS 37 ns 25 INFINEON Technologies 15 75 00 00 1.02 HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules 128 MB 1 Bank 2) 256 MB 1 Bank 3) 256 MB 1 Bank 4) 512 MB 1 Bank 1 GB 2 Banks 1 GB 1 Bank 2 GB 2 Banks Hex SPD Entry Value 128 MB 1 Bank 1) Byte# Description 20 20 40 40 80 80 01 01 31 Module Bank Density (per bank) 32 33 34 35 36-61 SDRAM Input Setup Time 128 MByte 256 Mbyte 512 MByte 1024 MByte 1.5 ns SDRAM Input Hold Time 0.8 ns SDRAM Data Input Setup Time 1.5 ns 15 SDRAM Data Input Hold Time 0.8 ns 08 Superset Information (may be used in future) SPD Revision – 00 Checksum for Bytes 0 - 62 – Manufacturer’s Information – Frequency Specification – 64 Details of Clocks – 8F Unused Storage Locations – FF 62 63 64-125 126 127 128+ 15 08 JEDEC 2 12 8E 16 2F 39 72 73 F4 F5 1) HYS72V16300GR-7 2) HYS72V16301GR-7 3) HYS72V32301GR-7 4) HYS72V32300GR-7 INFINEON Technologies 16 1.02 HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules Package Outlines for Raw Card AA Module Package JEDEC MO-161 Registered DIMM Modules Raw Card AA (L-DIM168-44) 133.35 ± 0.15 4 max. 38.10 ± 0.13 127.35 Register PLL Register 3 1 10 11 6.35 3 1.27 40 41 6.35 84 1.27± 0.1 42.18 66.68 3.125 2 94 95 124 125 168 4 ± 0.1 17.78 85 2.55 0.25 Detail of Contacts +0.5 1 L-DIM-168-44 1.27 note: all outline dimensions and tolerances are in accordance with the JEDEC standard INFINEON Technologies 17 1.02 HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules Package Outlines for Raw Card B Module Package JEDEC MO-161 Registered DIMM Modules Raw Card B (L-DIM168-37) 128MB, 256MB, 512MB & 1GB modules based on x4 SDRAM components 133.35 ± 0.15 4 max. 43.18 ± 0.13 127.35 Register Register PLL 3 1 10 11 6.35 3 1.27 40 41 6.35 84 1.27± 0.1 42.18 2 85 94 95 124 17.78 3.125 66.68 125 168 4 ±0.1 Register 2.55 0.25 Detail of Contacts +0.5 1 L-DIM-168-37 1.27 note: all outline dimensions and tolerances are in accordance with the JEDEC standard INFINEON Technologies 18 1.02 HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules Package Outlines for Raw Card B (with stacked components) Module Package JEDEC MO-161 Registered DIMM Modules Raw Card B (L-DIM168-37) 1 GByte and 2 GByte modules 133.35 ± 0.15 6.8 max. 43.18 ± 0.13 127.35 Register PLL 3 Register 1 10 11 6.35 3 1.27 40 41 6.35 84 1.27± 0.1 42.18 2 85 94 95 124 17.78 3.125 66.68 125 168 4 ±0.1 Register 2.55 0.25 Detail of Contacts +0.5 1 L-DIM-168-37-S 1.27 note: all outline dimensions and tolerances are in accordance with the JEDEC standard INFINEON Technologies 19 1.02 HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules Functional Description All these PC133 168-pin Registered DIMMs conform to a compatible set of timing and operation characteristics intended to comply with the 133 MHz standards. The Registered DIMMs achieve high speed data transfer rate up to 133 MHz, when in “registered mode”. The “registered mode” is achieved when the REGE input signal is in “high” state or the pin is not connected. Operation in “buffered mode” (REGE = “low”) needs careful system design to compensate all input signals for the extra delay time of the register components when in “buffered mode”. “Buffered mode” is limited to 66 Mhz maximum operation frequency. Registered Mode: All control and address signals are synchronized with the positive edge of externally supplied clocks and are registered on-DIMM and hence delayed by one clock cycle in arriving at the SDRAM devices. The use of the on-board register reduces the capacitive loading of the DIMM on input control and address signals. The SDRAM device data lines (DQ) are connected directly to the DIMM tabs through 10 Ohm series resistors. All the following timing diagrams and explanations show DIMM operation at the tabs, not SDRAM operation. The picture below depicts an overview of the effect of the Registered Mode on the data outputs (DQs) for a Read operation. Without the registers, the data is delayed according to the device CAS latency, in the case two clocks. With the register, the data is delayed according to the device CAS latency plus an additional clock cycle. This is known as the DIMM CAS latency, and in this example is four three. The data path can be thought of as a pipeline in which the register effectively lengthens the pipe by one clock cycle. Registered DIMM Burst Read Operation (BL = 4) T0 T1 T2 T3 T4 T5 T6 Read A NOP NOP NOP NOP NOP NOP CLK Command Device CAS latency = 2 t CK2 , DQ’s DIMM CAS latency = 3 t CK3 , DQ’s DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 Added for on-DIMM pipeline register One Clock Reg-DIMM Latency = 1 SPT03968 In case of a Burst Write Command the data-in is delayed one clock due the op-DIMM pipeline register also. Therefore, data for the first Burst Write cycle must be applied on the DQ pins on the next clock cycle after the Write command is issued. the remaining data inputs must be supplied on INFINEON Technologies 20 1.02 HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules each subsequent rising clock edge until the burst length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP Write A NOP NOP NOP NOP NOP NOP NOP DIN A0 DIN A1 DIN A2 DIN A3 don’t care CLK Command DQ’s The first data element and the Write are registered on the next clock edge Reg-DIMM Latency = 1 CLK Extra data is ignored after termination of a Burst. SPT03969 Registered DIMM Burst Write Operation (BL = 4) INFINEON Technologies 21 1.02 HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules INFINEON Technologies 22 1.02 HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules Change List 1.99 2.99 2.99 2.99 4.99 6.5.99 25.5.99 15.7.99 5.8.99 31.8.99 6.9.99 1.10.99 8.11.99 30.11.99 13.12.99 10.1.2000 25.9.2000 4.12.2000 18.1.2001 14.02.2001 3.4.2001 6.6.2001 06.09.2001 19.9.2001 17.12.2001 INFINEON Technologies First revision Iol & Ioh changed to 4 mA, Input capacitances on CLK adjusted to 12 PF according to INTEL Rev.1.2 registered DIMM specification, thz max changed to 7 ns Compliance Coded adjusted in accordance JEDEC PC133 Rev.0.9 specification Byte 21 changed from 16 to 1F according to JEDEC PC133 Rev.0.9 spec. Changed to final Infineon logo added Some SPD codes changed for PC100 2-2-2 compartibility 512 Mbyte and 1GB PC133 DIMM added Partnumber changes from HYS72Vxx200GR to HYS72Vxx300GR due to new gerber file L-DIMM168-37-2 CL2 condition for 256Mb based modules changed from -8(222) to -8A(322) 256MByte module based on 128 Mbit SDRAMs added Drawings for Raw Card B added Databookversion from R+L used, 256MByte added Checksum for 128Mb based module added some typoos corrected, Headline changed Thickness dimensions for 1 GByte module drawing changed to 8 max. Notes renumbered, note 1 added : Registered DIMM module operating temperature conditions, some parameters changed according to INTELs PC133 specifiction HYS72V32300GR-7.5 (256Mbit based 256Mbyte module added) HYS72V16301GR-7.5 added ICC currents on page 9 updated according to the latest values of the 64M S19, 128Mb S17 and 256Mb S20 datasheet Thickness for 1 GByte modules changed from 8.00 mm max.(JEDEC) to 6,40 typ. (actual) Clarification of “buffered mode”operation as a not tested functionality on these modules. Datasheet is for PC133 Registered DIMMs with components based on S17 process and further shrink versions only Changes in SPD-Code for 256Mb based modules in Byte 23, 127 and the Check sum in Byte 63 to make these module 100 % backward compatible to PC100-2-2-2 operation (TPCR_05 from 19.01.2001) -7 speed sort (PC133-222) added SPD Codes for -7 added 2 GByte Module added Typo in SPB04130 corrected ( new: SPB04130-2) Outline drawings changed to L-DIM-168-44, 37 & 37S Absolute maximum rating table added 1GByte module one bank with 512Mbit component added 1 GByte and 2 Gbyte modules with “inhouse” stacking added SCR: Thickness of modules with stacked components changed from 6.4 to 6.8 max 1 GByte and 2 Gbyte modules with “inhouse” stacking added SCR-028-2001-11-12 PC133 / TPCR_08 / JC42.5 Item 1138.5 : JEDEC changed Byte 62h (SPD Revision) from 02h to 12h Checksum changed therefore also 23 1.02