144 pin SO-DIMM SDRAM Modules HYS64V8200GDL HYS64V16220GDL 64MB & 128 MB PC100 / PC133 • 144 Pin Eight Byte Small Outline Dual-In-Line Synchronous DRAM Modules for PC 100 and PC133 notebook applications • one bank 8M x 64 and two bank 16M x 64 non-parity module organisation • Performance: -7 -7.5 -8 PC133 2-2-2 PC133 3-3-3 PC100 2-2-2 Units fCK Clock frequency (max.) 133 133 100 MHz tAC Clock access time 5.4 5.4 6 ns • Single +3.3V(± 0.3V ) power supply • Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave) • Auto Refresh (CBR) and Self Refresh • Decoupling capacitors mounted on substrate • All inputs, outputs are LVTTL compatible • Serial Presence Detect with E2PROM • Uses 8M x 16 128Mbit SDRAM components • 4096 refresh cycles every 64 ms • Gold contact pad, JEDEC MO-190 outline dimensions • This module family is fully compliant with the latest INTEL SO-DIMM layout and electrical specification • All PC133 modules are fully backward compatible for PC100 applications. INFINEON Technologies 1 9.01 HYS64V8200GDL/HYS64V16220GDL 144 pin SO-DIMM SDRAM Modules These INFINEON modules are industry standard 144 pin 8-byte Synchronous DRAM (SDRAM) Small Outline Dual In-line Memory Modules (SO-DIMM) which are organised as 8Mx64 (64MByte) and 16x64 (128MByte) high speed memory arrays designed for use in non-parity applications. These SO-DIMMs use SDRAMs in TSOPII packages. Decoupling capacitors are mounted on the board. The DIMMs use serial presence detects implemented via a serial E2PROM using the two pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All INFINEON 144-pin SO-DIMMs provide a high performance, flexible 8-byte interface in a 67,6 mm long footprint. Product Spectrum: Organisation 8M x 64 16M x 64 Partnumber Speed SDRAMs used HYS64V8200GDL-7 HYS64V8200GDL-7.5 HYS64V8200GDL-8 HYS64V16220GDL-7 HYS64V16220GDL-7.5 HYS64V16220GDL-8 PC133-222 PC133-333 PC100-222 PC133-222 PC133-333 PC100-222 Row Addr. Bank Select 12 BA0, BA1 Column Refresh Addr. Period 4 8Mx16 4k 9 64ms 8 8Mx16 Note: All partnumbers end with a place code (not shown), designating the die revision. Consult factory for current revision. Example: HYS64V16220GDL-8-C2, indicating Rev.C2 dies are used for SDRAM components. Card Dimensions: Organisation 8M x 64 16M x 64 Partnumber HYS64V8200GDL HYS64V16220GDL PCB-Board Layout INTEL Rev. 1.0/1.2 INTEL Rev. 1.0/1.2 L x H x T [mm] 67.60 x 25.40 x 3.80 67.60 x 31.75 x 3.80 Pin Names A0-A11 Address Inputs DQMB0 - DQMB7 Data Mask BA0,BA1 Bank Selects CS0, CS1 *) Chip Select DQ0 - DQ63 Data Input/Output Vcc Power (+3.3 Volt) RAS Row Address Strobe Vss Ground CAS Column Address Strobe SCL Clock for Presence Detect WE Read / Write Input SDA Serial Data Out for Presence Detect CKE0, CKE1 *) Clock Enable N.C. No Connection CLK0, CLK1 Clock Input *) CS1 and CKE1 on two bank modules only INFINEON Technologies 2 9.01 HYS64V8200GDL/HYS64V16220GDL 144 pin SO-DIMM SDRAM Modules Pin Configuration PIN # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 Front Side VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 Vss DQMB0 DQMB1 Vcc A0 A1 A2 Vss DQ8 DQ9 DQ10 DQ11 Vcc DQ12 DQ13 DQ14 DQ15 Vss NC NC CLK0 Vcc RAS WE CS0 CS1 INFINEON Technologies PIN # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 Back Side PIN # VSS DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 Vss DQMB4 DQMB5 Vcc A3 A4 A5 Vss DQ40 DQ41 DQ42 DQ43 Vcc DQ44 DQ45 DQ46 DQ47 Vss NC NC CKE0 Vcc CAS CKE1 N.C.(A12) N.C.(A13) 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 3 Front Side NC Vss NC NC Vcc DQ16 DQ17 DQ18 DQ19 Vss DQ20 DQ21 DQ22 DQ23 Vcc A6 A8 Vss A9 A10 Vcc DQMB2 DQMB3 Vss DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 Vss SDA Vcc PIN # 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 Back Side CLK1 Vss NC NC Vcc DQ48 DQ49 DQ50 DQ51 Vss DQ52 DQ53 DQ54 DQ55 Vcc A7 BA0 Vss BA1 A11 Vcc DQMB6 DQMB7 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 Vss SCL Vcc 9.01 HYS64V8200GDL/HYS64V16220GDL 144 pin SO-DIMM SDRAM Modules WE CS0 CS WE LDQM DQ0-DQ7 DQMB0 DQ0-DQ7 DQMB1 DQ8-DQ15 DQMB4 DQ32-DQ39 DQMB5 DQ40-DQ47 UDQM DQ8-DQ15 D0 CS WE LDQM DQ0-DQ7 DQMB2 DQ16-DQ23 DQMB3 DQ24-DQ31 DQMB6 DQ48-DQ55 DQMB7 DQ56-DQ63 UDQM DQ8-DQ15 D1 A0-A11, BA0, BA1 D0-D3 VCC D0-D3 D0-D3 RAS D0-D3 CAS D0-D3 CKE0 D0-D3 CLK0 4 SDRAM UDQM DQ8-DQ15 D2 CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D3 E2PROM (256 word x 8 Bit) C 1-C 4 VSS CS WE LDQM DQ0-DQ7 SA0 SA1 SA2 SCL SDA Note: All resistors are 10 Ω CLK1 10 pF SPB04133 Block Diagram for one bank 8M x 64 SDRAM DIMM - Module INFINEON Technologies 4 9.01 HYS64V8200GDL/HYS64V16220GDL 144 pin SO-DIMM SDRAM Modules WE CS0 CS1 DQMB0 DQ0-DQ7 DQMB1 DQ8-DQ15 DQMB2 DQ16-DQ23 DQMB3 DQ24-DQ31 CS WE LDQM DQ0-DQ7 CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D0 UDQM DQ8-DQ15 D4 CS WE LDQM DQ0-DQ7 CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D1 UDQM DQ8-DQ15 D5 A0-A11, BA0, BA1 DQMB4 DQ32-DQ39 DQMB5 DQ40-DQ47 DQMB6 DQ48-DQ55 DQMB7 DQ56-DQ63 CS WE LDQM DQ0-DQ7 CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D2 UDQM DQ8-DQ15 D6 CS WE LDQM DQ0-DQ7 CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D3 UDQM DQ8-DQ15 D7 D0-D7 VC C E 2 PROM (256 word x 8 Bit) D0-D7 C VSS D0-D7 RAS D0-D7 CAS D0-D7 CKE0 D0-D3 CKE1 D4-D7 CLK0 4 SDRAM CLK1 4 SDRAM SA0 SA1 SA2 SCL SDA Note: All resistors are 10 Ω Block Diagram for two bank 16M x 64 SDRAM DIMM - Module INFINEON Technologies 5 9.01 HYS64V8200GDL/HYS64V16220GDL 144 pin SO-DIMM SDRAM Modules Absolute Maximum Ratings Parameter Symbol Limit Values min. max. Unit Input / Output voltage relative to VSS VIN, VOUT – 1.0 4.6 V Power supply voltage on VDD VDD – 1.0 4.6 V Storage temperature range T STG -55 +150 oC Power dissipation (per SDRAM component) PD – 1 W Data out current (short circuit) IOS – 50 mA Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. Functional operation should be restricted to recommended operation conditions. Exposure to higher than recommended voltage for extended periods of time affect device reliability DC Characteristics TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V Parameter Symbol Limit Values min. max. Unit Input high voltage VIH 2.0 Vcc+0.3 Input low voltage VIL – 0.5 0.8 V Output high voltage (IOUT = – 4.0 mA) VOH 2.4 – V V Output low voltage (IOUT = 4.0 mA) VOL – 0.4 V Input leakage current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) II(L) – 20 20 µA Output leakage current (DQ is disabled, 0 V < VOUT < VDD) IO(L) – 20 20 µA Capacitance TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Limit Values Unit 8M x 64 max. 16M x 64 max. Input capacitance (A0 to A11, BA0, BA1) CI1 28 52 pF Input capacitance (RAS, CAS, WE, CKE0) CI2 25 46 pF Input Capacitance (CLK0, CLK1) CI3 35 35 pF Input capacitance (CS0) CI4 25 30 pF Input capacitance (DQMB0-DQMB7) CI5 10 15 pF Input / Output capacitance (DQ0-DQ63) CIO 12 18 pF Input Capacitance (SCL,SA0-2) Csc 8 8 pF Input/Output Capacitance Csd 0 10 pF INFINEON Technologies 6 9.01 HYS64V8200GDL/HYS64V16220GDL 144 pin SO-DIMM SDRAM Modules Operating Currents per memory bank (TA = 0 to 70oC, VDD = 3.3V ± 0.3V) (Recommended Operating Conditions unless otherwise noted) Parameter & Test Condition Symb. -7/-7.5 -8 Note ICC1 600 560 mA mA mA 1 ICC2P 6 6 mA 1 ICC2PS 4 4 mA 1 ICC2N 160 140 mA 1 ICC2NS 20 20 mA 1 OPERATING CURRENT trc=trcmin., tck=tckmin. Ouputs open, Burst Length = 4, CL=3 All banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access PRECHARGE STANDBY CURRENT in Power Down Mode CS =VIH (min.), CKE<=Vil(max) PRECHARGE STANDBY CURRENT in Non-Power Down Mode CS = VIH (min.), CKE>=Vih(min) tck = min. tck = Infinity tck = min. tck = Infinity NO OPERATING CURRENT CKE>=VIH(min.) ICC3N 200 180 mA 1 tck = min., CS = VIH(min), active state ( max. 4 banks) CKE<=VIL(max.) ICC3P 40 40 mA 1 BURST OPERATING CURRENT tck = min., Read command cycling ICC4 600 560 mA 1,2 AUTO REFRESH CURRENT tck = min., Auto Refresh command cycling mA 1 ICC5 720 680 ICC6 3.2 3.2 mA 1 SELF REFRESH CURRENT Self Refresh Mode, CKE=0.2V Notes: 1. These parameters depend on the cycle rate. These values are measured at 133 MHz for-7/ -7.5 and 100 MHz for -8 modules. Input signals are changed once during tck, excepts for ICC6 and for standby currents when tck=infinity. 2. These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and the data-out current is excluded. INFINEON Technologies 7 9.01 HYS64V8200GDL/HYS64V16220GDL 144 pin SO-DIMM SDRAM Modules AC Characteristics 1)2) TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns Symbol Parameter Unit Limit Values -7 PC133-222 -7.5 PC133-333 -8 PC100-222 min. max. min. max. min. max. CAS Latency = 3 tCK CAS Latency = 2 7.5 7.5 – – 7.5 10 – – 10 10 – – CAS Latency = 3 tCK CAS Latency = 2 – – 133 133 – – 133 100 – – 100 100 Access Time from Clock CAS Latency = 3 tAC CAS Latency = 2 – – 5.4 5.4 – – 5.4 6 – – 6 6 ns ns – 2.5 – 3 – ns Clock and Access Time Clock Cycle Time ns ns Clock Frequency MHz MHz 2, 3 Clock High Pulse Width tCH 2.5 Clock Low Pulse Width tCL 2.5 – 2.5 – 3 – ns Transition time tT 0.3 1.2 0.3 1.2 0.5 2 ns Input Setup Time tIS 1.5 – 1.5 – 2 – ns 4 Input Hold Time tIH 0.8 – 0.8 – 1 – ns 4 Power Down Mode Entry time tSB Setup and Hold Parameters – 1 – 1 – 1 CLK 4 Power Down Mode Exit Setup Time tPDE 1 – 1 – 1 – CLK 4 tRSC 2 – 2 – 2 – CLK Row to Column Delay Time tRCD 15 – 20 – 20 – ns 5 Row Precharge Time tRP 15 – 20 – 20 – ns 5 Row Active Time tRAS 42 100k 45 100k 50 100k ns 5 Row Cycle Time tRC Mode Register Set-up time Common Parameters 60 – 67 – 70 – ns 5 Activate(a) to Activate(b) Command tRRD period 14 – 15 – 16 – ns 5 CAS(a) to CAS(b) Command period tCCD 1 – 1 – 1 – CLK INFINEON Technologies 8 9.01 HYS64V8200GDL/HYS64V16220GDL 144 pin SO-DIMM SDRAM Modules Parameter Symbol Unit Limit Values -7 PC133-222 -7.5 PC133-333 -8 PC100-222 min. max. min. max. min. max. Refresh Cycle Refresh Period (4096 cycles) tREF – 64 – 64 – 64 ms Self Refresh Exit Time tSREX 1 – 1 – 1 – CLK 6 Data Out Hold Time tOH 3 – 3 – 3 – ns Data Out to Low Impedance Time tLZ 0 – 0 – 0 – ns Data Out to High Impedance Time tHZ 3 7 3 7 3 8 ns DQM Data Out Disable Latency tDQZ – 2 – 2 – 2 CLK Data Input to Precharge (write recovery) tWR 2 – 2 – 2 – CLK DQM Write Mask Latency tDQW 0 – 0 – 0 – CLK Read Cycle 7 Write Cycle INFINEON Technologies 9 9.01 HYS64V8200GDL/HYS64V16220GDL 144 pin SO-DIMM SDRAM Modules Notes: 1. All AC characteristics shown are for SDRAM components. An initial pause of 100µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 2. AC timing tests have Vil = 0.4 V and Vih = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between Vih and Vil. All AC measurements assume tT =1ns with the AC output load circuit shownSpecified tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V .. t CH 2.4 V 0.4 V CLOCK t CL t SETUP tT t HOLD INPUT 1.4 V t AC t LZ t AC t OH I/O OUTPUT 1.4 V t HZ 50 pF Measurement conditions for tac and toh SPT03404 3. If clock rising time is longer than 1ns, a time (tT -0.5) ns has to be added to this parameter. 4. If tT is longer than 1ns, a time (tT -1) ns has to be added to this parameter. 5. Any time that the refresh Period has been exceeded, a minimum of two Auto (CRB) Refresh commands must be given to “wake-up“ the device. 6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 7. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. INFINEON Technologies 10 9.01 HYS64V8200GDL/HYS64V16220GDL 144 pin SO-DIMM SDRAM Modules Serial Presence Detects A serial presence detect storage device - E2PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E 2PROM device during module production using a serial presence detect protocol ( I2C synchronous 2-wire bus) SPD-Table: Byte# Description SPD Entry Value 0 1 2 3 4 5 6 7 8 9 10 11 12 Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type 128 256 SDRAM 12 9 1/2 64 0 LVTTL 7.5 / 10.0 ns 5.4 / 6.0 ns none Self-Refresh, 15.6µs 13 14 15 SDRAM width, Primary Error Checking SDRAM data width Minimum clock delay for back-to-back random column address Burst Length supported Number of SDRAM banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM module attributes 16 17 18 19 20 21 22 23 24 25 26 27 SDRAM Device Attributes :General SDRAM Cycle Time at CL = 2 SDRAM Access Time from Clock at CL=2 SDRAM Cycle Time at CL = 1 SDRAM Access Time from Clock at CL=1 Minimum Row Precharge Time INFINEON Technologies HEX 8M x 64 16M x 64 -7 -7.5 -8 -7 -7.5 -8 80 08 04 0C 09 01 02 40 00 01 75 75 A0 75 75 A0 54 54 60 54 54 60 00 80 10 00 01 n/a tccd = 1 CLK 1, 2, 4 & 8 2 2, & 3 CS latency = 0 Write latency = 0 non buffered/non reg. Vcc tol +/- 10% 7.5 / 10.0 ns 5.4 / 6.0 ns 75 54 A0 60 A0 60 75 54 A0 60 A0 60 not supported not supported 00 00 FF FF FF FF 00 00 FF FF FF FF 15/ 20 ns 0F 14 14 0F 14 14 11 0F 04 06 01 01 00 0E 9.01 HYS64V8200GDL/HYS64V16220GDL 144 pin SO-DIMM SDRAM Modules SPD-Table (cont’d): Byte# Description 28 Minimum Row Active to Row Active delay 29 Minimum RAS to CAS delay 30 Minimum Ras pulse width 31 Module Bank Density (per bank) 32 SDRAM input setup time 33 SDRAM input hold time 34 SDRAM data input setup time 35 SDRAM data input hold time 36-61 Superset information 62 SPD Revision 63 Checksum for bytes 0 - 62 64- Manufactures’s information (optional) 125 126 Frequency Specification 127 Details 128+ Unused storage locations INFINEON Technologies SPD Entry Value 14 / 15 / 16 ns 15 / 20 ns 42 / 45 ns 64MB 1.5 / 2 ns 0.8 / 1 ns 1.5 / 2 ns 0.8 / 1 ns Hex -7 0E 8Mx64 -7.5 -8 0F 10 0F 2A 14 2D 14 2D 15 08 15 08 15 08 15 08 20 10 20 10 -7 0E 16Mx64 -7.5 -8 0F 10 0F 2A 14 2D 14 2D 15 08 15 08 15 08 15 08 20 10 20 10 E2 0B 69 10 FF 12 Revision 1.2 E1 0A PC100 68 64 87 C7 FF 12 9.01 HYS64V8200GDL/HYS64V16220GDL 144 pin SO-DIMM SDRAM Modules Package Outlines 64 MByte SO-DIMM Module package (JEDEC MO-190) HYS64V8200GDL (144 pin, dual read-out, single in-line memory module) 67,6 ± 0.15 3.8 max. 25.4 ± 0.13 63,6 3.3 1 23.2 59 61 32.8 143 1 ± 0.1 2.6 4.6 2 1.5 1.8 60 62 144 20 6 4 3.7 4 Detail of Contacts 0.6 0.2 -0.15 0.25 2.55 Detail of Chamfer 0.2 -0.15 0.8 L-DIM-144-10 Note: All tol eran ces accord ing to JEDEC stan dard INFINEON Technologies 13 9.01 HYS64V8200GDL/HYS64V16220GDL 144 pin SO-DIMM SDRAM Modules 128 MByte SO-DIMM Module package HYS64V16220GDL (144 pin, dual read-out, single in-line memory module) 67.6 ± 0.15 3.8 max. 31.75 ± 0.13 63.6 3.3 1 23.2 59 61 32.8 143 1± 0.1 2.5 24.5 4.6 2 1.5 1.8 60 62 144 20 6 4 3.7 4 0.25 0.2 -0.15 Detail of Chamfer 2.55 Detail of Contacts 0.6 0.2 -0.15 0.8 L-DIM-144-9 Note : All toleran ces according to JEDEC stan dard INFINEON Technologies 14 9.01